JP5680326B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent years, power semiconductor devices are used for power conversion and power control. Among such power semiconductor devices, a power MOSFET (Metal Oxide Semiconductor-Field Effect Transistor) has excellent high-speed switching performance and is used as a key device in the field of switching power supplies and the like.

  One type of power MOSFET is a trench gate type MOSFET. In this trench gate type MOSFET, a trench (groove) is formed in a semiconductor substrate, a trench gate insulating film such as an oxide film is formed on the bottom and wall surfaces inside the groove, and a trench gate electrode is further formed inside. Of structure.

  The trench gate type MOSFET having such a structure has a problem that the trench gate insulating film breaks down because a high electric field is applied to the trench gate insulating film.

  Specifically, as shown in FIG. 1, a trench gate type MOSFET has a P-type body formed by laminating an N-type drift layer 202 and a P-type body diffusion layer 203 on an N-type drain layer 201. A trench is formed from the side where the diffusion layer 203 is formed to the N − type drift layer 202. An N + type source layer 207 is formed on both sides of the opening of the trench, and thereafter, a trench gate insulating film 204 made of an oxide film is formed on the side surface and the bottom surface in the trench, and further inside the trench A gate electrode 205 is formed. The N-type drain layer 201 is provided with a drain electrode 206, and the surface of the P-type body diffusion layer 203 is provided with a source electrode 208 in contact with the N + type source layer 207. In the trench gate type MOSFET having such a structure, the lowermost end 205a which is the deepest position of the trench gate electrode 205 is formed at a position deeper than the lowermost end 203a which is the deepest position of the P-type body diffusion layer 203. . For this reason, the electric field concentrates on the trench gate insulating film 204 in the region surrounded by the broken line A, thereby causing the dielectric breakdown of the trench gate insulating film 204 and destroying the trench gate type MOSFET.

  In particular, in the case of a semiconductor device using SiC as the semiconductor layer and the semiconductor substrate, the drift layer is formed thin, so that the trench gate insulating film 204 is easily broken down.

Japanese Patent Laid-Open No. 10-98188 JP 2000-269487 A JP 2000-332243 A JP-A-2005-116822

  For this reason, a trench gate type MOSFET having a structure in which dielectric breakdown in the trench gate insulating film hardly occurs has been studied.

  For example, in order to avoid concentration of the electric field in the trench gate insulating film, as shown in FIG. 2, an N− type drift layer 212 and a P type body diffusion layer 213 are stacked on the N type drain layer 211. Then, a trench is formed in the P-type body diffusion layer 213 from the side where the P-type body diffusion layer 213 is formed. N + type source layers 217 are formed on both sides of the opening portion of the trench, and thereafter, a trench gate insulating film 214 made of an oxide film is formed on the side surface and the bottom surface in the trench, and further inside, the trench is formed. A structure in which the gate electrode 215 is formed can be considered. The N-type drain layer 211 is provided with a drain electrode 216, and the surface of the P-type body diffusion layer 213 is provided with a source electrode 218 in contact with the N + type source layer 217. In the trench gate type MOSFET having such a structure, the lowest end 215a which is the deepest position of the trench gate electrode 215 is formed at a position shallower than the lowest end 213a which is the deepest position of the P-type body diffusion layer 213. . Therefore, the concentration of the electric field in the trench gate insulating film 214 can be relaxed. However, since it becomes difficult to form a channel, there arises a problem that the on-resistance in the drain electrode 216 and the source electrode 218 increases.

  Further, as shown in FIG. 3, the N-type drift layer 222 and the P-type body diffusion layer 223 are stacked on the N-type drain layer 221, and the side where the P-type body diffusion layer 223 is formed. A trench extending to the N − type drift layer 222 is formed. N + type source layers 227 are formed on both sides of the opening portion of the trench, and thereafter, a trench gate insulating film 224 made of an oxide film is formed on the side surface and the bottom surface in the trench, and further inside the trench A configuration in which the gate electrode 225 is formed is conceivable. The trench gate insulating film 224 is formed with a film thickness different from the bottom and side surfaces of the trench, and the film thickness of the trench gate insulating film 224a on the bottom surface of the trench is the film thickness of the trench gate insulating film 224b on the side surface of the trench. It is formed to be thicker than the thickness. A drain electrode 226 is provided on the N-type drain layer 221, and a source electrode 228 is provided on the surface of the P-type body diffusion layer 223 so as to be in contact with the N + -type source layer 227. In the trench gate type MOSFET having such a structure, the bottom end 225a which is the deepest position of the trench gate electrode 225 is formed at a position deeper than the bottom end 223a which is the deepest position of the P-type body diffusion layer 223. Yes. Therefore, the trench gate insulating film 224a on the bottom surface of the trench is formed thick, and the trench gate insulating film 224a on the bottom surface of the trench is not easily destroyed. However, the trench gate insulating film 224b on the side surface of the trench is formed thinner than the trench gate insulating film 224a on the bottom surface of the trench, and the electric field is concentrated near the bottom surface of the trench in the trench gate insulating film 224b on the side surface of the trench. It has the problem that it ends up.

  The present invention has been made in view of the above, and an object thereof is to provide a trench gate type MOSFET having a structure in which a trench gate insulating film is not destroyed by an applied electric field without increasing an on-resistance. It is what.

The present invention provides a first semiconductor layer of a first conductivity type formed on a semiconductor substrate and a second semiconductor layer of a first conductivity type formed in a partial region on the first semiconductor layer. A third semiconductor layer of the second conductivity type formed on the first semiconductor layer and the second semiconductor layer, and a side on which the third semiconductor layer is formed. A trench having a bottom surface in the second semiconductor layer; a fourth semiconductor layer of a first conductivity type formed on both sides of the opening of the trench; and a gate insulating film formed on the bottom surface and side surfaces of the trench And a gate electrode formed in the trench through the gate insulating film, and the gate insulating film is formed to have a film thickness at the bottom surface of the trench larger than a film thickness at the side surface of the trench. A gate insulating film on the bottom surface of the trench The position of the interface in the depth direction with the gate electrode is formed at a position deeper than the interface in the depth direction between the second semiconductor layer and the third semiconductor layer, and the second semiconductor layer And the position of the interface in the depth direction between the bottom surface of the trench and the gate insulating film is formed at a position shallower than the interface in the depth direction between the first semiconductor layer and the third semiconductor layer , In a direction parallel to the surface of the semiconductor substrate, from the interface between the gate insulating film and the second semiconductor layer on the side surface of the trench to the interface between the second semiconductor layer and the third semiconductor layer A length X is defined between the second semiconductor layer and the third semiconductor layer from the interface between the first semiconductor layer and the third semiconductor layer in a direction perpendicular to the surface of the semiconductor substrate. The length to the interface is Y If, characterized X <Y der Rukoto.

The present invention also provides a first semiconductor layer of a first conductivity type formed on a semiconductor substrate and a second layer of a first conductivity type formed in a partial region on the first semiconductor layer. Formed from a semiconductor layer, a third semiconductor layer of the second conductivity type formed on the first semiconductor layer and the second semiconductor layer, and a side on which the third semiconductor layer is formed A trench having a bottom surface in the second semiconductor layer formed; a fourth semiconductor layer of a first conductivity type formed on both sides of the opening of the trench; and a gate formed on the bottom surface and side surfaces of the trench. An insulating film and a gate electrode formed in the trench through the gate insulating film, and the gate insulating film is thicker at the bottom surface of the trench than at the side surface of the trench. A gate formed on the bottom of the trench The position of the interface in the depth direction between the edge film and the gate electrode is formed at a position deeper than the interface in the depth direction between the second semiconductor layer and the third semiconductor layer. The position of the interface in the depth direction between the semiconductor layer and the gate insulating film on the bottom surface of the trench is formed at a position shallower than the interface in the depth direction between the first semiconductor layer and the third semiconductor layer. And in the direction parallel to the surface of the semiconductor substrate, from the interface between the gate insulating film and the second semiconductor layer on the side surface of the trench, the second semiconductor layer and the third semiconductor layer The length to the interface is not less than 0.1 μm and not more than the length at which the depletion layer is formed .

  Further, the present invention provides the second semiconductor layer and the third semiconductor layer from the interface between the gate insulating film and the second semiconductor layer on the side surface of the trench in a direction parallel to the surface of the semiconductor substrate. The length to the interface is 0.1 μm or more and not more than the length at which the depletion layer is formed.

  Further, the invention is characterized in that the impurity concentration in the second semiconductor layer is higher than the impurity concentration in the first semiconductor layer.

  Further, the present invention is characterized in that the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed of a material containing SiC.

  According to the present invention, in the first semiconductor layer, a fifth semiconductor layer of the first conductivity type is formed on a surface opposite to the surface on which the third semiconductor layer is formed. The drain electrode is formed on the surface of the fifth semiconductor layer, and the source electrode is formed on the surface of the third semiconductor layer in contact with the fourth semiconductor layer. .

  According to the present invention, a second conductive type semiconductor layer is formed on a first conductive type first semiconductor layer formed on a semiconductor substrate. In the second conductive type semiconductor layer, By forming a region of the first conductivity type in the predetermined region, a region other than the predetermined region is a region of the second conductivity type, and the region of the first conductivity type is the second semiconductor Forming a layer on the second semiconductor layer and the region of the second conductivity type, forming the second conductivity type semiconductor film on the region of the second conductivity type; Forming a third semiconductor layer made of a semiconductor film of conductivity type 2 and forming a trench having a bottom surface in the second semiconductor layer from the side on which the third semiconductor layer is formed; A fourth semiconductor layer of the first conductivity type is formed on both sides of the opening of the trench. Forming a gate insulating film on the side and bottom surfaces in the trench, and forming a gate electrode in the trench through the gate insulating film, the gate insulating film comprising: The film thickness at the bottom surface of the trench is formed thicker than the film thickness at the side surface of the trench, and the position of the interface in the depth direction between the gate insulating film and the gate electrode is the same as that of the second semiconductor layer. It is formed at a position deeper than the interface in the depth direction with the third semiconductor layer, and the position of the interface in the depth direction between the second semiconductor layer and the gate insulating film is the first semiconductor. It is characterized by being formed at a position shallower than the interface between the layer and the third semiconductor layer.

  According to the present invention, a first conductive type semiconductor layer is formed on a first conductive type first semiconductor layer formed on a semiconductor substrate, and the first conductive type semiconductor layer includes: By forming a region of the second conductivity type in a predetermined region, the region other than the predetermined region is a region of the first conductivity type, and the region of the first conductivity type is the second semiconductor Forming a layer on the second semiconductor layer and the region of the second conductivity type, forming the second conductivity type semiconductor film on the region of the second conductivity type; Forming a third semiconductor layer made of a semiconductor film of conductivity type 2 and forming a trench having a bottom surface in the second semiconductor layer from the side on which the third semiconductor layer is formed; A fourth semiconductor layer of the first conductivity type is formed on both sides of the opening of the trench. Forming a gate insulating film on the side and bottom surfaces in the trench, and forming a gate electrode in the trench through the gate insulating film, the gate insulating film comprising: The film thickness at the bottom surface of the trench is formed thicker than the film thickness at the side surface of the trench, and the position of the interface in the depth direction between the gate insulating film and the gate electrode is the same as that of the second semiconductor layer. It is formed at a position deeper than the interface in the depth direction with the third semiconductor layer, and the position of the interface in the depth direction between the second semiconductor layer and the gate insulating film is the first semiconductor. It is characterized by being formed at a position shallower than the interface between the layer and the third semiconductor layer.

  The present invention also includes a step of forming a second semiconductor layer of the first conductivity type on the first semiconductor layer of the first conductivity type formed on the semiconductor substrate, and the second semiconductor layer. Forming a second semiconductor layer of a second conductivity type thereon, and forming a first trench having a bottom surface in the second semiconductor layer from the side on which the third semiconductor layer is formed; The first trench is different from the step of forming the fourth semiconductor layer of the first conductivity type on both sides of the opening of the first trench and the side on which the third semiconductor layer is formed. Forming a second trench having a bottom surface in the third semiconductor layer in a portion; and a second conductivity type region in the second semiconductor layer region corresponding to the region of the bottom surface portion of the second trench. A semiconductor region is formed, and the second trench is made of a semiconductor material of a second conductivity type. A step of forming a layer included in the third semiconductor layer by embedding, a step of forming a gate insulating film on a side surface and a bottom surface in the first trench, and the first insulating layer via the gate insulating film. Forming a gate electrode in the trench, and the gate insulating film is formed so that the film thickness on the bottom surface of the first trench is larger than the film thickness on the side surface of the first trench. The position of the interface in the depth direction between the gate insulating film and the gate electrode is formed at a position deeper than the interface in the depth direction of the second semiconductor layer and the third semiconductor layer, The position of the interface in the depth direction between the second semiconductor layer and the gate insulating film is formed at a position shallower than the interface between the first semiconductor layer and the semiconductor region.

  The present invention also includes a step of forming a second semiconductor layer of the second conductivity type on the first semiconductor layer of the first conductivity type formed on the semiconductor substrate, and the third semiconductor layer. Forming a trench having a bottom surface in the third semiconductor layer from the side on which the first conductivity type is formed, and forming a fourth semiconductor layer of the first conductivity type on both sides of the opening of the trench; Implanting an impurity element into the bottom surface of the trench, forming a second semiconductor layer of the first conductivity type in a region from the bottom surface of the trench to the first semiconductor layer, and a side surface in the trench And a step of forming a gate insulating film on the bottom surface, and a step of forming a gate electrode in the trench through the gate insulating film, and the gate insulating film has a film thickness on a side surface of the trench, Film on the bottom of the trench The interface position in the depth direction between the gate insulating film and the gate electrode is deeper than the shallowest position at the interface between the second semiconductor layer and the third semiconductor layer. And the position of the interface in the depth direction between the second semiconductor layer and the gate insulating film is formed at a position shallower than the interface between the first semiconductor layer and the third semiconductor layer. It is characterized by being.

  According to the present invention, it is possible to provide a trench gate type MOSFET having a structure in which the trench gate insulating film is not destroyed by the applied electric field without increasing the on-resistance.

Structure diagram of conventional trench gate type MOSFET Structure of trench gate type MOSFET improved from FIG. 1 (1) Structure diagram of trench gate type MOSFET improved from FIG. 1 (2) Structure diagram of trench gate type MOSFET in the first embodiment Manufacturing process diagram of trench gate type MOSFET in the second embodiment Manufacturing process diagram of trench gate type MOSFET in the third embodiment Manufacturing process diagram of trench gate type MOSFET in the fourth embodiment Manufacturing process diagram of trench gate type MOSFET in the fifth embodiment

  The form for implementing this invention is demonstrated below.

[First Embodiment]
The semiconductor device according to the first embodiment will be described with reference to FIG. 4, a semiconductor device using SiC as a semiconductor material will be described as a semiconductor device in the present embodiment.

  In the semiconductor device according to the present embodiment, an N − type drift layer 12 and a P type body diffusion layer 13 (third semiconductor layer) formed by epitaxial growth are formed on an N type drain layer 11 (fifth semiconductor layer). Are stacked. The N − -type drift layer 12 includes two regions having different heights (depths), that is, a first region 12a (first semiconductor layer) formed on the substantially entire surface on the N-type drain layer 11 side and a P-type body. A second region 12b (second semiconductor layer) formed in a partial region on the first region 12a is provided so as to enter the diffusion layer 13 side. Therefore, the position of the interface 10a between the first region 12a which is the uppermost portion of the first region 12a of the N − type drift layer 12 and the P type body diffusion layer 13 is the second region of the N − type drift layer 12. The position is deeper than the interface 10b between the second region 12b, which is the uppermost part of 12b, and the P-type body diffusion layer 13.

  In addition, as a method for performing epitaxial growth, a film forming method by CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), MBE (Molecular Beam Epitaxy) or the like can be cited.

  The trench forms an N + type source layer 17 on the surface of the P type body diffusion layer 13, penetrates the N + type source layer 17 and the P type body diffusion layer 13, and is a second region 12 b of the N − type drift layer 12. A trench gate insulating film 14 made of an oxide film is formed on the side and bottom surfaces in the trench, and a trench gate electrode 15 is formed inside. Therefore, N + type source layers 17 (fourth semiconductor layers) are formed on both sides of the trench opening on the surface of the P type body diffusion layer 13.

  Further, the trench gate insulating film 14 is formed with a different film thickness on the bottom surface and the side surface of the trench, and the trench gate insulating film 14a on the bottom surface of the trench is thicker than the trench gate insulating film 14b on the side surface of the trench. Is formed. Here, the interface 10c between the trench gate insulating film 14a which is the lowermost part of the trench gate insulating film 14a and the second region 12b of the N − type drift layer 12, and the trench gate insulating film which is the uppermost part of the trench gate insulating film 14a 14a and the interface 10d between the trench gate electrode 15 and the interfaces 10a and 10b in the depth direction are formed so as to be an interface 10a, an interface 10c, an interface 10d, and an interface 10b in order from a deep position. That is, the interface 10b between the second region 12b and the P-type body diffusion layer 13 is formed at a position shallower than the interface 10d which is the uppermost part of the trench gate insulating film 14a, and the lowermost part of the trench gate insulating film 14a. An interface 10a between the first region 12a and the P-type body diffusion layer 13 is formed at a position deeper than the interface 10c. A drain electrode 16 is provided on the N-type drain layer 11, and a source electrode 18 is provided on the surface of the P-type body diffusion layer 13 in contact with the N + type source layer 17.

  Further, the second region 12b of the N − -type drift layer 12 is formed so that the cross-sectional shape before the trench is formed is a substantially rectangular shape. That is, since the semiconductor device having the structure shown in FIG. 4 uses SiC as a semiconductor material for forming each semiconductor layer, the diffusion of impurities hardly progresses in SiC. Therefore, the second region 12b can be formed in a substantially rectangular shape. Further, in the length in the second region 12b in the lateral direction of the trench, that is, in the direction parallel to the surface of the semiconductor substrate (the direction parallel to the film surface of the N-type drain layer 11 in FIG. 4), the trench gate insulating film 14b. The length X from the interface between the second region 12b of the N− type drift layer 12 and the interface between the second region 12b and the P type body diffusion layer 13 is 0.1 μm or more, and the distance that the depletion layer reaches It is formed to be as follows. Here, the thickness of the depletion layer can be obtained by the equation shown in (1).

Depletion layer thickness = (2εVbi / qNd) ^1/2 (1)
Note that ε is a dielectric constant, which is about 9 × 10 ⁻¹³ F / cm in the case of SiC. Vbi is a built-in potential and is 2 to 3V. q is an elementary charge and is 1.6 × 10 ⁻¹⁹ C. Nd is the concentration of the impurity element and is about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . Based on this condition, the minimum value of the depletion layer thickness obtained by the equation shown in (1) is about 0.15 μm. Therefore, in consideration of manufacturing errors and the like, the depletion layer thickness needs to be at least 0.1 μm or more. In addition, when a reverse bias is applied, the depletion layer expands, so that it is preferable that the pitch be 1/2 or less of the formed trench pitch. Further, in the direction perpendicular to the surface of the semiconductor substrate (the direction perpendicular to the film surface of the N-type drain layer 11 in FIG. 4), the length Y from the interface 10a to the interface 10b is 0.2 μm or less. In addition, the relationship between the length X and the length Y is preferably X <Y.

In the semiconductor device according to the present embodiment, a withstand voltage of 1000 V is assumed, and the N− type drift layer 12 is doped with nitrogen (N) as an impurity element at 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^−3. In the N − type drift layer 12, the second region 12b is formed to have a higher impurity element concentration than the first region 12a. Further, the P-type body diffusion layer 13 is doped with aluminum (Al) as an impurity element by 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ . In the description of this embodiment, the case where Al is used as the impurity element for forming the P-type is described, but B (boron) may be used as the impurity element.

  Next, in the semiconductor device in the present embodiment shown in FIG. 4 and the semiconductor device shown in FIGS. 1, 2, and 3, when a voltage of 1000 V is applied between the drain electrode and the source electrode, respectively. The result of examining the electric field strength in the trench gate insulating film will be described. As a result, it is 5.6 MeV in the case of the semiconductor device shown in FIG. 1, 1.4 MeV in the case of the semiconductor device shown in FIG. 2, and 2.1 MeV in the case of the semiconductor device shown in FIG. In the case of the semiconductor device shown in FIG. 4, it was 1.4 MeV.

  As described above, in the semiconductor device in the present embodiment shown in FIG. 4, the electric field strength in the trench gate insulating film of the semiconductor device shown in FIGS. 1 and 3 is lower, and the trench gate insulation of the semiconductor device shown in FIG. It was almost the same as the electric field strength in the film. In addition, the semiconductor device in the present embodiment has the N − type drift layer 12 shown in FIG. 4 from the lowermost end 213a that is the interface between the N − type drift layer 212 and the P type body layer 213 shown in FIG. Since the interface 10b between the second region 12b, which is the top of the two regions 12b, and the P-type body diffusion layer 13 is at a shallower position, the on-resistance is made lower than that of the semiconductor device shown in FIG. Can do.

  Therefore, in the semiconductor device according to the present embodiment, the trench gate insulating film 14 can be prevented from being destroyed by the applied electric field without increasing the on-resistance.

  In the above description, the NMOS is described. However, the semiconductor device in this embodiment can be a PMOS by switching the N-type and the P-type. In the above description, the case of using SiC as the semiconductor material has been described, but the same applies to the case of using Si.

  Further, specific examples of the semiconductor device according to the present embodiment include a power MOSFET and the like when SiC is used as the semiconductor material, and a power MOSFET and IGBT (Insulated) when Si is used as the semiconductor material. Gate Bipolar Transistor).

[Second Embodiment]
Next, a second embodiment will be described. The present embodiment is a method for manufacturing a semiconductor device.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG.

  First, as shown in FIG. 5A, an SiC N layer 111 is formed on an SiC substrate on which an N-type drain layer (not shown) is formed, and further, an SiC P layer is formed on the N layer 111. 112 is formed by epitaxial growth. Note that the N layer 111 is a first region (first semiconductor layer) of the N − type drift layer, and the thickness of the P layer 112 formed is that of an N − type drift layer described later. The thickness of the region 2 is substantially the same as the thickness of the region 2. In addition, as a method of forming by epitaxial growth, methods, such as CVD, PVD, MBE, are mentioned. Further, in order to form the N layer 111, nitrogen is doped as an impurity element, and in order to form the P layer 112, Al is doped as an impurity element.

  Next, as shown in FIG. 5B, an N layer 113 made of SiC is formed in a predetermined region of the P layer 112. The N layer 113 serves as a second region (second semiconductor layer) of the N − drift layer, and has an impurity concentration higher than that of the N layer 111 serving as the first region of the N − drift layer. Is formed to be high. In addition, since the N layer 113 is formed in the P layer 112, a region where the N layer 113 is not formed in the P layer 112 becomes the P layer 112a. As one method for forming the N layer 113, after forming the P layer 112, a resist pattern (not shown) having an opening is formed in a region where the N layer 113 is formed, and this resist pattern is used as a mask. The P layer 112 in the opening portion of the resist pattern is removed by etching until the surface of the N layer 111 is exposed, and thereafter, SiC doped with nitrogen as an impurity element is formed by epitaxial growth in the region removed by the etching. Thus, a method of forming the N layer 113 can be given. As another method, after forming the P layer 112, a resist pattern (not shown) having an opening is formed in a region where the N layer 113 is formed, and the resist pattern is used as a mask to form impurities in the P layer 112. There is a method of forming the N layer 113 in a region in the opening of the resist pattern by implanting nitrogen as an element.

  Next, as shown in FIG. 5C, a P layer 114 is formed on the P layer 112a and the N layer 113 by epitaxial growth. As a result, a P-type body diffusion layer 115 (third semiconductor layer) including the P layer 112a and the P layer 114 is formed.

  Next, as shown in FIG. 5D, a trench 116 is formed. The trench 116 is formed in a portion where the N layer 113 serving as the second region of the N − type drift layer is formed, penetrates the P layer 114 of the P type body diffusion layer 115, and the bottom surface of the trench 116 is the N layer. 113 is formed. Note that, before or after the formation of the trench 116, N + source layers 118 are formed on both sides of the opening of the trench 116. For example, an N + source layer 118 is formed on the surface of the P-type body diffusion layer 115, and then a mask (not shown) having an opening is formed in a region where the trench 116 is formed, and RIE (Reactive Ion Etching) or the like is formed. By dry etching, the N + source layer 118 and the P-type body diffusion layer 115 in the region where the opening is formed are penetrated and a part of the N layer 113 is removed. Note that the interface between the N layer 111 serving as the first region of the N − type drift layer and the P layer 112a in the P type body diffusion layer 115 is defined as 110a, and the N layer 113 serving as the second region of the N − type drift layer. When the interface between the P-type body diffusion layer 115 and the P layer 114 is 110b, the interface 110c serving as the bottom surface of the formed trench 116 is shallower than the interface 110a and deeper than the interface 110b. It forms so that it may become. In addition, as for the positional relationship between the formed trench 116 and the N layer 113, it is desirable that the alignment accuracy be good, but even if a slight positional deviation occurs, the characteristics of the manufactured semiconductor device are not affected. . That is, even if the position of the formed trench 116 is slightly shifted, the amount of current flowing through the wide portion of the N layer 113 in the film surface direction is large and the amount of current flowing through the narrow portion is small. Therefore, even if the position where the trench 116 is formed is slightly shifted, the amount of current flowing in one trench 116 is hardly changed.

  Next, as shown in FIG. 5E, a trench gate insulating film 117 is formed in the trench 116. The trench gate insulating film 117 is formed so that the thickness of the trench gate insulating film 117 a on the bottom surface of the trench 116 is larger than the film thickness of the trench gate insulating film 117 b on the side surface of the trench 116. Specifically, the film thickness of the trench gate insulating film 117a on the bottom surface of the trench 116 is made thicker than the film thickness of the trench gate insulating film 117b on the side surface of the trench 116 by performing film formation by CVD and thermal oxidation. Then, a trench gate insulating film 117 is formed. Note that the trench gate insulating film 117a on the bottom surface of the trench 116 is formed such that the position of the interface 110d that is the upper surface of the trench gate insulating film 117a is deeper than the interface 110b.

  Next, as shown in FIG. 5F, a trench gate electrode 118 is formed in the trench 116 in which the trench gate insulating film 117 is formed. Further, an N + source is formed on the surface of the P-type body diffusion layer 115. A source electrode 119 is formed in contact with the layer 118, and a drain electrode is formed on the surface of a drain layer (not shown). Thus, the semiconductor device is manufactured by the method for manufacturing the semiconductor device in the present embodiment.

  The manufacturing method of the semiconductor device according to the present embodiment manufactures a semiconductor device such as a trench gate type MOSFET having a structure in which the trench gate insulating film is not destroyed by an electric field without increasing the on-resistance by a simple process. can do.

[Third Embodiment]
Next, a third embodiment will be described. This embodiment is a method for manufacturing a semiconductor device, which is different from the second embodiment.

  A method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIG.

  First, as shown in FIG. 6A, an SiC N layer 131 is formed on an SiC substrate on which an N-type drain layer (not shown) is formed, and an N layer 132 is further formed on the N layer 131. It is formed by epitaxial growth. Note that the N layer 131 becomes a first region (first semiconductor layer) of the N − -type drift layer. The N layer 132 forms a second region of the N − type drift layer as will be described later, and has an impurity concentration higher than that of the N layer 131 serving as the first region of the N − type drift layer. To form.

  Next, as shown in FIG. 6B, a P layer 133 made of SiC is formed in a predetermined region of the N layer 132. Note that, when the P layer 133 is formed in the N layer 132, a region where the P layer 133 is not formed in the N layer 132 becomes the N layer 132a. As one method for forming the P layer 133, after forming the N layer 132, a resist pattern (not shown) having an opening is formed in a region where the P layer 133 is formed, and this resist pattern is used as a mask. The N layer 132 in the opening of the resist pattern is removed by etching until the surface of the N layer 131 is exposed, and thereafter, SiC doped with Al as an impurity element is formed by epitaxial growth in the region removed by the etching. The method of forming the P layer 133 by this is mentioned. As another method, after the N layer 132 is formed, a resist pattern (not shown) having an opening is formed in a region where the P layer 133 is formed, and the resist pattern is used as a mask to form impurities in the N layer 132. A method of forming the P layer 133 in the region in the opening of the resist pattern by injecting Al as an element can be mentioned. The N layer 132a after the P layer 133 is formed in this manner becomes the second region (second semiconductor layer) of the N − type drift layer.

  Next, as shown in FIG. 6C, a P layer 134 is formed on the N layer 132a and the P layer 133 by epitaxial growth. As a result, a P-type body diffusion layer 135 (third semiconductor layer) composed of the P layer 133 and the P layer 134 is formed.

  Next, as shown in FIG. 6D, a trench 136 is formed. The trench 136 is formed in a portion where the N layer 132a to be the second region of the N − type drift layer is formed, penetrates the P layer 134 of the P type body diffusion layer 135, and the bottom surface of the trench 136 is the N layer. It is formed to be 132a. Note that an N + source layer 139 is formed on both sides of the opening of the trench 136 before or after the trench 136 is formed. For example, an N + source layer 139 is formed on the surface of the P-type body diffusion layer 135, and then a mask (not shown) having an opening is formed in a region where the trench 136 is formed, and the opening is formed by dry etching such as RIE. The N + source layer 139 and the P-type body diffusion layer 135 in the region where the part is formed are formed by removing a part of the N layer 132a. Note that the interface between the N layer 131 serving as the first region of the N − type drift layer and the P layer 133 in the P type body diffusion layer 135 is denoted by 130a, and the N layer 132a serving as the second region of the N − type drift layer. When the interface between the P-type body diffusion layer 135 and the P layer 134 is 130b, the interface 130c serving as the bottom surface of the formed trench 136 is shallower than the interface 130a and deeper than the interface 130b. It forms so that it may become. In addition, as for the positional relationship between the formed trench 136 and the N layer 132a, it is desirable that the alignment accuracy be good, but even if a slight positional deviation occurs, the characteristics of the manufactured semiconductor device are not affected. . That is, even if the position of the formed trench 136 is slightly shifted, the amount of current flowing through the wide portion of the N layer 132a in the film surface direction is large, and the amount of current flowing through the narrow portion is small. Therefore, even if the position where the trench 136 is formed is slightly deviated, the amount of current flowing in one trench 136 is hardly changed.

  Next, as shown in FIG. 6E, a trench gate insulating film 137 is formed in the trench 136. The trench gate insulating film 137 is formed so that the film thickness of the trench gate insulating film 137a on the bottom surface of the trench 136 is larger than the film thickness of the trench gate insulating film 137b on the side surface of the trench 136. Note that the trench gate insulating film 137a on the bottom surface of the trench 136 is formed such that the position of the interface 130d that is the upper surface of the trench gate insulating film 137a is deeper than the interface 130b.

  Next, as shown in FIG. 6F, a trench gate electrode 138 is formed in the trench 136 in which the trench gate insulating film 137 is formed. Further, an N + source is formed on the surface of the P-type body diffusion layer 115. A source electrode 140 is formed in contact with the layer 139, and a drain electrode is formed on the surface of a drain layer (not shown). Thus, the semiconductor device is manufactured by the method of manufacturing a semiconductor device according to the semi-embodiment.

  In the method of manufacturing a semiconductor device according to the present embodiment, as in the second embodiment, the trench gate insulating film is not destroyed by an electric field without increasing the on-resistance by a simple process. A semiconductor device such as a trench gate type MOSFET can be manufactured.

  The contents of the film forming method other than the above are the same as those in the second embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. The present embodiment is a method for manufacturing a semiconductor device different from the second and third embodiments.

  A method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIG.

  First, as shown in FIG. 7A, an SiC N layer 151 is formed on an SiC substrate on which an N-type drain layer (not shown) is formed, and further, an SiC N layer is formed on the N layer 151. 152 is formed by epitaxial growth. Note that the N layer 151 becomes a first region (first semiconductor layer) of the N − type drift layer. Further, as will be described later, the N layer 152 forms a second region of the N − type drift layer, and has an impurity concentration higher than that of the N layer 151 serving as the first region of the N − type drift layer. To form. In order to form the N layer 151 and the N layer 152, nitrogen is doped as an impurity element.

  Next, as shown in FIG. 7B, a SiC P layer 153 is formed on the N layer 152. Specifically, P layer 153 is formed by depositing SiC doped with Al as an impurity element on N layer 152 by epitaxial growth.

  Next, as shown in FIG. 7C, a trench 154 (first trench) is formed. The trench 154 is formed so as to penetrate the P layer 153 and form the bottom surface of the trench 154 in the N layer 152. Note that, before or after the formation of the trench 154, N + source layers 161 are formed on both sides of the opening of the trench 154. For example, an N + source layer 161 is formed on the surface of the P layer 153, and then a mask (not shown) having an opening is formed in a region where the trench 154 is formed, and the mask opening is formed by dry etching such as RIE. A trench 154 is formed by passing through the N + source layer 161 and the P layer 153 in the region to be removed and removing a part of the N layer 152.

  Next, as shown in FIG. 7D, another different trench 155 (second trench) is formed between the trenches 154, and ion implantation of an impurity element is performed. Specifically, the trench 155 is formed by the same method as the trench 154. The bottom surface of the trench 155 is formed in the vicinity of the interface between the N layer 152 and the P layer 153 and at a position shallower than the interface between the N layer 152 and the P layer 153. For this reason, the bottom surface of the trench 155 is formed at a shallower position than the bottom surface of the trench 154. Thereafter, a mask (not shown) is formed in a region other than the trench 155, and an Al ion is implanted as an impurity element into the N layer 152 below the region where the trench 155 is formed, thereby forming a P layer 156. The position of the interface 150a between the P layer 156 formed in this way and the N layer 151 serving as the first region of the N− type drift layer is formed to be deeper than the interface 150c serving as the bottom surface of the trench 154. The Note that the position of the interface 150b which is the upper surface of the N layer 152 is shallower than the interface 150c. After the P layer 156 is formed in this way, the N layer 152 becomes the second region (second semiconductor layer) of the N − type drift layer.

  Next, as shown in FIG. 7E, a P layer 157 is formed in the trench 155, and a P-type body diffusion layer 158 (third semiconductor layer) composed of the P layers 153, 156, and 157 is formed. Thereafter, a trench gate insulating film 159 is formed in the trench 154. The trench gate insulating film 159 is formed so that the thickness of the trench gate insulating film 159 a on the bottom surface of the trench 154 is larger than the thickness of the trench gate insulating film 159 b on the side surface of the trench 154. Here, the trench gate insulating film 159a on the bottom surface of the trench 154 is formed so that the position of the interface 150d that is the top surface of the trench gate insulating film 159a on the bottom surface of the trench 154 is deeper than the interface 150b.

  Next, as shown in FIG. 7F, a trench gate electrode 160 is formed in the trench 155 in which the trench gate insulating film 159 is formed. Further, on the surface of the P-type body diffusion layer 158, A source electrode 162 is formed in contact with the N + source layer 161, and a drain electrode is formed on the surface of a drain layer (not shown). Thus, the semiconductor device is manufactured by the method for manufacturing the semiconductor device in the present embodiment.

  In the method for manufacturing a semiconductor device in the present embodiment, a semiconductor device such as a trench gate type MOSFET having a structure in which the trench gate insulating film is not destroyed by an electric field can be manufactured without increasing the on-resistance. Further, in this embodiment, it is not necessary to perform alignment when forming the trench 154, so that a semiconductor device with higher uniformity can be manufactured.

  The contents of the film forming method other than the above are the same as those in the second embodiment.

[Fifth Embodiment]
Next, a fifth embodiment will be described. The present embodiment is a method of manufacturing a semiconductor device different from the second and fourth embodiments.

  A method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIG.

  First, as shown in FIG. 8A, an SiC N layer 171 is formed on an SiC substrate on which an N-type drain layer (not shown) is formed, and an SiC P layer is formed on the N layer 171. 172 is formed by epitaxial growth. The N layer 171 becomes a first region (first semiconductor layer) of the N − type drift layer, and the P layer 172 becomes a P type body diffusion layer (third semiconductor layer). It is. Further, nitrogen is doped as an impurity element in order to form the N layer 171, and Al is doped as an impurity element in order to form the P layer 172.

  Next, as shown in FIG. 8B, a trench 173 is formed. Specifically, an N + source layer 178 is formed on the surface of the P layer 172, and then a mask (not shown) having an opening is formed in a region where the trench 173 is formed, and the N + source layer 178 and By removing the P layer 172 by dry etching such as RIE, a trench 173 is formed in the P layer 172. The N + source layer 178 can be formed either before or after the trench 173 is formed, and is formed on both sides of the opening of the trench 173. The trench 173 is formed such that the interface 170 c that is the lowermost end of the trench 173 is shallower than the interface 170 a between the N layer 171 and the P layer 172.

  Next, as shown in FIG. 8C, an oxide film 174 is formed. The oxide film 174 is formed with a substantially uniform film thickness inside the trench 173 by a method such as TEOS oxide film, thermal oxidation, or CVD.

  Next, as shown in FIG. 8D, an impurity element is ion-implanted into the region where the trench 173 is formed. Specifically, a mask (not shown) is formed in a region other than the region where the trench 173 is formed, and nitrogen ion implantation is performed as an impurity element. Since the bottom surface of the trench 173 is formed in a curved shape as shown in the figure, the implanted nitrogen is implanted so as to spread from the bottom surface of the trench 173 to form an N layer 175. The N layer 175 thus formed serves as the second region (second semiconductor layer) of the N − type drift layer. Since the oxide film 174 is formed on the side surface of the trench 173, the nitrogen ion-implanted does not spread to the P layer 172 from the side surface of the trench 173.

  Next, as shown in FIG. 8E, after removing the oxide film 174, a trench gate oxide film 176 is formed on the side and bottom surfaces of the trench 173. The formed trench gate oxide film 176 includes a trench gate oxide film 176a formed on the bottom surface of the trench 173, and a trench gate oxide film 176b formed on the side surface of the trench 173 thinner than the trench gate oxide film 176a. . The position of the interface 170d which is the upper part of the trench gate oxide film 176a formed on the bottom surface of the trench 173 is formed to be deeper than the shallowest position in the interface 170b between the N layer 175 and the P layer 172.

  Next, as shown in FIG. 8F, a trench gate electrode 177 is formed in the trench 173 in which the trench gate insulating film 176 is formed. Further, an N + source is formed on the surface of the P-type body diffusion layer 115. A source electrode 179 is formed in contact with the layer 178, and a drain electrode is formed on the surface of a drain layer (not shown). Thus, the semiconductor device is manufactured by the method for manufacturing the semiconductor device in the present embodiment.

  By the method for manufacturing a semiconductor device in this embodiment, a semiconductor device such as a trench gate type MOSFET having a structure in which the trench gate insulating film is not destroyed by an electric field can be manufactured without increasing the on-resistance.

  The contents of the film forming method other than the above are the same as those in the second embodiment.

  In the second to fifth embodiments, the semiconductor material using SiC is described. However, even when Si is used as the semiconductor material, a semiconductor device capable of obtaining the same effect is manufactured. be able to. Further, although the case where Al is used as the impurity element for forming the P-type is described, B (boron) may be used.

  As mentioned above, although the form which concerns on implementation of this invention was demonstrated, the said content does not limit the content of invention.

10a interface 10b interface 10c interface 10d interface 11 N-type drain layer (fifth semiconductor layer)
12 N− type drift layer 12a First region (first semiconductor layer)
12b Second region (second semiconductor layer)
13 P-type body diffusion layer (third semiconductor layer)
14 Trench gate insulating film 14a Trench gate insulating film (bottom surface of trench)
14b Trench gate insulating film (side surface of trench)
15 Trench gate electrode 16 Drain electrode 17 N + type source layer (fourth semiconductor layer)
18 Source electrode

Claims (2)

A second conductivity type semiconductor layer is formed on the first conductivity type first semiconductor layer formed on the semiconductor substrate. In the second conductivity type semiconductor layer, a first region is formed in a predetermined region. Forming a region other than the predetermined region by forming a region of the first conductivity type, and forming a region of the first conductivity type as the second semiconductor layer.
The second conductivity type semiconductor film is formed on the second semiconductor layer and the region of the second conductivity type, and the region of the second conductivity type and the semiconductor of the second conductivity type are formed. Forming a third semiconductor layer comprising a film;
A trench having a bottom surface is formed in the second semiconductor layer from the side where the third semiconductor layer is formed, and a fourth semiconductor layer of the first conductivity type is formed on both sides of the opening of the trench. Forming, and
Forming a gate insulating film on a side surface and a bottom surface in the trench;
Forming a gate electrode in the trench through the gate insulating film;
And the gate insulating film is formed with a film thickness on the bottom surface of the trench larger than a film thickness on the side surface of the trench,
The position of the interface in the depth direction between the gate insulating film and the gate electrode is formed at a position deeper than the interface in the depth direction between the second semiconductor layer and the third semiconductor layer,
The position of the interface between the second semiconductor layer and the gate insulating film in the depth direction is formed at a position shallower than the interface between the first semiconductor layer and the third semiconductor layer. A method for manufacturing a semiconductor device. Forming a first semiconductor layer of the first conductivity type on the first semiconductor layer of the first conductivity type formed on the semiconductor substrate;
Forming a third semiconductor layer of a second conductivity type on the second semiconductor layer;
A first trench having a bottom surface in the second semiconductor layer is formed from the side on which the third semiconductor layer is formed, and the first conductivity type second is formed on both sides of the opening of the first trench. 4 forming a semiconductor layer;
Forming a second trench having a bottom surface in the third semiconductor layer in a portion different from the first trench from the side on which the third semiconductor layer is formed;
A second conductivity type semiconductor region is formed in a region of the second semiconductor layer corresponding to a region of the bottom surface portion of the second trench, and the second trench is formed of a second conductivity type semiconductor material. Forming a layer included in the third semiconductor layer by embedding;
Forming a gate insulating film on a side surface and a bottom surface in the first trench;
Forming a gate electrode in the first trench through the gate insulating film;
The gate insulating film is formed so that the film thickness on the bottom surface of the first trench is thicker than the film thickness on the side surface of the first trench,
The position of the interface in the depth direction between the gate insulating film and the gate electrode is formed at a position deeper than the interface in the depth direction of the second semiconductor layer and the third semiconductor layer,
The position of the interface in the depth direction between the second semiconductor layer and the gate insulating film is formed at a position shallower than the interface between the first semiconductor layer and the semiconductor region. Device manufacturing method.

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