JP2017028244A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which further improves an IE effect.SOLUTION: A semiconductor device comprises: a first conductivity type semiconductor substrate; a body part 31 which is formed on a surface of the semiconductor substrate and extends in a predetermined extension direction; and a dummy trench part 30 including one and more branch parts 32 which extend from the body part in a direction different from the extension direction. The semiconductor substrate has a first conductivity type emitter region 12 and a second conductivity type base region 14 which are sequentially provided from a surface of the semiconductor substrate. The dummy trench part 30 has a dummy trench which pierces the emitter region 12 and the base region 14 from the surface of the semiconductor substrate and a dummy insulation part provided in the dummy trench.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

Conventionally, a configuration in which a trench gate is formed on a substrate surface in a semiconductor element is known (see, for example, Patent Document 1). In addition, a configuration is known in which a part of trench gates is connected to an emitter potential or the like to form a dummy gate. By providing the dummy gate, a carrier injection promoting effect (IE effect) is generated.
[Prior art documents]
[Patent Literature]
Japanese Patent Application Laid-Open No. 2002-353456

  From the viewpoint of reducing the on-voltage of the semiconductor element, it is preferable to further enhance the IE effect.

  In one aspect of the present invention, a first conductivity type semiconductor substrate, a main body formed on the surface of the semiconductor substrate and extending in a predetermined extending direction, and a direction different from the extending direction from the main body. And a dummy trench portion including one or more branch portions extending in the direction of the semiconductor substrate, the semiconductor substrate having a first conductivity type emitter region provided in order as viewed from the surface of the semiconductor substrate, and a second conductivity type The dummy trench portion provides a semiconductor device having a dummy trench penetrating the emitter region and the base region from the surface of the semiconductor substrate, and a dummy insulating portion provided in the dummy trench.

  The summary of the invention does not enumerate all the features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a plan view showing an example of a semiconductor device 100. FIG. It is a figure which shows an example of the aa 'cross section in FIG. It is a figure which shows an example of the bb 'cross section in FIG. 6 is a plan view illustrating another example of the semiconductor device 100. FIG. 6 is a plan view illustrating another example of the semiconductor device 100. FIG. 6 is a plan view showing another example of a dummy trench portion 30. FIG. FIG. 6 is a diagram showing another example of a cross section taken along the line aa ′ of the semiconductor substrate 10. FIG. 6 is a diagram showing another example of a cross section taken along the line aa ′ of the semiconductor substrate 10. FIG. 6 is a diagram showing another example of a bb ′ cross section of the semiconductor substrate 10. 6 is a plan view illustrating another example of the semiconductor device 100. FIG. 3 is a diagram showing a cross section of the semiconductor device 100 taken along the line ee ′. FIG. It is a figure which shows the structure of the semiconductor device 200 which concerns on a comparative example. The cc 'cross section in FIG. 12 is shown. The dd 'cross section in FIG. 12 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a plan view showing an example of the semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip having a transistor portion 70 including a transistor such as an IGBT (Insulated Gate Bipolar Transistor) and a diode portion 80 including a diode such as a FWD (Free Wheel Diode). In FIG. 1, the chip surface around the chip end is shown, and other regions are omitted.

  1 shows the active region of the semiconductor substrate in the semiconductor device 100, the semiconductor device 100 may have a breakdown voltage structure portion surrounding the active region. The active region refers to a region where current flows when the semiconductor device 100 is controlled to be in an on state. The voltage withstanding structure part alleviates electric field concentration on the surface side of the semiconductor substrate. The pressure | voltage resistant structure part has a structure which combined the guard ring, the field plate, RESURF, and these, for example.

  The semiconductor device 100 of this example includes a gate electrode 50, an emitter electrode 52, a gate trench portion 40, a dummy trench portion 30, an emitter trench portion 60, a well region 17, an emitter region 12, a base region 14, and contacts on the surface side of the chip. The region 15 has a contact hole 54 and a contact hole 55. The emitter electrode 52 is an example of a first surface side electrode, and the gate electrode 50 is an example of a second surface side electrode.

  The gate trench portion 40, the dummy trench portion 30, the emitter trench portion 60, the well region 17, the emitter region 12, the base region 14, and the contact region 15 are formed inside the semiconductor substrate, and the emitter electrode 52 and the gate electrode 50. Is provided above the surface of the semiconductor substrate.

  An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 50 and the surface of the semiconductor substrate, but is omitted in FIG. Contact hole 54 and contact hole 55 are formed through the interlayer insulating film. The emitter electrode 52 is in contact with the semiconductor substrate through the contact hole 54. The gate electrode 50 is in contact with the semiconductor substrate through the contact hole 55.

  The emitter electrode 52 and the gate electrode 50 are formed of a material containing metal. For example, at least a partial region of each electrode is formed of aluminum. Each electrode may have a region formed of a material containing tungsten.

  The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals in a region of the transistor portion 70 along a predetermined arrangement direction. The dummy trench portion 30 is not electrically connected to the gate electrode 50. By providing the dummy trench portion 30 that is not connected to the gate electrode 50, the IE effect can be generated.

  The gate trench portion 40 is connected to the gate electrode 50 through the contact hole 55. The gate trench portion 40 controls whether or not to form a current channel in a base region formed on the back side of the emitter region 12 in the semiconductor substrate.

  The gate trench portion 40 has a facing portion 41 and a protruding portion 43. The facing portion 41 is formed by extending in a predetermined extending direction within a range facing the dummy trench portion 30. The protruding portion 43 is further extended from the facing portion 41 and is formed in a range not facing the dummy trench portion 30. In this example, two opposing portions 41 provided on both sides of the dummy trench portion 30 are connected by one protruding portion 43. At least a part of the protrusion 43 may have a curved shape.

  A contact hole 55 is formed in the insulating layer covering the protrusion 43. The contact hole 55 may be formed corresponding to a region of the protrusion 43 that is farthest from the facing portion 41. The protruding portion 43 of this example has a portion extending in a direction orthogonal to the facing portion 41 in a region farthest from the facing portion 41. The contact hole 55 may be formed corresponding to the portion of the protrusion 43.

  The dummy trench portion 30 includes a main body portion 31 formed by extending in a predetermined extending direction on the surface of the semiconductor substrate, and a branch extending from the main body portion 31 in a direction different from the extending direction of the main body portion 31. Part 32. The main body 31 in this example has a linear shape, and is formed by extending in a direction perpendicular to the arrangement direction of the trenches described above. The plurality of branch portions 32 may be provided in parallel to each other. The main body portion 31 of this example is provided to face the facing portion 41 of the gate trench portion 40 and extends in the same extending direction as the facing portion 41 of the gate trench portion 40. One or more main body portions 31 are provided between the two facing portions 41.

  One or more branch parts 32 are provided for one main body part 31. The branch part 32 in this example has a linear shape, and extends in a direction orthogonal to the extending direction of the main body part 31. The branch portion 32 may extend in a direction from the main body portion 31 toward the facing portion 41 of the gate trench portion 40. The branch part 32 may be provided on both sides of the main body part 31. In this example, two branch portions 32 are provided on both sides of the main body portion 31 from the same portion in the extending direction of the main body portion 31. In another example, the branch part 32 on one side of the main body part 31 and the branch part 32 on the other side may be provided in different portions in the extending direction of the main body part 31. The branch portions 32 on one side of the main body portion 31 and the branch portions 32 on the other side may be alternately provided in the extending direction of the main body portion 31.

  The branch portion 32 of this example is provided inside the contact region 15 on the surface of the semiconductor substrate. The entire branch portion 32 may be provided so as not to protrude from the contact region 15 on the surface of the semiconductor substrate. At least a part of the branch portions 32 may not be in contact with the gate trench portion 40. Further, at least some of the branch portions 32 may be in contact with the gate trench portion 40. When the branch portion 32 is provided in the emitter region 12 on the surface of the semiconductor substrate, the branch portion 32 is preferably not in contact with the gate trench portion 40. Thereby, a region functioning as a channel can be left between the branch portion 32 and the gate trench portion 40.

  Thus, since the dummy trench part 30 has the branch part 32, the area which the dummy trench part 30 occupies in the surface of a semiconductor substrate can be increased. Thereby, the IE effect can be enhanced. Further, the branch portion 32 branches off from the main body portion 31, whereby the shape of the dummy trench portion 30 can be complicated. Thereby, compared with the case where the linear dummy trench part of the same area is provided, IE effect can be heightened further. For example, the region in contact with the dummy trench portion 30 can efficiently suppress the passage of holes. By providing the branch portion 32, the total length of the end sides of the dummy trench portion 30 on the surface of the semiconductor substrate can be increased, and the passage of holes can be efficiently suppressed. In addition, in the dummy trench portion 30 of this example, a plurality of corners surrounding two sides of the branch portion 32 and the main body portion 31 are formed at the connection portion between the branch portion 32 and the main body portion 31. Such a corner-shaped region can efficiently suppress the passage of holes. For this reason, the dummy trench part 30 of this example can raise the IE effect efficiently.

  Each branch part 32 may have the same width. The width of the branch part 32 refers to the length of the branch part 32 in a direction perpendicular to the extending direction of the branch part 32. In another example, the branch part 32 may have a different width in the extending direction. For example, the width of the branch portion 32 may decrease stepwise as the distance from the main body portion 31 increases. Since the branch part 32 has a step shape, the length of the end side of the above-described dummy trench part 30 and the number of corners can be increased.

  The emitter trench part 60 is provided in the region of the diode part 80. The emitter trench portion 60 may have the same shape as the gate trench portion 40 on the surface of the semiconductor substrate. However, the length of the emitter trench portion 60 in the extending direction may be shorter than that of the gate trench portion 40. The length of the emitter trench portion 60 in this example is the same as that of the dummy trench portion 30.

  The emitter trench part 60 has a main body part 61 and a branch part 62. On the surface of the semiconductor substrate, the shape of the main body portion 61 may be the same as that of the gate trench portion 40. That is, the main body 61 may include a plurality of linear extending portions and a connecting portion that connects two adjacent extending portions. The connecting portion may have a curved portion like the protruding portion 43.

  The branch 62 may have the same arrangement and shape as the branch 32. One or more branch parts 62 are provided for one main body part 61. The branch part 62 in this example has a linear shape, and extends in a direction orthogonal to the extending direction of the main body part 61. The branch part 62 may connect two extending parts in the main body part 61. The branch part 62 in this example is not connected to the gate trench part 40.

  The gate electrode 50 is formed so as to cover a part of the protrusion 43. The gate electrode 50 is formed so as to cover a portion where the contact hole 55 is provided in the protruding portion 43. The gate electrode 50 in this example is not formed above the facing portion 41, the dummy trench portion 30, and the emitter trench portion 60.

  The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the emitter trench portion 60, the well region 17, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 of this example is formed so as to cover a part of the well region 17 and the gate trench portion 40.

  The well region 17 is formed in a predetermined range from the end of the semiconductor substrate on the side where the gate electrode 50 is provided. A part of the dummy trench portion 30, the emitter trench portion 60, and the facing portion 41 on the gate electrode 50 side is formed in the well region 17. The entire protrusion 43 may be formed in the well region 17. The semiconductor substrate has a first conductivity type, and the well region 17 has a second conductivity type different from that of the semiconductor substrate. The semiconductor substrate of this example is N− type, and the well region 17 is P + type. In this example, the first conductivity type will be described as N-type, and the second conductivity type will be described as P-type. However, the first and second conductivity types may be opposite conductivity types.

  The base region 14 is formed in at least a part of the region sandwiched between the facing portion 41 of the gate trench portion 40, the main body portion 31 of the dummy trench portion 30, and the extending portion of the emitter trench portion 60. The base region 14 is a second conductivity type having a lower impurity concentration than the well region 17. The base region 14 in this example is P-type.

  A contact region 15 of the second conductivity type having a higher impurity concentration than the base region 14 is formed on the surface of the base region 14. The contact region 15 in this example is P + type. In the transistor portion 70, the first conductivity type emitter region 12 having an impurity concentration higher than that of the semiconductor substrate is selectively formed on a part of the surface of the contact region 15. The emitter region 12 of this example is N + type.

  Each of the contact region 15 and the emitter region 12 includes an opposing portion 41 of the gate trench portion 40, a main body portion 31 of the dummy trench portion 30, and an extending portion of the emitter trench portion 60, from one adjacent trench portion to the other To the trench portion. The one or more contact regions 15 and the one or more emitter regions 12 of the transistor portion 70 are formed so as to be alternately exposed along the extending direction of the trench portion in a region sandwiched between the trench portions.

  In the transistor portion 70, the contact hole 54 is formed above each region of the contact region 15, the emitter region 12, and the dummy trench portion 30. In order to maximize the contact area between the emitter region 12 and the emitter electrode 52, the contact hole 54 is formed from one adjacent trench portion to the other trench portion. Further, the contact hole 54 may be formed so as to expose the entire range of the surface of the emitter region 12. Further, the contact hole 54 may be formed so as to expose the entire range of the surface of the contact region 15. However, the contact hole 54 is not formed in a region corresponding to the base region 14 and the well region 17.

  Further, the contact hole 54 does not have to be formed above the gate trench portion 40 and may be formed. However, when the contact hole 54 is formed above the gate trench portion 40, an insulating portion that insulates the electrode in the trench from the emitter electrode 52 may be formed at the upper end in the trench of the gate trench portion 40.

  The contact hole 54 exposes the main body portion 31 of the dummy trench portion 30 in a range facing the emitter region 12 and the contact region 15. The contact hole 54 also exposes the branch portion 32 extending from the main body portion 31. As will be described later, the emitter region 12 may be exposed on the inner wall of the trench in the dummy trench portion 30. The emitter electrode 52 may be formed through the contact hole 54 and into the trench of the dummy trench portion 30.

  Thereby, the emitter electrode 52 can contact not only the surface of the emitter region 12 exposed on the surface of the semiconductor substrate but also the side surface of the emitter region 12 exposed on the trench inner wall of the dummy trench portion 30. Contact resistance can be reduced. For this reason, the on-voltage of the semiconductor device 100 can be reduced.

  In the diode portion 80, the contact hole 54 is formed above each of the contact region 15, the base region 14, and the emitter trench portion 60. The contact hole 54 in this example is not formed in the base region 14 closest to the gate electrode 50 among the plurality of base regions 14. In this example, the contact hole 54 of the transistor part 70 and the contact hole 54 of the diode part 80 have the same length in the extending direction of each trench part.

  In the diode portion 80, the contact hole 54 is formed from one extending portion adjacent to the diode portion 80 to the other extending portion in order to maximize the contact area between the contact region 15 and the base region 14 and the emitter electrode 52. The However, the contact hole 54 is not formed in a region corresponding to the base region 14 and the well region 17.

  The contact hole 54 is formed so as to expose the emitter trench portion 60. Similarly to the dummy trench part 30, the base region 14 may be exposed on the inner wall of the emitter trench part 60. The emitter electrode 52 is formed through the contact hole 54 and into the trench of the emitter trench portion 60.

  Thereby, the emitter electrode 52 can contact not only the surface of the base region 14 exposed on the surface of the semiconductor substrate but also the side surface of the base region 14 exposed on the inner wall of the emitter trench portion 60. Therefore, the contact resistance with the base region 14 can be reduced.

  FIG. 2 is a diagram illustrating an example of the aa ′ cross section in FIG. 1. The semiconductor device 100 of this example includes the semiconductor substrate 10, the emitter electrode 52, and the collector electrode 24 in the cross section. The emitter electrode 52 is formed on the surface of the semiconductor substrate 10. The emitter electrode 52 is electrically connected to the emitter terminal 53.

  The collector electrode 24 is formed on the back surface of the semiconductor substrate 10. The collector electrode 24 is electrically connected to the collector terminal. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal. Further, in this specification, the surface on the emitter electrode 52 side of each member such as a substrate, a layer, and a region is referred to as a front surface, and the surface on the collector electrode 24 side is referred to as a back surface or bottom. A direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.

  The semiconductor substrate 10 may be a silicon substrate, and may be a silicon carbide substrate, a nitride semiconductor substrate, or the like. On the surface side of the semiconductor substrate 10, a P− type base region 14 is formed. Further, the N + type emitter region 12 is selectively formed in a partial region on the surface side of the base region 14.

  The semiconductor substrate 10 further includes an N + type accumulation region 16, an N− type drift region 18, an N− type buffer region 20, a P + type collector region 22, and an N + type cathode region 82. The accumulation region 16 is formed on the back side of the base region 14. The impurity concentration of the accumulation region 16 is higher than the impurity concentration of the drift region 18.

  The accumulation region 16 is formed between adjacent trenches. For example, in the transistor portion 70, the accumulation region 16 is formed between the main body portion 31 of the dummy trench portion 30 and the gate trench portion 40. The accumulation region 16 may be provided so as to cover the entire region between the main body portion 31 and the gate trench portion 40. By providing the storage region 16, the IE effect can be enhanced and the on-voltage can be reduced.

  The drift region 18 is formed on the back side of the accumulation region 16. The buffer region 20 is formed on the back side of the drift region 18. The impurity concentration of the buffer region 20 is higher than the impurity concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the back side of the base region 14 from reaching the collector region 22 and the cathode region 82.

  The collector region 22 is formed on the back side of the buffer region 20 in the transistor portion 70 region. The cathode region 82 is formed on the back side of the buffer region 20 in the region of the diode portion 80. A collector electrode 24 is provided on the back surfaces of the collector region 22 and the cathode region 82.

  On the surface side of the semiconductor substrate 10, one or more gate trench portions 40, one or more dummy trench portions 30 (the main body portion 31 is shown in FIG. 2), and one or more emitter trench portions 60 are formed. Each trench portion reaches the drift region 18 from the surface of the semiconductor substrate 10 through the base region 14. In this example, the gate trench portion 40 and the dummy trench portion 30 reach the drift region 18 from the surface of the semiconductor substrate 10 through the emitter region 12, the base region 14, and the accumulation region 16. Further, the emitter trench portion 60 penetrates the base region 14 and the accumulation region 16 from the surface of the semiconductor substrate 10 and reaches the drift region 18.

  The gate trench portion 40 includes a gate trench 46 formed on the surface side of the semiconductor substrate 10, an insulating film 42, a gate conductive portion 44, and a gate insulating portion 37. The gate trench 46 is formed from the surface of the semiconductor substrate 10 to the drift region 18 through the emitter region 12, the base region 14 and the accumulation region 16.

  The insulating film 42 is formed to cover the inner wall of the gate trench 46. The insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 46. The gate conductive portion 44 is formed inside the insulating film 42 inside the gate trench 46. That is, the insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

  The gate insulating portion 37 is formed above the gate conductive portion 44 and insulates the gate conductive portion 44 and the emitter electrode 52 from each other. The gate insulating portion 37 in this example is formed inside the gate trench 46. The gate insulating portion 37 includes, for example, silicon oxide, silicon nitride, or other insulating material. The thickness of the gate insulating portion 37 in the depth direction may be larger than the thickness of the insulating film 42 at the bottom of the gate trench 46.

  In this example, at least a part of the end surface of the gate insulating portion 37 on the semiconductor substrate 10 side is the same height as the surface of the semiconductor substrate 10. As an example, the entire end face of the gate insulating portion 37 may be formed on the same plane as the surface of the semiconductor substrate 10. Thereby, the unevenness | corrugation of the surface of the semiconductor substrate 10 can be reduced, and the structure laminated | stacked on the upper surface of the semiconductor substrate 10 can be formed easily.

  The gate conductive portion 44 includes at least a region facing the adjacent base region 14. Each of the gate conductive portions 44 is electrically connected to the gate terminal 51. In this example, the gate conductive portion 44 is electrically connected to the gate electrode 50 at the protruding portion 43 as shown in FIG. Further, the gate electrode 50 is electrically connected to the gate terminal 51. When a predetermined voltage is applied to the gate conductive portion 44 via the gate terminal 51, a channel is formed in the surface layer of the interface in contact with the gate trench 46 in the base region 14.

  The dummy trench portion 30 (the main body portion 31 in the example of FIG. 2) has a dummy trench 38 and a dummy insulating portion 39 formed on the surface side of the semiconductor substrate 10. In FIG. 2, the structure of the main body 31 is shown. The branch part 32 may also have the same structure as the main body part 31. The dummy trench 38 is formed so as to penetrate the emitter region 12, the base region 14, and the accumulation region 16 from the surface of the semiconductor substrate 10.

  The dummy insulating portion 39 is provided inside the dummy trench 38. As shown in FIG. 2, the dummy insulating portion 39 may be filled from the bottom of the dummy trench 38 to a predetermined height in the dummy trench 38. In this case, the dummy trench 38 is not provided with a conductive material such as polysilicon. For this reason, the conductive material in the dummy trench 38 does not conduct with the base region 14 or the like of the semiconductor substrate 10. For this reason, the reliability of the semiconductor device 100 can be improved.

  The width of the dummy trench 38 may be smaller than the width of the gate trench 46. Thus, the dummy insulating portion 39 can be filled in the dummy trench 38 in the process of forming the insulating film 42 in the gate trench 46. Note that the insulating film 42 and the dummy insulating portion 39 may be formed by different processes. Further, the width of the dummy trench 38 may be the same as the width of the gate trench 46.

  The dummy trench 38 may be formed shallower than the gate trench 46. In this case, the dummy trench 38 having a small width and the gate trench 46 having a large width can be formed by the same etching process. The dummy trench 38 and the gate trench 46 may be formed by different etching processes. Further, the dummy trench 38 may be formed to the same depth as the gate trench 46.

  The dummy insulating portion 39 may be filled in the entire dummy trench 38 or may be filled in a part of the dummy trench 38. The dummy insulating portion 39 may be filled in the dummy trench 38 so that at least a part of the emitter region 12 is exposed on the side wall of the dummy trench 38. The upper end of the dummy insulating portion 39 may be provided in the middle of the emitter region 12 in the depth direction.

  As described above, the emitter electrode 52 is formed above the surface of the semiconductor substrate 10 and is in contact with the surface of the emitter region 12. The emitter electrode 52 of this example is also formed in a region in the dummy trench 38 where the dummy insulating portion 39 is not provided. As a result, the emitter electrode 52 can be in contact with the surface of the emitter region 12 and can also be in contact with the emitter region 12 on the side wall of the dummy trench 38. Thereby, the contact resistance between the emitter electrode 52 and the emitter region 12 can be lowered.

  In addition, the structure of the dummy trench part 30 is not limited to the example of FIG. Similar to the gate trench portion 40, the dummy trench portion 30 may have an insulating film that covers the inner wall of the dummy trench 38 and a conductive material such as polysilicon surrounded by the insulating film. In this case, the reliability of the insulating film must be ensured. However, since the dummy trench portion 30 and the gate trench portion 40 have the same structure, a part of the dummy trench portion 30 and the gate trench portion 40 is formed by the same process. Can be formed.

  The emitter electrode 52 may have a plug portion 36 disposed in the dummy trench 38. Plug portion 36 is in contact with emitter region 12 exposed on the side wall of dummy trench 38. Plug portion 36 may be formed of the same material as the region of emitter electrode 52 formed above the surface of semiconductor substrate 10, or may be formed of a different material.

  As an example, the plug portion 36 is formed of a material containing tungsten, and the emitter electrode 52 other than the plug portion 36 is formed of a material not containing tungsten. By forming the plug portion 36 from a material containing tungsten, the plug portion 36 can be easily formed inside the fine dummy trench.

  In the present example, the gate trench portions 40 and the main body portions 31 of the dummy trench portions 30 are alternately arranged in a predetermined arrangement direction as shown in FIG. Moreover, each trench part may be arrange | positioned at a fixed space | interval. However, the arrangement of the trenches is not limited to the above example. A plurality of gate trench portions 40 may be disposed between the two main body portions 31. The number of gate trench portions 40 provided between the main body portions 31 may not be constant.

  The diode unit 80 is provided in a region adjacent to the transistor unit 70. The diode unit 80 includes a base region 14, a storage region 16, a drift region 18, and a buffer region 20 that are the same layer as the transistor unit 70. A cathode region 82 is provided on the back side of the buffer region 20 of the diode unit 80. The diode unit 80 includes one or more emitter trench units 60. Further, the emitter region 12 is not formed in the diode portion 80.

  The emitter trench portion 60 is formed to reach the drift region 18 from the surface side of the base region 14 through the base region 14 and the accumulation region 16. Each emitter trench portion 60 has an emitter trench 68 and an emitter insulating portion 69, similar to the dummy trench portion 30. The emitter trench part 60 may have the same structure as the main body part 31 of the dummy trench part 30.

  The base region 14 may be exposed on the side wall of the emitter trench 68. The emitter electrode 52 may have a plug portion disposed inside the emitter trench 68. The plug portion contacts the base region 14 exposed on the side wall of the emitter trench 68. With such a configuration, the contact resistance between the emitter electrode 52 and the base region 14 can be reduced.

  In this example, the interval between the trench portions in the transistor portion 70 in the cross section and the interval between the emitter trench portions 60 in the diode portion 80 are the same. As shown in FIG. 2, when the gate trench portions 40 and the main body portions 31 are alternately arranged in the transistor portion 70, the distance between the gate trench portions 40 and the main body portion 31, the distance between the emitter trench portions 60, and May be the same. The length of the plug portion disposed in the emitter trench 68 may be the same as the length of the plug portion 36 disposed in the dummy trench 38.

  FIG. 3 is a diagram illustrating an example of a bb ′ cross section in FIG. 1. In FIG. 3, the storage area 16 is omitted. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 26, the emitter electrode 52, and the collector electrode 24 in the cross section. The semiconductor substrate 10 has the branch part 32 of the dummy trench part 30 in the cross section. The structure and size of the branch part 32 may be the same as the main body part 31 shown in FIG.

  The branch portion 32 in this example is formed so as to penetrate the contact region 15 and the base region 14. In the example of FIG. 3, the branch portion 32 is provided in one contact region 15, but a plurality of branch portions 32 may be provided in one contact region 15. Further, a branch portion 32 penetrating the emitter region 12 and the base region 14 may be provided.

  The interlayer insulating film 26 is formed between the gate electrode 50 and the emitter electrode 52 and the semiconductor substrate 10. Contact holes 54 and 55 are formed in the interlayer insulating film 26.

  The contact hole 54 exposes at least a part of the dummy trench portion 30 (the branch portion 32 in FIG. 3), the emitter region 12, and the contact region 15 on the surface of the semiconductor substrate 10. The emitter electrode 52 passes through the contact hole 54 and contacts the dummy trench portion 30, the emitter region 12, and the contact region 15.

  The emitter electrode 52 may be in contact with the contact region 15 in the dummy trench of the branch portion 32. The emitter electrode 52 of this example has a plug portion 36 disposed in the dummy trench of the branch portion 32. The plug portion 36 inserted into the branch portion 32 and the main body portion 31 may be integrally formed.

  The contact hole 55 exposes at least a part of the protruding portion 43 of the gate trench portion 40 on the surface of the semiconductor substrate 10. A through hole is formed in the gate insulating portion 37 of the gate trench portion 40 exposed by the contact hole 55. The gate electrode 50 is in contact with the gate conductive portion 44 through the contact hole 55 and the through hole of the gate insulating portion 37. The gate electrode 50 has a plug portion 56 that passes through the through hole of the gate insulating portion 37. The plug portion 56 may be formed of the same material as the plug portion 36 shown in FIG.

  Next, an example of a method for manufacturing the semiconductor device 100 shown in FIGS. 1 to 3 will be described. However, the manufacturing method of the semiconductor device 100 is not limited to this example. First, a semiconductor substrate 10 having the same conductivity type as that of the drift region 18 (which will be described as N-type in this example) is prepared.

  Next, an etching mask having a predetermined pattern is provided on the surface of the semiconductor substrate 10 to form a plurality of trenches for the gate trench portion 40, the dummy trench portion 30 and the emitter trench portion 60. After forming the trench, an insulating film is formed on the inner wall of the gate trench. In addition, an insulating portion is filled in the dummy trench and the emitter trench. The insulating film of the gate trench and the insulating part of the dummy trench emitter trench may be formed in the same process. After forming an insulating film in the gate trench, the gate trench is filled with a conductive material.

Next, P-type impurities are implanted from the surface side of the semiconductor substrate, and heat treatment is performed at a temperature of about 1100 degrees C. for about 2 hours to form a P-type base region 14 shallower than the trench over the entire surface of the semiconductor substrate 10 To do. Next, N-type impurities are implanted from the surface side of the semiconductor substrate 10 to form an N-type accumulation region 16 deeper than the base region 14 and shallower than the trench. For example, the N-type accumulation region 16 is formed by ion implantation of phosphorus at an acceleration voltage of 2.8 MeV and about 5.0 × 10 ¹² / cm ² .

  Next, N-type impurities are selectively implanted from the surface side of the semiconductor substrate 10 using a mask having an opening corresponding to the emitter region 12. Thereby, the N + type emitter region 12 is selectively formed inside the P type base region 14.

  Thereafter, an interlayer insulating film 26 is formed on the surface side of the semiconductor substrate 10. The interlayer insulating film 26 is also formed above the conductive portion in the gate trench. The interlayer insulating film 26 formed in the gate trench functions as the gate insulating portion 37. Here, the insulating part formed in the upper part of the dummy trench and the emitter trench may be removed to expose the side surface of the emitter region 12 in the trench.

  In addition, a through hole is formed in the gate insulating portion 37 at the protruding portion 43 of the gate trench portion 40. Further, a contact hole 54 and a contact hole 55 are formed in the interlayer insulating film 26. Then, the emitter electrode 52 and the gate electrode 50 are formed. Each electrode may be formed on the surface of the semiconductor substrate 10 after the plug portion 36 and the plug portion 56 are formed.

Next, after selenium is ion-implanted from the back surface side of the semiconductor substrate 10 at about 1.0 × 10 ¹⁴ / cm ^2, for example, heat treatment is performed at a temperature of about 900 ° C. for about 2 hours. Thereby, an N + type buffer region 20 is formed on the back side of the semiconductor substrate 10. The remaining N− type region of the semiconductor substrate 10 becomes the drift region 18. By using selenium having a large diffusion coefficient, the buffer region 20 can be formed at a deep position. In addition, before the buffer region 20 is formed, the semiconductor substrate 10 may be polished to adjust the thickness.

  Instead of ion implantation of selenium, the N + type buffer region 20 may be formed by ion implantation of protons at different doses a plurality of times. Thereby, the buffer region 20 in which the impurity concentration increases from the substrate front side toward the substrate back side can be formed.

Next, P-type impurities are ion-implanted from the back surface side of the semiconductor substrate 10 at a dose of, for example, 1.0 × 10 ¹³ / cm ² or more and 4.0 × 10 ¹³ / cm ² or less. As a result, a P + type collector region 22 thinner than the buffer region 20 is formed on the back surface side of the semiconductor substrate 10. When the dose amount of the P-type impurity is less than 1.0 × 10 ¹³ / cm ² , the collector region and the collector electrode cannot be ohmic-bonded, which is not preferable. In the diode portion 80, a cathode region 82 is formed. Then, a collector electrode 24 and the like are appropriately formed on the back side of the semiconductor substrate 10.

  FIG. 4 is a plan view illustrating another example of the semiconductor device 100. The semiconductor device 100 in this example is different from the example of FIG. 1 in that the branch part 32 is also provided inside the emitter region 12 on the surface of the semiconductor substrate. Other structures may be the same as those of the semiconductor device 100 shown in FIGS.

  In this example, the branch portion 32 is provided for each emitter region 12 and for each contact region 15. The branch portion 32 provided in the emitter region 12 and the branch portion 32 provided in the contact region 15 may be provided in parallel. The branch portion 32 provided in the emitter region 12 is not connected to the gate trench portion 40. That is, in the emitter region 12, a semiconductor region remains between the branch portion 32 and the gate trench portion 40. This region functions as a channel region. The branch portion 32 provided in the emitter region 12 and the branch portion 32 provided in the contact region 15 may have the same length.

  Thus, the IE effect can be enhanced by forming the branch portion 32. Further, since the branch portion 32 and the gate trench portion 40 are separated from each other in the emitter region 12, a channel region can be secured and the channel density can be maintained.

  FIG. 5 is a plan view showing another example of the semiconductor device 100. The semiconductor device 100 in this example is different from the semiconductor device 100 shown in FIGS. 1 to 4 in that the branch portion 32 provided in the contact region 15 on the surface of the semiconductor substrate is connected to the gate trench portion 40. To do. The other structure may be the same as any one of the semiconductor devices 100 shown in FIGS. Note that the branch portion 32 provided in the emitter region 12 is not connected to the gate trench portion 40.

  By forming the branch portion 32 in this way, the IE effect can be enhanced. Further, by connecting the branch portion 32 in the contact region 15 to the gate trench portion 40, the number of corner portions can be increased, and the IE effect can be further enhanced.

  The branch part 62 in the diode part 80 may be connected to the gate trench part 40 or may not be connected. Further, some branch parts 62 may be connected to the gate trench part 40. In the example of FIG. 5, the branch portion 32 provided in the contact region 15 and the branch portion 62 provided on the straight line are connected to the gate trench portion 40.

  When connecting the branch part 62 to the gate trench part 40, the gate trench part 40 and the dummy trench part 30 may be formed in different steps. For example, after forming the gate conductive portion 44 inside the gate trench portion 40, the dummy trench 38 connected to the gate trench 46 may be formed. After forming the dummy trench 38, the dummy insulating portion 39 is formed. The step of forming the dummy insulating portion 39 may be the same as the step of forming the interlayer insulating film 26.

  FIG. 6 is a plan view showing another example of the dummy trench portion 30. The dummy trench portion 30 of this example has a plurality of branch portions 32 inside one contact region 15 on the surface of the semiconductor substrate. The dummy trench portion 30 of this example may be applied to any of the semiconductor devices 100 shown in FIGS.

  The number of branch portions 32 provided in one contact region 15 may be larger than the number of branch portions 32 provided in one emitter region 12. One emitter region 12 may be provided with one branch portion 32, and one contact region 15 may be provided with a plurality of branch portions 32.

  Further, the width of the contact region 15 in the extending direction of the main body 31 may be larger than the width of the emitter region 12. Further, the interval P1 between the branch portions 32 in the extending direction of the main body portion 31 may be constant. The branch portion 32 may not be formed at the boundary between the contact region 15 and the emitter region 12, and may also be formed at the boundary between the contact region 15 and the emitter region 12.

  In each semiconductor device 100 shown in FIGS. 1 to 6, the length (D2-D1) of the branch portion 32 is equal to the distance D2 between the main body portion 31 and the gate trench portion 40 (ie, the gate trench 46). It may be half or more and may be 3/4 or more. The distance D1 between the branch portion 32 and the gate trench portion 40 may be constant, and may be different for each branch portion 32. The distance between the branch portion 32 provided in the emitter region 12 and the gate trench portion 40 may be larger than the distance between the branch portion 32 provided in the contact region 15 and the gate trench portion 40.

  Further, the interval P1 between the branch parts 32 may be smaller than the distance D2 between the main body part 31 and the gate trench part 40. The interval P1 may be less than or equal to half of the distance D2. By forming the branch portions 32 at a high density, the IE effect can be further enhanced.

  FIG. 7 is a diagram illustrating another example of the cross section along the line aa ′ of the semiconductor substrate 10. In FIG. 7, the vicinity of the surface of the semiconductor substrate 10 is shown, and other portions are omitted. The semiconductor device 100 of this example includes a plurality of main body portions 31 between two gate trench portions 40. The other structure may be the same as any one of the semiconductor devices 100 shown in FIGS. With such a configuration, the IE effect can be further enhanced.

  The plurality of main body portions 31 may be arranged at the same interval. The interval between the main body 31 and the gate trench 40 may be the same as the interval between the main bodies 31 or may be wider. By widening the distance between the main body 31 and the gate trench 40, the channel region can remain even if manufacturing variations occur.

  FIG. 8 is a view showing another example of the cross section taken along the line aa ′ of the semiconductor substrate 10. In FIG. 7, the vicinity of the surface of the semiconductor substrate 10 is shown, and other portions are omitted. The semiconductor device 100 of this example further includes a P + type floating region 90 separated from the base region 14 in a region adjacent to the bottom portion of the dummy trench portion 30 (in FIG. 8, the bottom portion of the dummy trench 38 in the main body portion 31). . The other structure may be the same as any one of the semiconductor devices 100 shown in FIGS.

  The floating region 90 is formed along the main body portion 31 and may not be formed in the branch portion 32. The width of the floating region 90 in the direction connecting the two gate trench portions 40 may be larger than the width of the main body portion 31. The width of the floating region 90 may be more than half of the distance between the two gate trench portions 40. The distance between the floating region 90 and the gate trench portion 40 may be larger than the distance between the branch portion 32 and the gate trench portion 40.

  Further, the bottom portion of the floating region 90 may be provided at a position deeper than the bottom portion of the gate trench portion 40 when viewed from the surface of the semiconductor substrate 10. The bottom portion of the main body portion 31 may be provided at a position shallower than the bottom portion of the gate trench portion 40. By providing the floating region 90, the IE effect can be further enhanced.

  Further, as shown in FIG. 7, when a plurality of main body portions 31 are provided between the two gate trench portions 40, the floating region 90 may be formed at the bottom of each main body portion 31. The floating regions 90 of the respective main body portions 31 may be separated from each other or may be connected.

  FIG. 9 is a diagram illustrating another example of the bb ′ cross section of the semiconductor substrate 10. The semiconductor device 100 of this example has branch portions 32 having different depths. The other structure may be the same as any one of the semiconductor devices 100 shown in FIGS.

  The dummy trench of the branch part 32-1 provided at the position closest to the well region 17 in the extending direction of the main body part 31 may be formed to a position deeper than the dummy trenches of the other branch part 32-2. For example, the dummy trench of the branch part 32-1 is formed to a position deeper than the bottom part of the well region 17.

  The width of the dummy trench in the branch portion 32-1 may be larger than the width of the dummy trench in the other branch portion 32-2. Thereby, the branch part 32 from which depth differs can be formed in the same process. Further, the branch part 32-1 may be connected to the gate trench part 40. Thereby, the well region 17 and the emitter region 12 of the active region can be separated by a deep dummy trench. The branch portion 32-1 is preferably filled with an insulating material.

  FIG. 10 is a plan view showing another example of the semiconductor device 100. The semiconductor device 100 in this example is different from the examples in FIGS. 1 to 9 in that the branch part 45 is also provided in the gate trench part 40 on the surface of the semiconductor substrate. The other structure may be the same as any one of the semiconductor devices 100 shown in FIGS.

  The branch part 45 of this example has the same structure as the other part of the gate trench part 40 and is formed with the same depth as the other part of the gate trench part 40. For example, the branch portion 45 includes a gate trench 46, an insulating film 42, a gate conductive portion 44, and a gate insulating portion 37. The branch portion 45 is provided extending from a predetermined portion of the gate trench portion 40 in a direction different from the extending direction of the dummy trench portion 30. As an example, the branch portion 45 is provided by extending from the gate trench portion 40 in a direction perpendicular to the extending direction. The branch portion 45 extends from the gate trench portion 40 in the direction toward the dummy trench portion 30. However, the branch portion 45 is formed in a range that does not contact the dummy trench portion 30.

  The branch part 32 of the dummy trench part 30 in this example is formed in the emitter region 12 in the plan view. Further, the branch portion 45 of the gate trench portion 40 is formed in the contact region 15 in the plan view. The branch portions 32 and the branch portions 45 may be provided alternately in the extending direction of the main body portion 31 of the dummy trench portion 30. With such a structure, the IE effect can be further enhanced.

  FIG. 11 is a diagram showing an ee ′ cross section of the semiconductor device 100. In FIG. 11, the storage area 16 is omitted. The semiconductor device 100 of this example is different from the example shown in FIG. 4 in that it further includes a branch portion 45, and the position of the branch portion 32 is different. The other structure is the same as the example shown in FIG. In FIG. 3, the storage area 16 is omitted.

  The branch portion 45 of the gate trench portion 40 is formed through the contact region 15 from the surface of the semiconductor substrate 10. The branch portion 45 further penetrates the base region 14. The branch portion 45 may further penetrate the accumulation region 16.

  The branch portion 32 of the dummy trench portion 30 is formed through the emitter region 12 from the surface of the semiconductor substrate 10. The branch portion 32 further penetrates the base region 14. The branch portion 32 may further penetrate the accumulation region 16. The branch part 32 may be formed shallower than the branch part 45. Further, the branch portion 32 and the branch portion 45 may be formed shallower than the well region 17.

  FIG. 12 is a diagram illustrating a configuration of a semiconductor device 200 according to the comparative example. The semiconductor device 200 includes a transistor portion 270 and a diode portion 280. Further, on the surface side of the semiconductor device 200, a gate electrode 250, an emitter electrode 252, a gate trench part 240, a dummy trench part 230, an emitter trench part 260, a well region 217, an emitter region 212, a base region 214, a contact region 215, a contact It has holes 226, 228, 249, 254 and polysilicon layers 221, 225, 248.

  The dummy trench part 230 is formed in a straight line and does not have a branch part. For this reason, it is relatively difficult to enhance the IE effect. On the other hand, in the semiconductor device 100, since the dummy trench portion 30 has the branch portion 32, the IE effect can be easily enhanced.

  FIG. 13 shows a cc ′ cross section in FIG. The semiconductor device 200 includes a semiconductor substrate 210, an emitter electrode 252, an insulating portion 238, and a collector electrode 224 in the cross section. Further, the gate terminal 251 is electrically connected to the gate conductive portion 244, and the emitter terminal 253 is electrically connected to the emitter electrode 252.

  In the semiconductor substrate 10, a gate trench portion 240, a dummy trench portion 230, an emitter trench portion 260, an emitter region 212, a base region 214, a storage region 216, a drift region 218, a buffer region 220, a collector region 222, and a cathode region 282 are formed. Is done. The gate trench portion 240 has an insulating film 242 and a gate conductive portion 244. The dummy trench part 230 has an insulating film 232 and a dummy conductive part 234. The emitter trench portion 260 has an insulating film 262 and an emitter conductive portion 264.

  Since the semiconductor device 200 is provided with the dummy conductive portion 234 in the dummy trench portion 230, the insulation reliability of the insulating film 232 is tested so that the dummy conductive portion 234 is not electrically connected to the semiconductor region of the semiconductor substrate 10. Is preferred. On the other hand, according to the semiconductor device 100 shown in FIG. 2, since the dummy conductive portion is not provided in the dummy trench portion 30, it is not necessary to test the insulation reliability of the dummy insulating portion 39.

  In the semiconductor device 200, the emitter region 212 is not exposed on the sidewall of the trench of the dummy trench portion 230. For this reason, the emitter electrode 252 and the emitter region 212 are in contact only on the surface of the semiconductor substrate 210. When the semiconductor device 200 is miniaturized, the area of the emitter region 212 exposed on the surface of the semiconductor substrate 210 is reduced, and the contact resistance between the emitter electrode 252 and the emitter region 212 is increased.

  In the semiconductor device 200, the insulating portion 238 is formed on the surface of the semiconductor substrate 210. In this case, in order to reliably insulate the gate conductive portion 244 and the emitter electrode 252, the insulating portion 238 is provided so as to cover a wider range than the gate trench portion 240. That is, the insulating part 238 covers a part of the surface of the emitter region 212. For this reason, the area of the emitter region 212 exposed on the surface of the semiconductor substrate 210 is further reduced. Therefore, in the semiconductor device 200, it is difficult to achieve both miniaturization of the semiconductor device and a low on-voltage.

  On the other hand, according to the semiconductor device 100 shown in FIG. 2, the emitter electrode 52 can come into contact with the surface and side surfaces of the emitter region 12. For this reason, even if the semiconductor device 100 is miniaturized, the contact resistance between the emitter electrode 52 and the emitter region 12 can be sufficiently reduced.

  Further, according to the semiconductor device 100 shown in FIG. 2, since the gate insulating part 37 is formed in the gate trench, the gate insulating part 37 does not cover the surface of the emitter region 12. Therefore, the contact area between the emitter electrode 52 and the emitter region 12 can be increased.

  FIG. 14 shows a dd ′ cross section in FIG. The semiconductor device 200 includes a semiconductor substrate 210, an emitter electrode 252, a gate electrode 250, a collector electrode 224, a polysilicon layer 221, a polysilicon layer 248, and an insulating portion 238 in the cross section.

  The polysilicon layer 221 and the polysilicon layer 248 are formed on the surface of the semiconductor substrate 210, and connect the conductive portion in each trench to the emitter electrode 252 or the gate electrode 250. The semiconductor device 200 selectively includes a polysilicon layer 221 and a polysilicon layer 248 on the surface of the semiconductor substrate 210. For this reason, unevenness is generated on the surface of the semiconductor substrate 210, and it is not easy to form a layer formed above the surface of the semiconductor substrate 210 such as the insulating portion 238.

  On the other hand, according to the semiconductor device 100 shown in FIGS. 2 and 3, since the emitter electrode 252 and the gate electrode 250 are in direct contact with the conductive portion in each trench, the polysilicon layer is formed on the surface of the semiconductor substrate 10. It is not necessary to provide it. For this reason, unevenness on the surface of the semiconductor substrate 10 can be reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  Note that “upper” and “upper”, “lower” and “lower” in the claims or the specification indicate directions opposite to each other. However, the terms “upper” and “upper” are not limited to the direction opposite to the direction of gravity. Further, the terms “lower” and “lower” are not limited to the direction of gravity. For example, in a semiconductor device mounted on an electrical device, it is clear that the semiconductor device can be included in the present invention even when the gate electrode or the like is disposed on the ground-side surface of the semiconductor substrate. is there.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 16 ... Storage region, 17 ... Well region, 18 ... Drift region, 20 ... Buffer region, 22 ... Collector region, 24 ... Collector electrode, 26 ... Interlayer insulating film, 30 ... Dummy trench part, 31 ... Body part, 32 ... Branch part, 36 ... Plug part, 37 ... Gate insulation part, 38 ... Dummy trench, 39 ... Dummy insulation part, 40 ... Gate trench part, 41 ... Counter part, 42 ... Insulation Membrane, 43 ... projecting portion, 44 ... gate conductive portion, 45 ... branch, 46 ... gate trench, 50 ... gate electrode, 51 ... gate terminal, 52 ... emitter Electrode 53 ... Emitter terminal 54 ... Contour 55 ... contact hole, 56 ... plug part, 60 ... emitter trench part, 61 ... main body part, 62 ... branch part, 68 ... emitter trench, 69 ... emitter Insulating part, 70 ... transistor part, 80 ... diode part, 82 ... cathode region, 90 ... floating region, 100 ... semiconductor device, 200 ... semiconductor device, 210 ... semiconductor Substrate, 212 ... emitter region, 214 ... base region, 215 ... contact region, 216 ... storage region, 217 ... well region, 218 ... drift region, 220 ... buffer region 221 ... polysilicon layer, 222 ... collector region, 224 ... collector electrode, 225 ... polysilicon layer, 226 ... contact hole 228 ... contact hole, 230 ... dummy trench part, 232 ... insulating film, 234 ... dummy conductive part, 238 ... insulating part, 240 ... gate trench part, 242 ... insulating Membrane, 244 ... Gate conductive portion, 248 ... Polysilicon layer, 249 ... Contact hole, 250 ... Gate electrode, 251 ... Gate terminal, 252 ... Emitter electrode, 253 ... Emitter terminal, 254... Contact hole, 260... Emitter trench part, 262... Insulating film, 264... Emitter conductive part, 270... Transistor part, 280.・ Cathode region

Claims (20)

A first conductivity type semiconductor substrate;
A dummy trench that is formed on the surface of the semiconductor substrate and includes a main body extending in a predetermined extending direction and one or more branch portions extending from the main body in a direction different from the extending direction. And
With
The semiconductor substrate has a first conductivity type emitter region and a second conductivity type base region provided in order as viewed from the surface of the semiconductor substrate;
The dummy trench portion is
A dummy trench penetrating the emitter region and the base region from the surface of the semiconductor substrate;
And a dummy insulating part provided in the dummy trench. The semiconductor device according to claim 1, wherein the dummy insulating portion is filled from a bottom portion of the dummy trench to a predetermined height in the dummy trench. The semiconductor device according to claim 2, wherein the branch portion extends in a direction orthogonal to the extending direction of the main body portion. A gate trench part formed on the surface of the semiconductor substrate;
The gate trench portion is
A gate trench penetrating the emitter region and the base region of the semiconductor substrate;
A gate conductive portion provided inside the gate trench,
The body portion of the dummy trench is provided to face the gate trench,
The branch portion of the dummy trench is provided extending toward the gate trench,
The semiconductor device according to claim 2, wherein at least a part of the branch portion of the dummy trench is not in contact with the gate trench. The semiconductor substrate is further connected to the base region, has an impurity concentration higher than that of the base region, and further has a second conductivity type contact region exposed on the surface of the semiconductor substrate;
The semiconductor device according to claim 4, wherein at least a part of the branch portion is provided inside the contact region on a surface of the semiconductor substrate. The branch portion of at least a part of the dummy trench is provided inside the emitter region on the surface of the semiconductor substrate,
The semiconductor device according to claim 5, wherein the branch portion provided inside the emitter region on the surface of the semiconductor substrate is not in contact with the gate trench. The emitter region and the contact region are alternately provided along the extending direction in a region sandwiched between the gate trench portion and the dummy trench portion on the surface of the semiconductor substrate.
The semiconductor device according to claim 6, wherein the number of the branch portions provided in the contact region is greater than the number of the branch portions provided in the emitter region on the surface of the semiconductor substrate. The semiconductor device according to claim 7, wherein an interval between the branch portions in the extending direction of the main body portion is constant. 9. The semiconductor device according to claim 4, wherein a length of the branch portion is at least half of a distance between the main body portion of the dummy trench and the gate trench. The semiconductor device according to claim 4, wherein an interval between the branch portions in the extending direction of the main body portion is smaller than a distance between the main body portion and the gate trench. The semiconductor device according to claim 4, wherein the dummy trench is formed to a position shallower than the gate trench. The semiconductor device according to claim 11, wherein a width of the dummy trench is smaller than a width of the gate trench. The semiconductor substrate further includes a first conductivity type accumulation region provided on the back side of the base region and having a higher impurity concentration than the semiconductor substrate;
The semiconductor device according to claim 4, wherein the dummy trench further penetrates the accumulation region. The semiconductor device according to claim 4, wherein the semiconductor substrate further includes a floating region of a second conductivity type separated from the base region in a region adjacent to the bottom of the dummy trench.   The semiconductor device according to claim 14, wherein a bottom portion of the floating region is provided at a position deeper than a bottom portion of the gate trench. The semiconductor substrate further includes a second conductivity type well region provided outside the emitter region on the surface of the semiconductor substrate and having a higher impurity concentration than the base region;
The dummy trench of the branch part provided at a position closest to the well region in the extending direction is formed to a position deeper than the dummy trench of the other branch part. The semiconductor device according to item. The semiconductor device according to claim 16, wherein a width of the dummy trench in the branch portion closest to the well region is larger than a width of the dummy trench in another branch portion. A first surface side electrode provided above the surface of the semiconductor substrate and in contact with the surface of the emitter region;
The dummy insulating portion is filled in the dummy trench so that at least a part of the emitter region is exposed on a sidewall of the dummy trench.
The semiconductor device according to claim 4, wherein the first surface side electrode is in contact with the emitter region also on a side wall of the dummy trench. The semiconductor device according to claim 18, wherein the gate trench portion further includes a gate insulating portion that is provided above the gate conductive portion inside the gate trench and insulates the first surface side electrode from the gate conductive portion. apparatus. The semiconductor device according to claim 4, wherein the gate trench portion includes one or more branch portions extending in a direction different from the extending direction.

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