JP5673702B2 - Game machine - Google Patents

Description

  The present invention relates to gaming machines such as pachinko machines and slot machines.

  A gaming machine represented by a pachinko machine mainly has a main control board that controls the game, a payout control board that operates based on various commands transmitted from the main control board, a display control board, and sound effects. A control board, a lamp control board, and the like, and a display device and a payout device connected thereto, and various devices such as a game ball launching device are configured. For example, when a game ball driven into the game area by the launching device wins a winning opening, the main control board detects the winning signal, and the number of prize balls to be paid out is instructed from the main control board to the payout control board. In accordance with this instruction, the payout device is controlled by the payout control board, and award balls are paid out.

  Here, for example, if a power failure occurs before the payout of the winning ball is completed, even if the power failure is resolved, the winning ball cannot be paid out for winnings before the power failure. In order to respond to this example, it is possible to back up the power supply of the gaming machine and supply the driving voltage to the gaming machine even in the event of a power failure so that the gaming machine can continue to operate. In the event of a power outage, the backup power supply will also go down, so simply backing up the gaming machine power supply will not be able to cope.

  The present invention has been made to solve the above-described problems and the like, and an object thereof is to provide a gaming machine that can suitably cope with a power failure.

In order to achieve this object, the gaming machine according to claim 1 includes first control means for controlling a game, and second control means for performing predetermined control based on a control command transmitted from the first control means. A power failure signal output means for outputting to the first control means a power failure signal that is switched from the first state to the second state when a power failure occurs, and the first control means and the second control in the third state. operation means is performed, reset signal output operation of the first control means and said second control means when the fourth state to output a reset signal is stopped to the first control means and said second control means The reset signal output means is output from the reset signal output means after a predetermined period when the power failure signal is switched from the first state to the second state by the power failure signal output means. The so that the reset signal is switched from the third state to the fourth state, a first reset signal switching means for switching the reset signal is output to the first control means and said second control means, the power failure is eliminated that The reset signal output to the first control means and the second control means so that the reset signal output from the reset signal output means switches from the fourth state to the third state. Second reset signal switching means for switching, and the first control means has power failure processing execution means for executing power failure processing when the power failure signal is switched from the first state to the second state. In addition, when the predetermined power failure process is being performed, the next power failure process is not performed .
When the power failure occurs, the gaming machine according to claim 2 has a first control means for controlling the game, a second control means for performing a predetermined control based on a control command transmitted from the first control means, and A power failure signal output means for outputting a power failure signal that is switched from the first state to the second state to the first control means, and in the case of the third state, the operations of the first control means and the second control means are performed, and a reset signal output means operation of the first control means and said second control means outputs a reset signal is stopped to the first control means and said second control means when the fourth state, said reset The signal output means outputs the reset signal output from the reset signal output means after a predetermined period after the power failure signal is switched from the first state to the second state by the power failure signal output means. Third to switch from state to the fourth state, the a first reset signal switching means for switching the reset signal to be output to the first control means and said second control means, the power failure signal by the power failure signal output means If There is switched from the second state to the first state, so that the reset signal outputted from the reset signal output means is switched from said fourth state to said third state, said first control means and said Second reset signal switching means for switching the reset signal output to the second control means , wherein the first control means is configured to switch the power failure signal from the first state to the second state. has a power failure processing execution means for executing a power failure processing, has the following power failure processing is configured so as not to be executed when running a predetermined said power failure processing .
According to a third aspect of the present invention, when a power failure occurs, the first control means for controlling the game, the second control means for performing predetermined control based on the control command transmitted from the first control means, and A power failure signal output means for outputting a power failure signal that is switched from the first state to the second state to the first control means, and in the case of the third state, the operations of the first control means and the second control means are performed, and a reset signal output means operation of the first control means and said second control means outputs a reset signal is stopped to the first control means and said second control means when the fourth state, said reset The signal output means outputs the reset signal output from the reset signal output means after a first period after the power failure signal is switched from the first state to the second state by the power failure signal output means. Third to switch from state to the fourth state, the a first reset signal switching means for switching the reset signal to be output to the first control means and said second control means, the power failure signal by the power failure signal output means The first control is performed so that the reset signal output from the reset signal output means is switched from the fourth state to the third state after a second period when the second state is switched from the second state to the first state. And a second reset signal switching means for switching the reset signal output to the second control means , wherein the first control means switches the power failure signal from the first state to the second state. If there is a power outage process, the power outage process execution means for executing the power outage process is configured so that the next power outage process is not executed when the predetermined power outage process is executed. To have.
A gaming machine according to a fourth aspect is the gaming machine according to the third aspect, wherein the first period and the second period are the same period.
The gaming machine according to claim 5 is the gaming machine according to any one of claims 1 to 4, wherein the first state is a high state, the second state is a low state, and the third state is a high state. The fourth state is a low state.
A gaming machine according to a sixth aspect is the gaming machine according to any one of the first to fifth aspects, wherein the gaming machine is a pachinko gaming machine.

  According to the gaming machine of the present invention, it is possible to cope with a power failure.

It is a front view of the game board of the pachinko machine which is one Example of this invention. It is the block diagram which showed roughly the electrical structure of the pachinko machine. It is the circuit diagram which showed the schematic function of the power failure monitoring circuit. It is the figure which showed the truth table of the monostable multivibrator comprised by IC of HC221. It is the figure which showed the truth table of the D type flip-flop comprised with IC of HC74. It is a timing chart of a power failure monitoring circuit when a power failure occurs after the power of the pachinko machine is turned on and operates stably. It is a timing chart of a power failure monitoring circuit when a momentary power failure having a very short power failure time occurs. It is a timing chart of a power failure monitoring circuit when the output time of a power failure signal is 18 ms or more. It is the circuit diagram which showed the schematic function of the power failure monitoring circuit in 2nd Example. In 2nd Example, it is a timing chart of the power failure monitoring circuit when the power failure of the pachinko machine is turned on and the power failure occurs after stable operation. In 2nd Example, it is a timing chart of the power failure monitoring circuit when the momentary power failure of the power failure time occurs. In 2nd Example, it is a timing chart of a power failure monitoring circuit in case the output time of a power failure signal becomes 18 ms or more.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In this embodiment, a pachinko machine that is a kind of a ball game machine, in particular, a first type pachinko game machine will be described as an example of the game machine. Of course, the present invention can be used for other gaming machines such as a third-class pachinko gaming machine, a coin gaming machine, and a slot machine.

  FIG. 1 is a front view of a game board of a pachinko machine P according to the present embodiment. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 balls are paid out when a hit ball is won. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction. In each of the three divided display areas, the symbols are displayed in a variable manner while scrolling from right to left in the horizontal direction.

  Below the LCD display 3, a symbol operating port (first type starting port) 4 is provided. When the hit ball passes through the symbol operating port 4, the above-described variation display of the LCD display 3 is started. Below the symbol operating port 4, a specific winning port (large winning port) 5 is provided. The specific winning opening 5 is a big hit when the display result after the fluctuation of the LCD display 3 coincides with one of the predetermined symbol combinations, so that the hitting ball is easy to win for a predetermined time (for example, 30 It is released until seconds have passed or 10 hit balls have been won.

  A V zone 5a is provided in the specific winning opening 5, and when the hit ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.

  In addition, a plurality of lamps 7 are disposed at various locations around the game board 1 and its periphery. These lamps 7 are turned on or off in accordance with the contents of the game to excite the interest of the game and display the progress of the game to the player.

  FIG. 2 is a block diagram schematically showing the electrical configuration of the pachinko machine P. As shown in FIG. As shown in FIG. 2, the pachinko machine P includes a power failure monitoring circuit 20 and a plurality of control boards H, D, S, and L connected to the main control board C. The main control board C is for controlling the game contents, and includes signals output from various switches SW connected to the main control board C and counter values provided in the main control board C. Based on this, a control command is transmitted to each control board H, D, S, L to control the game.

  On the main control board C, an MPU 11 as a one-chip microcomputer is mounted. The MPU 11 includes a CPU as an arithmetic unit, a ROM that stores a control program, a RAM 12 that stores various data in a rewritable manner when the control program is executed, a timer interrupt circuit, a free running counter, a watch dog timer, In addition to these circuits, various circuits such as chip select logic are built in one chip, and in addition to these circuits, random numbers used to control the game of the pachinko machine P (control to determine whether or not a big hit) is generated And an ID output circuit for storing an identification number (ID number) unique to the MPU 11 and outputting the identification number by a predetermined operation.

  The backup voltage is supplied to the MPU 11 even when the power is turned off. Therefore, even if the power is turned off due to the occurrence of a power failure or the like, the data in the RAM 12 of the MPU 11 is retained (backed up). Since the remaining payout number of prize balls is stored in the RAM 12, the remaining payout number of prize balls can be continuously stored even during a power failure, and the remaining prize balls can be paid out after the power failure is resolved. Note that the RAM 12 of this embodiment has all the data backed up, and data other than the above-mentioned prize ball payout remaining number is also backed up. However, it is not always necessary to back up all data in the RAM 12, and instead of backing up all the data, only a part of the data in the RAM 12 may be backed up.

  The payout control board H performs payout control of prize balls and rental balls based on signals output from the various switches SW and control commands sent from the main control board C. In addition to the main control board C, A launch control board B for controlling a launch motor 10 for launching a ball to a game area in the game board 1 and a payout motor 9 for paying out a prize ball or a rental ball are connected.

  The RAM 13 of the payout control board H is supplied with a backup voltage even when the power is turned off. Therefore, even when the power is turned off due to the occurrence of a power failure or the like, the data in the RAM 13 is retained (backed up). The RAM 13 stores the payout remaining number of prize balls and rental balls, so that these can be stored even during a power failure and the remaining prize balls and rental balls can be paid out after the power failure is resolved. Note that the RAM 13 of this embodiment is backed up in the same way as in the case of the RAM 12 of the MPU 11 described above, and therefore, data other than the number of remaining payouts of prize balls and rental balls is also backed up. However, it is not always necessary to back up all the data in the RAM 13, and instead of backing up all the data, only a part of the data in the RAM 13 may be backed up.

  Data backed up on the main control board C and the payout control board H can be erased (cleared) by pressing a clear switch (not shown) provided on the back side of the pachinko machine P. Note that the clearing of the backup data is performed only when the clear switch is operated at a predetermined timing so that the clearing is not performed by mistake. For example, when the power is turned on while the clear switch is operated, the power is turned off while the clear switch is operated, the clear switch is operated multiple times within a predetermined time, or the clear switch is Two or more are provided, and the backup data is cleared when the clear switch is operated in a predetermined order or simultaneously.

  The display control board D is for controlling the fluctuation display of the LCD display 3 based on the control command transmitted from the main control board C. The sound effect control board S is for outputting sound effects in accordance with the progress of the game from the speaker 6 based on the control command transmitted from the main control board C. The lamp control board L is the main control board. This is for controlling the lighting and extinguishing of each lamp 7 based on the control command transmitted from C.

  Between the main control board C and the control boards H, D, S, and L, buffers 8 having fixed inputs and outputs are respectively connected (only one is shown in FIG. 2). Therefore, transmission / reception between the main control board C and each control board H, D, S, L is performed only in one direction from the main control board C to each control board H, D, S, L. , D, S, L cannot be performed on the main control board C.

  The power failure monitoring circuit 20 outputs a power failure signal 21 to the main control board C and the payout control board H when the power is turned off or when a power failure occurs, and under predetermined conditions after the power is turned on or after the power failure signal 21 is output. This is a circuit for outputting a reset signal 22 to each control board C, H, D, S, L, B. Details of the power failure monitoring circuit 20 will be described with reference to FIG.

  FIG. 3 is a circuit diagram illustrating a schematic function of the power failure monitoring circuit 20. For ease of explanation, the description of each element such as a resistor, a capacitor, and a diode that does not affect the explanation of the function is omitted.

  The power failure monitoring circuit 20 has a voltage detector 25 for inputting an output voltage of +33 volts (hereinafter referred to as “+33 V”) of a power supply circuit (not shown). A Schmitt trigger type buffer BF1 is connected. The output end of the buffer BF1 is connected to one end of the 2-input AND AD1 and the D terminal of the D-type flip-flop FF. Specifically, this voltage detector 25 is made up of MB3761 manufactured by Fujitsu Limited. When the voltage of + 33V output from the power supply circuit is monitored and this voltage drops to approximately 22 volts or less, a power failure occurs. (Including power-off, the same applies hereinafter), and the output is switched from low to high. By switching the output, the power failure signal 21 is output to the main control board C and the payout control board H as described later.

  When a power failure occurs, it is necessary to stop the progress of the game control and execute the control end process. Therefore, until the end process is completed, the control system drive voltage +5 volts (hereinafter “+5 V”) is required. Output) must be maintained by the power supply circuit. For this reason, in this embodiment, when the voltage for +33 V drops to approximately 22 volts or less so that a sufficient time for the termination processing can be secured (specifically, a time of 9 ms or more can be secured). The power failure signal 21 is output. Since the processing time for the end processing and the time for maintaining the output of +5 V vary depending on the type of the machine, of course, the voltage value of about 22 volts used as the output trigger of the power failure signal 21 in this embodiment is also dependent on the type of the machine. Go up and down.

  The power failure monitoring circuit 20 has a reset IC 26 for inputting an output voltage of + 5V from a power supply circuit (not shown), and a Schmitt trigger type buffer BF2 is connected to the output terminal of the reset IC 26. Yes. The output end of the buffer BF2 is connected to one end of the two 2-input ANDs AD1 and AD3 and to the CLR terminals of the two monostable multivibrators MM1 and MM2. The reset IC 26 outputs a low level for a predetermined time (9 ms in this embodiment) after a voltage of +5 V, which is a drive voltage of the control system, is output from the power supply circuit, and then maintains a high output. As will be described later, when the power is turned on, the output of the reset IC 26 is output to the control boards C, H, D, S, L, and B as the reset signal 22.

  The output terminal of the AND AD1 to which the outputs of the voltage detector 25 and the reset IC 26 are input via the buffers BF1 and BF2 are the input terminals of the Schmitt trigger type inverters IV1 and IV2, and the B of the monostable multivibrator MM1 in the previous stage. And the CLR terminal of the flip-flop FF, respectively. The outputs of the inverters IV1 and IV2 are output as the power failure signal 21 to the main control board C and the payout control board H, respectively. The Q bar terminal of the monostable multivibrator MM1 is connected to the B terminal of the subsequent monostable multivibrator MM2. The Q bar terminal is connected to the CK terminal of the flip-flop FF and one end of the 2-input AND AD2. It is connected. The Q bar terminal of the flip-flop FF is connected to the other end of the 2-input AND AD2.

  The monostable multivibrators MM1 and MM2 are both configured by HC221 ICs. As shown in the truth table in FIG. 4, when a high signal is input to the CLR terminal, a high signal is always output from the Q bar terminal, and in this state, the input signal at the B terminal changes from low to high. When it rises, the output of the Q bar terminal is set low for a certain time (9 ms in this embodiment). That is, a one-shot low pulse of 9 ms is output from the Q bar terminal. In this embodiment, the other terminals of the monostable multivibrators MM1 and MM2 are connected so that the output time of the low pulse from the Q bar terminal is 9 ms and the operation shown in the truth table of FIG. 4 is performed. Yes. Note that even if the signal input to the B terminal changes while the one-shot low pulse is output from the Q bar terminal, the change is ignored and does not affect the output pulse of the Q bar terminal. In FIG. 4, the “X” mark in the table indicates that the state of the input signal does not matter.

  The flip-flop FF is composed of an HC74 IC. As shown in the truth table in FIG. 5, a high signal is output from the Q bar terminal when a low signal is input to the CLR terminal, and a high signal is input to the CLR terminal and the D terminal. When the input signal of the terminal rises from low to high, the output of the Q bar terminal is set to low. In FIG. 5, the “X” mark in the table indicates that the state of the input signal does not matter.

  The output terminal of the AND AD2 connected to the Q bar terminal of the subsequent monostable multivibrator MM2 and the Q bar terminal of the flip-flop FF is connected to one end of the two-input AND AD3. As described above, the output signal of the reset IC 26 is input to the other input terminal of the AND AD3 via the buffer BF2. Further, five buffers BF3 to BF8 are connected to the output terminal of the AND AD3, and the outputs of the five buffers BF3 to BF8 are used as reset signals 22 as control boards C, H, D, S, Output to L and B respectively.

  Next, the operation of the power failure monitoring circuit 20, that is, the output operation of the power failure signal 21 and the reset signal 22 will be described with reference to FIGS. FIG. 6 is a timing chart of the power failure monitoring circuit 20 when a power failure occurs (including when the power is turned off) after the pachinko machine P is powered on and stably operates.

  First, when the power is turned on, the voltage of + 5V increases, and when the voltage reaches the normal operating range voltage (+ 5V is normal), each IC outputs a signal in its initial state. The reset IC 26 also starts to operate, outputs a low signal for 9 ms, and then outputs a high signal (see BF2 output). This output is output as a reset signal 22 to each control board C, H, D, S, L, B via the AND AD3 and each of the buffers BF3 to BF8. C, H, D, S, L, and B start operation. That is, when the 9 ms reset signal 22 is input to each of the control boards C, H, D, S, L, and B, the pachinko machine P starts operating.

  When a power failure occurs (or when the power is turned off), first, the output voltage of +33 V starts to gradually decrease. When this drops below approximately 22V, the output of the voltage detector 25 goes from low to high and the output of the buffer BF1 goes high. During this time, since the output voltage of + 5V maintains a normal value, the reset IC 26 outputs high, and the output of the buffer BF2 is high. Therefore, when the output of the buffer BF1 becomes high, the output of the AND AD1 rises from low to high, and the outputs of the inverters IV1 and IV2 conversely fall from high to low. This is output as the power failure signal 21 to the main control board C and the payout control board H which store data so as to be backed up.

  When the output of the AND AD1 rises, a high signal is input to the CLR terminal of the monostable multivibrator MM1, so that a one-shot low pulse that maintains low for 9 ms is output from the Q bar terminal. At the rise of the low pulse of 9 ms, a one-shot low pulse that maintains low for 9 ms is output from the Q bar terminal of the subsequent monostable multivibrator MM2, thereby causing one input of AND AD2 to become low. The output of AND AD2 changes from high to low. As a result, the output of the AND AD3 also changes from high to low, and the reset signal 22 is output to the control boards C, H, D, S, L, and B via the buffers BF3 to BF8.

  The output of the buffer BF1 remains high if the power failure continues at the timing when 9 ms elapses from the output of the reset signal 22, that is, the output of the Q bar terminal of the monostable multivibrator MM2 rises from low to high. It is. Therefore, since the output of AND AD1 is also high, a high signal is input to the D terminal and CLR terminal of the flip-flop FF, so that the output of the Q bar terminal of the monostable multivibrator MM2 input to the CK terminal rises. Then, the output of the Q bar terminal of the flip-flop FF becomes low. Since the output of the Q bar terminal is input to the AND AD2, the output of the AND AD2 is low even if the output of the Q bar terminal of the monostable multivibrator MM2 changes from low to high while the power failure continues. As a result, the reset signal 22 continues to output low while the power failure continues.

  In this manner, after the power failure signal 21 is output, the output of the reset signal 22 is on standby for 9 ms during which the one-shot low pulse is output from the monostable multivibrator MM1 in the previous stage. During 9 ms, power outage processing (game end processing at power outage) can be executed. Therefore, since the game operation can be stopped after completing the game end processing, the game can be resumed normally from the state before the power failure after the power failure is resolved.

  FIG. 7 is a timing chart of the power failure monitoring circuit 20 when an instantaneous power failure having an extremely short power failure time occurs. Even when a momentary power failure as shown in FIG. 7 occurs, according to the power failure monitoring circuit 20 of this embodiment, the time of the power failure processing (game end processing) of 9 ms and the output time of the reset signal 22 of 9 ms are obtained. It can be secured.

  After the power failure occurs, the power failure disappears while the 9-shot one-shot low pulse is output from the Q bar terminal of the subsequent monostable multivibrator MM2, and when the output voltage of + 33V becomes higher than + 22V, the voltage detector 25 The output falls from high to low. As a result, the output of the buffer BF1 also falls from high to low, and the output of the AND AD1 becomes low. Then, the outputs of the inverters IV1 and IV2 rise from low to high, and the output of the power failure signal 21 is thereby released.

  Since the output of the AND AD1 is also input to the CLR terminal of the flip-flop FF, when the output of the AND AD1 goes low, the output of the Q bar terminal of the flip-flop FF is always regardless of the signal input to the CK terminal. Become high. Therefore, at the timing when the output of the Q bar terminal of the monostable multivibrator MM2 rises from low to high, the output of the AND AD2 becomes high, and as a result, the output of the AND AD3 also becomes high via the buffers BF3 to BF8. The reset signal 22 output to each control board C, H, D, S, L, B is cancelled.

  Here, the reset signal 22 is output when the output of the Q-bar terminal of the subsequent monostable multivibrator MM2 becomes low, but the output of the Q-bar terminal is maintained for 9 ms. Even if it is eliminated in a short time, the output time of the reset signal 22 can be secured at least 9 ms. Therefore, it is possible to reliably reset the control boards C, H, D, S, L, and B even when a momentary power failure occurs.

  As is apparent from the circuit diagram of FIG. 3, even if a power failure is resolved while a one-shot low pulse is output from the Q bar terminal of the preceding monostable multivibrator MM1, two monostable multivibrators MM1 , MM2 each output a 9-ms one-shot low pulse. Therefore, similarly to the case described above, it is possible to secure a time of 9 ms power outage processing (game end processing) and an output time of the 9 ms reset signal 22. In this case, the output time of the power failure signal 21 increases or decreases depending on the duration of the power failure, but the main control board C and the payout control board H are configured to start the power failure process at the falling edge of the power failure signal 21. Therefore, even if the output time of the power failure signal 21 is shortened, the power failure processing (game end processing at the time of power failure) can be reliably executed.

  Similarly, even when a one-shot low pulse is repeatedly output from the Q bar terminal of the monostable multivibrator MM1 in the preceding stage, the occurrence and elimination of a power failure is repeated, that is, the output of the buffer BF1 is high and low. Since the change of the input signal while the monostable multivibrators MM1 and MM2 output the one-shot low pulse is ignored even if it is repeatedly changed in the two monostable multivibrators MM1 and MM2, A 9-ms one-shot low pulse is output. Therefore, similarly to the above case, even if the occurrence and cancellation of the power failure are repeated, it is possible to secure the time for the power failure processing (game end processing) of 9 ms and the output time of the reset signal 22 of 9 ms. It is.

  FIG. 8 is a timing chart of the power failure monitoring circuit 20 when the output time of the power failure signal 21 is 18 ms or more. As shown in FIG. 8, according to the power failure monitoring circuit 20 of the present embodiment, the output of the reset signal 22 is maintained while the power failure continues.

  After a power failure occurs, after a 9-ms one-shot low pulse is output from the Q bar terminal of the subsequent monostable multivibrator MM2, that is, at the timing when the output of the Q bar terminal of the monostable multivibrator MM2 rises from low to high. If the power failure continues, the output of the buffer BF1 remains high. Therefore, since the output of AND AD1 is also high, a high signal is input to the D terminal and CLR terminal of the flip-flop FF, so that the output of the Q bar terminal of the monostable multivibrator MM2 input to the CK terminal rises. Then, the output of the Q bar terminal of the flip-flop FF becomes low. Since the output of the Q bar terminal is input to the AND AD2, the output of the AND AD2 is low even if the output of the Q bar terminal of the monostable multivibrator MM2 changes from low to high while the power failure continues. As a result, the reset signal 22 continues to output low while the power failure continues.

  Thereafter, when the output voltage of +33 V becomes higher than +22 V and the power failure is resolved, the output of the voltage detector 25 falls from high to low, and as a result, the output of the AND AD1 also becomes low. Then, the outputs of the inverters IV1 and IV2 rise from low to high, and the output of the power failure signal 21 is thereby released.

  Further, when the output of the buffer BF1 becomes low due to the elimination of the power failure, the output of the AND AD1 also becomes low, and the input of the CLR terminal of the flip-flop FF becomes low, so that the output of the Q bar terminal of the flip-flop FF becomes high. . As described above, since the output of the Q bar terminal of the subsequent monostable multivibrator MM2 is already high at this time, the output of AND AD2 is also high, and the output of AND AD3 is also high, The reset signal 22 output to each control board C, H, D, S, L, B is released via BF3 to BF8.

  Thus, even when the reset signal 22 is output for 9 ms, the output is maintained when the power failure continues. Therefore, the resumption of the game during a power failure can be prevented, and the control of the game can be resumed after the power failure is resolved.

  As described above, according to the pachinko machine P of the present embodiment, when the power failure is resolved, even if the power failure is resolved before the drive voltage (+5 V) of the control system is reduced, the power failure monitoring circuit 20 Since the reset signal 22 can be output to each of the control boards C, H, D, S, L, and B, it is possible to reliably resume the control of the game that has been terminated due to a power failure. Therefore, even if a momentary power outage with a very short power failure occurs, the operation of the pachinko machine P can be continued.

  Next, the power failure monitoring circuit 30 of the second embodiment will be described with reference to FIGS. The power failure monitoring circuit 30 of the second embodiment has the following functions in addition to the functions of the power failure monitoring circuit 20 of the first embodiment described above.

  First, the reset signal 22 is configured to be output for a predetermined time (9 ms in this embodiment) after the power failure signal 21 is output. As a result, the reset signal 22 is reliably output after the power failure signal 21 is released (the reset signal 22 is raised), and each control board C, H, D, S, L, B is reset (operated). Can do.

  Second, the output of the power failure signal 21 is latched to prevent the power failure signal 21 from being repeatedly output in a short time. When the power failure signal 21 is output, the main control board C and the payout control board H execute power failure processing (game end processing at power failure) by NMI (non-maskable interrupt) processing. If the power failure signal 21 is repeatedly output within a short time, the NMI processing nest increases and causes problems such as stack over. In addition, when the power failure process is repeatedly executed, the power failure process may be executed beyond the originally scheduled power failure process execution time (9 ms in the present embodiment). Then, the reset signal 22 is output, and the power failure process ends in the middle. Then, after the power failure is eliminated, there is a problem that the control cannot be returned to normal and the pachinko machine P cannot be operated normally. In order to solve these problems, the output of the power failure signal 21 is latched to prevent the power failure signal 21 from being repeatedly output in a short time.

  In the power failure monitoring circuit 20 of the first embodiment, it is determined that a power failure has occurred when the output voltage of +33 volts is lowered to approximately 22 volts or less by the voltage detector 25. The power failure monitoring circuit 30 uses a power failure detection IC 31 in place of the voltage detector 25, monitors the AC voltage wave that has been full-wave rectified by the power failure detection IC 31, and if the AC voltage wave stops, It is determined that it has occurred. In the following, the same parts as those in the first embodiment described above are denoted by the same reference numerals, description thereof is omitted, and only different parts will be described.

  FIG. 9 is a circuit diagram showing a schematic function of the power failure monitoring circuit 30 of the second embodiment. For ease of explanation, the description of each element such as a resistor, a capacitor, and a diode that does not affect the explanation of the function is omitted.

  The power failure monitoring circuit 30 has a power failure detection IC 31 for inputting a +24 volt AC wave (hereinafter referred to as “+24 VB”) that is full-wave rectified from a power supply circuit (not shown). Specifically, this power failure detection IC 31 is made up of M5297P manufactured by Mitsubishi Electric Corporation, and monitors the + 24VB full-wave rectified waveform output from the power supply circuit. The output is switched from high to low. A Schmitt trigger type inverter IV11 is connected to the output end of the power failure detection IC31, and the output end of the inverter IV11 is connected to one end of the 2-input AND AD11.

  Further, the power failure monitoring circuit 30 includes a reset IC 26 that inputs an output voltage of +5 V from a power supply circuit (not shown). The reset IC 26 outputs a low level for a predetermined time (18 ms in the second embodiment) after a voltage of +5 V, which is a control system drive voltage, is output from the power supply circuit, and then maintains a high output. A Schmitt trigger type buffer BF11 is connected to the output terminal of the reset IC 26, and the output terminal of the buffer BF11 is one of two two-input ANDs AD11 and AD12, and three monostable circuits composed of HC221 ICs. The multivibrators MM11, MM12, and MM13 are connected to CLR terminals, respectively.

  The output terminal of the AND AD11 is connected to the CLR terminal of the flip-flop FF11 composed of an IC of HC74, the CK terminal of the flip-flop FF12, and the B terminal of the monostable multivibrator MM11.

  As described above, the flip-flop FF12 has the CK terminal connected to the output terminal of the AND AD11, the D terminal to + 5V, the CLR terminal to the output terminal of the AND AD13 and one end of the 2-input AND AD14, and the Q bar terminal The other end of the two-input AND AD 14 is connected to each other. As shown in the truth table of FIG. 5, in the flip-flop FF12, when the input to the CK terminal rises in a state in which high is input to the CLR terminal, the output of the Q bar terminal becomes low. As a result, a low signal is output from the AND AD 14. The low signal is output as the power failure signal 21 to the main control board C and the payout control board H via the Schmitt trigger type buffers BF12 and BF13.

  The low output of the Q bar terminal of the flip-flop FF12 is maintained (latched) until a low is input to the CLR terminal. Therefore, until the output of the AND AD 13 becomes low, the power failure detection IC 31 repeatedly detects the occurrence of the power failure and the detection of the cancellation of the power failure, or the output of the AND AD 11 repeats the high / low due to the influence of noise or the like. However, since the output of the Q bar terminal remains low, it is possible to prevent the low output of the AND AD 14, that is, the power failure signal 21 from being repeatedly output. As a result, NMI (non-maskable interrupt) processing on the main control board C and the payout control board H can be normally executed without causing problems such as stack over due to an increase in nests. Further, the power failure process can be prevented from being repeatedly executed, and the power failure process can be reliably ended while the 9 ms low pulse is output from the Q bar terminal of the monostable multivibrator MM11.

  In the monostable multivibrator MM11, as described above, the B terminal is connected to the output terminal of the AND AD11, the CLR terminal is connected to the output terminal of the buffer BF11, and the Q bar terminal is the B terminal of the subsequent monostable multivibrator MM12. It is connected to the. In the subsequent monostable multivibrator MM12, as described above, the CLR terminal is connected to the output terminal of the buffer BF11, the Q terminal is connected to the CK terminal of the flip-flop FF11, and the Q bar terminal is the other end of the 2-input AND AD12. Are connected to each other. As described above, the CLR terminal of the flip-flop FF11 is connected to the output terminal of the AND AD11, the D terminal is connected to + 5V, and the Q bar terminal is connected to one end of the AND AD13. The other end of the AND AD 13 is connected to the output end of the AND AD 12.

  Therefore, when a power failure is detected by the power failure detection IC 31 and the output of the AND AD 11 becomes high, first, a 9-ms one-shot low pulse is output from the Q bar terminal of the previous monostable multivibrator MM 11, and at the rising timing, A 9-ms one-shot high pulse is output from the Q terminal of the subsequent monostable multivibrator MM12, and a 9-ms one-shot low pulse is output from the Q bar terminal. By outputting a one-shot high pulse from the Q terminal of the monostable multivibrator MM12, the output of the Q bar terminal of the flip-flop FF11 becomes low, and the output of the AND AD13 also becomes low.

  The monostable multivibrator MM13 is composed of an HC221 IC. As described above, the CLR terminal is connected to the output terminal of the buffer BF11, the B terminal is connected to the output terminal of the AND AD14, and the Q bar terminal is a flip-flop. Each is connected to the CK terminal of FF13. The flip-flop FF13 is composed of an HC74 IC, and its D terminal is output to + 5V, the CLR terminal is output to the output terminal of the AND AD12, and the Q terminal is output to the five buffers BF3 to BF8. As in the first embodiment, the outputs of these five buffers BF3 to BF8 are output as reset signals 22 to the control boards C, H, D, S, L, and B, respectively.

  Next, the operation of the power failure monitoring circuit 30 of the second embodiment, that is, the output operation of the power failure signal 21 and the reset signal 22 will be described with reference to FIGS. FIG. 10 is a timing chart of the power failure monitoring circuit 30 when a power failure occurs (including when the power is turned off) after the pachinko machine P is powered on and stably operates.

  First, when the power is turned on, the voltage of + 5V increases, and when the voltage reaches the normal operating range voltage (+ 5V is normal), each IC outputs a signal in its initial state. At the same time, the reset IC 26 also starts to operate, outputs a low signal for a predetermined time set in the reset IC 26 (about 18 ms in this embodiment), and then outputs a high signal (A). This high signal is input to the AND AD12 via the buffer BF11, and the output of the AND AD12 is set to high. Then, the output of the AND AD13 is also high, and the output of the AND AD14 is also high. As described above, when the output of the AND AD 14 becomes high (A), the output state of the power failure signal 21 is canceled.

  When the output state of the power failure signal 21 is released, that is, when the output of the AND AD 14 becomes high, the input of the B terminal of the monostable multivibrator MM13 rises. At this time, since a high signal is input to the CLR terminal, a one-shot low pulse that maintains a low level for 9 ms is output from the Q bar terminal as shown in the truth table of FIG. Since the CLR terminal of the flip-flop FF13 is inputted with the high signal that is the output of the AND AD12, as shown in the truth table of FIG. 5, the output of the Q terminal of the flip-flop FF13 at the rising edge of the 9 ms low pulse. Becomes high (I). This is output to the control boards C, H, D, S, L, and B through the buffers BF3 to BF8 as the rising edge of the reset signal 22, and the control boards C, H, D, S, L, and B ( That is, the pachinko machine P) starts operating. Thus, since the reset signal 22 rises after 9 ms from the cancellation of the power failure signal 21, each control board C, H, D, S, L, B can be operated after the power failure state is reliably canceled. .

  When a power failure occurs (or when the power supply is turned off), the + 24VB voltage generated by full-wave rectification of the AC voltage does not rise to 0 volts (c). When such a state continues for a predetermined time, the output of the power failure detection IC 31 changes from high to low (D), and the output of the inverter IV11 becomes high. During this time, since the output voltage of + 5V maintains a normal value, the reset IC 26 outputs high, and the output of the buffer BF11 is high. Therefore, when the output of the inverter IV11 becomes high, the output of the AND AD11 rises from low to high, and the rising signal is input to the CK terminal of the flip-flop FF12. At this time, the output of the AND AD13 is high, and a high signal is input to the CLR terminal of the flip-flop FF12. Therefore, the timing when the output of the AND AD11 becomes high, that is, the output of the power failure detection IC 31 is low. At this timing, the output of the Q bar terminal of the flip-flop FF12 becomes low, and as a result, the output of the AND AD 14 also becomes low, and the power failure signal 21 is output to the main control board C and the payout control board H. With the output of the power failure signal 21, power failure processing (game end processing at the time of power failure) is started on both control boards C and H.

  On the other hand, when the output of the power failure detection IC 31 becomes low (D), as a result, the output of the inverter IV11 becomes high, and when the output of the AND AD11 becomes high, the high signal of the AND AD11 is output from the monostable multivibrator MM11. A rising signal is input to the B terminal. At this time, since a high signal is input to the CLR terminal of the monostable multivibrator MM11, a one-shot low pulse that maintains a low level for 9 ms is output from the Q bar terminal in response to the rise of the output of the AND AD11. Is done.

  While the low pulse of 9 ms is output, the output of the Q bar terminal of the subsequent monostable multivibrator MM12 is kept high, and the output of the AND AD12 is also kept high. Therefore, the output of the Q terminal of the flip-flop FF13 is kept high, and as a result, the output of the low signal from the Q terminal of the flip-flop FF13, that is, the output of the reset signal 22 is prohibited. Therefore, in the main control board C and the payout control board H, the reset signal 22 is not output for 9 ms during which the one-shot low pulse is output from the Q bar terminal of the monostable multivibrator MM11, and the power failure process is reliably executed. be able to.

  When the 9 ms low pulse output from the Q bar terminal of the monostable multivibrator MM11 rises (e), the rise signal is input to the B terminal of the subsequent monostable multivibrator MM12, and therefore the subsequent monostable A 9 ms one shot high pulse is output from the Q terminal of the multivibrator MM12, while a 9 ms one shot low pulse is output from the Q bar terminal. When a low pulse is output from the Q bar terminal, the output of the AND AD12 also becomes low, and as a result, the input of the CLR terminal of the flip-flop FF13 becomes low and the output of the Q terminal becomes low. As a result, the reset signal 22 is output to the control boards C, H, D, S, L, and B via the buffers BF3 to BF8. Since the reset signal 22 is continuously output at least while a 9 ms low pulse is output from the Q bar terminal of the monostable multivibrator MM12, the reset signal 22 is sent to each control board C, H, D, S, L, B. It can be reset reliably.

  When the output of the AND AD12 becomes low (e), the output of the AND AD13 also becomes low. As a result, the output of the Q bar terminal of the flip-flop FF12 becomes high, but since the output of the AND AD13 is already low, the output of the AND AD14 remains low and the output of the power failure signal 21 is continued.

  When the low pulse output from the Q bar terminal of the monostable multivibrator MM12 rises, the output of the AND AD12 becomes high, but at that time, the output of the Q bar terminal of the flip-flop FF11 is low. The output of the AND AD 13 remains low. Therefore, the power failure signal 21 output from the AND AD 14 remains low.

  Moreover, the power failure signal 21 is input to the B terminal of the monostable multivibrator MM13 that controls the reset signal 22 (which is output 9 ms longer in this embodiment), but the power failure signal 21 remains low and does not change. The output of the Q bar terminal of the monostable multivibrator MM13 remains high. As a result, even if the input of the CLR terminal of the flip-flop FF13 changes from low to high, the output of the Q terminal, that is, the reset signal 22 The output continues to stay low.

  In this manner, after the power failure signal 21 is output, the output of the reset signal 22 is on standby for 9 ms during which the one-shot low pulse is output from the Q bar terminal of the monostable multivibrator MM11. Sometimes power outage processing (game end processing during power outage) can be executed for 9 ms. Therefore, since the game operation can be stopped after completing the game end processing, the game can be resumed normally from the state before the power failure after the power failure is resolved.

  Further, since the power failure signal 21 is output via the flip-flop FF11 as a latch circuit, the output of the power failure detection IC 31 becomes low, the output of the AND AD11 becomes high, and as a result, once the Q of the flip-flop FF12 is obtained. After the output of the bar terminal becomes low and the power failure signal 21 is output, the power failure signal 21 is not released until the input of the CLR terminal of the flip-flop FF12 changes from high to low and further changes to high. Therefore, even if the output of the power failure detection IC 31 repeats high / low during that time, the power failure signal 21 is not repeatedly output. Therefore, it is possible to avoid the increase in the nesting of the NMI processing due to the repeated output of the power failure signal 21 and the accompanying stack over, and to prevent the power failure processing from being repeatedly executed, and to operate the pachinko machine P normally. It can be done.

  FIG. 11 is a timing chart of the power failure monitoring circuit 30 when an instantaneous power failure having an extremely short power failure time occurs. Even when a momentary power failure as shown in FIG. 11 occurs, according to the power failure monitoring circuit 30 of the second embodiment, the time for the 9 ms power failure processing (game end processing) and the output of the 9 ms reset signal 22 are output. Time can be secured. Further, during the 18 ms (18 ms in total of the time for the 9 ms power failure processing and the output time of the 9 ms reset signal 22), the detection of the occurrence of the power failure and the detection of the power failure cancellation by the power failure detection IC 31 are repeated a plurality of times. Even in the case of failure, the output of the power failure signal 21 can be stopped once. In addition, the reset signal 22 is not started up almost simultaneously with the release of the power failure signal 21, but after the power failure signal 21 is released, the reset signal 22 is started up after 9 ms has elapsed. Each control board C, H, D, S, L, B can be reset to start each control board C, H, D, S, L, B normally.

  After a power failure occurs, if the power failure is resolved while a 9-ms one-shot low pulse is being output from the Q bar terminal of the previous monostable multivibrator MM11, and the output of the power failure detection IC 31 rises from low to high (f) The output of the inverter IV11 falls from high to low. As a result, the output of the AND AD11 becomes low, but since the output of the AND AD13 is high at this time, the latch state of the flip-flop FF12 does not change and the low output of the Q bar terminal is maintained. Therefore, the low output of the AND AD 14 is maintained as it is, and as a result, the power failure signal 21 remains output.

  Thereafter, when the output of the Q bar terminal of the preceding monostable multivibrator MM11 rises (G), the rising signal is input to the B terminal of the subsequent monostable multivibrator MM12, so A 9-ms one-shot high pulse is output from the Q terminal of the vibrator MM12, while a 9-ms one-shot low pulse is output from the Q-bar terminal. When a low pulse is output from the Q bar terminal, the output of the AND AD12 also becomes low, and as a result, the input of the CLR terminal of the flip-flop FF13 becomes low and the output of the Q terminal becomes low. As a result, the reset signal 22 is output to the control boards C, H, D, S, L, and B via the buffers BF3 to BF8. The reset signal 22 is continuously output during a period in which a low pulse of 9 ms is output from the Q bar terminal of the monostable multivibrator MM12, in which a low continues to be input to the CLR terminal of the flip-flop FF13.

  When the output of the AND AD12 becomes low (G), the output of the AND AD13 also becomes low, and the output of the Q bar terminal of the flip-flop FF12 becomes high. However, since the output of the AND AD 13 is already low, the output of the AND AD 14 is kept low and the output of the power failure signal 21 is continued.

  When the low pulse output from the Q bar terminal of the monostable multivibrator MM12 rises (g), the output of the AND AD12 becomes high. At this time, since the output of the inverter IV11 is low due to the elimination of the power failure, the output of the AND AD11 is also low. Therefore, since the output of the Q bar terminal of the flip-flop FF11 is reset to high, the output of the AND AD13 becomes high at the timing when the output of the AND AD12 becomes high, and as a result, the output of the AND AD14 also becomes high. Thus, the output of the power failure signal 21 is canceled.

  When the power failure signal 21 is released, that is, when the output of the AND AD 14 rises from low to high, the input signal to the B terminal of the monostable multivibrator MM13 also rises, and as a result, from the Q bar terminal of the monostable multivibrator MM13. A one-shot low pulse is output that maintains a low for 9 ms.

  At the rise of this one-shot low pulse, the output of the AND AD12 has already returned to high, and a high signal has been input to the CLR terminal of the flip-flop FF13, so that the Q bar terminal of the monostable multivibrator MM13 At the timing when the output rises, the output of the Q terminal of the flip-flop FF13 becomes high and the reset signal 22 rises.

  FIG. 12 is a timing chart of the power failure monitoring circuit 30 when the output time of the power failure signal 21 is 18 ms or more. As shown in FIG. 12, according to the power failure monitoring circuit 30 of the present embodiment, the power failure signal 21 is maintained in output while the power failure continues, and the reset signal 22 is output after the power failure signal 21 is released. The output is maintained for another 9 ms.

  When the output of the power failure detection IC 31 rises from low to high due to the cancellation of the power failure (S), the output of the inverter IV11 falls from high to low, and as a result, the output of the AND AD11 becomes low. When the output of the AND AD11 becomes low, the input to the CLR terminal of the flip-flop FF11 also becomes low, and a high signal is output from the Q bar terminal of the flip-flop FF11. At this time, since the output of the AND AD12 is already high, the output of the AND AD13 becomes high, and the output of the AND AD14 becomes high in combination with the high output of the Q bar terminal of the flip-flop FF12. Therefore, when the power failure is resolved after 18 ms or more after the power failure signal 21 is output, the output of the power failure signal 21 is canceled together with the cancellation of the power failure.

  When the power failure signal 21 is released, that is, when the output of the AND AD 14 rises from low to high, the input signal to the B terminal of the monostable multivibrator MM13 also rises, and as a result, from the Q bar terminal of the monostable multivibrator MM13. A one-shot low pulse is output that maintains a low for 9 ms.

  At the rising edge of this one-shot low pulse (S), the output of the AND AD12 is high, and a high signal is input to the CLR terminal of the flip-flop FF13. Therefore, the Q bar terminal of the monostable multivibrator MM13 The output of the Q terminal of the flip-flop FF13 becomes high and the reset signal 22 rises. As described above, the reset signal 22 rises after the elapse of 9 ms set by the monostable multivibrator MM13 after the release of the power failure signal 21, so that the control boards C, H, D are surely released after the power failure signal 21 is released. , S, L, B can be reset and each control board C, H, D, S, L, B can be started normally.

  The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, in the above-described embodiment, the power failure signal 21 is output only to the main control board C and the payout control board H configured to be able to retain data (can be backed up) even during a power failure. The control board D, S, L, B may be output.

  Moreover, as the power failure monitoring means according to claim 1, not only the power failure monitoring circuits 20 and 30 constituted by a plurality of electronic components, but also a power failure monitoring IC which is one IC in which these functions are built in one chip, A power failure monitoring process by software control may be substituted. Similarly, the reset means according to claim 1 is not only one constituted by a plurality of electronic components as part of the power failure monitoring circuits 20 and 30, but also one IC having these functions built in one chip. It may be replaced by a reset IC or a reset process by software control. Further, the control means described in claim 1 may be replaced not only by a control board such as the main control board C and the payout control board H but also by a function that achieves its function by software control.

  You may implement this invention in the pachinko machine etc. of a different type from the said Example. For example, once a big hit, a pachinko machine that raises the expected value of the big hit until a big hit state occurs (for example, two times or three times) including that (for example, a two-time right item, a three-time right item) May also be implemented. Moreover, after a jackpot symbol is displayed, it may be implemented as a pachinko machine that enters a special game state on the condition that a ball is awarded in a predetermined area. Further, in addition to the pachinko machine, the game machine may be implemented as various game machines such as an alepatchi, a sparrow ball, a slot machine, a game machine in which a so-called pachinko machine and a slot machine are integrated.

  In the slot machine, for example, a symbol is changed by operating a control lever in a state where a symbol effective line is determined by inserting coins, and a symbol is stopped and confirmed by operating a stop button. Is. Therefore, the basic concept of the slot machine is that it is provided with variable display means for confirming and displaying the identification information after variably displaying the identification information string composed of a plurality of identification information, and resulting from the operation of the starting operation means (for example, the operation lever). Then, the change of the identification information is started, and the change of the identification information is stopped due to the operation of the operation means for stop (for example, the stop button) or after the lapse of a predetermined time, and the fixed identification information at the time of the stop Is a slot machine provided with special game state generating means for generating a special game state advantageous to the player on the condition that the specific identification information is a necessary condition. In this case, coins, medals, etc. are representative examples of game media As mentioned.

  In addition, as a specific example of a gaming machine in which a pachinko machine and a slot machine are integrated, a variable display means for displaying a symbol after a symbol string composed of a plurality of symbols is displayed, and a handle for launching a ball is provided. What is not provided. In this case, after throwing a predetermined amount of spheres based on a predetermined operation (button operation), for example, the change of the symbol is started due to the operation of the operation lever, for example, due to the operation of the stop button, or With the passage of time, the fluctuation of the symbol is stopped, and a jackpot state advantageous to the player is generated on the condition that the confirmed symbol at the time of stoppage is a so-called jackpot symbol. A lot of balls are paid out.

  The modification of this invention is shown below. A power failure monitoring circuit that outputs a power failure signal when a power failure occurs, a game control, and a control board that executes a game control end process when a power failure signal output from the power failure monitoring circuit is input, and the power failure A gaming machine having a reset circuit for outputting a reset signal to the control board in order to resume the game control by the control board when the power failure is resolved after the power failure signal is output by the monitoring circuit. . Note that the power failure monitoring circuit may be configured by individually combining a plurality of electronic components, or may be configured by an IC in which they are built in one chip. Similarly, the reset circuit may be configured by combining a plurality of electronic components individually, or may be configured by an IC in which they are built in one chip.

  In the gaming machine 0, the reset circuit waits for the reset signal to be output after the power failure signal is output by the power failure monitoring circuit until the termination process by the control board is completed (or a predetermined time after the power failure signal is output). A gaming machine 1 characterized by: When the reset signal is output, the progress of the control stops, but this reset circuit resets after the power failure signal is output and until the termination process by the control board is completed (or a predetermined time after the power failure signal is output). Since the signal output is waited, the operation of the game can be stopped after the game end processing is completed when a power failure occurs. Therefore, after the power failure is resolved, the game can be resumed from the state before the power failure.

  In the gaming machine 0 or 1, the gaming machine 2 is characterized in that the reset circuit maintains a reset signal output for a predetermined time. Even in the case of a momentary power failure with a very short power failure time, the reset signal is output for a predetermined time, so that the control board can be reliably reset. Therefore, the control of the game that has been terminated due to the power failure can be resumed after the power failure is resolved.

  In the gaming machine 1 or 2, even after the termination process by the control board is completed after the power failure signal is output by the power failure monitoring circuit (or after a predetermined time has elapsed after the power failure signal is output) The gaming machine 3 is characterized in that the reset circuit continues to output the reset signal while the power failure signal from the power failure monitoring circuit is output. The reset process of the control board is started after the reset signal is output, but the reset circuit maintains the output of the reset signal while the power failure signal is output, that is, during the power failure. It is possible to prevent resumption and resume the control of the game after the power failure is resolved.

  In any of the gaming machines 0 to 3, the power failure occurs after the power failure signal is output by the power failure monitoring circuit and until the termination process by the control board is completed (or within a predetermined time after the power failure signal is output). The gaming machine 4 according to claim 4, wherein the reset circuit outputs the reset signal only once even when the signal is output a plurality of times.

  In any one of the gaming machines 0 to 3, the power failure monitoring circuit maintains a power failure signal output for a predetermined time. After a power failure signal is output, even if a power failure signal is repeatedly output at least within the time during which the power failure process (game end processing) is performed, for example, a momentary power interruption with a very short power failure time may be repeated. However, it is possible to prevent the power failure process from being repeatedly executed. Therefore, it is possible to prevent the power failure processing from being duplicated and finish the power failure processing within a predetermined time, and avoid the occurrence of a stack over of the stack that stores the return address after the power failure processing. It can be operated normally.

  In the gaming machine 5, the power failure monitoring circuit includes a latch circuit, and the power failure signal is output via the latch circuit. The output of the power failure signal is maintained until the clear signal is input to the latch circuit. The latch circuit is exemplified by the flip-flop FF12 of FIG.

  In the gaming machine 6, the clear signal of the latch circuit is output at least after the execution time of the power failure process has elapsed.

  In any one of the gaming machines 0 to 7, the reset circuit maintains the output of the reset signal for a predetermined time or more after the output of the power failure signal is canceled. By outputting the reset signal longer than the period during which the power failure signal is output, that is, by performing the reset signal release after the power failure signal is released, the control on the control board can be performed in a state where the power failure signal is reliably released. Can start. Therefore, the control on the control board can be started normally.

  In the gaming machine 8, the reset circuit includes a reset signal output extension circuit that extends an output period of the reset signal in response to release of the power failure signal. In addition, as this reset signal output extension circuit, monostable multivibrator MM13 which operate | moves by the cancellation | release of the power failure signal 21 is illustrated.

  In any of the gaming machines 0 to 9, a display device for displaying symbols and the like, a payout device for paying out valuable values (including not only premium spheres and coins but also data written on magnetic cards), and sound effects A sounding device that emits light, a lamp that is turned on or off, a main control board that controls a game, a display control board that controls display of the display device based on a command transmitted from the main control board, A payout control board for controlling the payout device based on a command transmitted from the main control board to perform a payout of valuable value, and a sound effect from the sound generator based on a command transmitted from the main control board A sound effect control board to be emitted, and a lamp control board for controlling lighting or extinguishing of the lamp based on a command transmitted from the main control board, The power monitoring circuit outputs a power failure signal to the main control board (and the payout control board), and the reset circuit outputs a reset signal to all of the control boards. A gaming machine 10.

  In the gaming machine 10, the main control board (and the payout control board) is configured to be able to back up (hold) predetermined data even in the event of a power failure.

  The gaming machine 12 is provided with a clear switch (reset switch) for clearing data that is backed up (held) in the event of a power failure. The backup data can be cleared by the clear switch, for example, in the following case. (1) When the clear switch is operated. (2) When the power is turned on with the clear switch operated. (3) When the power is turned off while the clear switch is operated. In this case, the backup data is cleared in the termination process, or in the termination process, the fact that the clear switch is operated when the power is turned off is stored, and the backup data is cleared at the next power-on. Anyway. (4) When the clear switch is operated a plurality of times within a predetermined time. (5) When two or more clear switches are provided and the clear switches are operated in a predetermined order or simultaneously.

  The gaming machine 13 according to claim 1, wherein the gaming machine is a pachinko machine. Above all, the basic configuration of a pachinko machine is equipped with an operation handle, and in response to the operation of the operation handle, a ball is launched into a predetermined game area, and the ball is awarded to an operating port arranged at a predetermined position in the game area. As a necessary condition (or passing through the working port), the identification information variably displayed on the display device is confirmed and stopped after a predetermined time. In addition, when a special gaming state occurs, a variable winning device (specific winning opening) disposed at a predetermined position in the gaming area is opened in a predetermined manner so that a ball can be won, and a value corresponding to the number of winnings is obtained. Examples include those to which values (including data written on magnetic cards as well as premium balls) are given.

  The gaming machine 14 according to claim 1, wherein the gaming machine is a slot machine. Above all, the basic configuration of the slot machine is “variable display means for confirming and displaying the identification information after variably displaying the identification information string composed of a plurality of identification information, and resulting from the operation of the starting operation means (for example, the operation lever). Alternatively, when a predetermined time elapses, the variation of the identification information is stopped, and a special gaming state advantageous to the player is generated on the condition that the fixed identification information at the time of the stop is the specific identification information. A gaming machine provided with a special gaming state generating means. In this case, examples of the game media include coins and medals.

  The gaming machine 15 according to claim 1, wherein the gaming machine is a fusion of a pachinko machine and a slot machine. Among them, the basic configuration of the fused gaming machine includes “a variable display means for confirming and displaying identification information after variably displaying an identification information string composed of a plurality of identification information, and a starting operation means (for example, an operation lever). The fluctuation of the identification information is started due to the operation, and the fluctuation of the identification information is stopped due to the operation of the operation means for stop (for example, the stop button) or after a predetermined time elapses. Special game state generating means for generating a special game state advantageous to the player on the condition that the confirmed identification information is the specific identification information, and using a ball as a game medium and starting to change the identification information In this case, the game machine is configured to require a predetermined number of balls and to be paid out when a special gaming state occurs.

20,30 outage monitoring circuit (reset signal output means)
21 Power failure signal 22 Reset signal 26 Reset IC
31 Power failure detection IC
C Main control board (first control means)
H payout control board D display control board (the second control means)
S sound effect control board (second control means)
L Lamp control board (second control means)
B fire control board P pachinko machine (game machine)

Claims (6)

First control means for controlling a game;
Second control means for performing predetermined control based on a control command transmitted from the first control means;
A power failure signal output means for outputting to the first control means a power failure signal that is switched from the first state to the second state when a power failure occurs;
In the third state, the first control means and the second control means are operated, and in the fourth state, the reset signal is used to stop the operations of the first control means and the second control means. A gaming machine comprising first control means and reset signal output means for outputting to the second control means ,
The reset signal output means includes
After a predetermined period when the power failure signal is switched from the first state to the second state by the power failure signal output unit, the reset signal output from the reset signal output unit is changed from the third state to the fourth state. First reset signal switching means for switching the reset signal output to the first control means and the second control means so as to switch;
When the power failure is resolved, the reset signal output from the reset signal output means is output to the first control means and the second control means so that the fourth state is switched to the third state. Second reset signal switching means for switching the reset signal;
The first control means includes
When the power failure signal is switched from the first state to the second state, there is a power failure processing execution means for performing power failure processing,
Gaming machine, wherein the following power failure processing is configured so as not to be executed when running a predetermined the power outage process. First control means for controlling a game;
Second control means for performing predetermined control based on a control command transmitted from the first control means;
A power failure signal output means for outputting to the first control means a power failure signal that is switched from the first state to the second state when a power failure occurs;
In the third state, the first control means and the second control means are operated, and in the fourth state, the reset signal is used to stop the operations of the first control means and the second control means. A gaming machine comprising first control means and reset signal output means for outputting to the second control means ,
The reset signal output means includes
After a predetermined period when the power failure signal is switched from the first state to the second state by the power failure signal output unit, the reset signal output from the reset signal output unit is changed from the third state to the fourth state. First reset signal switching means for switching the reset signal output to the first control means and the second control means so as to switch;
When the power failure signal is switched from the second state to the first state by the power failure signal output unit, the reset signal output from the reset signal output unit is switched from the fourth state to the third state. Second reset signal switching means for switching the reset signal output to the first control means and the second control means ,
The first control means includes
When the power failure signal is switched from the first state to the second state, there is a power failure processing execution means for performing power failure processing,
Gaming machine, wherein the following power failure processing is configured so as not to be executed when running a predetermined the power outage process. First control means for controlling a game;
Second control means for performing predetermined control based on a control command transmitted from the first control means;
A power failure signal output means for outputting to the first control means a power failure signal that is switched from the first state to the second state when a power failure occurs;
In the third state, the first control means and the second control means are operated, and in the fourth state, the reset signal is used to stop the operations of the first control means and the second control means. A gaming machine comprising first control means and reset signal output means for outputting to the second control means ,
The reset signal output means includes
After the first period when the power failure signal is switched from the first state to the second state by the power failure signal output unit, the reset signal output from the reset signal output unit is changed from the third state to the fourth state. First reset signal switching means for switching the reset signal output to the first control means and the second control means so as to switch to
After the second period when the power failure signal is switched from the second state to the first state by the power failure signal output unit, the reset signal output from the reset signal output unit is changed from the fourth state to the third state. A second reset signal switching means for switching the reset signal output to the first control means and the second control means so as to switch to
The first control means includes
When the power failure signal is switched from the first state to the second state, there is a power failure processing execution means for performing power failure processing,
Gaming machine, wherein the following power failure processing is configured so as not to be executed when running a predetermined the power outage process.   The gaming machine according to claim 3, wherein the first period and the second period are the same period. The first state is a high state, the second state is a low state;
The gaming machine according to claim 1, wherein the third state is a high state and the fourth state is a low state.   The gaming machine according to claim 1, wherein the gaming machine is a pachinko gaming machine.

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