JP5668819B2 - Memory manufacturing method - Google Patents

Description

  The present invention relates to a method of manufacturing a memory having a memory element in which an ionized layer is formed using a target containing a refractory metal element and a chalcogen element.

In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.
However, the DRAM is a volatile memory in which information is lost when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

For example, flash memory, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.
Accordingly, extensive research and product development have been conducted on the various types of nonvolatile memories described above.

However, the various nonvolatile memories described above have advantages and disadvantages.
Flash memory has a high degree of integration, but is disadvantageous in terms of operation speed.
FeRAM has a limit in microfabrication for high integration and has a problem in a manufacturing process.
MRAM has a problem of power consumption.

Accordingly, a new type of memory element has been proposed that is particularly advantageous for the limit of microfabrication of the memory element.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes. When a voltage is applied between the two electrodes, the metal contained in the electrode diffuses as ions in the ionic conductor, thereby changing the electrical characteristics such as the resistance value or capacitance of the ionic conductor.
It is possible to configure a memory device using this characteristic.
Specifically, the ionic conductor is made of a solid solution of a chalcogen element (S, Se, Te) and a metal, and more specifically, a material in which Ag, Cu, Zn is dissolved in AsS, GeS, GeSe. (For example, refer to Patent Document 1).

  In addition to the chalcogen element described above, an element such as Zr or Al has been proposed to be included in the above-described ionic conductor layer (hereinafter referred to as an ionized layer) (for example, Patent Documents). 2).

Special Table 2002-536840 Publication JP 2009-43758 A

The ionization layer of the memory element described above can be formed by co-sputtering using a plurality of targets or by periodic lamination of layers having a thickness of about 1 nm of constituent elements.
However, in order to improve the uniformity of the composition of the ionized layer and reduce the variation from wafer to wafer, it is preferable to form the ionized layer using a single target.

  By the way, it can be considered that the ionization layer of the above-described memory element has a configuration of M1 element-M2 element-chalcogen element. In this configuration, each element is classified in terms of the melting point of the element, the M1 element is a refractory metal such as Ti, Zr, Hf, V, Nb, and Ta, and the M2 element is, for example, Cu, Al, Si, Ge, Mg, Ga, etc., and the chalcogen element consists of S, Se, and Te.

Of these elements, the melting point of the M1 element (refractory metal element) often exceeds the boiling point of the chalcogen element or is close to the boiling point of the chalcogen element. Therefore, it is difficult to dissolve the component elements at a time, and it is difficult to produce a target by a dissolution method.
On the other hand, when trying to produce a target by the powder sintering method, among these M1 element powders, for example, Ti, Zr, and Hf are highly ignitable and there is a risk of igniting during the sintering process. It is also difficult to sinter using raw materials.
These problems become more conspicuous as a large-diameter target is obtained, and it is difficult to obtain a large target.

  In order to solve the above-described problems, the present invention provides a method for manufacturing a memory using a target manufactured by a manufacturing method capable of manufacturing a target containing a refractory metal element without causing ignition. To do.

The memory manufacturing method of the present invention is a method for manufacturing a memory constituted by a plurality of memory elements. Then, Ti, Zr, Hf, V, Nb, Ta and one or more refractory metal elements selected from the element group of lanthanoid elements and Al are used, and the particle size is 100 μm as the refractory metal element used as a raw material. Using the above materials, a step of producing an alloy ingot of an alloy containing only a refractory metal element and Al, a step of pulverizing the alloy ingot, and one or more kinds of chalcogen elements selected from S, Se, and Te One or more elements selected from Ge and Cu are alloyed to produce a second alloy ingot containing a chalcogen element, a second alloy ingot is pulverized, and the pulverized alloy ingot is pulverized. The target manufactured by the manufacturing method of a target including the process of producing a target using a 2nd alloy ingot is used. And using this alloy target, the process of forming the ionization layer of the memory element containing the element to ionize by sputtering is included.

According to the manufacturing method of the memory of the present invention described above, by using a refractory metal element and Al, particle size as the high-melting-point metal element serving as a raw material using a 100μm or more materials, only the high-melting metal element and Al The process of producing the alloy ingot of this alloy, and the process of grind | pulverizing this alloy ingot are included. Thereby, even if a refractory metal element that easily ignites when powdered is used, it is possible to obtain a powder such as a powder material for sintering without causing ignition. Moreover, since the melting point of the alloy ingot is lower than the melting point of the refractory metal element, the difference from the melting point of the chalcogen element is reduced.
Furthermore, one or more kinds of chalcogen elements selected from S, Se and Te are alloyed with one or more elements selected from Ge and Cu to produce a second alloy ingot, and the second alloy ingot is pulverized. The target containing the refractory metal element and the chalcogen element without causing ignition during sintering by the step of producing the target using the pulverized alloy ingot and the pulverized second alloy ingot Can be produced.
And the ionization layer of a memory element is formed using the target manufactured by this manufacturing method. This makes it possible to form an ionized layer containing a refractory metal element with only one target.

Further, according to the method for manufacturing a memory of the present invention, it is possible to form an ionization layer of a memory element that constitutes a memory containing a refractory metal element with only one target.
As a result, the number of cathodes of the film forming apparatus for forming the ionization layer of the memory element can be reduced as compared with the case of using a plurality of targets such as co-sputtering, thereby simplifying the manufacturing apparatus and greatly increasing the throughput. Can be improved.
Furthermore, variations in composition and film thickness between wafers, which tend to be co-sputtering or periodic lamination, can be reduced.

It is a schematic sectional drawing of one Embodiment of the memory element which comprises the memory of this invention. FIG. 4 is a diagram illustrating IV characteristics of a memory element that constitutes the memory of Example 1; FIG. 3 is a diagram illustrating RV characteristics of a memory element that constitutes the memory of Example 1; FIG. 3 is a diagram showing resistance values of a memory element when a rewrite operation is repeatedly performed on the memory element constituting the memory of Example 1. It is the figure which compared the fluctuation | variation of the initial resistance value (median value) of a memory element in each sample of Example 1 and Comparative Example 2.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
The description will be given in the following order.
1. 1. Outline of the present invention 2. Embodiment of memory element and memory Experimental example

<1. Summary of the present invention>
First, prior to the description of embodiments and experimental examples of the present invention, an outline of the present invention will be described.

The target of the present invention contains a refractory metal element, an element other than the refractory metal element (metal element), and a chalcogen element.
The refractory metal element is one or more refractory metal elements selected from Ti, Zr, Hf, V, Nb, Ta, and a group of lanthanoid elements (Ln) (M1 element group).
Other elements (metal elements) other than the refractory metal element are one or more elements selected from Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga (M2 element group).
The chalcogen element is at least one chalcogen element selected from S, Se, and Te.

The target of the present invention containing the above-mentioned three kinds of elements is not present in the past, and a new target can be realized.
Thereby, since the layer containing the three kinds of elements described above can be formed by sputtering using one target, the layer is formed with a stable composition as compared with sputtering using a plurality of targets. Can do.

The method for producing a target of the present invention is a method for producing a target containing a chalcogen element, and performs the following steps.
(1) One or more refractory metal elements selected from Ti, Zr, Hf, V, Nb, Ta, and a group of lanthanoid elements (M1 element group), and other elements other than this element group The process of using and producing an alloy ingot.
(2) A step of pulverizing the alloy ingot.
(3) A step of producing a target using the pulverized alloy ingot and one or more chalcogen elements selected from S, Se, and Te.

The target manufacturing method of the present invention includes the step (1) of producing the alloy ingot and the step (2) of crushing the alloy ingot, and therefore uses a refractory metal element that easily ignites when powdered. Even so, it becomes possible to make the powder without ignition. Moreover, since the melting point of the alloy ingot is lower than the melting point of the refractory metal element, the difference from the melting point of the chalcogen element is reduced.
Further, using the pulverized alloy ingot and the chalcogen element of (3), a target containing a refractory metal element and a chalcogen element is produced without causing ignition during sintering by the process of producing the target. can do.
And even a large target of 100 mmφ or more can be manufactured without the risk of ignition.
Therefore, it is possible to perform film formation on a large-diameter wafer by enlarging the target so as to cope with the increase in size of the wafer.

  In the step of producing the alloy ingot of (1), preferably, a material having a particle size of 100 μm or more is used as a refractory metal element as a raw material. Thereby, the risk of ignition can be further reduced.

  In the step of producing the alloy ingot of (1), it is preferable that the element other than the element group of the refractory metal element is Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, Ga (M2 One or more elements selected from the group of elements) are used. As a result, the melting point of the alloy ingot can be sufficiently lowered than the melting point of the refractory metal element, and the difference from the melting point of the chalcogen element can be reduced. Therefore, the target containing the refractory metal element and the chalcogen element It becomes easy to make.

In the target manufacturing method of the present invention, more preferably, the following steps are performed.
(4) The process of alloying a chalcogen element and other elements other than one or more chalcogen elements to produce a second alloy ingot containing the chalcogen element.
(5) A step of pulverizing the second alloy ingot.
Then, using the alloy ingot pulverized in the step (2) and the second alloy ingot pulverized in the step (5), the step of producing the target (3) is performed.

  In the step (4) of producing the second alloy ingot, it is preferable that the melting point of the second alloy ingot is higher than the melting point of the chalcogen element. If it does in this way, it has the advantage that sintering at the time of producing the 2nd alloy ingot becomes easy.

  In addition, in the step of producing the second alloy ingot of (4), as elements other than the chalcogen element, Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, Ga (M2 element group) One or more elements selected from can be used. In this way, finally, a target containing the refractory metal element, the element of the M2 element group, and the chalcogen element, that is, the above-described target of the present invention can be produced.

The memory according to the present invention includes a plurality of memory elements. The memory element includes an ionization layer containing an element to be ionized.
Further, the ionization layer of the memory element is formed using the target of the present invention.
This makes it possible to form an ionized layer containing a refractory metal element with only one target.

The method for manufacturing a memory according to the present invention applies a target manufacturing method according to the present invention when manufacturing a memory constituted by a plurality of memory elements, and uses the target manufactured by this manufacturing method. An ionization layer of the memory element is formed.
Thereby, it is possible to produce a target containing a refractory metal element and a chalcogen element without causing ignition during pulverization or sintering. Using this target, only one target can be used to produce a refractory metal. An ionized layer containing an element can be formed.

According to the memory and the manufacturing method thereof of the present invention, the ionization layer can be formed with only one target, so that the ionization layer is formed as compared with the case of using a plurality of targets such as cosputtering. The number of cathodes of the film forming apparatus can be reduced.
For this reason, a manufacturing apparatus can be simplified and a throughput can be improved significantly.
Furthermore, it is possible to reduce variations in composition and film thickness between wafers, which tend to be co-sputtering or periodic lamination.

In the memory of the present invention, an ionization layer is formed using the target of the present invention. Therefore, an ionization layer containing the same element as the target, that is, a refractory metal element (element of the M1 element group), a metal element other than the refractory metal element (element of the M2 element group), and a chalcogen element Is formed.
Of the above-described elements constituting the ionized layer, the chalcogen element acts as an ion conductive material that becomes an anion.
Further, Ti, Zr, Hf, which are 4A group transition metal elements of refractory metal elements (elements of the M1 element group), and V, Nb, Ta, which are 5A group transition metal elements, are ionized into cations. Thus, it is reduced on the electrode to form a conductive path (filament) in a metallic state. Similarly, Cu or the like of the M2 element group forms a conductive path (filament) in a metal state.

By providing a lower electrode and an upper electrode in the ionization layer and applying a voltage to the ionization layer of the memory element through these electrodes, the resistance value of the ionization layer is changed, and the memory element is changed according to the state of the resistance value of the ionization layer. Information can be recorded and held in
The outline of the operation of recording information in the memory element is as described below.
When a positive voltage is applied to the memory element in the high resistance state, the ionized metal element (Ti, Zr, etc.) in the ionization layer is ionized to become a cation. This cation conducts ions through the ionized layer and is combined with electrons on the electrode side to be deposited, and a low resistance conduction path (filament) reduced to a metallic state is formed at the interface with the electrode. As a result, the resistance value of the ionization layer of the memory element is lowered and changes from the initial high resistance state to the low resistance state.
On the other hand, when a negative voltage is applied to the memory element in the low resistance state, the metal element in the conduction path is oxidized and ionized, dissolved in the ionized layer or combined with the chalcogen element in the ionized layer, and the conduction path disappears. . As a result, the resistance value of the ionization layer of the memory element is increased and changes from the low resistance state to the high resistance state.
In either case, even if the voltage applied to the memory element is removed after the resistance value of the memory element changes, the state of the resistance value of the memory element is maintained, so that recorded information is retained. be able to.

<2. Embodiment of Memory Element and Memory>
Subsequently, as specific embodiments of the present invention, memory devices constituting the memory and embodiments of the memory will be described.
As an embodiment of the present invention, FIG. 1 shows a schematic cross-sectional view of an embodiment of a memory element constituting a memory.
In the memory element 10, a high resistance layer 12, an ionization layer 13, and an upper electrode 14 are stacked in this order on a lower electrode 11. For example, the lower electrode 11 is formed on a silicon substrate on which a CMOS circuit (not shown) is formed.

For the lower electrode 11 and the upper electrode 14, a wiring material used in a semiconductor process, such as TiW, Ti, W, Cu, Al, Mo, Ta, silicide, or the like can be used.
In addition, when using an electrode material that may cause ion conduction in an electric field such as Cu, it is used by covering the Cu electrode with a material that is difficult to ionize or thermally diffuse such as W, WN, TiN, or TaN. Also good.

An oxide or a nitride is used for the high resistance layer 12. For example, one or more elements selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y among rare earth elements, and Si, An oxide containing Cu is used.
The high resistance layer 12 has a sufficiently higher resistance value than the ionization layer 13.
The high resistance layer 12 is formed thinner than the other layers so that the current flowing through the memory element 10 does not become too small.

The ionized layer 13 can be configured to contain an ionizing element, an element selected from Te, Se, and S (chalcogen element) and other elements.
In the present embodiment, the ionized layer 13 includes a refractory metal element, an element other than the refractory metal element (metal element), and a chalcogen element.
The refractory metal element is one or more refractory metal elements selected from Ti, Zr, Hf, V, Nb, Ta, and a group of lanthanoid elements (Ln) (M1 element group).
Other elements (metal elements) other than the refractory metal element are one or more elements selected from Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga (M2 element group).
The chalcogen element is at least one chalcogen element selected from S, Se, and Te.

Of these elements, the chalcogen element acts as an ion conductive material that becomes an anion.
In addition, Ti, Zr, Hf, which are Group 4A transition metal elements, V, Nb, Ta, which are Group 5A transition metal elements, and Cu, etc. of the M2 element group are ionized to become cations, and the electrodes It is reduced above to form a conductive path (filament) in a metallic state.
Further, Al, Ge, Si, Mg, etc. in the M2 element group are oxidized at the interface between the ionization layer 13 and the electrode when the memory element is changed from the low resistance state to the high resistance state, and thus a stable oxide film. Form.

The high resistance layer 12 and the ionized layer 13 can be collectively referred to as a “storage layer” for recording and storing information.
The memory element 10 having the above-described configuration has a characteristic that the impedance of the memory layer (the high resistance layer 12 and the ionization layer 13) or the impedance of the ionization layer 13 is changed by applying a voltage pulse or a current pulse.

Further, in the present embodiment, the ionization layer 13 of the memory element 10 is formed using a target containing a refractory metal element, an element other than the refractory metal element (metal element), and a chalcogen element (that is, the book described above). Inventive target). As a result, the ionized layer 13 can be formed by using only one target, so that the number of cathodes of the film forming apparatus for forming the ionized layer 13 is reduced as compared with the case of using a plurality of targets such as co-sputtering. it can. For this reason, a manufacturing apparatus can be simplified and a throughput can be improved significantly.
Furthermore, variations in composition and film thickness between wafers, which tend to be co-sputtering or periodic lamination, can be reduced.

The memory element 10 of this embodiment can be operated as follows to store information.
First, for example, a positive potential (+ potential) is applied to the upper electrode 14, and a positive voltage is applied to the memory element 10 so that the lower electrode 11 side becomes negative. As a result, ions of the elements to be ionized from the ionization layer 13 are ion-conducted, combined with electrons on the lower electrode 11 side and deposited, and a conduction path is formed in the high-resistance layer 12, whereby the high-resistance layer 12. The resistance value of becomes low. Each of the layers other than the high resistance layer 12 originally has a lower resistance value than the resistance value of the high resistance layer 12, so that the resistance value of the entire memory element 10 is also lowered by lowering the resistance value of the high resistance layer 12. be able to.

  Thereafter, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by this recording process.

On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM.
In the erasing process, for example, a negative potential (−potential) is applied to the upper electrode 14, and a negative voltage is applied to the memory element 10 so that the lower electrode 11 side becomes positive. Thereby, the element of the conduction path formed in the high resistance layer 12 is oxidized and ionized, and dissolved in the ionized layer 13 or combined with the chalcogen element in the ionized layer 13 to form a compound.
Then, the conduction path disappears or decreases from within the high resistance layer 12, and the resistance value of the high resistance layer 12 increases. Since each layer other than the high resistance layer 12 originally has a low resistance value, the resistance value of the entire memory element 10 can be increased by increasing the resistance value of the high resistance layer 12.

  After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the memory element 10 and erase the recorded information.

  For example, when a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, “0” to “1” are recorded in the process of recording information by applying a positive voltage. Instead, it can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the memory element 10 and the material composition of the high resistance layer 12, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio between the initial resistance value and the resistance value after recording is approximately twice or more. Therefore, it is sufficient if the resistance value before recording is 100Ω, the resistance value after recording is 50Ω, or the resistance value before recording is 100 kΩ, and the resistance value after recording is 50 kΩ. The initial resistance value is set so as to satisfy such a condition.
The resistance value of the high resistance layer 12 can be controlled by, for example, the amount of oxygen contained in the oxide of the high resistance layer 12 before the heat treatment, the oxide film thickness, or the like.

According to the configuration of the memory element 10 described above, the high resistance layer 12 and the ionization layer 13 are sandwiched between the lower electrode 11 and the upper electrode 14. Thereby, when a positive voltage (+ potential) is applied to the upper electrode 14 so that the lower electrode 11 side becomes negative, a conduction path containing a large amount of ionized elements is formed in the high resistance layer 12. Thus, the resistance value of the high resistance layer 12 is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded.
Further, by applying a negative voltage (−potential) to the upper electrode 14 to the memory element 10 in the state after recording as described above so that the lower electrode 11 side becomes positive, The formed conduction path disappears. As a result, the resistance value of the high resistance layer 12 is increased, and the resistance value of the entire memory element 10 is increased. Then, by stopping the application of the negative voltage and preventing the voltage from being applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

By using the memory element 10 having the above-described configuration, a memory (storage device) can be configured by arranging a large number of memory elements 10 such as columns or matrices.
For each memory element 10, wiring connected to the lower electrode 11 side and wiring connected to the upper electrode 14 side are provided, and each memory element 10 is arranged near the intersection of these wirings, for example. You can do so.
If necessary, a memory cell is configured by connecting a memory element selection MOS transistor or a diode to the memory element 10. Further, it is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via wiring.

The memory of the present invention can be applied to various memories.
For example, a PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), and a RAM (random access memory) that can be recorded / erased / reproduced at high speed can be used.

In the above-described embodiment, the high resistance layer 12 is provided in contact with the ionization layer 13. However, in the memory element constituting the memory of the present invention, the high resistance layer is not essential, and there is no high resistance layer. It is also possible.
When the high resistance layer 12 is provided in contact with the ionization layer 13 as in the above-described embodiment, there is an advantage that the information retention characteristic can be further stabilized.

<3. Experimental example>
Next, a target was actually fabricated, and a memory composed of memory elements was manufactured using the fabricated target.
And about the manufactured memory, the characteristic of the memory element was investigated.

Example 1
First, Zr scrap having a size of 1 mm ³ is used as a raw material for Zr of the refractory metal element group M1, and 1 cm ³ of Al pellets and 3 cm ² of Cu thin plate are melted in a high-frequency melting furnace as the raw material for the element group M2. Then, an AlCuZr alloy ingot was produced.
Next, the alloy ingot was pulverized by an atrider to produce an alloy powder having a particle size of 106 μm or less.

Next, the AlCuGeTeZr target base material was obtained by mixing and sintering this alloy powder, Te powder having a particle size of 75 μm or less, and Ge powder having a particle size of 32 to 106 μm.
Next, this target base material was cut into a disk shape having a thickness of 5 mm and a diameter of 300 mm to obtain a target.
And the produced target was adhere | attached on the backing plate of the sputtering device by In soldering.

Next, a Gd oxide film 2 nm was formed as the high resistance layer 12 on the CMOS circuit where the lower electrode 11 made of a W (tungsten) layer was formed.
Subsequently, an AlCuGeTeZr layer having a film thickness of about 60 nm was formed as the ionized layer 13 using the previously prepared target.
Further, a W layer of 50 nm was formed thereon as the upper electrode 14, and the memory element 10 whose cross-sectional structure was shown in FIG.
In this manner, a memory cell array having a large number of memory elements 10 was formed on the wafer to obtain a memory sample of Example 1.

The operating characteristics of the memory elements constituting the sample memory of Example 1 were examined. Specifically, the voltage supplied to the memory element was changed, and changes in the current and the resistance of the memory element were examined.
As a result, the IV characteristic of the memory element is shown in FIG. 2, and the RV characteristic of the memory element is shown in FIG.
As shown in FIGS. 2 and 3, this memory element has a high resistance of about 10 MΩ in the initial state, but the resistance is lowered by biasing the lower electrode 11 side to negative. Next, when the lower electrode 11 side is biased to the plus side, it returns to the high resistance state again, and a good memory operation is shown.

  Further, a voltage pulse with a voltage Vw = 3V, a current of about 100 μA and a pulse width of 10 ns is applied as a write pulse, and a voltage pulse with a voltage of Ve = 2V, a current of about 100 μA and a pulse width of 10 ns is applied as an erase pulse, Repeated rewrite operation was performed. For each rewrite operation, the resistance value in the high resistance state and the resistance value in the low resistance state of the memory element were measured. As a measurement result, the relationship between the number of repetitions and the resistance value of the memory element is shown in FIG.

  As shown in FIG. 4, even when rewriting is performed repeatedly, the resistance values in the high resistance state and the low resistance state do not change greatly, showing good operating characteristics, and good memory operating characteristics are obtained.

(Comparative Example 1)
As a comparative example, as a Zr raw material of the metal element group M1, a powder having a particle size of 106 μm or less, as an Al, Cu, Ge raw material of the element group M2, Al is a powder having a particle size of 53 to 106 μm, Cu is a powder having a particle size of 25 to 35 μm As the Ge, a powder having a particle size of 32 to 106 μm was used. Further, sintering was performed using a powder having a particle size of 75 μm or less as a raw material for Te of the chalcogen element group.
However, since oxygen in the atmosphere and Zr powder reacted and ignited, the target base material could not be produced.

(Example 2)
A Zr scrap having a size of 1 mm ³ was used as a Zr raw material of the metal element group M1, and an Al powder raw material of the element group M2 was mixed and melted in a high-frequency melting furnace to produce an AlZr alloy ingot. This was pulverized to obtain an alloy powder.
Next, Ge, Cu, and Te raw materials were melted in a high frequency melting furnace to prepare an alloy ingot, and then pulverized to obtain an alloy powder.
Next, these two types of alloy powders were mixed so as to have a desired composition ratio and sintered, thereby obtaining an AlCuGeTeZr target base material.
Next, this target base material was cut into a disk shape having a thickness of 5 mm and a diameter of 300 mm to obtain a target.
Thereafter, in the same manner as in Example 1, a memory cell array having a large number of memory elements 10 was formed on a wafer, and a memory sample of Example 2 was obtained.

  When the characteristics of the sample memory of Example 2 were evaluated in the same manner as in Example 1, good memory characteristics could be obtained.

(Comparative Example 2)
In Example 1, the ionized layer 12 of the memory element 10 was formed using an AlCuGeTeZr alloy target.
On the other hand, the ionized layer 12 of the memory element 10 was formed by a co-sputtering method in which four types of targets of Al, Zr, Cu, and GeTe were simultaneously discharged. Other than that was carried out similarly to Example 1, the memory cell array which has many memory elements 10 on the wafer was formed, and it was set as the memory sample of the comparative example 2. FIG.

(Evaluation of initial resistance variation)
The initial resistance of the memory element 10 of each memory sample was measured and the variation was evaluated when the film was formed using the alloy target of Example 1 and when the film was formed by cosputtering of Comparative Example 2. .
Specifically, 11 wafers were put in the same cassette, and the ionized layer 12 was formed on the memory element 10 of each wafer in the film forming apparatus, thereby forming a memory cell array on each wafer. Then, the initial resistance value of the memory element 10 of the 4 kB memory cell array formed near the center of the wafer was measured, and the median value of this resistance value was obtained.
As an evaluation result, FIG. 5 shows variations in the initial resistance value (median value) of the memory element depending on the number of film formations, that is, the number of wafers (first to eleventh sheets).

FIG. 5 shows that when the film is formed by cosputtering in Comparative Example 2, the resistance value increases as the number of film formation increases. On the other hand, when the film was formed using the alloy target of Example 1, it can be seen that the resistance value fluctuates little even when the number of film formation increases.
This is presumably because if the film formation is continued by the co-sputtering method, unnecessary elements adhere to the surface of the target and the film composition fluctuates.
On the other hand, when a single alloy target is used, a target having the same component as that of the film to be deposited is used. Few.
Therefore, it can be said that the film formation of the ionization layer of the memory with the alloy target is less suitable for mass production with less composition fluctuation.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

10 memory element, 11 lower electrode, 12 high resistance layer, 13 ionization layer, 14 upper electrode

Claims (3)

A method of manufacturing a memory composed of a plurality of memory elements,
Ti, Zr, Hf, V, Nb, Ta, and one or more refractory metal elements selected from the element group of lanthanoid elements and Al are used, and the particle size is 100 μm or more as the refractory metal element used as a raw material. A step of producing an alloy ingot of the alloy of only the refractory metal element and Al, a step of pulverizing the alloy ingot, and one or more kinds of chalcogen elements selected from S, Se, and Te Alloying one or more elements selected from Ge and Cu to produce a second alloy ingot containing the chalcogen element, crushing the second alloy ingot, and crushing the alloy ingot using the second alloy ingot was pulverized and, using the target produced by the production method of the target and a step of producing a target
A method for manufacturing a memory, comprising a step of forming an ionization layer of the memory element containing an element to be ionized by sputtering. The method for manufacturing a memory according to claim 1 , wherein the melting point of the second alloy ingot is higher than the melting point of the chalcogen element. 2. The method of manufacturing a memory according to claim 1, wherein the alloy ingot of an AlZr alloy is produced using the refractory metal element as Zr, and Te, Ge, and Cu are alloyed to produce the second alloy ingot.

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