JP5655228B2 - Manufacturing method of semiconductor structure - Google Patents
Manufacturing method of semiconductor structure Download PDFInfo
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- JP5655228B2 JP5655228B2 JP2008223713A JP2008223713A JP5655228B2 JP 5655228 B2 JP5655228 B2 JP 5655228B2 JP 2008223713 A JP2008223713 A JP 2008223713A JP 2008223713 A JP2008223713 A JP 2008223713A JP 5655228 B2 JP5655228 B2 JP 5655228B2
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- 239000004065 semiconductor Substances 0.000 title claims description 163
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 112
- 239000002070 nanowire Substances 0.000 claims description 76
- 150000001875 compounds Chemical class 0.000 claims description 51
- 239000010408 film Substances 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- 239000002994 raw material Substances 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 15
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 14
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical group [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- -1 InGaN Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910002704 AlGaN Inorganic materials 0.000 claims description 3
- 229910017115 AlSb Inorganic materials 0.000 claims description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910005542 GaSb Inorganic materials 0.000 claims description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 3
- 229910021478 group 5 element Inorganic materials 0.000 description 14
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 11
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 9
- 229910000070 arsenic hydride Inorganic materials 0.000 description 9
- 125000004429 atom Chemical group 0.000 description 8
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
- 229910021480 group 4 element Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 150000002902 organometallic compounds Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002073 nanorod Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Crystals, And After-Treatments Of Crystals (AREA)
- Photovoltaic Devices (AREA)
Description
本発明は、半導体基板と、その表面から延びる半導体ナノワイヤとを含む半導体構造物の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor structure including a semiconductor substrate and semiconductor nanowires extending from the surface thereof.
シリコントランジスタを高性能化するために、１）トランジスタを柱状として高密度に集積化すること、２）シリコンよりも電子移動度が高い半導体材料をシリコン基板の一部に集積すること、が提案されている。つまり、シリコン基板上にIII−V族化合物半導体のナノワイヤを成長させれば、シリコントランジスタの高性能化が実現されうる。 In order to improve the performance of silicon transistors, it has been proposed to 1) integrate the transistors in a columnar shape with a high density, and 2) integrate a semiconductor material having a higher electron mobility than silicon on a part of the silicon substrate. ing. That is, if a nanowire of a III-V compound semiconductor is grown on a silicon substrate, high performance of the silicon transistor can be realized.
シリコン基板上にIII−V族化合物半導体（ＧａＰ、ＧａＡｓ、ＩｎＰ、ＩｎＡｓなど）ナノワイヤを成長させた例が報告がされている（非特許文献１〜３を参照）。ところが、これらの報告では、１）シリコン基板上に成長させるナノワイヤを位置制御できなかったり、２）ナノワイヤの成長方向を制御できないなどの問題がある。
前記の通り、シリコン基板上に半導体ナノワイヤを成長させるときに、その成長方向を制御できない、つまり基板面に対して選択的に垂直に成長させることが困難であった。本発明は、シリコンを始めとするIV族半導体基板上に、基板面に対して垂直に延びるIII−V族化合物半導体ナノワイヤを配置することを第一の目的とする。それにより、例えば、シリコントランジスタの高性能化を実現する。また、ゲルマニウム基板にIII−V族化合物半導体ナノワイヤを配置することをも可能として、ゲルマニウム基板上の太陽電池に代表される半導体素子の高性能化を実現する。 As described above, when a semiconductor nanowire is grown on a silicon substrate, the growth direction cannot be controlled, that is, it is difficult to grow selectively perpendicularly to the substrate surface. The first object of the present invention is to dispose III-V compound semiconductor nanowires extending perpendicularly to the substrate surface on a group IV semiconductor substrate such as silicon. Thereby, for example, high performance of the silicon transistor is realized. In addition, it is possible to dispose III-V compound semiconductor nanowires on the germanium substrate, thereby realizing high performance of a semiconductor element typified by a solar cell on the germanium substrate.
III−V族化合物半導体を、シリコン基板を始めとするIV族半導体基板に、成長方向を制御しつつ形成するには、IV族半導体基板の表面の結晶構造が重要である。つまりIII−Ｖ族化合物半導体は、その種類によって、IV族半導体基板の（１１１）Ａ面に対して垂直に成長したり、（１１１）Ｂ面に対して垂直に成長したりする。 In order to form a group III-V compound semiconductor on a group IV semiconductor substrate such as a silicon substrate while controlling the growth direction, the crystal structure of the surface of the group IV semiconductor substrate is important. That is, the group III-V compound semiconductor grows perpendicularly to the (111) A plane of the group IV semiconductor substrate or grows perpendicular to the (111) B plane, depending on the type.
（１１１）Ａ面に対して垂直に成長するIII−V族化合物半導体の例には、ＩｎＰ、ＧａＰ、ＩｎＧａＰが含まれる。一方、その他のIII−V族化合物半導体は、（１１１）Ｂ面に対して垂直に成長する。 Examples of III-V group compound semiconductors grown perpendicular to the (111) A plane include InP, GaP, and InGaP. On the other hand, other group III-V compound semiconductors grow perpendicular to the (111) B plane.
本発明者は、このIV族半導体基板の表面の結晶構造によって、III−V族化合物半導体の成長方向が制御されるという性質を利用することを検討した。その結果、IV族半導体基板の表面の結晶構造を適切に制御することが可能となり、IV速半導体基板に、III−V族化合物半導体を方向制御をしつつ形成することを可能とした。 The present inventor has studied to utilize the property that the growth direction of the III-V compound semiconductor is controlled by the crystal structure of the surface of the group IV semiconductor substrate. As a result, the crystal structure of the surface of the group IV semiconductor substrate can be appropriately controlled, and the group III-V compound semiconductor can be formed on the IV speed semiconductor substrate while controlling the direction.
すなわち本発明は、以下に示す半導体構造物の製造方法に関する。
［１］IV族半導体基板と、前記IV族半導体基板の表面から垂直に延びるIII−V族化合物半導体ナノワイヤとを含む半導体構造物の製造方法であって、
（１１１）面を有するIV族半導体基板と、前記（１１１）面を被覆し、開口部を有する絶縁膜とを含む基板を準備するステップと；前記基板について、化合物半導体ナノワイヤを成長させるのに必要な温度範囲よりも高い温度で高温熱処理を行うことにより生じた（１１１）７×７面を介し、化合物半導体ナノワイヤを成長させるのに必要な温度範囲よりも低い温度で低温熱処理をして（１１１）１×１面とするステップと；前記基板に前記低温熱処理の条件下で、III族原料またはV族原料を供給して、前記（１１１）面を、（１１１）Ａ面または（１１１）Ｂ面に変換するステップと；前記（１１１）Ａ面または（１１１）Ｂ面に、V族原料とIII族原料を交互に供給することで、III−V族化合物半導体の薄膜を形成するステップと；前記III−V族化合物半導体の薄膜を形成した後に、前記IV族半導体基板の表面から前記開口部を通して、III−V化合物半導体ナノワイヤを成長させるステップとを含む、製造方法。
That is, this invention relates to the manufacturing method of the semiconductor structure shown below.
[1] A method for producing a semiconductor structure comprising a group IV semiconductor substrate and a group III-V compound semiconductor nanowire extending vertically from the surface of the group IV semiconductor substrate,
Preparing a substrate comprising a group-IV semiconductor substrate having a (111) plane and an insulating film covering the (111) plane and having an opening; necessary for growing compound semiconductor nanowires on the substrate; The low temperature heat treatment is performed at a temperature lower than the temperature range necessary for growing the compound semiconductor nanowires through the (111) 7 × 7 plane generated by performing the high temperature heat treatment at a temperature higher than the temperature range (111). ) steps and to 1 × 1 surface; under conditions of the low-temperature heat treatment to the substrate, by supplying the group III source or group V material, said (111) plane, (111) a plane or (111) B Converting into a plane; forming a thin film of a III-V group compound semiconductor by alternately supplying a group V source and a group III source to the (111) A plane or the (111) B plane; III-V grouping Forming a compound semiconductor thin film, and then growing a III-V compound semiconductor nanowire from the surface of the group IV semiconductor substrate through the opening.
［２］前記開口部を有する絶縁膜を含む基板を準備した後に、前記基板を高温熱処理することにより、前記IV半導体基板の表面に形成された自然酸化膜を除去するステップ、をさらに含む、［１］に記載の製造方法。
［３］前記（１１１）Ａ面または（１１１）Ｂ面に、V族原料とIII族原料を交互に供給するステップは、前記変換された面が前記（１１１）Ａ面のときはまずIII族原料を供給し、その後V族原料とIII族原料を交互に供給し、前記変換された面が前記（１１１）Ｂ面のときはまずV族原料を供給し、その後III族原料とV族原料を交互に供給する、［１］に記載の製造方法。
［４］前記（１１１）面を（１１１）１×１面とするステップと、前記（１１１）面を前記（１１１）Ａ面または（１１１）Ｂ面に変換するステップとを、順に行なうか、または同時に行う、［１］に記載の製造方法。
[2] After preparing a substrate including an insulating film having the opening, the substrate further includes a step of removing a natural oxide film formed on the surface of the IV semiconductor substrate by performing a high-temperature heat treatment on the substrate. 1].
[3] The step of alternately supplying the group V raw material and the group III raw material to the (111) A surface or the (111) B surface is such that when the converted surface is the (111) A surface, first the group III The raw material is supplied, and then the Group V raw material and the Group III raw material are alternately supplied . When the converted surface is the (111) B surface, the Group V raw material is supplied first, and then the Group III raw material and the Group V raw material are supplied. Are alternately supplied . The production method according to [1].
[4] The step of setting the (111) plane as a (111) 1 × 1 plane and the step of converting the (111) plane into the (111) A plane or the (111) B plane are sequentially performed. Or the manufacturing method as described in [1] performed simultaneously.
［５］前記IV族半導体基板はシリコン基板またはゲルマニウム基板である、［１］に記載の製造方法。
［６］前記III族原料は、ホウ素、アルミニウム、ガリウム、インジウムおよびタリウムのいずれかを含むガスまたはそれに類する化合物である、［１］に記載の製造方法。
［７］前記V族原料は、窒素、リン、ヒ素、アンチモン、ビスマスのいずれかを含むガスまたはそれに類する化合物である、［１］に記載の製造方法。
［８］前記III−V化合物半導体は、ＩｎＡｓ、ＩｎＰ、ＧａＡｓ、ＧａＮ、ＩｎＳｂ、ＧａＳｂ、ＡｌＳｂ、ＡｌＧａＡｓ、ＩｎＧａＡｓ、ＩｎＧａＮ、ＡｌＧａＮ、ＧａＮＡｓ、ＩｎＡｓＳｂ、ＧａＡｓＳｂ、ＩｎＧａＳｂ、ＡｌＩｎＳｂ、ＩｎＧａＡｌＮ、ＡｌＩｎＧａＰ、ＩｎＧａＡｓＰまたはＧａＩｎＡｓＮ、ＩｎＧａＡｌＳｂ、ＩｎＧａＡｓＳｂ、ＡｌＩｎＧａＰＳｂである、［１］に記載の製造方法。
［９］前記（１１１）面を被覆する絶縁膜は、前記IV族半導体基板の表面の熱酸化膜である、［１］に記載の製造方法。
[5] The manufacturing method according to [1], wherein the group IV semiconductor substrate is a silicon substrate or a germanium substrate.
[6] The manufacturing method according to [1], wherein the group III raw material is a gas containing any of boron, aluminum, gallium, indium, and thallium or a similar compound.
[7] The production method according to [1], wherein the group V raw material is a gas containing any of nitrogen, phosphorus, arsenic, antimony, and bismuth or a similar compound.
[8] The III-V compound semiconductor is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, or GaInAsN. The manufacturing method according to [1], which is InGaAlSb, InGaAsSb, or AlInGaPSb.
[9] The manufacturing method according to [1], wherein the insulating film covering the (111) plane is a thermal oxide film on the surface of the group IV semiconductor substrate.
さらに本発明は、以下に示す半導体構造物に関する。
［１０］IV族半導体基板と、前記IV族半導体基板の（１１１）面を（１１１）１×１面を経て変換された（１１１）Ａ面または（１１１）Ｂ面の表面から延びる、複数本のIII−V族化合物半導体ナノワイヤとを含む半導体構造物であって、前記複数本のIII−V族化合物半導体ナノワイヤのうちの９０％以上が、前記IV族半導体基板の前記（１１１）Ａ面または前記（１１１）Ｂ面の表面から垂直に延びている、半導体構造物。
［１１］前記IV族半導体基板の表面１ｃｍ2あたり、１億本以上の前記III−V族化合物半導体ナノワイヤを有する、［１０］に記載の半導体構造物。
Furthermore, this invention relates to the semiconductor structure shown below.
[10] A group IV semiconductor substrate and a plurality of (111) planes of the group IV semiconductor substrate extending from the (111) A plane or (111) B plane converted through the (111) 1 × 1 plane Of the group III-V compound semiconductor nanowires, wherein 90% or more of the plurality of group III-V compound semiconductor nanowires is the (111) A plane of the group IV semiconductor substrate or A semiconductor structure extending vertically from the surface of the (111) B surface .
[11] The semiconductor structure according to [10], which has 100 million or more of the III-V compound semiconductor nanowires per 1 cm 2 of the surface of the group IV semiconductor substrate.
本発明により、シリコンを始めとするIV族半導体基板に、III-V族化合物半導体ナノワイヤを、基板表面に垂直に、かつ高密度に配置することができる。それにより、シリコントランジスタなどの高性能化やゲルマニウム基板上の太陽電池の高効率化に寄与する。 According to the present invention, III-V compound semiconductor nanowires can be arranged on a group IV semiconductor substrate such as silicon at a high density perpendicular to the substrate surface. This contributes to higher performance of silicon transistors and the like and higher efficiency of solar cells on germanium substrates.
半導体構造物について
本発明における半導体構造物とは、IV族半導体基板と、IV族半導体基板の表面から延びるIII−V族化合物半導体ナノワイヤとを有する。IV族半導体基板の表面には、複数本のナノワイヤが配置されていてもよい。
About Semiconductor Structure The semiconductor structure in the present invention includes a group IV semiconductor substrate and a group III-V compound semiconductor nanowire extending from the surface of the group IV semiconductor substrate. A plurality of nanowires may be arranged on the surface of the group IV semiconductor substrate.
本発明における半導体構造物は、IV族半導体基板の表面から垂直に延びる半導体ナノワイヤを選択的に有しており、一方で、IV族半導体基板の表面から垂直ではなく、斜めに（例えば基板表面との交差角度が約２０℃）延びる半導体ナノワイヤをあまり有さないことを特徴とする。選択的とは、例えば半導体ナノワイヤの総本数に対して通常は６０％以上、好ましくは８０％以上、より好ましくは９０％以上の半導体ナノワイヤが、基板表面に対して垂直に延びていることをいう。 The semiconductor structure according to the present invention selectively includes semiconductor nanowires extending perpendicularly from the surface of the group IV semiconductor substrate, while not obliquely perpendicular to the surface of the group IV semiconductor substrate (for example, with the substrate surface). It is characterized by few semiconductor nanowires extending at an intersection angle of about 20 ° C. “Selective” means that, for example, 60% or more, preferably 80% or more, more preferably 90% or more of semiconductor nanowires extend perpendicularly to the substrate surface with respect to the total number of semiconductor nanowires. .
このように、半導体ナノワイヤが、基板表面に対して選択的に垂直に配置されているので、高密度に配置することも可能となる。例えば、ナノワイヤの配列周期をナノメートル領域の精度で制御することが可能で、1平方センチメートル当たりのナノワイヤの本数を 1０億本以上、さらには１０００億本以上の高密度に配列することができる。ナノワイヤの太さは、直径（例えば、円相当径）が２００ｎｍ、さらには５０ｎｍ以下にすることができる。 As described above, since the semiconductor nanowires are selectively arranged perpendicularly to the substrate surface, they can be arranged at high density. For example, the arrangement period of nanowires can be controlled with accuracy in the nanometer range, and the number of nanowires per square centimeter can be arranged at a high density of 100 billion or more, and further 100 billion or more. As for the thickness of the nanowire, the diameter (for example, equivalent circle diameter) can be set to 200 nm, and further to 50 nm or less.
本発明における半導体構造物のIV族半導体の例には、シリコン半導体やガリウム半導体が含まれる。また、III−V族化合物半導体は、２つの元素からなる半導体、３つの元素からなる半導体、４つの元素からなる半導体、それ以上の元素からなる半導体のいずれでもよい。２つの元素からなる半導体の例には、ＩｎＡｓ、ＩｎＰ、ＧａＡｓ、ＧａＮ，ＩｎＳｂ、ＧａＳｂ、ＡｌＳｂが含まれ；３つの元素からなる半導体の例には、ＡｌＧａＡｓ、ＩｎＧａＡｓ、ＩｎＧａＮ、ＡｌＧａＮ、ＧａＮＡｓ、ＩｎＡｓＳｂ、ＧａＡｓＳｂ、ＩｎＧａＳｂ、ＡｌＩｎＳｂが含まれ；４つ以上の元素からなる半導体の例には、ＩｎＧａＡｌＮ、ＡｌＩｎＧａＰ、ＩｎＧａＡｓＰ、ＧａＩｎＡｓＮ、ＩｎＧａＡｌＳｂ、ＩｎＧａＡｓＳｂ、ＡｌＩｎＧａＰＳｂが含まれる。 Examples of the group IV semiconductor of the semiconductor structure in the present invention include a silicon semiconductor and a gallium semiconductor. The III-V compound semiconductor may be a semiconductor composed of two elements, a semiconductor composed of three elements, a semiconductor composed of four elements, or a semiconductor composed of more elements. Examples of semiconductors consisting of two elements include InAs, InP, GaAs, GaN, InSb, GaSb, AlSb; examples of semiconductors consisting of three elements include AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb. , GaAsSb, InGaSb, AlInSb; examples of semiconductors composed of four or more elements include InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb, and AlInGaPSb.
従来、「ＶＬＳ法」という、触媒金属を用いた手法で得られていたナノワイヤは、成長中に触媒金属が不純物として混入する難点があった。これと比較して、本発明の選択成長法によれば、結晶内の不純物がより少ない、高品質な半導体ナノワイヤを得ることができる。 Conventionally, nanowires obtained by a technique using a catalyst metal called “VLS method” have a problem that the catalyst metal is mixed as an impurity during growth. Compared with this, according to the selective growth method of the present invention, it is possible to obtain a high-quality semiconductor nanowire with fewer impurities in the crystal.
半導体構造物の製造プロセスについて
本発明における半導体構造物は、（１１１）面を有するIV半導体基板１であって、その（１１１）面１−１が、開口部３を有する絶縁膜２で被覆されている基板を準備するステップ（図１Ｃ参照）と；半導体ナノワイヤ４を成長させるステップとを含む（図１Ｄ参照）。
Manufacturing Process of Semiconductor Structure A semiconductor structure in the present invention is an IV semiconductor substrate 1 having a (111) plane, and the (111) plane 1-1 is covered with an insulating film 2 having an opening 3. Preparing a substrate (see FIG. 1C); and growing semiconductor nanowires 4 (see FIG. 1D).
IV半導体基板１は、（１１１）面１−１を有していればよく、例えばｎ型シリコン（１１１）基板である（図１Ａ参照）。図１Ｂに示されるように、IV族半導体基板１の（１１１）面１−１を覆う絶縁膜２を配置する。絶縁膜２の材質は特に限定されず、無機絶縁材料からなる膜であればよい。無機絶縁材料の例には、酸化シリコン、窒化シリコンなどが含まれる。酸化シリコン膜は、例えばシリコン基板を熱酸化して形成することができる。もちろん、スパッタ法などの通常の薄膜形成法で形成してもよい。IV族半導体基板１の（１１１）面１−１を被覆する絶縁膜２の厚さは特に限定されず、数十ｎｍであればよいが、２０ｎｍ以下であることが好ましい。 The IV semiconductor substrate 1 only needs to have the (111) plane 1-1, and is, for example, an n-type silicon (111) substrate (see FIG. 1A). As shown in FIG. 1B, an insulating film 2 covering the (111) plane 1-1 of the group IV semiconductor substrate 1 is disposed. The material of the insulating film 2 is not particularly limited as long as it is a film made of an inorganic insulating material. Examples of the inorganic insulating material include silicon oxide and silicon nitride. The silicon oxide film can be formed, for example, by thermally oxidizing a silicon substrate. Of course, you may form by normal thin film formation methods, such as a sputtering method. The thickness of the insulating film 2 covering the (111) plane 1-1 of the group IV semiconductor substrate 1 is not particularly limited and may be several tens of nm, but is preferably 20 nm or less.
IV族半導体基板１の（１１１）面１−１を被覆する絶縁膜２には、一つまたは二つ以上の開口部３が形成される。絶縁膜２の開口部３は、電子線（ＥＢ）リソグラフィーや、フォトリソグラフィーを用いて、IV族半導体基板１の（１１１）面１−１を被覆する絶縁膜２をパターニングして形成すればよい。開口部３を通してIV族半導体基板１の（１１１）面１−１が露出している。 One or two or more openings 3 are formed in the insulating film 2 covering the (111) plane 1-1 of the group IV semiconductor substrate 1. The opening 3 of the insulating film 2 may be formed by patterning the insulating film 2 covering the (111) surface 1-1 of the group IV semiconductor substrate 1 using electron beam (EB) lithography or photolithography. . The (111) plane 1-1 of the group IV semiconductor substrate 1 is exposed through the opening 3.
絶縁膜２の開口部３の形状は任意であり、矩形、三角形、六角形、または円形などのいずれでもよい。開口部３の開口面積は特に制限されないが、開口部３を通して半導体ナノワイヤ４を成長させる（後述）ので、所望の半導体ナノワイヤ４の太さに応じて、開口部３の面積を設定する。つまり、開口部３の面積が小さいほど細い半導体ナノワイヤ４を成長させることができる。開口部３の開口面積の円相当径の目安は、約３０〜６００ｎｍである。 The shape of the opening 3 of the insulating film 2 is arbitrary, and may be any of a rectangle, a triangle, a hexagon, or a circle. The opening area of the opening 3 is not particularly limited, but the semiconductor nanowire 4 is grown through the opening 3 (described later), so the area of the opening 3 is set according to the desired thickness of the semiconductor nanowire 4. That is, as the area of the opening 3 is smaller, the thinner semiconductor nanowire 4 can be grown. The standard of the equivalent circle diameter of the opening area of the opening 3 is about 30 to 600 nm.
IV族半導体基板１の表面には、通常、自然酸化膜が形成されている。この自然酸化膜は、半導体ナノワイヤ４の成長（後述）を阻害するので、除去されることが好ましい。そこで、IV半導体基板１の（１１１）面１−１を覆う絶縁膜２に開口部３を設けた後、高温熱処理することにより、IV半導体基板１の表面に形成された自然酸化膜を除去することが好ましい。高温熱処理は、水素ガスや、窒素ガス、アルゴンガスのような不活性ガス雰囲気中で行えばよく、約９００℃の条件で熱処理すればよい。 A natural oxide film is usually formed on the surface of the group IV semiconductor substrate 1. Since this natural oxide film inhibits the growth (described later) of the semiconductor nanowire 4, it is preferably removed. Therefore, the natural oxide film formed on the surface of the IV semiconductor substrate 1 is removed by providing an opening 3 in the insulating film 2 covering the (111) plane 1-1 of the IV semiconductor substrate 1 and then performing high-temperature heat treatment. It is preferable. The high-temperature heat treatment may be performed in an inert gas atmosphere such as hydrogen gas, nitrogen gas, or argon gas, and may be heat-treated at about 900 ° C.
高温熱処理により自然酸化膜を除去するとともに、IV族半導体と自然酸化膜との界面の結晶構造から、酸素原子が除去されると考えられる。除去された酸素原子の代わりに、後述のIII族原子またはV族原子が吸着すると考えられる（後に詳細に説明する）。 It is considered that the natural oxide film is removed by high-temperature heat treatment, and oxygen atoms are removed from the crystal structure at the interface between the group IV semiconductor and the natural oxide film. It is considered that a group III atom or group V atom described later is adsorbed instead of the removed oxygen atom (described in detail later).
高温熱処理後の（１１１）面は、１×１構造で構成される。ところが、そのまま基板の温度を下げると、図２に示した分類（化合物半導体成長温度範囲）のように不規則な原子配列が基板表面に形成される。しかしながら、さらに温度を４００℃程度にまで下げると再び、基板表面が１×１構造に回復する。 The (111) plane after the high-temperature heat treatment has a 1 × 1 structure. However, when the temperature of the substrate is lowered as it is, an irregular atomic arrangement is formed on the substrate surface as shown in the classification (compound semiconductor growth temperature range) shown in FIG. However, when the temperature is further lowered to about 400 ° C., the substrate surface is restored to the 1 × 1 structure again.
そこで本発明におけるプロセスは、高温熱処理後に、一旦、低温（約４００℃程度）にまで基板温度を下げることを特徴とする。低温とは、化合物半導体ナノワイヤを成長させるのに必要な温度よりも低い。それにより、（１１１）面を、（１１１）１×１面に変換する。（１１１）面とは、図３Ａに示されるように、原子配列を構成する最小単位が２原子間隔×１原子間隔となっている面をいう。つまり（１１１）面は、（１１１）１×２面とも称される。一方、（１１１）１×１面とは、図３Ｂに示されるように、原子配列を構成する最小単位が１原子間隔×１原子間隔となっている面をいう。 Therefore, the process in the present invention is characterized in that the substrate temperature is once lowered to a low temperature (about 400 ° C.) after the high-temperature heat treatment. Low temperature is lower than the temperature required to grow compound semiconductor nanowires. Thereby, the (111) plane is converted into a (111) 1 × 1 plane. As shown in FIG. 3A, the (111) plane refers to a plane in which the minimum unit constituting the atomic arrangement is 2 atomic intervals × 1 atomic interval. That is, the (111) plane is also referred to as a (111) 1 × 2 plane. On the other hand, as shown in FIG. 3B, the (111) 1 × 1 plane refers to a plane in which the minimum unit constituting the atomic arrangement is 1 atomic interval × 1 atomic interval.
後述の通り、IV族半導体基板の（１１１）１×１面は、III族元素またはV族元素により、（１１１）Ａ面または（１１１）Ｂ面に変換される。ここで、（１１１）Ａ面とは表面にIII族元素が配置している面を、（１１１）Ｂ面とはＶ族元素が配置している面をいう。 As will be described later, the (111) 1 × 1 plane of the group IV semiconductor substrate is converted into a (111) A plane or a (111) B plane by a group III element or a group V element. Here, the (111) A plane is a plane on which a group III element is arranged, and the (111) B plane is a plane on which a group V element is arranged.
IV族半導体基板の（１１１）１×１面を、（１１１）Ａ面または（１１１）Ｂ面にすると、その面からIII−V族化合物半導体を成長させやすくなる。III−V族化合物半導体の（１１１）Ａ面または（１１１）Ｂ面は、（１１１）２×２面、つまり最小単位が２原子間隔×２原子間隔の周期で構成された構造である。よって、IV族半導体基板の表面に、２原子間隔×２原子間隔よりも小さい最小単位でIII元素またはV族元素が配置されていると、その表面にIII−V族化合物半導体が成長しやすい。 When the (111) 1 × 1 plane of the group IV semiconductor substrate is a (111) A plane or a (111) B plane, a III-V group compound semiconductor is easily grown from that plane. The (111) A plane or the (111) B plane of the III-V compound semiconductor has a (111) 2 × 2 plane, that is, a structure in which the minimum unit is a period of 2 atomic intervals × 2 atomic intervals. Therefore, when a group III element or group V element is arranged on the surface of the group IV semiconductor substrate in a minimum unit smaller than 2 atom intervals × 2 atom intervals, a III-V group compound semiconductor is likely to grow on the surface.
一方、シリコン基板を熱処理することによって生じやすい（１１１）面の安定構造は、（１１１）７×７面であると報告されている（Surf. Sci. 164 (1985) 367）。（１１１）７×７面を、（１１１）Ａ面または（１１１）Ｂ面に変換しても、最小単位が７原子間隔×７原子間隔の配列周期となる。この最小単位は、III−V族化合物半導体の結晶構造における配列周期の最小単位よりも大きすぎる。よって、その表面にIII−V族化合物半導体は成長しにくい。 On the other hand, it has been reported that the stable structure of the (111) plane that is likely to occur by heat treatment of the silicon substrate is the (111) 7 × 7 plane (Surf. Sci. 164 (1985) 367). Even if the (111) 7 × 7 plane is converted to the (111) A plane or the (111) B plane, the minimum unit is an array period of 7 atomic intervals × 7 atomic intervals. This minimum unit is too larger than the minimum unit of the arrangement period in the crystal structure of the III-V compound semiconductor. Therefore, the III-V compound semiconductor is difficult to grow on the surface.
（１１１）面を、（１１１）１×１面にするための低温熱処理は、約３５０〜４５０℃（例えば、約４００℃）の温度で行えばよい。また低温とは、半導体ナノワイヤを成長させるために必要な温度よりも低い。低温熱処理は、水素ガス、窒素ガス、アルゴンガス、ヘリウムガスなどの不活性ガス囲気下で行うことが好ましい。 The low temperature heat treatment for making the (111) plane into the (111) 1 × 1 plane may be performed at a temperature of about 350 to 450 ° C. (for example, about 400 ° C.). The low temperature is lower than the temperature necessary for growing semiconductor nanowires. The low-temperature heat treatment is preferably performed in an atmosphere of an inert gas such as hydrogen gas, nitrogen gas, argon gas, or helium gas.
IV半導体基板の（１１１）面を低温熱処理により（１１１）１×１面に変換するとともに、III族原料またはV族原料を供給して、（１１１）Ａ面または（１１１）Ｂ面に変換する。III族原料とは、ホウ素、アルミニウム、ガリウム、インジウムおよびタリウムのいずれかを含むガス（有機金属化合物であってもよい）であることが好ましく、例えばトリメチルインジウムなどの有機アルキル金属化合物である。Ｖ族原料とは、窒素、リン、ヒ素、アンチモン、ビスマスのいずれかを含むガス（有機金属化合物であってもよい）であることが好ましく、例えばアルシンである。III族原料またはV族原料の供給は、４００〜５００℃にて行うことが好ましい。 The (111) surface of the IV semiconductor substrate is converted into a (111) 1 × 1 surface by low-temperature heat treatment, and a group III material or a group V material is supplied to convert it to a (111) A surface or a (111) B surface. . The group III raw material is preferably a gas containing any one of boron, aluminum, gallium, indium and thallium (which may be an organometallic compound), for example, an organic alkyl metal compound such as trimethylindium. The group V raw material is preferably a gas containing any of nitrogen, phosphorus, arsenic, antimony, and bismuth (which may be an organometallic compound), such as arsine. The supply of the Group III material or the Group V material is preferably performed at 400 to 500 ° C.
（１１１）Ａ面または（１１１）Ｂ面への変換は、（１１１）１×１面への変換の後に行ってもよいが、同時に行ってもよい。つまり、（１１１）面を、約４００℃での低温熱処理により（１１１）１×１面に変換しながら、III族原料またはV族原料も供給して（１１１）Ａ面または（１１１）Ｂ面に変換することもできる。 The conversion to the (111) A plane or the (111) B plane may be performed after the conversion to the (111) 1 × 1 plane, but may be performed simultaneously. In other words, the (111) plane is converted to the (111) 1 × 1 plane by low-temperature heat treatment at about 400 ° C., and the group III material or the group V material is supplied to the (111) plane or the (111) plane B. Can also be converted.
前記の通り、IV族半導体基板の（１１１）面を、高温（例えば９００℃）熱処理して自然酸化膜を除去するときに、酸素原子が除去される。酸素原子が除去された状態で（１１１）面とすると、IV族元素同士の結合が切れている部分が形成される。高温熱処理したあとの（１１１）面は、図２に示すように１×１構造で構成され、そのまま温度を下げると、図２の分類に記した、様々な不規則な原子配列周期が表面に形成される。さらに温度を４００℃程度まで下げることで、１×１構造に回復する。回復した１×１構造は、熱力学的に不安定であり、この状態にIII族元素またはV族元素を供給すると、III族元素またはV族元素は、最表面のSi原子と置き換わるようにIII族原子またはV族原子が表面吸着して、（１１１）Ａ面または（１１１）Ｂ面を形成する。このため、比較的容易に、（１１１）Ａ面または（１１１）Ｂ面が得られる。 As described above, when the (111) plane of the group IV semiconductor substrate is heat-treated at a high temperature (for example, 900 ° C.) to remove the natural oxide film, oxygen atoms are removed. When the (111) plane is formed in a state where oxygen atoms are removed, a portion where bonds between group IV elements are broken is formed. The (111) plane after the high-temperature heat treatment has a 1 × 1 structure as shown in FIG. 2. When the temperature is lowered as it is, various irregular atomic arrangement periods described in the classification of FIG. It is formed. Further, by reducing the temperature to about 400 ° C., the 1 × 1 structure is restored. The recovered 1 × 1 structure is thermodynamically unstable, and when a group III element or group V element is supplied to this state, the group III element or group V element is replaced with a surface Si atom. Group atoms or Group V atoms are adsorbed on the surface to form (111) A plane or (111) B plane. For this reason, the (111) A surface or the (111) B surface can be obtained relatively easily.
交互原料供給変調法について
次に、（１１１）Ａ面または（１１１）Ｂ面に変換された（１１１）面に、さらにIII族元素を含む原料ガスと、V族元素を含む原料ガスとを、交互に提供する（「交互原料供給変調」ともいう）ことが好ましい。これにより、絶縁膜の開口部を通して露出した基板表面に、III−V化合物半導体の薄膜を形成する。この交互原料供給変調法による薄膜形成は、III−Ｖ族化合物半導体ナノロッドを成長させる（後述）ために必要な温度よりも低い温度にて行うことが好ましい。具体的には約４００℃で行うか、または４００℃から昇温しながら行ってもよい。
About the alternate raw material supply modulation method Next, on the (111) plane converted to the (111) A plane or the (111) B plane, a source gas further containing a group III element, and a source gas containing a group V element, It is preferable to provide them alternately (also referred to as “alternating raw material supply modulation”). Thereby, a thin film of a III-V compound semiconductor is formed on the substrate surface exposed through the opening of the insulating film. The thin film formation by this alternate material supply modulation method is preferably performed at a temperature lower than that required for growing III-V compound semiconductor nanorods (described later). Specifically, it may be carried out at about 400 ° C. or while raising the temperature from 400 ° C.
具体的には、（１１１）Ａ面が形成されている場合は、まずIII族元素を含む原料ガスを供給し；その後、V族元素を含む原料ガス供給する。さらに、III族元素を含む原料ガスとV族元素を含む原料ガスとを交互に繰り返し供給する。
一方、（１１１）Ｂ面が形成されている場合は、まずV族元素を含む原料ガスを供給し；その後、III族元素を含む原料ガス供給する。さらに、V族元素を含む原料ガスとIII族元素を含む原料ガスとを交互に繰り返し供給する。
Specifically, when the (111) A plane is formed, first, a source gas containing a group III element is supplied; then, a source gas containing a group V element is supplied. Further, a source gas containing a group III element and a source gas containing a group V element are alternately and repeatedly supplied.
On the other hand, when the (111) B surface is formed, first, a source gas containing a group V element is supplied; then, a source gas containing a group III element is supplied. Further, a source gas containing a group V element and a source gas containing a group III element are alternately and repeatedly supplied.
V族元素を含む原料ガスとIII族元素を含む原料ガスとを、それぞれ数秒供給し、互いの供給の間に数秒のインターバルを設けることが好ましい。化合物半導体の薄膜が所望の厚さになるまで、V族元素を含む原料ガスとIII族元素を含む原料ガスとを交互に供給すればよい。何回か繰り返してガスを供給することにより、III−V化合物半導体の薄膜を形成する。 It is preferable to supply a source gas containing a group V element and a source gas containing a group III element for several seconds, respectively, and provide an interval of several seconds between the supply. A source gas containing a group V element and a source gas containing a group III element may be alternately supplied until the compound semiconductor thin film has a desired thickness. By repeatedly supplying the gas several times, a thin film of III-V compound semiconductor is formed.
この交互原料供給変調は、（１１１）Ａ面または（１１１）Ｂ面に変換したときに変換できなかった部位があったとしても、（１１１）Ａ面または（１１１）Ｂ面を再形成することができるという、補償効果もある。交互原料供給変調により、IV族元素とIII族元素またはＶ族元素が結合するからである。 This alternate material supply modulation re-forms the (111) A surface or the (111) B surface even if there is a portion that could not be converted when converted to the (111) A surface or the (111) B surface. There is also a compensation effect that can be done. This is because the group IV element and the group III element or the group V element are bonded by the alternating raw material supply modulation.
この後、半導体ナノワイヤを成長させるために基板温度を上げるが、交互原料供給変調により形成されたIII−V化合物半導体の薄膜は、基板に吸着したIII族元素やIV族元素が熱で乖離することを防ぐこともできる。 After this, the substrate temperature is raised in order to grow semiconductor nanowires, but the III-V compound semiconductor thin film formed by alternating source supply modulation has the group III elements and group IV elements adsorbed on the substrate separated by heat. Can also be prevented.
III−V化合物半導体の薄膜を形成した後に、IV族半導体基板の表面から、絶縁膜の開口部を通して、III−V族化合物半導体を成長させて、半導体ナノワイヤを成長させる（図１Ｄ）。III−V族化合物半導体ナノワイヤの成長は、例えば、有機金属化学気相エピタキシ法（「ＭＯＶＰＥ法」ともいう）や、分子線エピタキシ法（「ＭＢＥ法」ともいう）により行われるが、好ましくはＭＯＶＰＥ法により行われる。 After forming a thin film of a III-V compound semiconductor, a group III-V compound semiconductor is grown from the surface of the group IV semiconductor substrate through the opening of the insulating film to grow semiconductor nanowires (FIG. 1D). The growth of the group III-V compound semiconductor nanowire is performed by, for example, a metal organic chemical vapor phase epitaxy method (also referred to as “MOVPE method”) or a molecular beam epitaxy method (also referred to as “MBE method”), but preferably MOVPE. Done by law.
ＭＯＶＰＥ法による半導体ナノワイヤの形成は、通常のＭＯＶＰＥ装置を用いて行うことができる。つまり、所定の温度にて減圧条件下で、III族元素を含む原料ガスと、V族元素を含む原料ガスとを提供することが好ましい。
例えば、ＩｎＡｓナノワイヤを形成するときは、約５４０℃にて、水素化ヒ素（ＡｓＨ３）とトリメチルインジウムを提供すればよい。また、ＧａＡｓナノワイヤを形成するときは、約７５０℃にて、水素化ヒ素（ＡｓＨ３）とトリメチルガリウムを提供すればよい。
Formation of semiconductor nanowires by the MOVPE method can be performed using a normal MOVPE apparatus. That is, it is preferable to provide a source gas containing a group III element and a source gas containing a group V element under a reduced pressure condition at a predetermined temperature.
For example, when forming InAs nanowires, arsenic hydride (AsH 3 ) and trimethylindium may be provided at about 540 ° C. When forming GaAs nanowires, arsenic hydride (AsH 3 ) and trimethylgallium may be provided at about 750 ° C.
本発明の半導体構造物の製造方法によれば、IV族半導体基板の表面を（１１１）１×１面として、かつ（１１１）Ａ面またはＢ面にしているので、III−V族化合物半導体を、基板表面に対して垂直に成長させることができる。 According to the method for manufacturing a semiconductor structure of the present invention, the surface of the group IV semiconductor substrate is the (111) 1 × 1 plane and the (111) A plane or the B plane. Can be grown perpendicular to the substrate surface.
［実施例１］シリコン基板面へのＩｎＡｓナノワイヤの形成
ｎ型シリコン（１１１）半導体基板を、熱酸化処理して、表面に２０ｎｍの酸化シリコン膜を形成した。形成された酸化シリコン膜を、電子線ビームリソグラフィとウェットケミカルエッチングにより開口させて、シリコン表面を露出させた。開口の形状を六角形として、開口の面積円相当径は６０ｎｍとした。
[Example 1] Formation of InAs nanowires on a silicon substrate surface An n-type silicon (111) semiconductor substrate was thermally oxidized to form a 20 nm silicon oxide film on the surface. The formed silicon oxide film was opened by electron beam lithography and wet chemical etching to expose the silicon surface. The shape of the opening was hexagonal, and the area circle equivalent diameter of the opening was 60 nm.
得られた基板を、減圧横型MOVPE装置（大陽日酸製HR2339）にセットした。MOVPE装置の内圧は０．１atmにすることができる。基板にセットしたMOVPE装置の内温を９２５℃に上昇させて、同温度にて５分間維持した（図４Ａの符号１０参照）。これにより、基板表面に形成された自然酸化膜を除去した。 The obtained substrate was set in a reduced pressure horizontal MOVPE apparatus (HR2339 manufactured by Taiyo Nippon Sanso). The internal pressure of the MOVPE device can be 0.1 atm. The internal temperature of the MOVPE apparatus set on the substrate was raised to 925 ° C. and maintained at that temperature for 5 minutes (see reference numeral 10 in FIG. 4A). Thereby, the natural oxide film formed on the substrate surface was removed.
その後、装置の内温を９２５℃から４００℃に降温した。４００℃にて水素化ヒ素（ＡｓＨ３）を、キャリアガスである水素ガスとともに供給した（図４Ａの符号１１参照）。水素化ヒ素の分圧を１．３×１０−４atmとした。 Thereafter, the internal temperature of the apparatus was lowered from 925 ° C. to 400 ° C. Arsenic hydride (AsH 3 ) was supplied at 400 ° C. together with hydrogen gas as a carrier gas (see reference numeral 11 in FIG. 4A). The partial pressure of arsenic hydride was 1.3 × 10 −4 atm.
次に、交互原料供給変調法によりＩｎＡｓの薄膜を形成した（図４Ａの符号１２参照）。交互原料供給変調の条件を図４Ｂに示す。図４Ｂに示されるように、水素化ヒ素とトリメチルインジウムの供給を、交互に行った。つまり、トリメチルインジウムの供給を２秒間（符号２０）、水素ガスによるインターバルを１秒間（符号２１）、水素化ヒ素の供給を２秒間（符号２２）、水素ガスによるインターバルを２秒間（符号２３）の組合せを１サイクルとして、このサイクルを繰り返した。具体的には、２分間かけて前記サイクルを２０回繰り返した。 Next, an InAs thin film was formed by an alternating material supply modulation method (see reference numeral 12 in FIG. 4A). The conditions for alternating raw material supply modulation are shown in FIG. 4B. As shown in FIG. 4B, arsenic hydride and trimethylindium were alternately supplied. That is, the supply of trimethylindium for 2 seconds (reference 20), the hydrogen gas interval for 1 second (reference 21), the arsenic hydride supply for 2 seconds (reference 22), and the hydrogen gas interval for 2 seconds (reference 23) This cycle was repeated with a combination of Specifically, the cycle was repeated 20 times over 2 minutes.
また、供給される水素化ヒ素の分圧を２．５×１０−４atm、トリメチルインジウムの分圧を９．６×１０−７atmとした。 The partial pressure of arsenic hydride supplied was 2.5 × 10 −4 atm, and the partial pressure of trimethylindium was 9.6 × 10 −7 atm.
その後、装置の内温を４００℃から５４０℃に昇温した。５４０℃にて、水素化ヒ素と、トリメチルインジウムを水素ガスとともに供給して、ＩｎＡｓナノワイヤを、ＭＯＶＰＥ法で成長させた（図４Ａの符号１３参照）。 Thereafter, the internal temperature of the apparatus was increased from 400 ° C. to 540 ° C. Arsenic hydride and trimethylindium were supplied together with hydrogen gas at 540 ° C., and InAs nanowires were grown by the MOVPE method (see reference numeral 13 in FIG. 4A).
その結果、２μｍ程度のＩｎＡｓナノワイヤが基板表面に形成された。そのＳＥＭ写真を図７に示す。図７に示されるように、ナノワイヤは基板面に対して、選択的に垂直に成長している。 As a result, InAs nanowires of about 2 μm were formed on the substrate surface. The SEM photograph is shown in FIG. As shown in FIG. 7, the nanowires are selectively grown perpendicular to the substrate surface.
［実施例２］
実施例１と同様であるが、図５Ａのグラフに示されるように、交互原料供給変調法によるＩｎＡｓの薄膜形成（図４Ａの符号１２参照）を行わなかった。
[Example 2]
As in Example 1, as shown in the graph of FIG. 5A, thin film formation of InAs (see reference numeral 12 in FIG. 4A) by the alternating material supply modulation method was not performed.
［比較例１］
実施例１に対して、４００℃での低温熱処理（図４Ａの符号１１参照）と、交互原料供給変調法によるＩｎＡｓの成長（図４Ａの符号１２参照）を行わなかった（図５Ｂを参照）。つまり、９２５℃で高温熱処理したのち、５４０℃にまでは降温させるが、４００℃にまで降温させなかった。５４０℃にてそのままＭＯＶＰＥ法よりＩｎＡｓナノワイヤを成長させた。
[Comparative Example 1]
Example 1 was not subjected to low-temperature heat treatment at 400 ° C. (see reference numeral 11 in FIG. 4A) and InAs growth (see reference numeral 12 in FIG. 4A) by the alternating material supply modulation method (see FIG. 5B). . That is, after the high temperature heat treatment at 925 ° C., the temperature was lowered to 540 ° C., but not lowered to 400 ° C. InAs nanowires were grown as they were at 540 ° C. by the MOVPE method.
図６には、実施例１〜２と比較例１で得られた半導体構造物における、半導体ナノワイヤの制御結果が示される。図６において、●は基板面に対して垂直に成長したナノワイヤの割合を；■は基板面に対して傾いて成長したナノワイヤの割合を；○は開口部からナノワイヤが成長しなかった割合を示す。 FIG. 6 shows the control result of the semiconductor nanowires in the semiconductor structures obtained in Examples 1 and 2 and Comparative Example 1. In FIG. 6, ● indicates the proportion of nanowires grown perpendicular to the substrate surface; ■ indicates the proportion of nanowires grown with inclination relative to the substrate surface; ○ indicates the proportion of nanowires that did not grow from the openings .
図６に示されたように、比較例１では垂直に成長したナノワイヤの割合が約３０％であって低く、またナノワイヤが成長していない確立も高かった。これに対して実施例１および２は、垂直に成長したナノワイヤの割合が高い。この結果は、高熱処理後にいったん４００℃にて低温熱処理を施したことによることが示唆される。 As shown in FIG. 6, in Comparative Example 1, the proportion of nanowires grown vertically was about 30%, which was low, and the probability that nanowires were not grown was high. In contrast, Examples 1 and 2 have a high percentage of nanowires grown vertically. This result suggests that the low temperature heat treatment was once performed at 400 ° C. after the high heat treatment.
また実施例１は、実施例２と比較して、さらに垂直に成長したナノワイヤの割合が高い。これは、交互原料供給変調により半導体薄膜を形成しているためである。 In addition, compared to Example 2, Example 1 has a higher percentage of nanowires grown vertically. This is because the semiconductor thin film is formed by alternating source supply modulation.
［実施例３］シリコン基板面へのＧａＡｓナノワイヤの形成
実施例１と同様に、ｎ型シリコン（１１１）半導体基板の表面に、開口部を有する絶縁膜を形成し、得られた基板を減圧横型MOVPE装置にセットした。さらに、実施例１と同様に、９２５℃にて処理して基板に形成された自然酸化膜を除去し（図８Ａの符号３０）、その後４００℃に戻して水素化ヒ素（ＡｓＨ３）を提供した（図８Ａの符号３１）。
[Example 3] Formation of GaAs nanowires on silicon substrate surface In the same manner as in Example 1, an insulating film having an opening was formed on the surface of an n-type silicon (111) semiconductor substrate, and the resulting substrate was formed into a reduced pressure horizontal type. Set in MOVPE device. Furthermore, as in Example 1, the natural oxide film formed on the substrate was removed by treatment at 925 ° C. (reference numeral 30 in FIG. 8A), and then returned to 400 ° C. to provide arsenic hydride (AsH 3 ). (Reference numeral 31 in FIG. 8A).
次に、交互原料供給変調法によりＧａＡｓの薄膜を形成した（図８Ａの符号３２参照）。装備の内温を、３分かけて、４００℃から７５０℃にあげながら、水素化ヒ素とトリメチルインジウムを交互に供給した。供給する水素化ヒ素の分圧を２．５×１０−４atm、トリメチルガリウムの分圧を１．０×１０−６atmとした。 Next, a GaAs thin film was formed by the alternating source supply modulation method (see reference numeral 32 in FIG. 8A). Arsenic hydride and trimethylindium were alternately supplied while raising the internal temperature of the equipment from 400 ° C. to 750 ° C. over 3 minutes. The partial pressure of arsenic hydride supplied was 2.5 × 10 −4 atm, and the partial pressure of trimethylgallium was 1.0 × 10 −6 atm.
また、供給のタイミングは、実施例１と同様に、トリメチルガリウムの供給を２秒間、水素ガスによるインターバルを１秒間、水素化ヒ素の供給を２秒間、水素ガスによるインターバルを２秒間の組合せを１サイクルとして、このサイクルを３０回繰り返した。 Similarly to the first embodiment, the supply timing is 1 for the combination of supplying trimethylgallium for 2 seconds, supplying hydrogen gas for 1 second, supplying arsenic hydride for 2 seconds, and using hydrogen gas for 2 seconds. As a cycle, this cycle was repeated 30 times.
装置の内温を４００℃から７５０℃にかげながら交互原料供給変調することにより、インジウムと比較して蒸発しやすいガリウムの蒸発を抑制しつつ、（１１１）Ｂ面を形成することができた。 By alternating supply of raw materials while increasing the internal temperature of the apparatus from 400 ° C. to 750 ° C., the (111) B plane could be formed while suppressing evaporation of gallium, which is easier to evaporate than indium.
また、ＧａＡｓナノワイヤの形成の場合は、交互原料供給変調の工程は必ずしも必要ではなく、この工程を省略したとしても、ナノワイヤの成長方向を垂直に制御することができる。Ｇａ金属はその融点（２９℃）が低いため、溶融しやすい。そのためＧａＡｓナノワイヤの形成の場合は、ＡｓＨ３存在下で低温熱処理をすることにより、交互原料供給変調の工程をしなくても、本発明の効果を得ることもできる。 Further, in the case of forming GaAs nanowires, the alternating material supply modulation step is not necessarily required, and even if this step is omitted, the growth direction of the nanowires can be controlled vertically. Ga metal is easy to melt because its melting point (29 ° C.) is low. Therefore, in the case of forming GaAs nanowires, the effect of the present invention can be obtained by performing a low-temperature heat treatment in the presence of AsH 3 without performing the alternating material supply modulation step.
さらに、７５０℃にて水素化ヒ素と、トリメチルガリウムを水素ガスとともに供給して、ＧａＡｓナノワイヤを、ＭＯＶＰＥ法で成長させた（図８Ａの符号３３参照）。その結果、３μｍ程度のＧａＡｓナノワイヤが基板表面に形成された。そのＳＥＭ写真を図８Ｂに示す。図８Ｂに示されるように、ナノワイヤは基板面に対して、選択的に垂直に成長している。ほぼ１００％のナノワイヤが垂直に成長していることが確認された。 Furthermore, arsenic hydride and trimethylgallium were supplied together with hydrogen gas at 750 ° C., and GaAs nanowires were grown by the MOVPE method (see reference numeral 33 in FIG. 8A). As a result, GaAs nanowires of about 3 μm were formed on the substrate surface. The SEM photograph is shown in FIG. 8B. As shown in FIG. 8B, nanowires are selectively grown perpendicular to the substrate surface. It was confirmed that almost 100% of nanowires were growing vertically.
本発明により、シリコントランジスタやIII-V族化合物半導体太陽電池などの高性能化や高機能化が実現される。 According to the present invention, high performance and high functionality of a silicon transistor, a III-V compound semiconductor solar cell, and the like are realized.
１ IV族半導体基板
１−１ （１１１）面
２ 絶縁膜
３ 開口部
４ 半導体ナノワイヤ
1 Group IV Semiconductor Substrate 1-1 (111) Surface 2 Insulating Film 3 Opening 4 Semiconductor Nanowire
Claims (11)
（１１１）面を有するIV族半導体基板と、前記（１１１）面を被覆し、開口部を有する絶縁膜とを含む基板を準備するステップと、
前記基板について、化合物半導体ナノワイヤを成長させるのに必要な温度範囲よりも高い温度で高温熱処理を行うことにより生じた（１１１）７×７面を介し、化合物半導体ナノワイヤを成長させるのに必要な温度範囲よりも低い温度で低温熱処理をして（１１１）１×１面とするステップと、
前記基板に前記低温熱処理の条件下で、III族原料またはV族原料を供給して、前記（１１１）１×１面を、（１１１）Ａ面または（１１１）Ｂ面に変換するステップと、
前記（１１１）Ａ面または（１１１）Ｂ面に、V族原料とIII族原料を交互に供給することで、III−V族化合物半導体の薄膜を形成するステップと、
前記III−V族化合物半導体の薄膜を形成した後に、前記IV族半導体基板の表面から前記開口部を通して、III−V化合物半導体ナノワイヤを成長させるステップとを含む、製造方法。 A method for producing a semiconductor structure comprising a group IV semiconductor substrate and a group III-V compound semiconductor nanowire extending perpendicularly from the surface of the group IV semiconductor substrate,
Preparing a substrate including a group IV semiconductor substrate having a (111) plane and an insulating film covering the (111) plane and having an opening;
About the substrate , the temperature necessary for growing the compound semiconductor nanowire through the (111) 7 × 7 plane generated by performing the high temperature heat treatment at a temperature higher than the temperature range necessary for growing the compound semiconductor nanowire. A low temperature heat treatment at a temperature lower than the range to form a (111) 1 × 1 surface;
And converting under conditions of the low-temperature heat treatment to the substrate, by supplying the group III source or group V raw material, the (111) 1 × 1 surface, the (111) A plane or (111) B plane,
Forming a thin film of a III-V compound semiconductor by alternately supplying a group V material and a group III material to the (111) A surface or the (111) B surface;
And forming a III-V compound semiconductor nanowire from the surface of the group IV semiconductor substrate through the opening after forming a thin film of the group III-V compound semiconductor.
前記変換された面が前記（１１１）Ａ面のときはまずIII族原料を供給し、その後V族原料とIII族原料を交互に供給し、
前記変換された面が前記（１１１）Ｂ面のときはまずV族原料を供給し、その後III族原料とV族原料を交互に供給する、請求項１に記載の製造方法。 The step of alternately supplying the group V material and the group III material to the (111) A surface or the (111) B surface,
When the converted surface is the (111) A surface, first supply a group III material, and then supply a group V material and a group III material alternately,
2. The method according to claim 1, wherein when the converted surface is the (111) B surface, a Group V material is first supplied, and then a Group III material and a Group V material are alternately supplied.
前記複数本のIII−V族化合物半導体ナノワイヤのうちの９０％以上が、前記IV族半導体基板の前記（１１１）Ａ面または前記（１１１）Ｂ面の表面から垂直に延びている、半導体構造物。 A group IV semiconductor substrate, and a plurality of III− layers extending from the (111) A plane or the (111) B plane converted from the (111) 1 × 1 plane of the (111) plane of the group IV semiconductor substrate. A semiconductor structure including a group V compound semiconductor nanowire,
90% or more of the plurality of group III-V compound semiconductor nanowires extend vertically from the surface of the (111) A plane or the (111) B plane of the group IV semiconductor substrate. .
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| JP5409707B2 (en) * | 2011-06-15 | 2014-02-05 | シャープ株式会社 | Semiconductor element, method for manufacturing semiconductor element, light emitting diode, photoelectric conversion element, solar cell, lighting device, backlight and display device |
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| CN104445057A (en) * | 2014-12-11 | 2015-03-25 | 中国科学院合肥物质科学研究院 | Gallium arsenide nanowire array and preparation method thereof |
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| US9698239B2 (en) | 2015-08-12 | 2017-07-04 | International Business Machines Corporation | Growing groups III-V lateral nanowire channels |
| US9859397B2 (en) | 2015-08-12 | 2018-01-02 | International Business Machines Corporation | Growing groups III-V lateral nanowire channels |
| US10103242B2 (en) | 2015-08-12 | 2018-10-16 | International Business Machines Corporation | Growing groups III-V lateral nanowire channels |
| US10763340B2 (en) | 2015-08-12 | 2020-09-01 | International Business Machines Corporation | Growing Groups III-V lateral nanowire channels |
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