JP7008292B2 - Nitride semiconductor light emitting device and its manufacturing method - Google Patents

Description

The present invention relates to a nitride semiconductor light emitting device and a method for manufacturing the same.
The present invention relates to a nitride semiconductor light emitting device and a method for manufacturing the same.

Most semiconductor devices are formed by laminating a p-type semiconductor layer and an n-type semiconductor layer. In order to realize an element that operates with high efficiency, a p-type semiconductor layer and an n-type semiconductor layer having a small electric resistance are required. However, a nitride semiconductor useful as an ultraviolet visible light wavelength region light emitting / receiving element has an electrical resistivity of about 1 Ωcm in a p-type semiconductor layer. This is 100 times or more higher than the electrical resistivity of n-type nitride semiconductors, n-type GaAs (gallium arsenide) and p-type GaAs, which are infrared semiconductors, of 0.01 Ωcm or less. Further, there is a problem that p-type AlGaN cannot be obtained with AlGaN having a large bandgap and a large AlN (aluminum nitride) mole fraction, which is necessary in the deep ultraviolet region.

The tunnel junction is a pn junction in which p-type semiconductor impurities and n-type semiconductor impurities, which are semiconductor impurities, are added to each of the p-type semiconductor layer and the n-type semiconductor layer at a higher concentration than in a normal pn junction. As a result, in the tunnel junction, the thickness of the depletion layer formed at the interface between the p-type semiconductor layer and the n-type semiconductor layer becomes thinner than that in the normal pn junction. As a result, when a reverse bias voltage is applied to the p-type semiconductor layer and the n-type semiconductor layer of the tunnel junction, electrons pass through the depleted layer and move from the valence band of the p-type semiconductor layer to the conduction band of the n-type semiconductor layer (tunnel). can do. That is, in the tunnel junction, a current can flow from the n-type semiconductor layer to the p-type semiconductor layer.

Therefore, in a nitride semiconductor device, most of the p-type semiconductor layer, which is a source of holes having a lower mobility and a larger effective mass than electrons, has a higher mobility than holes by using a tunnel junction. It can be replaced with an n-type semiconductor layer, which is a source of electrons having a small effective mass. That is, by using a tunnel junction for the nitride semiconductor element, most of the p-type semiconductor layer having a large electric resistance can be replaced with an n-type semiconductor layer having a small electric resistance. If the electrical resistance of the tunnel junction itself can be further reduced, the electrical resistance of the conventional element can be further reduced, and further, the deep ultraviolet light emitting element, which is currently delayed in practical use, can be put into practical use. .. However, nitride semiconductors have a large bandgap, and it is difficult to increase the concentration of acceptors. For this reason, it has been considered difficult to reduce the electrical resistance in tunnel junctions using nitride semiconductors.

The nitride semiconductor light emitting device of Non-Patent Documents 1 and 2 uses a GaInN layer as a tunnel junction layer. As a result, in this nitride semiconductor light emitting device, the band gap of the tunnel junction layer becomes small, and a large polarization charge is generated by the piezopolarization generated by the addition of InN (indium nitride). Therefore, the nitride semiconductor is generated through the tunnel junction. It is disclosed that an extremely low voltage drop is exhibited in a low current density region (100 A / cm ² or less) required for driving an LED which is a light emitting element.

On the other hand, the nitride semiconductor light emitting device having the tunnel junction of Non-Patent Document 3 is a p-type semiconductor layer on the surface side of the device in the high current density region (up to 10 kA / cm ² ) required for laser driving. It is disclosed that the drive voltage is about 2 V (volt) higher than that of a conventional device having a p-type contact layer.

S. Krishnamoorthy, et al ,, "Polarization-engineered GaN / InGaN / GaN tunnel diodes", Applied Physics Letter, (USA), November 2010, Vol. 97, Issue20 M. Kaga, et al ,, "GaInN-Based Tunnel Junctions in n? P? N Light Emitting Diodes" Japanese Journal of Applied Physics, 2013, Vol. 52, Number8S D. Minamikawa, et al ,, "GaInN-based tunnel junctions with high InN mole fractions grown by MOVPE" Physica Status Solidi, May 2015, Vol. 252, Issue 5, P. 1127-1131

In order to further reduce the driving voltage for driving the nitride semiconductor element, the thickness of the depletion layer of the tunnel junction layer is reduced by increasing the concentration of semiconductor impurities added to the tunnel junction layer, and the tunnel junction is formed. The probability that electrons will tunnel through the layer should be increased. However, when the concentration of semiconductor impurities added to the tunnel junction layer exceeds the higher concentration of 1 × 10 ¹⁹ cm ^-3 , the crystallinity of the tunnel junction layer decreases and the surface flatness of the crystals of the tunnel junction layer is good. It is known that it will disappear. That is, although the electrical resistance of the tunnel junction layer can be reduced by increasing the concentration of the semiconductor impurities added to the tunnel junction layer, the surface flatness of the crystals of the tunnel junction layer is not good. Therefore, it is considered difficult to add a higher concentration of semiconductor impurities to the tunnel junction layer for a light emitting device such as a laser that reflects light on the surface of a crystal and resonates it.

The present invention has been made in view of the above-mentioned conventional circumstances, and provides a nitride semiconductor light emitting device and a method for manufacturing the same, wherein the electric resistance of the device is sufficiently small and a current can flow with high efficiency. It is an issue to be solved.

Specifically, as a result of diligent studies by the inventors based on the above results, the amount of n-type semiconductor impurities added, which are semiconductor impurities in the nitride semiconductor tunnel junction layer, is as high as 1 × 10 ²⁰ cm ^-3 or more. To form a tunnel junction layer with low electrical resistance. Then, the semiconductor impurities of the n-GaN layer, which is a surface layer, grows the surface flatness of the crystals of the tunnel junction layer, which has become poor due to the addition of n-type semiconductor impurities at a high concentration, on the surface side of the tunnel junction layer. It is recovered by controlling the concentration and growth conditions of. In this way, we have found a method for obtaining a nitride semiconductor device having low electrical resistance and good crystal surface flatness.

In the conventional method for manufacturing a semiconductor device, when each layer is laminated and crystal growth is performed, the surface of each layer or the interface of the layer to be laminated is sequentially laminated while always maintaining good flatness. As a result, the conventional method for manufacturing a semiconductor device can satisfactorily exhibit the function of layers that are laminated and joined next to each other, and a higher performance device can be obtained. On the other hand, in the present invention, in order to give priority to reducing the electric resistance of the device, semiconductor impurities are added to the tunnel junction layer at a higher concentration. As a result, the surface flatness of the crystals in the tunnel junction layer becomes poor. Then, by controlling the concentration of semiconductor impurities in the layer structure for crystal growth on the surface side of the tunnel junction layer, growth conditions, and the like, the surface flatness of the crystal of the tunnel junction layer, which has become unfavorable, is restored. In this way, a nitride semiconductor device having good crystal surface flatness is obtained. That is, the present invention is different from the conventional technical common sense.

The nitride semiconductor light emitting device of the present invention is
A tunnel junction layer with semiconductor impurities added,
The surface layer formed on the upper side of the tunnel junction layer and
Equipped with
The interface of the tunnel junction layer on the surface layer side is a crystal surface grown three-dimensionally, and diffusion of the p-type semiconductor impurity, which is a semiconductor impurity, is suppressed from the tunnel junction layer .
The surface layer is characterized in that the tunnel junction layer side is three-dimensionally grown .

In this nitride semiconductor light emitting device, island-shaped crystals are formed at the interface on the surface layer side of the tunnel junction layer to which semiconductor impurities are added, and the island-shaped crystals are formed along the surface of the layer and the layer. It is formed by three-dimensional growth that grows away from the surface of the island. That is, this nitride semiconductor light emitting device adds semiconductor impurities to the tunnel junction layer at a high concentration. As a result, the nitride semiconductor light emitting device can suppress the thickness of the depletion layer formed in the tunnel junction layer, so that electrons and holes can pass through the depletion layer satisfactorily. Therefore, this nitride semiconductor light emitting device can make the electric resistance of the tunnel junction layer smaller. That is, this nitride semiconductor light emitting device can satisfactorily pass a current.

Further, the method for manufacturing a nitride semiconductor light emitting device of the present invention is as follows.
A tunnel junction layer forming step of adding an amount of semiconductor impurities that grows three-dimensionally and causing the three-dimensional growth to form a tunnel junction layer in which diffusion of the p-type semiconductor impurity, which is a semiconductor impurity, is suppressed .
A surface layer forming step of two-dimensionally growing a surface layer on the upper side of the tunnel junction layer formed by executing the tunnel junction layer forming step,
Equipped with
In the surface layer forming step, the surface layer is characterized in that it grows two-dimensionally after the three-dimensional growth continues .

This method for manufacturing a nitride semiconductor light emitting device includes a tunnel junction layer forming step of adding a semiconductor impurity in an amount that grows three-dimensionally to form a tunnel junction layer. That is, in this method of manufacturing a nitride semiconductor light emitting device, a high concentration of semiconductor impurities is added to the tunnel junction layer. Therefore, since this method for manufacturing a nitride semiconductor light emitting device can suppress the thickness of the depletion layer formed in the tunnel junction layer, electrons and holes can satisfactorily pass through the depletion layer. Therefore, this method for manufacturing a nitride semiconductor light emitting device can further reduce the electrical resistance of the tunnel junction layer. That is, this method for manufacturing a nitride semiconductor light emitting device can manufacture a nitride semiconductor light emitting device having a tunnel junction layer capable of allowing a good current to flow.

Therefore, the nitride semiconductor light emitting device of the present invention has a sufficiently small electric resistance, whereby a current can flow with high efficiency. Further, the method for manufacturing a nitride semiconductor light emitting device of the present invention can manufacture a nitride semiconductor light emitting device in which the electric resistance of the device is sufficiently small and a current can flow with high efficiency.

It is a schematic diagram which shows the structure which formed the element of Example 1. FIG. It is a schematic diagram showing the structure of the sample layer of Examples 2 to 4 and Comparative Examples 1 to 3, in which (A) shows the structure of the sample layer of Examples 2 to 4, and (B) is Comparative Example 2. 3 shows the structure of the sample layer, and (C) shows the structure of the sample layer of Comparative Example 1. It is a figure which shows the AFM image of the surface of the 2nd n-GaN layer of the sample of the comparative example 1 to 3, and (A) is a comparative example which added concentration of Si to the tunnel junction layer is 7 × 10 ¹⁹ cm ^-3 . It is an AFM image of the surface of the 2nd n-GaN layer of the sample of 1 and (B) is the 2nd n-GaN of the sample of Comparative Example 2 in which the addition concentration of Si to the tunnel junction layer is 1 × 10 ²⁰ cm ^-3 . It is an AFM image of the surface of the layer, and (C) is an AFM image of the surface of the second n-GaN layer of the sample of Comparative Example 3 in which the concentration of Si added to the tunnel junction layer is 2 × 10 ²⁰ cm ^-3 . .. It is a figure which shows the AFM image of the surface of the tunnel junction layer of the sample of the comparative example 3. FIG. It is a figure which shows the AFM image of the surface of the 2nd n-GaN layer of the sample of Example 2, (A) is the AFM image of the surface of the 2n-GaN layer when the thickness of the 2n-GaN layer is 20 nm. (B) is an AFM image of the surface of the second n-GaN layer when the thickness of the second n-GaN layer is 50 nm, and (C) is the second n- when the thickness of the second n-GaN layer is 400 nm. It is an AFM image of the surface of a GaN layer. It is a graph which shows the addition concentration of Si and Mg which are semiconductor impurities in the depth direction of the sample of Example 2 and Comparative Example 1, and (A) is the graph in the depth direction of the crystal of the sample of Example 2. The respective addition concentrations of Si and Mg are shown, and (B) shows the respective addition concentrations of Si and Mg in the crystal depth direction of the sample of Comparative Example 1. It is a graph which shows the magnitude of the voltage with respect to the current density of the sample of Examples 2-4 and Comparative Example 1.

A preferred embodiment of the present invention will be described.

The nitride semiconductor light emitting device of the present invention may be a crystal surface in which the surface of the surface layer is two-dimensionally grown. In this case, in this nitride semiconductor light emitting device, the tunnel junction layer whose interface on the surface layer side is three-dimensionally grown can be covered with the two-dimensionally grown surface layer. That is, in this nitride semiconductor light emitting device, since the tunnel junction layer grown three-dimensionally by adding semiconductor impurities at a high concentration is covered with the surface layer grown two-dimensionally, the tunnel junction layer having a smaller electric resistance can be obtained. It can be used for elements.

The method for manufacturing a nitride semiconductor light emitting device of the present invention may include a surface layer forming step for two-dimensionally growing the surface layer on the upper side of the tunnel junction layer formed by executing the tunnel junction layer forming step. In this case, in this method for manufacturing a nitride semiconductor light emitting device, the surface layer can be formed by two-dimensional growth by executing the surface layer forming step. Therefore, in this method of manufacturing a nitride semiconductor light emitting device, the three-dimensionally grown tunnel junction layer can be covered by two-dimensionally growing and laminating the surface layer on the surface side of the three-dimensionally grown tunnel junction layer. Therefore, in this method for manufacturing a nitride semiconductor light emitting device, a tunnel junction layer grown three-dimensionally by adding semiconductor impurities can be used for the device, so that a nitride semiconductor having a tunnel junction layer having a smaller electric resistance is provided. A light emitting element can be manufactured.

Next, Examples 1 to 4 and Comparative Examples 1 to 3 embodying the nitride semiconductor light emitting device of the present invention will be described with reference to the drawings.

<Example 1>
Example 1 shows the structure of a nitride semiconductor element common to the samples of Examples 2 to 4 and the samples of Comparative Examples 1 to 3 described later, and a method for manufacturing the same. As shown in FIG. 1, the nitride semiconductor device of the first embodiment has a first n-GaN layer 11, a GaInN / GaN5 weight element well active layer 12, a p-AlGaN layer 13, a p-GaN layer 14, and a tunnel junction layer 15. , And a second n-GaN layer 16 which is a surface layer.

The nitride semiconductor element of Example 1 is a GaN template 10 formed on the surface side of a sapphire substrate S (hereinafter referred to as a substrate) (the table is the upper side in FIG. 1, the same applies hereinafter) via a low temperature deposition buffer layer B. The crystal grows by laminating on the surface side of the surface using the MOCVD method (organic metal vapor phase growth method). The surface of the sapphire substrate S is the C surface ((0001) surface).

First, the first n-GaN layer 11 is laminated on the surface of the GaN template 10 formed on the surface side of the substrate to grow crystals. Specifically, first, the substrate is set in the reactor. Then, NH ₃ (ammonia), which is a raw material of N (nitrogen), and H ₂ (hydrogen), which is a carrier gas, are supplied into the reactor, and the temperature inside the reactor is adjusted to raise the temperature of the substrate to 1050 ° C. To. Then, TMGa (trimethylgallium), which is a raw material for Ga (gallium), and SiH ₄ (silane), which is a raw material for Si (silicon), which is an n-type semiconductor impurity which is a semiconductor impurity, are supplied into the reaction furnace. The first n-GaN layer 11 having a thickness of 2 μm is laminated and crystallized. The amount of SiH ₄ supplied into the reaction furnace is adjusted so that the concentration of Si, which is an n-type semiconductor impurity added to the first n-GaN layer 11, is 8 × 10 ¹⁸ cm ^-3 .

Next, the GaInN / GaN5 weight well active layer 12 is laminated on the surface of the first n-GaN layer 11 to grow crystals. The GaInN / GaN5 weight element well active layer 12 has a GaInN well layer (not shown) and a GaN barrier layer (not shown).

First, the GaInN well layer is laminated to grow crystals. Specifically, the supply of H ₂ , TMGa, and SiH ₄ into the reactor will be stopped. Then, N ₂ (nitrogen) is supplied as a carrier gas into the reactor. Then, the temperature inside the reactor is adjusted to bring the temperature of the substrate to 780 ° C. Then, TEGa (triethyl gallium), which is a raw material for Ga, and TMIn (trimethylindium), which is a raw material for In (indium), are supplied into the reaction furnace, and a GaInN well layer having a thickness of 2 nm is laminated to grow crystals. Let me.

Next, a GaN barrier layer is laminated on the surface of the GaInN well layer to grow crystals. Specifically, the supply of TMIn into the reactor is stopped, and a GaN barrier layer having a thickness of 10 nm is laminated to grow crystals. The GaInN quantum well layer and the GaN barrier layer grown in this way are used as one pair, and five pairs of these one pair are laminated to grow crystals. In this way, the GaInN / GaN5 weight well active layer 12 is formed. Then, the supply of TEGa and TMIn to the reactor is stopped.

Next, the p-AlGaN layer 13 is laminated on the surface of the GaInN / GaN5 weight well active layer 12 to grow crystals. Specifically, the carrier gas supplied into the reactor is switched from N ₂ to H ₂ . Then, the temperature inside the reactor is adjusted to bring the temperature of the substrate to 1000 ° C. Then, in the reaction furnace, TMGa (trimethylaluminum) which is a raw material of TMGa and Al (aluminum), and Cp ₂ Mg (cyclopentadienyl magnesium) which is a raw material of Mg (magnesium) which is a p-type semiconductor impurity which is a semiconductor impurity. ) Is supplied, and a p-AlGaN layer 13 having a thickness of 20 nm is laminated to grow crystals. The amount of Cp ₂ Mg supplied into the reaction furnace is adjusted so that the concentration of Mg, which is a p-type semiconductor impurity added to the p-AlGaN layer 13, is 2 × 10 ¹⁹ cm ^-3 .

Next, the p-GaN layer 14 is laminated on the surface of the p-AlGaN layer 13 to grow crystals. Specifically, the supply of TMAl to the reactor is stopped, and the p-GaN layer 14 having a thickness of 160 nm is laminated to grow crystals. The concentration of Mg, which is a p-type semiconductor impurity added to the p-GaN layer 14, is 4 × 10 ¹⁹ cm ^-3 . Then, the supply of TMGa and Cp ₂ Mg to the reactor is stopped, and the carrier gas is switched from H ₂ to N ₂ . Then, the temperature inside the reactor is adjusted to bring the temperature of the substrate to 720 ° C.

Next, the tunnel junction layer 15 is formed on the surface of the p-GaN layer 14. The tunnel junction layer 15 has a p ⁺⁺ -GaInN layer (not shown) and an n ⁺⁺ -GaN layer (not shown). Here, p ⁺⁺ means a state in which Mg, which is a p-type semiconductor impurity, is added at a high concentration, and n ⁺⁺ means a state in which Si, which is an n-type semiconductor impurity, is added in a high concentration.

TEGa, Cp ₂ Mg, and a predetermined amount of TMIn are supplied into the reactor. In this way, a p ⁺⁺ -GaInN layer having a thickness of 2 nm is grown. The flow rate of Cp ₂ Mg is adjusted so that the concentration of Mg, which is a p-type semiconductor impurity added to the p ⁺⁺ -GaInN layer, is 1 to 2 × 10 ²⁰ cm ^-3 . The mole fraction of InN in the p ⁺⁺ -GaInN layer is 0.35. In this way, the crystal growth of the p ⁺⁺ -GaInN layer is completed.

Next, an n ⁺⁺ -GaN layer is laminated on the surface of the p ⁺⁺ -GaInN layer to grow crystals. Specifically, after the p ⁺⁺ -GaInN layer is laminated and crystal growth is performed, the supply of Cp ₂ Mg and TMIn to the reaction furnace is stopped. Then, SiH ₄ is supplied into the reactor, and an n ⁺⁺ -GaN layer having a thickness of 15 nm is laminated to grow crystals. The flow rate of SiH ₄ is adjusted so that the concentration of Si, which is an n-type semiconductor impurity added to the n ⁺⁺ -GaN layer, is 1 × 10 ²⁰ cm ^-3 or more. That is, the tunnel junction layer 15 adds an n-type semiconductor impurity which is a semiconductor impurity.

Next, the second n-GaN layer 16 is laminated on the surface of the tunnel junction layer 15 to grow crystals. Specifically, the carrier gas supplied into the reactor is switched from N ₂ to H ₂ . Then, the temperature inside the reactor is adjusted to bring the temperature of the substrate to 980 ° C. Then, the second n-GaN layer 16 is laminated with a thickness of 400 nm to grow crystals. The concentration of Si, which is an n-type semiconductor impurity added to the second n-GaN layer 16, is 1 × 10 ¹⁹ cm ^-3 . The growth pressure, which is the atmospheric pressure in the reaction furnace in which the second n-GaN layer 16 is laminated and the crystal grows, can be adjusted to a desired value. Then, the supply of TMGa and SiH ₄ to the reactor is stopped to end the crystal growth. Then, the carrier gas supplied into the reactor is switched from H ₂ to N ₂ . Then, when the temperature in the reactor is adjusted and the temperature of the substrate becomes 400 ° C. or lower, the supply of NH ₃ to the reactor is stopped. Then, after the temperature of the substrate reaches room temperature, the inside of the reactor is purged and the substrate is taken out from the reactor.

Next, a device capable of injecting a current is formed using a substrate in which crystals are grown in this way to form a layered structure.

First, in a plan view from the surface, a circular mesa structure 20 having a diameter of 35 μm is formed on the substrate. Specifically, the mesa structure 20 is formed on the substrate by using photolithography and dry etching. More specifically, a circular photoresist or metal mask having a diameter of 35 μm is formed on the surface of the second n-GaN layer 16 which is laminated on the outermost surface of the substrate and crystal-grown (not shown). The area directly under the photoresist or metal mask is not removed by etching. Further, the region where the photoresist or the metal mask is not formed is etched until the first n-GaN layer 11 is exposed on the surface. In this way, the mesa structure 20 having a circular shape with a diameter of 35 μm is formed on the substrate.

Next, the substrate on which the mesa structure 20 was formed was annealed at 725 ° C. for 30 minutes in an O ₂ (oxygen) atmosphere, and the embedded p-AlGaN layer 13, the p-GaN layer 14, and the tunnel junction layer were subjected to an annealing treatment. Activates Mg in the p ⁺⁺ -GaInN layer of 15. Here, activation means that H (hydrogen) bonded to Mg, which is a p-type semiconductor impurity, is released to activate Mg, and the p-AlGaN layer 13 and p-GaN layer 14 to which Mg is added, And to improve the electrical conductivity of the p ⁺⁺ -GaInN layer of the tunnel junction layer 15. By activating in this way, Mg was inactivated from each side surface of the p-AlGaN layer 13, the p-GaN layer 14, and the p ⁺⁺ -GaInN layer of the tunnel junction layer 15 whose side surfaces were exposed by etching. To leave.

Next, the first electrode 21 and the second electrode 22 are formed. Specifically, the first electrode 21 having a circular shape is formed on the surface of the mesa structure 20. Further, the annular second electrode 22 is formed on the exposed surface of the first n-GaN layer 11 so as to surround the mesa structure 20. The first electrode 21 and the second electrode 22 are Ti / Al / Ti / Au. Further, the first electrode 21 and the second electrode 22 are collectively formed. In this way, the nitride semiconductor device of Example 1 in which a current flows from the first electrode 21 through the tunnel junction layer 15 and the GaInN / GaN 5 weight element well active layer 12 to the second electrode 22 is formed.

<Comparative Examples 1 to 3>
Samples of Comparative Examples 1 to 3 were prepared by using the method for manufacturing a nitride semiconductor device of Example 1. Specifically, in the samples of Comparative Examples 1 to 3, the concentration of Si added to the n ⁺⁺ -GaN layer of the tunnel junction layer 15 is changed in the method for manufacturing the nitride semiconductor device of Example 1. .. Further, in the samples of Comparative Examples 1 to 3, the growth pressure, which is the atmospheric pressure in the reaction furnace when the second n-GaN layer 16 was laminated and the crystal was grown, was set to 90 kPa. Table 1 shows the concentration of Si added to each of the n ⁺⁺ -GaN layers of the tunnel junction layer 15 of the samples of Comparative Examples 1 to 3.

The sample of Comparative Example 1 was crystal-grown while always maintaining good surface flatness. As shown in FIG. 3A, the sample of Comparative Example 1 has an atomic layer step formed on the surface of the second n-GaN layer 16, and it can be seen that the surface flatness is good. In the sample of Comparative Example 1, the RMS (root mean square) value of the surface step is 0.3 nm. That is, as shown in FIG. 2C, the sample of Comparative Example 1 has good surface flatness of the surface 16C of the second n-GaN layer 16. Further, since the sample of Comparative Example 1 was crystal-grown while always maintaining good surface flatness, it is considered that the surface 15C of the n ⁺⁺ -GaN layer of the tunnel junction layer 15 also has good surface flatness. ..

Further, as shown in FIG. 3B, in the sample of Comparative Example 2, a plurality of pits P1 which are crystal defects are formed on the surface of the second n-GaN layer 16. The sample of Comparative Example 2 has a surface step RMS value of 1.48 nm. Further, as shown in FIG. 3C, the sample of Comparative Example 3 has a plurality of pits P2 having a large area formed on the surface of the second n-GaN layer 16 as compared with the sample of Comparative Example 2. In the sample of Comparative Example 3, the RMS value of the surface step is 19.0 nm. From this, when the concentration of Si added to the tunnel junction layer 15 becomes higher, it has a greater effect on the surface flatness of the device, and thus has a greater effect on the optical and electrical characteristics of the device. I understood.

Further, FIG. 4 shows the results of observing the surface of the tunnel junction layer 15 with AFM after temporarily suspending the crystal growth of the sample of Comparative Example 3 when the crystal growth of the tunnel junction layer 15 was completed. In the sample of Comparative Example 3, although the thickness of the n ⁺⁺ -GaN layer of the tunnel junction layer 15 to which Si was added to a high concentration (2 × 10 ²⁰ cm ^-3 ) was as thin as 15 nm, the n ⁺⁺ -GaN layer was formed. It was found that the surface had grown three-dimensionally and the surface flatness had begun to deteriorate. In the sample of Comparative Example 3 at this time, the RMS value of the surface step is 0.67 nm. Here, three-dimensional growth is a direction in which island-shaped crystals independent of the surroundings are formed on the surface of the layer in which crystals are growing, and the island-shaped crystals are in the direction along the surface of the layer and in the direction away from the surface of the layer. Is to grow into. The surface of the three-dimensionally grown crystal does not have good surface flatness.

That is, in the sample of Comparative Example 3, as shown in FIG. 2B, the surface flatness of the surface 15B of the n ⁺⁺ -GaN layer of the tunnel junction layer 15 and the surface 16B of the second n-GaN layer 16 is not good. .. Further, in the sample of Comparative Example 2, since a plurality of pits P1 which are crystal defects are formed on the surface of the second n-GaN layer 16, n ⁺⁺ -GaN of the tunnel junction layer 15 is formed as in the sample of Comparative Example 3. It is considered that the surface flatness of the surface 15B of the layer is not good.

On the other hand, in the sample of Comparative Example 1, the surface flatness of the surface 16C of the second n-GaN layer 16 is better than that of the samples of Comparative Examples 2 and 3, but the concentration of Si added to the tunnel junction layer 15 is good. Is lower than the samples of Comparative Examples 2 and 3, so that the electrical resistance of the tunnel junction layer 15 is higher than that of the samples of Comparative Examples 2 and 3.

<Examples 2 to 4>
The quantum well layer and the like are composed of laminated layers (several nm) having an extremely thin thickness. For this reason, in the prior art, in order to obtain a layer having good surface flatness, it is common to grow crystals by laminating and slowing down the growth rate of crystal growth. Further, in the prior art, when forming an element structure by laminating layers, it is determined that once the surface flatness of the layer formed by laminating and crystal growth becomes poor, a good element structure cannot be obtained at that time. Therefore, it has been common practice to stop the crystal growth.

However, the inventors have impaired the surface flatness of the tunnel junction layer 15 that has been intentionally laminated and crystal-grown, and further, the second n-, which is a surface layer that is laminated on the tunnel junction layer 15 and crystal-grown. A sample in which the crystal surface of the tunnel junction layer 15 whose surface flatness is not good is embedded by controlling the concentration and growth conditions of the semiconductor impurities in the GaN layer 16 to restore the crystal surface flatness to a good one is prepared. Made. Specifically, the samples of Examples 2 to 4 were prepared by using the method for manufacturing a nitride semiconductor device of Example 1.

More specifically, the samples of Examples 2 to 4 are tunnel-junctioned when the n ⁺⁺ -GaN layer of the tunnel junction layer 15 is laminated and crystal-grown in the method for manufacturing a nitride semiconductor element of Example 1. A tunnel junction layer 15 is formed by adding a certain amount of n-type semiconductor impurities to the layer 15 while adjusting the growth rate so as to grow three-dimensionally (tunnel junction layer forming step). Then, the second n-GaN layer 16 is two-dimensionally grown on the upper side of the tunnel junction layer 15 formed by executing the tunnel junction layer forming step (surface layer forming step). That is, the samples of Examples 2 to 4 include a tunnel junction layer 15 to which an n-type semiconductor impurity is added, and a second n-GaN layer 16 formed on the upper side of the tunnel junction layer 15, and the second n-GaN. The interface of the tunnel junction layer 15 on the layer 16 side grows three-dimensionally.

In the surface layer forming step, the growth pressure, which is the atmospheric pressure in the reaction furnace, is set to 20 kPa, and NH ₃ , which is the raw material of N, which is a group V element, is compared with the conditions when the samples of Comparative Examples 1 to 3 are prepared. , The temperature of the substrate when the group V raw material / group III raw material supply ratio, which is the supply ratio to the reaction furnace with TEGa, which is the raw material of Ga, which is a group III element, is made larger, or when the crystals are laminated and grown into crystals. I'm making it higher. As a result, in the samples of Examples 2 to 4, the crystals can be easily grown two-dimensionally when the second n-GaN layer 16 is laminated and the crystals grow. That is, in the samples of Examples 2 to 4, the surface of the second n-GaN layer 16 is two-dimensionally grown. Here, the two-dimensional growth is the crystal growth on the surface of the layer in which the crystal is growing in the direction along the surface of the layer. Atomic layer steps are formed on the surface of the two-dimensionally grown crystal, and the surface flatness is good.

The samples of Examples 2 to 4 are Si added to the n ⁺⁺ -GaN layer of the tunnel junction layer 15 in order to make the electrical resistance of the tunnel junction layer 15 smaller than that of the samples of Comparative Examples 1 to 3 in the tunnel junction layer forming step. The concentration of the above is changed to a higher concentration than that of the samples of Comparative Examples 1 to 3. Table 2 shows the concentration of Si added to each of the n ⁺⁺ -GaN layers of the samples of Examples 2 to 4.

The change in surface flatness with respect to the layer thickness of the sample of Example 2 thus prepared was investigated. Specifically, in the surface layer forming step of the sample of Example 2, the state of the crystal surface of the second n-GaN layer 16 when the layer thickness of the second n-GaN layer 16 is 20 nm, 50 nm, and 400 nm. The results of observing the above using AFM are shown in FIGS. 5 (A) to 5 (C).

As shown in FIG. 5A, in the sample of Example 2, when the thickness of the second n-GaN layer 16 is 20 nm (hereinafter referred to as layer thickness 20 nm), crystals are three-dimensionally grown. The RMS value of the surface step at this time is 1.24 nm. Further, as shown in FIG. 5B, in the sample of Example 2, when the thickness of the second n-GaN layer 16 is 50 nm (hereinafter referred to as layer thickness 50 nm), crystals start to grow two-dimensionally. The RMS value of the surface step at this time is 3.89 nm. Then, as shown in FIG. 5C, it was found that the sample of Example 2 formed an extremely flat surface in which the atomic layer step was observed when the thickness of the second n-GaN layer 16 was 400 nm. rice field. The RMS value of the surface step at this time is 0.28 nm. The RMS value when the layer thickness is 50 nm is larger than the RMS value when the layer thickness is 20 nm. It is considered that this is because in the step of crystal growth of the second n-GaN layer 16, the three-dimensional growth of the crystal continued until at least the layer thickness of the second n-GaN layer 16 reached 50 nm. Further, in the samples of Examples 3 and 4, the RMS values of the surface steps when the thickness of the second n-GaN layer 16 was 400 nm were 0.22 nm and 0.26 nm, respectively.

That is, in the samples of Examples 2 to 4, as shown in FIG. 2A, Si is added to the n ⁺⁺ -GaN layer of the tunnel junction layer 15 at a higher concentration than the samples of Comparative Examples 1 to 3. It is considered that the surface flatness of the surface 15A of the n ⁺⁺ -GaN layer of the tunnel junction layer 15 is not good. Further, in the samples of Examples 2 to 4, the atomic layer step is formed, and the RMS value is smaller than the surface of the second n-GaN layer 16 of the sample of Comparative Example 1 having good surface flatness. That is, the samples of Examples 2 to 4 have good surface flatness of the surface 16A of the second n-GaN layer 16.

The results of elemental analysis of Mg and Si in the depth direction of the sample of Example 2 and the sample of Comparative Example 1 are shown in FIGS. 6A and 6B. As shown in FIG. 6B, in the sample of Comparative Example 1 in which crystals were grown by laminating while always maintaining good surface flatness ^, the concentration of Mg added in the tunnel junction layer 15 was 1 × 10 ²⁰ cm. ^3. The addition concentration of Si is 7 × 10 ¹⁹ cm ^-3 . Further, it was found that the sample of Comparative Example 1 had a higher concentration of Mg contained in the second n-GaN layer 16 than the sample of Example 2. It is considered that this is because Mg is taken in during the crystal growth of the second n-GaN layer 16 due to the memory effect of Mg. As a result, the electrons added by adding Si to the second n-GaN layer 16 are electrically canceled by the holes added by incorporating Mg into the second n-GaN layer 16, and the second n- It was also found that the electrical resistance of the GaN layer 16 was increased.

Further, as shown in FIG. 6A, in the sample of Example 2, the concentration of Mg added was 2 × 10 ²⁰ cm ^-3 and the concentration of Si added was 5 × 10 ²⁰ cm ⁻ in the tunnel junction layer 15. It is ³ . The sample of Example 2 has a lower concentration of Mg contained in the second n-GaN layer 16 than the sample of Comparative Example 1.

The following are possible causes for this. It is considered that Mg added to the tunnel junction layer 15 is easy to diffuse from the C-plane ((0001) plane) and difficult to diffuse from the non-C-plane. When the tunnel junction layer 15 grows three-dimensionally, the proportion of the area of the C-plane formed on the surface of the tunnel junction layer 15 decreases, and the proportion of the area of the non-C-plane increases. It is considered that this is because Mg added to the tunnel junction layer 15 is suppressed from diffusing from the tunnel junction layer 15.

That is, when the crystal growth of the tunnel junction layer 15, the surface flatness of the tunnel junction layer 15 is temporarily deteriorated, so that Mg added to the tunnel junction layer 15 is less likely to diffuse from the tunnel junction layer 15. It was found that the concentration of Mg added to the tunnel junction layer 15 could be suppressed from decreasing, and the electrical resistance of the tunnel junction layer 15 could be made smaller. Further, it is possible to suppress that the electrons added by adding Si to the second n-GaN layer 16 are electrically canceled by the holes added by incorporating Mg into the second n-GaN layer 16. Therefore, it was found that the electrical resistance of the second n-GaN layer 16 can also be made smaller. That is, the Mg contained in each of the tunnel junction layer 15 and the second n-GaN layer 16 formed by being laminated on the upper side of the tunnel junction layer 15 and crystal-grown by three-dimensionally growing the tunnel junction layer 15. The concentration can be adjusted.

FIG. 7 shows the results of measuring the magnitude of the voltage with respect to the current density by applying a voltage to each of the samples of Examples 2 to 4 and Comparative Example 1. The driving voltage of the samples of Examples 2 to 4 is significantly reduced as compared with the sample of Comparative Example 1. In particular, when the current density is 3 kA / cm ² , the drive voltage of the samples of Examples 2 and 3 is about 10 V (volt) lower than that of the sample of Comparative Example 1. That is, after the tunnel junction layer 15 is intentionally grown three-dimensionally to form the tunnel junction layer 15 having poor surface flatness, the second n-GaN layer 16 is further laminated on the tunnel junction layer 15 to form a two-dimensional crystal. It grows and restores the surface flatness to a good one. As a result, it was found that a nitride semiconductor device having a smaller electric resistance and a good surface flatness and having excellent characteristics as a light emitting device can be obtained.

As described above, in this nitride semiconductor device, an island-shaped crystal is formed at the interface on the second n-GaN layer 16 side of the tunnel junction layer 15 to which the n-type semiconductor impurity is added, and the island-shaped crystal is formed independently of the surroundings. Is formed by three-dimensional growth that grows along the surface of the layer and away from the surface of the layer. That is, in this nitride semiconductor element, n-type semiconductor impurities are added to the tunnel junction layer 15 at a high concentration. As a result, the nitride semiconductor device can suppress the thickness of the depletion layer formed in the tunnel junction layer 15, so that electrons and holes can pass through the depletion layer satisfactorily. Therefore, this nitride semiconductor device can make the electric resistance of the tunnel junction layer 15 smaller. That is, this nitride semiconductor device can satisfactorily pass a current.

Further, this method for manufacturing a nitride semiconductor device includes a tunnel junction layer forming step of adding an n-type semiconductor impurity in an amount that grows three-dimensionally to form the tunnel junction layer 15. That is, in this method of manufacturing a nitride semiconductor device, a high concentration of n-type semiconductor impurities is added to the tunnel junction layer 15. Therefore, since this method for manufacturing a nitride semiconductor device can suppress the thickness of the depletion layer formed in the tunnel junction layer 15, electrons and holes can satisfactorily pass through the depletion layer. Therefore, this method for manufacturing a nitride semiconductor device can further reduce the electrical resistance of the tunnel junction layer 15. That is, this method for manufacturing a nitride semiconductor device can manufacture a nitride semiconductor device having a tunnel junction layer 15 capable of allowing a good current to flow.

Therefore, this nitride semiconductor device has a sufficiently small electric resistance, which allows a current to flow with high efficiency. Further, in this method of manufacturing a nitride semiconductor device, the electric resistance of the device is sufficiently small, so that it is possible to manufacture a nitride semiconductor device capable of passing a current with high efficiency.

Further, in this nitride semiconductor device, the surface of the second n-GaN layer 16 is two-dimensionally grown (the RMS value of the surface step of the crystal is 0.28 nm or less). Therefore, in this nitride semiconductor device, the tunnel junction layer 15 whose interface on the second n-GaN layer 16 side is three-dimensionally grown can be covered with the second n-GaN layer 16 which is two-dimensionally grown. That is, in this nitride semiconductor device, the tunnel junction layer 15 that has grown three-dimensionally due to the addition of n-type semiconductor impurities at a high concentration is covered with the second n-GaN layer 16 that has grown two-dimensionally, so that it has a smaller electrical resistance. The tunnel junction layer 15 provided can be used for the element.

Further, in this nitride semiconductor device, the semiconductor impurity is an n-type semiconductor impurity. Therefore, this nitride semiconductor device forms a tunnel junction layer by adding an n-type semiconductor impurity in an amount in which the interface on the surface layer side of the tunnel junction layer 15 grows three-dimensionally. As a result, the nitride semiconductor device can form the second n-GaN layer 16 not with the p-type semiconductor layer but with the n-type semiconductor layer. Thereby, this nitride semiconductor element can have a smaller electric resistance.

Further, this method for manufacturing a nitride semiconductor device includes a surface layer forming step for two-dimensionally growing the second n-GaN layer 16 on the upper side of the tunnel junction layer 15 formed by executing the tunnel junction layer forming step. .. Therefore, in this method for manufacturing a nitride semiconductor device, the second n-GaN layer 16 can be two-dimensionally grown and formed by executing the surface layer forming step. Therefore, in this method of manufacturing a nitride semiconductor device, a second n-GaN layer 16 is two-dimensionally grown and laminated on the surface side of a three-dimensionally grown tunnel junction layer 15 to obtain a three-dimensionally grown tunnel junction layer 15. Can be covered. Therefore, in this method for manufacturing a nitride semiconductor device, since the tunnel junction layer 15 grown three-dimensionally by adding an n-type semiconductor impurity can be used for the device, the tunnel junction layer 15 having a smaller electric resistance is provided. Nitride semiconductor devices can be manufactured.

Further, in this method for manufacturing a nitride semiconductor element, the semiconductor impurity is an n-type semiconductor impurity. Therefore, in this method of manufacturing a nitride semiconductor device, a tunnel junction layer 15 is formed by adding an amount of n-type semiconductor impurities that grows three-dimensionally. Thereby, in this method of manufacturing the nitride semiconductor element, the second n-GaN layer 16 can be formed not by the p-type semiconductor layer but by the n-type semiconductor layer. Thereby, this method for manufacturing a nitride semiconductor device can manufacture a nitride semiconductor device having a smaller electric resistance.

The present invention is not limited to Examples 1 to 4 described with reference to the above description and drawings, and for example, the following examples are also included in the technical scope of the present invention.
(1) In Examples 1 to 4, the back surface side of the tunnel junction layer has a general blue LED structure, but the present invention is not limited to this, and the voltage drop in the high current density region is greatly improved. Alternatively, a surface emitting laser structure in which a multilayer film reflecting mirror is provided on the back surface side of the first n-GaN layer may be used.
(2) In Examples 1 to 4, Mg is used as the p-type semiconductor impurity, but the present invention is not limited to this, and the p-type semiconductor impurities such as Zn, Be, Ca, Sr, and Ba may be used. ..
(3) In Examples 1 to 4, Si is used as the n-type semiconductor impurity, but the present invention is not limited to this, and Ge or the like, which is an n-type semiconductor impurity, may be used.
(4) In Examples 1 to 4, the p-AlGaN layer is laminated on the surface of the GaInN / GaN5 weight element well active layer, but the present invention is not limited to this, and p- is formed on the surface of the GaInN quantum well active layer. It is not necessary to stack and form AlGaN layers.
(5) In Examples 1 to 4, a sapphire substrate is used, but the present invention is not limited to this, and other substrates such as a gallium nitride substrate and an AlN substrate may be used.
(6) In Examples 1 to 4, the thickness of the p ⁺⁺ -GaInN layer of the tunnel junction layer is set to 2 nm, but the thickness is not limited to this, and the thickness of the p ⁺⁺ -GaInN layer of the tunnel junction layer may be smaller than 2 nm. It may be larger than 2 nm.
(7) In Examples 1 to 4, the thickness of the n ⁺⁺ -GaN layer of the tunnel junction layer is set to 15 nm, but the thickness is not limited to this, and the thickness of the n ⁺⁺ -GaInN layer of the tunnel junction layer may be smaller than 15 nm. It may be larger than 15 nm.
(8) In Examples 1 to 4, the InN mole fraction of the p ⁺⁺ -GaInN layer of the tunnel junction layer is set to 0.35, but the present invention is not limited to this, and the InN mole fraction of the p ⁺⁺ -GaInN layer of the tunnel junction layer is not limited to this. The rate may be less than 0.35 or greater than 0.35.
(9) In Examples 1 to 4, the crystals are grown by laminating using the MOCVD method, but the present invention is not limited to this, and the crystals may be grown by laminating using other methods such as HVPE and LPEE. ..

15 ... Tunnel junction layer 16 ... Second n-GaN layer (surface layer)

Claims (9)

A tunnel junction layer with semiconductor impurities added,
The surface layer formed on the upper side of the tunnel junction layer and
Equipped with
The interface of the tunnel junction layer on the surface layer side is a crystal surface grown three-dimensionally, and diffusion of the p-type semiconductor impurity, which is a semiconductor impurity, is suppressed from the tunnel junction layer .
A nitride semiconductor light emitting device characterized in that the tunnel junction layer side of the surface layer is three-dimensionally grown . The nitride semiconductor light emitting device according to claim 1, wherein the surface of the surface layer is a two-dimensionally grown crystal surface. The n-type first nitride semiconductor layer to which n-type semiconductor impurities are added, and the n-type first nitride semiconductor layer,
A p-type second nitride semiconductor layer to which p-type semiconductor impurities have been added, and a p-type second nitride semiconductor layer,
The active region between the first nitride semiconductor layer and the second nitride semiconductor layer,
A tunnel junction layer formed on the second nitride semiconductor layer and
A surface layer formed in contact with the upper side of the tunnel junction layer and
Equipped with
The tunnel junction layer is
A second high-concentration impurity layer, which is a nitride semiconductor formed on the surface of the second nitride semiconductor layer side and to which the p-type semiconductor impurities are added at a higher concentration than that of the second nitride semiconductor layer.
It has a first high-concentration impurity layer which is a nitride semiconductor formed on the surface of the second high-concentration impurity layer and to which the n-type semiconductor impurities are added at a higher concentration than the first nitride semiconductor layer. death,
The surface layer is the n-type nitride semiconductor layer, and the tunnel junction layer side is three-dimensionally grown.
A nitride semiconductor light emitting device, wherein the interface of the tunnel junction layer on the surface layer side is a crystal surface grown three-dimensionally, and diffusion of the p-type semiconductor impurities from the tunnel junction layer is suppressed. The nitride semiconductor light emitting device according to claim 3, wherein the first high-concentration impurity layer has a concentration of the n-type semiconductor impurity of 1 × 10 ²⁰ cm ^-3 or more. The nitride semiconductor light emitting device according to any one of claims 2 to 4, wherein the surface layer is a GaN layer having a thickness larger than 400 nm. The n-type semiconductor impurity is either Si or Ge, and is
The fifth aspect of the present invention is a direct reference to claims 3, 4, and 4, wherein the p-type semiconductor impurity is any one of Mg, Zn, Be, Ca, Sr, and Ba. The nitride semiconductor light emitting device according to any one of the following items. A tunnel junction layer forming step of adding an amount of semiconductor impurities that grows three-dimensionally and causing the three-dimensional growth to form a tunnel junction layer in which diffusion of the p-type semiconductor impurity, which is a semiconductor impurity, is suppressed .
A surface layer forming step of two-dimensionally growing a surface layer on the upper side of the tunnel junction layer formed by executing the tunnel junction layer forming step,
Equipped with
A method for manufacturing a nitride semiconductor light emitting device , wherein in the surface layer forming step, the surface layer grows two-dimensionally after three-dimensional growth continues . On the board,
The n-type first nitride semiconductor layer to which n-type semiconductor impurities are added, and the n-type first nitride semiconductor layer,
A p-type second nitride semiconductor layer to which p-type semiconductor impurities have been added, and a p-type second nitride semiconductor layer,
The active region between the first nitride semiconductor layer and the second nitride semiconductor layer,
And the laminating process of laminating
Next, a tunnel junction layer forming step of forming a tunnel junction layer on the second nitride semiconductor layer,
Next, it has a surface layer forming step in which the surface layer is two-dimensionally grown in contact with the upper side of the tunnel junction layer.
The tunnel junction layer forming step is a second nitride semiconductor in which the p-type semiconductor impurity is added to the surface of the second nitride semiconductor layer side at a higher concentration than that of the second nitride semiconductor layer. A first high-concentration nitride semiconductor in which a high-concentration impurity layer is formed and the n-type semiconductor impurity is added to the surface of the second high-concentration impurity layer at a higher concentration than that of the first nitride semiconductor layer. Including the step of forming an impurity layer
In the tunnel junction layer forming step, the n-type semiconductor impurity is added in an amount that grows three-dimensionally and the n-type semiconductor impurity is grown three-dimensionally to form the tunnel junction layer in which the diffusion of the p-type semiconductor impurity is suppressed .
A method for manufacturing a nitride semiconductor light emitting device in which the surface layer grows two-dimensionally after three-dimensional growth continues in the surface layer forming step . The first high-concentration impurity layer undergoes crystal growth under the condition that the concentration of the n-type semiconductor impurity is 1 × 10 ²⁰ cm ^-3 or more and the interface on the surface layer side becomes a three-dimensionally grown crystal surface.
In the surface layer forming step, the first conductive type nitride semiconductor layer is used as the surface layer under the condition that the surface becomes a crystal surface having two-dimensional growth at a higher temperature than the step of forming the tunnel junction layer. The method for manufacturing a nitride semiconductor light emitting device according to claim 8 , wherein the process is a growing process.

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