JP2019182712A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device formed by growing a crystal having low defects into a large area.SOLUTION: The semiconductor device formed on a silicon substrate using a plane direction (111) as one surface comprises: an insulation film formed on the one surface while including a through hole in the thickness direction orthogonal to the one surface; and a semiconductor layer constituted as an III-V group compound semiconductor including In, Ga and As, charged into the through hole and formed on the insulation film so as to cover the through hole. In the semiconductor layer, an atomic step existing on an exposed surface along the one surface has a height orthogonal to the one surface and equal to or less than three atomic layers.SELECTED DRAWING: Figure 1

Description

  The disclosure of this specification relates to a semiconductor device having a compound semiconductor as a composition.

  In the compound semiconductor, the band gap can be controlled by adjusting the composition of the constituent elements. As a compound semiconductor, for example, an InGaAs system which is a group III-V compound semiconductor is known. InGaAs has a smaller band gap than Si and has sensitivity in a long wavelength region. For this reason, it is expected as a constituent material of an infrared sensor that detects light having a wavelength longer than that of visible light.

  From the viewpoint of controlling the sensitivity wavelength region with higher accuracy or suppressing dark current, the InGaAs crystal is required to have a crystal having a low defect and a wide domain. In other words, it is required to obtain a large-area InGaAs crystal with high crystallinity.

  Patent Document 1 discloses a semiconductor device in which pillar-shaped InGaAs crystals are grown as nanowires on a silicon substrate. This disclosure is a technique that can realize low defects in a III-V group compound semiconductor.

  Patent Document 2 discloses a technique for reducing defects in a group III-V compound semiconductor that is epitaxially grown on a buffer layer by forming a buffer layer on Si serving as a substrate.

  Non-Patent Document 1 discloses a method of growing an InGaAs crystal around an InAs crystal grown in a pillar shape from an InAs nucleus, and an InGaAs crystal formed by the method. This technique is a knowledge for obtaining an InGaAs crystal having a large InGaAs area, in which the growth of the InGaAs crystal starts from the side surface of the InAs crystal serving as the axis and proceeds in the direction in which the step in the crystal faces. .

Republished 2011/105397 JP 2012-39115 A

M. Deura, et. Al, “Uniform InGaAs micro-discs on Si by micro-channel selective-area MOVPE”, Indium Phosphide & Related Materials, 2009. IPRM '09. IEEE.

  Although the semiconductor device disclosed in Patent Document 1 can realize low defects, there is a problem that a large-area III-V group compound semiconductor cannot be obtained. In addition, although the semiconductor device disclosed in Patent Document 2 is intended to reduce the crystal defects, it is unclear whether a large area can be realized in addition to not realizing sufficiently low defects.

  On the other hand, although the InGaAs crystal disclosed in Non-Patent Document 1 has a large area, it has been found that threading dislocation occurs between the InAs crystal serving as the axis and the growing InGaAs crystal. It has also been found that step bunching is likely to occur during crystal growth in the direction in which the step faces. Step bunching can cause defects in the groove structure at the interface when there are InGaAs crystals grown from a plurality of InAs axes on the same Si substrate. As described above, in terms of crystal growth of the III-V group compound semiconductor, the large area and the low defects are not compatible.

  Therefore, an object of the disclosure of this specification is to provide a semiconductor device in which a crystal having a low defect grows in a large area.

  The invention disclosed herein employs the following technical means to achieve the above object. In the claims and in this section, the numerical values shown in parentheses and braces are Miller indices.

  In order to achieve the above object, a semiconductor device disclosed in this specification is a semiconductor device formed on a silicon substrate having a plane orientation (111) as one surface, and has a through-hole in a thickness direction orthogonal to the one surface. And an insulating film formed on one surface while having a structure, and a III-V group compound semiconductor containing In, Ga, and As, and filling the through hole and covering the through hole on the insulating film The atomic step existing on the exposed surface along one surface of the semiconductor layer has a height of 3 atomic layers or less perpendicular to the one surface.

  The inventor succeeded in step-flow growth of a semiconductor layer that is a group III-V compound semiconductor in a direction along one surface of the silicon substrate, starting from the inside of the through hole. The atomic step formed on the exposed surface of the semiconductor layer along one surface is formed as a step with a relatively small step having a height of 1 to 3 atomic layers. The atoms constituting the III-V compound semiconductor contribute to the growth of the semiconductor layer by adsorbing to the atomic step. Therefore, it is possible to increase the area of the exposed surface.

  The inventor has found that many of the atomic steps on the exposed surface exhibit a predetermined plane orientation. In this plane orientation, the difference in lattice constant is small between the atomic step to be adsorbed and the portion constituted by the adsorbing atoms, and the stress between them can be relaxed. For this reason, step flow growth is promoted while suppressing generation of crystal defects such as threading dislocations. Since the semiconductor layer is formed so as to spread in the radial direction around the through hole when one surface of the silicon substrate is viewed from the front, it is easy to increase the area of the exposed surface.

1A and 1B are a cross-sectional view and a top view illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is the figure which carried out the bird's-eye photography of the semiconductor device with the scanning electron microscope. It is a figure which shows the result by the X ray diffraction method of a pillar part and a disk part. It is a figure which shows the sequence which concerns on the manufacturing method of a semiconductor device.

  Hereinafter, a plurality of modes for carrying out the present disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to the matters described in the preceding embodiment may be denoted by the same reference numerals, and redundant description may be omitted. When only a part of the configuration is described in each mode, the other modes described above can be applied to the other parts of the configuration. Not only combinations of parts that clearly indicate that combinations are possible in each form, but also forms may be partially combined even if they are not clearly specified, as long as there is no problem with the combination. Is possible.

(First embodiment)
First, a schematic configuration of the semiconductor device according to the present embodiment will be described with reference to FIGS. In each figure and specification, numbers in parentheses are Miller indices, those indicated by parentheses () indicate plane orientations, and those indicated by square brackets [] indicate directions. The curly braces {} are used to display equivalent plane orientations collectively. In addition, angle brackets <> indicate equivalent directions at once.

  This semiconductor device is a III-V group compound semiconductor, and is composed of, for example, InGaAs as a main component and is used for a photodiode or the like.

  As shown in FIG. 1, the semiconductor device 100 is formed on a silicon substrate 200. The semiconductor device 100 includes a semiconductor layer 10 containing InGaAs as a main component and an insulating film 30 for forming the pillar portion 12. The semiconductor layer 10 in the present embodiment includes a disk portion 11 and a pillar portion 12 serving as an axis for forming the disk portion 11, but is a III-V group compound semiconductor containing In, Ga, and As. The semiconductor layer 10 is integrally formed.

  The silicon substrate 200 is a single crystal substrate having a surface orientation (111) exposed on one surface 200a. The cross-sectional view in FIG. 1 is a view seen from a direction orthogonal to the orientation flat.

  The insulating film 30 is a silicon oxide film formed on the one surface 200 a of the silicon substrate 200. The film thickness is approximately 100 nm, for example. The insulating film 30 can be formed by a generally known method. For example, it may be formed by a sputter deposition method or may be formed by thermal oxidation. The insulating film 30 is partially formed with a through hole 30a. The through hole 30a penetrates the insulating film 30 in the thickness direction, and the one surface 200a of the silicon substrate 200 is exposed from the insulating film 30 at the position where the through hole 30a is formed. The through hole 30a is formed in a columnar shape, for example. That is, when the one surface 200a is viewed from the front, the exposed portion of the one surface 200a is circular. In this embodiment, the diameter is about 1 μm to 2 μm.

  The semiconductor layer 10 has a disk part 11 and a pillar part 12. The pillar portion 12 is a crystal body mainly composed of InGaAs. The pillar portion 12 is formed in accordance with the shape of the through hole 30a formed in the insulating film 30, and is formed in a substantially cylindrical shape. The upper surface of the pillar portion 12 that does not contact the silicon substrate 200 has a (111) plane orientation. The pillar portion 12 is formed so as to extend in the penetrating direction of the through hole 30a, and is formed so as to protrude from one surface of the insulating film 30 that does not contact the silicon substrate 200. In the pillar portion 12, a portion protruding from the insulating film 30 becomes an axis for growing the disk portion 11. As will be described later, the pillar portion 12 is also formed by growing an InGaAs crystal generated inside the through hole 30a as a nucleus.

  The disk part 11 is a crystal body mainly composed of InGaAs. The disk portion 11 is formed so as to spread on the surface of the insulating film 30 with the central axis of the columnar pillar portion 12 as an axis, and has a substantially hexagonal shape when the insulating film 30 is viewed from the front. The disk portion 11 is formed with a thickness in the axial direction of the pillar portion 12, and as shown in FIG. One side surface of the hexagonal column is parallel to the orientation flat of the silicon substrate 200, and as shown in FIG. 1, this surface is a (−110) plane. FIG. 2 is a result of photographing with a scanning electron microscope (SEM) in which the disk unit 11 is viewed from above.

  The disk portion 11 has an exposed surface 10a that is parallel to the one surface 200a of the silicon substrate 200 and exposed to the outside. As shown in FIG. 1, the exposed surface 10a is a crystal surface with the (111) plane exposed. Each of the six side surfaces forming the disk portion 11 has an exposed {−110} plane.

  The exposed surface 10a in the disk part 11 has an atomic step 10b from a microscopic viewpoint. The atomic step 10b in the present embodiment has a height of 1 to 3 atomic layers, and is about 0.3 nm to 1.5 nm.

  There are no crystal planes without atomic steps, but it is known that conventional InGaAs crystals cause step bunching with atomic step heights of several tens of atomic layers (tens of nanometers) or more during the growth process. Yes. On the other hand, in this embodiment, the height of the atomic step 10b formed on the exposed surface 10a is suppressed to 3 atomic layers or less by adopting the pillar portion 12 mainly composed of InGaAs. The terrace length between the atomic step 10b and another adjacent atomic step 10b is about 100 nm to 500 nm.

  The disk portion 11 is formed by so-called step flow growth in which each element of In, Ga, and As is adsorbed on the atomic step 10b to grow crystals. That is, the disk portion 11 is formed to expand and grow in the radial direction when the axis of the pillar portion 12 is the center. Specifically, each element of In, Ga, and As is mainly adsorbed on the atomic step 10b along the three sides of a substantially equilateral triangle indicated by a broken line in the top view of FIG. The atomic step 10b along these three sides has (101), (011), and (110) plane orientations. Since these are equivalent plane orientations, they can be expressed as {110}. Accordingly, the direction of step flow growth is [101], [011], and [110] as shown in FIG. Since these are equivalent directions, they can be expressed as <110>. In addition, the equilateral triangle shown with a broken line does not show the shape of a terrace directly, but shows the extending direction of the atomic step 10b for convenience. The main atomic steps 10b formed on the exposed surface 10a are formed so that the surfaces orthogonal to the exposed surface 10a are substantially parallel to the sides of the triangle.

Further, the concentration of Ga atoms in the disk portion 11 increases as the distance from the pillar portion 12 serving as an axis increases. FIG. 3 shows composition data obtained by the X-ray diffraction method. The horizontal axis is the value of 2θ with respect to the diffraction angle θ, and the vertical axis is the diffraction intensity. The diffraction intensity is normalized by the peak of Si (111) as the base. It is known that the peak of InAs is 2θ≈25.45 degrees, and the peak of GaAs is 2θ≈27.30 degrees. In In _(1-x) Ga _x As, when the concentration of Ga with respect to In increases (x increases), the peak of diffraction intensity is set to 2θ, from 25.45 degrees to 27.30 degrees. It increases continuously in the range up to. According to the results shown in FIG. 3, the peak indicating In ₉₀ Ga ₁₀ As is detected in both the pillar portion 12 and the disk portion 11, and is broad on the side where the Ga concentration increases.

The fact that a peak indicating In ₉₀ Ga ₁₀ As is detected in both the disk portion 11 and the pillar portion 12 is that stress caused by the difference in lattice constant is relaxed in the vicinity of the interface between the disk portion 11 and the pillar portion 12. Therefore, it is presumed that the Ga concentration is substantially the same as the Ga concentration of the pillar portion 12.

  Further, in the result shown in FIG. 3, in the region where x> 0.1, the diffraction intensity changes more broadly in the disk portion 11 than in the pillar portion 12, so that the distance from the pillar portion 12 is large. It is presumed that the Ga concentration is increasing. This is presumed to be caused by the difference in diffusion length of each component of In, Ga, and As. It is considered that Ga having a relatively long diffusion length can easily reach the end of the semiconductor layer 10. As described above, the Ga concentration is relatively increased continuously in the radial direction around the axis of the pillar portion 12.

  Next, with reference to FIG. 4, the manufacturing method of the semiconductor device 100 concerning this embodiment is demonstrated.

  First, a single crystal silicon substrate 200 having a (111) surface exposed on one surface 200a is prepared. It is preferable that the (111) plane of the silicon substrate 200 is sufficiently cleaned.

Next, the insulating film 30 is formed on the one surface 200a. The insulating film 30 can be formed, for example, by oxidizing the silicon substrate 200 to form a SiO ₂ thin film. A through hole 30a is formed in the insulating film 30 by patterning. The cross section of the through-hole 30a in this embodiment is circular, and the diameter is about 1 μm to 2 μm. The diameter is not particularly limited, but if the diameter of the through hole 30a is too large, a plurality of formation nuclei, which will be described later, which serve as nuclei for the growth of the pillar portion 12 are generated, and the crystal of the pillar portion 12 is formed. There is a risk of increasing the grain boundary, and the diameter of the through hole 30a is preferably 5 μm or less. Further, if the through hole 30a is too small, the formed pillar portion 12 is also small, and it may be difficult to grow the disk portion 11 in a large area.

  Next, the silicon substrate 200 on which the insulating film 30 is formed is put into a CVD furnace. Then, the temperature of the silicon substrate 200 is raised and the surface is cleaned again.

The silicon substrate 200 is maintained at a predetermined temperature for a time that can be sufficiently cleaned, and then the temperature is lowered. Arsine (AsH ₃ ) is introduced at a partial pressure of approximately 4430 × 10 ⁻⁴ Torr in accordance with the start of temperature drop.

Next, a process of forming formation nuclei 21 that serve as nuclei for growth of the pillar portion 12 is performed. Specifically, as shown in FIG. 4, when the temperature of the silicon substrate 200 is lowered to 610 ° C., trimethylgallium (TMG) and trimethylindium (TMI) are respectively divided by 17.9 × 10 ⁻ Installation begins at ⁴ Torr. Arsine will be continuously introduced. At this time, in particular, the flow of arsine, TMG, and TMI is generated and supplied in the direction along the axial direction while rotating the silicon substrate 200 at 900 rpm with respect to the axis orthogonal to the one surface 200a. When the state in which the partial pressures of arsine, TMG, and TMI are stable is continued for about 5 seconds, one single crystal grain of InGaAs is generated inside the through hole 30a.

After the formation process of the formation nucleus 21, the formation process of the pillar part 12 is implemented. The partial pressure of TMG is set to 5.18 × 10 ⁻⁴ Torr, and the partial pressure of TMI is set to 3.48 × 10 ⁻⁴ Torr. Thus, by increasing the molar ratio of the group V source to the group III source (V / III ratio), the direction of crystal growth of InGaAs can be directed to the vertical growth along the axial direction of the through hole 30a. In the step of forming the pillar portion 12, the supply of arsine is reduced to a partial pressure of about 3228 × 10 ⁻⁴ Torr. After about 60 minutes, the height of the pillar portion 12 along the axial direction can be reduced to about 1 μm. In the process of forming the formation nuclei 21, since only one formation nuclei 21 is generated, the pillar portion 12 is generated almost as a single crystal with few defects such as grain boundaries.

Next, a step of forming the disk portion 11 is performed. The temperature of the silicon substrate 200 is raised to approximately 640 ° C., the TMG partial pressure is set to 25.44 × 10 ⁻⁴ Torr, and the TMI partial pressure is set to 113.6 × 10 ⁻⁴ Torr. Thus, by reducing the V / III ratio, the direction of crystal growth of InGaAs can be directed to the lateral growth corresponding to the radial direction when the axis of the through hole 30a is the center. This growth is step flow growth and grows in the <110> direction as described above. Further, the growth rate can be a growth with little deviation for each atomic step 10b, and the exposed surface 10a is suppressed in which the generation of step bunching is suppressed. In the present embodiment, when the exposed surface 10a of the disk portion 11 is viewed from the front, the longest distance from the central axis of the through hole 30a to the end of the disk portion 11 is 1.3 times or more the radius of the through hole 30a. It has become.

  The formation process of the disk part 11 is continued until the area of the exposed surface 10a of the disk part 11 reaches a desired size. In the end sequence of the formation process of the disk portion 11, the supply of TMG and TMI is first stopped. Thereafter, the temperature lowering of the silicon substrate 200 is started. As a result of the temperature drop, when the temperature reaches 200 ° C., the supply of arsine is stopped and the temperature of the silicon substrate 200 is lowered to room temperature.

  In this way, the semiconductor device 100 can be manufactured.

  As disclosed above, since the InGaAs disk portion 11 can be integrally grown around the pillar portion 12 of InGaAs single crystal, the occurrence of threading dislocation between the pillar portion 12 and the disk portion 11 can be suppressed. . Further, since the crystal growth of the disk portion 11 is growth along the disk surface by step flow growth, a large area can be realized. Then, during step flow growth, deviation in the crystal growth rate in the atomic step 10b can be suppressed, and generation of step bunching can be suppressed. Therefore, a lower defect InGaAs crystal can be obtained in a large area.

(Other embodiments)
The preferred embodiment has been described above, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist disclosed in this specification.

  In the manufacturing method described with reference to FIG. 4, values such as temperature and partial pressure are not limited to those values, and the size to be formed of the pillar portion 12 and the disk portion 11 and a desired film thickness. This should be set as appropriate.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 11 ... Disk part, 10a ... Exposed surface, 10b ... Atomic step, 12 ... Pillar part, 21 ... Formation nucleus, 30 ... Insulating film, 30a ... Through-hole, 200 ... Silicon substrate

Claims (7)

A semiconductor device formed on a silicon substrate having a plane orientation (111) as one surface,
An insulating film formed on the one surface while having a through hole in a thickness direction perpendicular to the one surface;
A semiconductor layer that is configured as a III-V group compound semiconductor containing In, Ga, and As, is filled in the through hole, and is formed on the insulating film so as to cover the through hole,
In the semiconductor layer, the atomic step existing on the exposed surface along the one surface is a semiconductor device having a height of 3 atomic layers or less perpendicular to the one surface.   2. The semiconductor device according to claim 1, wherein the atomic step includes {110} in a plane orientation orthogonal to the exposed surface.   The semiconductor device according to claim 1, wherein the semiconductor layer has a Ga content that continuously increases as the distance from the through hole increases in a radial direction along the exposed surface.   4. The semiconductor layer according to claim 1, wherein the semiconductor layer has a hexagonal column shape in which the exposed surface along the one surface includes (111) as a surface orientation and a {−110} surface is exposed as a side surface. Semiconductor device.   5. The semiconductor device according to claim 1, wherein the through hole has a cylindrical shape, and the diameter of the through hole when the one surface is viewed from the front is 5 μm or less.   The semiconductor device according to claim 5, wherein a thickness of the semiconductor layer perpendicular to the exposed surface is larger than a diameter of the through hole.   The longest distance from the central axis of the through hole to the end of the semiconductor layer when the exposed surface of the semiconductor layer is viewed from the front is 1.3 times or more the radius of the through hole. Item 7. The semiconductor device according to Item 6.