JP5652259B2 - Analog to digital converter - Google Patents

Description

  The present invention relates to an analog-digital converter.

  An analog-digital converter (AD converter or ADC) converts an analog input signal into a digital output signal (AD conversion). For example, the analog voltage of the analog input signal is compared with a reference voltage corresponding to each bit of the digital output signal, and the magnitude of the analog voltage is converted into a digital signal.

  The AD converter holds an analog input signal to be converted by a track and hold circuit or a sample and hold circuit, and AD converts the held analog signal. The AD converter includes a flash type ADC that simultaneously converts a held analog signal into a multi-bit digital signal, and a successive approximation type ADC that sequentially determines the higher bits of the digital signal. The present application relates to a successive approximation ADC.

  The successive approximation AD converter includes a track-and-hold circuit or sample-and-hold circuit, a digital-to-analog converter (ADC), a comparator that compares the held analog signal with the reference voltage generated by the ADC, A register circuit for storing the comparison result and a control circuit for supplying a digital signal corresponding to the reference voltage to the DAC according to the comparison result. Then, the digital signal is converted into a multi-bit digital signal by performing successive comparison with the binary search algorithm from the upper bit to the lower bit.

  As a conversion method, there are a clock synchronous type in which AD conversion is performed bit by bit in synchronization with a clock and a clock asynchronous type in which AD conversion of all bits is performed within one clock. Clock asynchronous AD converters are compatible with high-speed operation, and higher speeds are required.

JP-A-5-152960 Japanese Patent Laid-Open No. 5-199116

  In recent years, successive approximation AD converters are required to operate at higher speeds. In particular, a clock asynchronous AD converter capable of high-speed operation can shorten the AD conversion time once and increase the ADC sampling frequency even if the number of bits of the digital signal indicating the ADC resolution is increased. Desired.

  The conventional successive approximation AD converter has a problem that the internal analog circuit portion such as the comparator cannot follow the high-speed internal clock in the AD converter, and the conversion accuracy is remarkably lowered.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a successive approximation AD converter with higher speed.

The first aspect of the AD converter is an AD converter that converts an analog input signal into a digital output signal,
An N-stage comparison unit that compares the analog input signal with a reference voltage and sequentially outputs each bit of the digital output signal according to the comparison result;
A logic circuit for sequentially generating a reference voltage generation digital signal corresponding to the reference voltage based on each bit of the digital output signal output by the comparison unit;
A DA converter that generates the reference voltage based on the reference voltage generation digital signal,
Each of the N-stage comparison units includes a comparator that changes from a reset state to a determination state in response to a determination state of the state control signal from the previous stage, and a subsequent stage when the comparator outputs a comparison result in the determination state. A state control signal generation unit for making a state control signal to the comparison unit of
In response to the trigger clock, the comparator of the N-stage comparison unit sequentially performs a comparison operation from the upper bit to the lower bit.

  According to the first aspect, it is possible to provide a successive approximation AD converter that is faster.

It is a circuit diagram of a successive approximation AD converter in the present embodiment. It is a circuit diagram of comparators COMP1-4 in the comparison unit. 2 is a configuration diagram of a logic circuit 14. FIG. It is a figure which shows operation | movement of the successive approximation type AD converter in 1st Embodiment shown in FIG. It is a figure which shows an example of the relationship between the analog input signal Vin and the reference voltage Vdac. It is a circuit diagram of the AD converter in 2nd Embodiment. FIG. 10 is a circuit diagram of comparators COMP1-4 in the second embodiment. It is a figure which shows operation | movement of the AD converter in 2nd Embodiment. FIG. 10 is a circuit diagram of an 8-bit AD converter according to a third embodiment. 3 is a circuit diagram of a 3-bit shift register 32. FIG. 3 is a circuit diagram of an internal clock control circuit 30. FIG. 2 is a circuit diagram of a logic circuit 14. FIG. It is an operation | movement waveform diagram of the AD converter in 3rd Embodiment. It is a block diagram of the AD converter of the comparative example corresponding to this Embodiment. It is a figure which shows the comparison result of the simulation with the AD converter of 1st, 2nd embodiment, and the AD converter of a comparative example.

  FIG. 1 is a circuit diagram of a successive approximation AD converter according to the present embodiment. This AD converter converts the analog input signal Vin_th obtained by holding the analog input signal Vin by the track and hold circuit 10 into digital output signals D1-D4. The track-and-hold circuit 10 tracks the analog input signal Vin while the external clock ECLK generated by the external clock generator 12 is at the H level, and holds it at the timing when it becomes the L level. The track and hold circuit 10 may be a sample and hold circuit that samples and holds the analog input signal Vin at the rising edge of the external clock ECLK. The external clock ECLK is a trigger clock that triggers the AD converter to start AD conversion.

  The AD converter compares the held analog input signal Vin_th with the reference voltage Vdac and sequentially outputs each bit of the digital output signal corresponding to the comparison result, and the comparison unit includes a comparison unit CU1-4. A logic circuit 14 that sequentially generates a reference voltage generation digital signal DAC1-4 corresponding to the reference voltage Vdac based on each bit of the output digital output signal, and a reference voltage Vdac based on the reference voltage generation digital signal DAC1-4 A DA converter 16.

  Each of the four-stage comparison units CU1-4 includes a comparator COMP1-3 that transitions from the reset state to the determination state in response to the change of the state control signal CLK1-4 from the previous stage to the determination state (L level). A state control signal generation unit that sets a state control signal CLK2-4 to the subsequent stage when the comparator transitions to the determination state and outputs a comparison result. The state control signal generation unit includes, for example, an EOR gate EOR1-3 that inputs the differential outputs OP1-3 and OM1-3 of the comparators COMP1-3, an inverter INV1-3, and an OR gate OR1-3.

  The state control signal CLK1 to the first-stage comparison unit CU1 is an external clock (trigger clock) ECLK output from the external clock generation circuit 12. When the external clock ECLK is at H level, the first-stage state control signal CLK1 is in a reset state. (H level), and the 2-4 stage state control signals CLK2-4 via the OR gates OR1-3 are also in the reset state (H level). That is, in the initial state, the state control signals CLK1-4 to all the comparison units CU1-4 are in the reset state (H level).

  When the external clock ECLK changes from the H level to the L level, the first-stage state control signal CLK1 changes from the reset state (H level) to the determination operation state (L level). Furthermore, when the comparator COMP1 of the first stage performs a judgment operation and the differential outputs OP1 and OM1 become H, L or L, H, the EOR gate EOR1 sets the output to the H level, and the state control signal CLK2 to the subsequent stage is reset. From the state (H level) to the judgment operation state (L level). This operation is also transmitted to the second-stage comparator COMP2, the third-stage comparator COMP3, and the fourth-stage comparator COMP4, and the comparators of the respective comparison units perform comparison operations sequentially and sequentially.

  Each comparison unit CU1-4 further includes a flip-flop DFF1-4 that takes in the positive output OP1-4 of each comparator COMP1-4 in response to the rising edge of the output of the EOR gate, and is latched there The comparison result DOUT1-4 is supplied to the control circuit 14 having a 4-bit register as a signal of each bit of the digital output signal from the most significant to the least significant.

  FIG. 2 is a circuit diagram of the comparators COMP1-4 in the comparison unit. Comparator COMP # (# = 1-4) includes P-channel transistors P1 and P2 for a load whose gate is biased with a bias voltage Vb, and an N-channel transistor in which a positive input IP and a negative input IM are input to the gate, respectively. N7 and N8, and N-channel transistors N5 and N6 having a latch function with their gates and drains cross-connected. Furthermore, P channel transistors P3 and P4 to which a state control signal / CLK which is an internal clock is input, and an N channel transistor N9 for a current circuit are included. The state control signal / CLK is an inverted signal of the state control signal CLK.

  As is apparent from the circuit of FIG. 2, when the state control signal CLK is H level, that is, when the inverted signal / CLK is L level, the transistors P3 and P4 are turned on, the transistor N9 is turned off, and the output pair OP and OM are Both become H level. This is the reset state. On the other hand, when the state control signal CLK is at L level, that is, when the inverted signal / CLK is at H level, the transistors P3 and P4 are non-conductive and the transistor N9 is conductive, and the output pair OP and OP depend on the difference between the input pair IP and IM. , OM becomes H, L or L, H, and one of the output pair OP, OM becomes the power supply VDD and the other becomes the ground VSS by the latch circuit by the transistors N5, N6. This is the determination operation state.

  Therefore, in each comparison unit, if the comparators COMP1-4 are in the reset state, the output of the EOR gate is L level, and if it is in the judgment operation state, the output of the EOR gate is H level.

  FIG. 3 is a configuration diagram of the logic circuit 14. The logic circuit 14 includes a 4-bit register (RG1-4) 14-1 that latches the comparison result DOUT1-4 output from each comparison unit CU1-4, and a reference voltage generation digital signal to the DAC circuit that generates the reference voltage Vdac. And SAR logic circuit 14-2 for generating signals DAC1-4.

  When the state control signal CLK1 that is the external clock ECLK becomes H level after the 4-bit determination operation is finished, the 4-bit register 14-1 responds to the rising edge to the flip-flops DFF1-4 of each comparison unit. The latched comparison result DOUT1-4 is taken into the 4-bit register RG1-4.

  The SAR logic circuit 14-2 (1) sets the corresponding digital signal DAC1-4 to H level in synchronization with the comparison timing of each comparison unit CU1-4, and (2) after the comparison operation of each comparison unit is completed. The digital signals DAC1-4 are set to H level or L level according to the comparison result DOUT1-4. Therefore, the subsequent OR gate in the SAR logic circuit 14-2 performs the above operation (1) by setting the digital signals DAC1-4 to the H level according to the output of the previous AND gate and the internal clock / CLK4. After the operation (1), the digital signals DAC1-4 are set to the H level or the L level according to the comparison results DOUT1-4 of the respective comparison units.

FIG. 4 is a diagram showing the operation of the successive approximation AD converter in the first embodiment shown in FIG. FIG. 4 shows one AD conversion operation, and one AD conversion operation is composed of a tracking period in which the external clock ECLK is at the H level and a hold period in which the external clock ECLK is at the L level. That is, the times T1 to T5 are as follows.
T1: Analog input signal Vin tracking period
T2: Most significant bit MSB judgment period
T3: Second bit judgment period
T4: Third bit judgment period
T5: Fourth bit determination period Further, the operation states of the comparators COMP1-4 of each comparison unit are as follows.
R: Reset state (state control signal CLK = H)
J: Judgment operation status (status control signal CLK = L)
X: Operation indefinite state And FIG. 4 also shows the transition of the H and L levels of the state control signals CLK1-4, which are internal clocks of the respective comparison units.

  FIG. 5 is a diagram illustrating an example of the relationship between the analog input signal Vin and the reference voltage Vdac. In this example, the analog input signal Vin is at a potential between the reference voltages 3Vre / 4 and Vref. The operation of the successive approximation AD converter according to the first embodiment will be described below with reference to FIG. 4 for the example of FIG.

  In FIG. 4, first, at time T1, the analog input signal Vin is tracked by the track and hold circuit 10, and Vin = Vin_th. At this time, the state control signal CLK1 = H, which is an internal clock, is set by the external clock ECLK = H, and the other state control signals CLK2,3,4 = H are set by the OR gates OR1,2,3. Therefore, all the comparators COMP1-4 are all in the reset state.

At time T2, when the external clock ECLK = L, the state control signal CLK1 = L, the comparator COMP1 enters the determination state, and the determination of the most significant bit MSB is started. At this time, the SAR logic circuit 14-2 sets the DAC1 of the MSB of the digital input signal of the DAC circuit 16 to the H level by CLK1 = L and CLK2 = H, and all the lower-order DAC2-4 are set to the L level. The reference voltage Vdac generated by the following values:
Vdac = Vref / 2 * 1 + Vref / 4 * 0 + Vref / 8 * 0 + Vref / 16 * 0 = Vref / 2 (1)
According to FIG. 5, since Vin> Vdac = Vref / 2, the output (determination result) of the comparator COMP1 is OP1 = H and OM1 = L. However, since the state control signals CLK2 to 4 = H, the other comparators COMP2 to COMP4 are in a reset state.

  When the determination operation of the comparator COMP1 is completed, the output pair OP, OM is at the H, L level or the L, H level. Therefore, the output of the EOR gate EOR1 rises, and at the rising edge, the determination result of the comparator COMP1 is held by the flip-flop DFF1, and is output to the subsequent 4-bit register circuit. According to the example of FIG. 5, the most significant bit MSB (DOUT1) is determined to be H level, and the digital signal D1 after AD conversion is H level (D1 = H).

At time T3 in FIG. 4, when the output of the OR gate OR1 changes from the H level to the L level, the state control signal that is the internal clock becomes CLK2 = L, and the comparator COMP2 starts the determination of the second bit. . At this time, the first bit DAC1 of the digital input signal of the DAC circuit 16 is set to DAC1 = H by the determination result DOUT1 = H of the first bit at time T2, and the second bit DAC2 is CLK2 = L, CLK3 = Due to H, DAC2 = H, lower bits DAC3 and 4 below it are set to L, and the reference voltage Vdac becomes the following value.
Vdac = Vref / 2 * 1 + Vref / 4 * 1 + Vref / 8 * 0 + Vref / 16 * 0 = 3Vref / 4 (2)
According to the example of FIG. 5, since Vin> Vdac = 3Vref / 4, the output (determination result) of the comparator COMP2 is OP2 = H and OM2 = L. However, since the state control signals CLK3,4 = H, the comparators COMP3,4 are in the reset state.

  After completion of the determination of the comparator COMP2, the determination result of the comparator COMP2 is held by the flip-flop DFF2 at the rising edge of the output of the EOR gate EOR2, and is output to the subsequent 4-bit register circuit 14. The second bit D2 of the determination result is determined to be H level (D2 = H).

Next, at time T4 in FIG. 4, when the output of the OR gate OR2 changes from H to L, the state control signal which is an internal clock becomes CLK3 = L, and the third bit determination is started by the comparator COMP3. The At this time, the 1st and 2nd bit DAC1 and 2 of the digital input signal of the DAC circuit are both at the H level according to the judgment results DOUT1 and DOUT2, and the 3rd bit DAC3 becomes DAC3 = H when CLK3 = L and CLK4 = H. , The lower bit DAC4 below it is set to L level, and the reference voltage Vdac has the following value.
Vdac = Vref / 2 * 1 + Vref / 4 * 1 + Vref / 8 * 1 + Vref / 16 * 0 = 7Vref / 8 (3)
According to FIG. 5, Vin <Vdac = 7Vref / 4, and the output (determination result) of the comparator COMP3 is OP3 = L and OM3 = H. However, because CLK4 = H, the comparator COMP4 is in a reset state.

  After completion of the determination of the comparator COMP3, the determination result of the comparator COMP3 is held by the flip-flop DFF3 at the rising edge of the output of the EOR gate EOR3, and is output to the subsequent 4-bit register circuit. The third bit D3 is determined to be L level (D3 = L).

At time T5 in FIG. 4, when the output of the OR gate OR3 changes from H level to L level, the state control signal that is the internal clock becomes CLK4 = L, and the comparator COMP4 starts to determine the least significant bit LSB. The At this time, the digital input signals DAC1,2,3 of the DAC circuit are at the H, H, L level based on the determination results DOUT1, 2, 3, and the lowest DAC4 is set to DAC4 = H by CLK4 = L. The reference voltage Vdac generated by is the following value.
Vdac = Vref / 2 * 1 + Vref / 4 * 1 + Vref / 8 * 0 + Vref / 16 * 1 = 13Vref / 16 (4)
According to FIG. 5, since Vin> Vdac = 13Vref / 16, the output (determination result) of the comparator COMP4 is OP4 = H and OM4 = L. After completion of the determination of the comparator COMP4, the determination result of the comparator COMP4 is held by the flip-flop DFF4 at the rising edge of the output of the EOR gate EOR4, and is output to the subsequent 4-bit register circuit. The least significant bit D4 is determined to be H (D4 = H).

  When all bits have been judged, the external clock ECLK changes to H level, and the judgment result DOUT1-4 latched by the flip-flop DFF-4 in each comparison unit becomes the H level of the internal clock CLK1 (= ECLK). At the rising edge, the data is latched in the 4-bit register 14-1. After the AD conversion is completed, the external clock signal ECLK becomes H level, so that the state again returns to the time T1 in FIG. By repeating the operation from time T1 to time T4 in FIG. 4, the AD conversion operation synchronized with the external clock ECLK is repeated.

  According to the first embodiment, the comparators COMP1-4 in the four comparison units are sequentially changed from the reset state to the determination state, and the 4-bit digital signal DOUT1 is obtained by binary search from the most significant bit to the least significant bit. -4 is sequentially determined asynchronously and sequentially to the external clock ECLK. Therefore, as compared with the case where one comparator is used four times, it is not necessary to return the comparator to the reset operation, so that the determination of the 4-bit digital signal can be completed in a short time. Therefore, the AD converter can follow even if the frequency of the external clock ECLK is increased.

[Second Embodiment]
In the second embodiment, in the AD converter according to the first embodiment, after each of the comparators COMP1-4 completes the determination operation, the comparators are put into a power-down state to reduce power consumption. To do.

  FIG. 6 is a circuit diagram of the AD converter according to the second embodiment. The configuration different from the first embodiment of FIG. 1 is that the comparators COMP1-4 in each comparison unit CU1-4 have an enable state and a disable state (operation state and operation stop state) in addition to the reset state and determination state. ) And the output of the inverter INV1-4 is input to each comparator COMP1-4 as the enable signal EN1-4.

  The comparators COMP1-4 perform a determination operation in response to the H level of the state control signal CLK1-4 when the enable signal EN1-4 is at the H level. When the enable signal EN1-4 becomes the L level, the state control signal Regardless of the level of CLK1-4, the operation is stopped and a power-down state is achieved in which no through current flows. Therefore, each comparator COMP1-4 is reset in the initial state and does not consume current. When it enters the judgment state, it consumes current by the judgment operation, and after the judgment operation, it is stopped and does not consume current again. That is, power saving can be achieved.

  FIG. 7 is a circuit diagram of the comparators COMP1-4 in the second embodiment. A configuration different from the circuit of the comparator of FIG. 2 is that an AND gate 20 for inputting the state control signal / CLK and the enable signal EN is provided at the gate of the current source transistor N9. The rest is the same as FIG.

  With this configuration, the state control signal / CLK is reset at the L level (CLK = H), the output pair OP, OM is both set to the VDD level (H level), / CLK = H (CLK = L) and EN = H, the judgment state is entered, the output of the AND gate 20 becomes L level when the enable signal EN = L with the state control signal / CLK = H, the transistor N9 becomes non-conductive, the through current is eliminated, and the power down state is entered. . Thereafter, when the state control signal / CLK = L level again, the transistors P3 and P4 become conductive, and the output pair OP and OM are pulled up to the VDD level to be in a reset state.

  FIG. 8 is a diagram illustrating the operation of the AD converter according to the second embodiment. This operation is the operation when the analog input signal Vin of FIG. 5 is input, as in the first embodiment. Accordingly, each of the comparison units CU1-4 sequentially performs the determination operation from the most significant bit to the least significant bit in response to the change of the external clock ECLK from the H level to the L level. Is the same.

  However, in the case of the second embodiment, after the comparator COMP1-4 completes the comparison operation in each comparison unit CU1-4, the output of the corresponding inverter INV1-4 falls from the H level to the L level. Thus, the comparator is stopped. In other words, the current source transistor N9 of the comparator is turned off and enters a power down state. This power-down state is maintained until the AD conversion is completed. This is an operation different from that of the first embodiment.

  That is, in FIG. 8, at time T2, after the comparator COMP1 performs a comparison operation in response to the L level of the state control signal CLK1, the output of the EOR gate EOR1 becomes H level and the output of the inverter INV1 becomes L level. Therefore, the comparator COMP1 in the operating state is stopped (powered down). Similarly, at time T3, T4, and T5, the comparators COMP2, 3, and 4 perform the comparison operation in response to the L level of the state control signals CLK2, 3, 4, and then the inverters INV2, 3, 4, Becomes the L level, the enable signals EN2, 3, and 4 become the L level, and the comparator changes from the operating state to the operation stopped state (power down state). As a result, after the comparators COMP1, 2, 3, and 4 complete the comparison operation and the comparison result is latched in the flip-flops DFF1, 2, 3, and 4 in the subsequent stage, each comparator is put into a power-down state. Therefore, wasteful current consumption is prevented.

[Third Embodiment]
In the first and second embodiments, four comparison units CU1-4 are provided to generate a 4-bit digital output signal. In order to increase the digital output resolution by increasing the number of bits of the digital output signal to more than 4 bits, it is required to increase the number of comparison units CU corresponding to the number of bits. This undesirably increases the circuit scale.

  Therefore, in the AD converter according to the third embodiment, the number of bits larger than 4 bits, for example, 8 bits, 12 bits, and 16 bits, can be obtained by repeating the 4-bit sequential comparison operation by a plurality of comparison units a plurality of times. Convert to digital output signal.

  FIG. 9 is a circuit diagram of an 8-bit AD converter according to the third embodiment. Similar to the AD converter of the first embodiment shown in FIG. 1, a track-and-hold circuit 10 that tracks and holds the analog input signal Vin and a four-stage circuit that compares the held analog input signal Vin_th with the reference voltage Vdac. The comparison unit CU1-4, the comparison result DOUT1-4 of each comparison unit are latched, the logic circuit 14 that generates the digital signal DAC1-8 according to the comparison result, and the digital signal DAC1-8 to the analog reference voltage Vdac And a DA converter 16 for conversion. The comparator of the third embodiment is the same circuit as that of the first embodiment.

  Unlike the first embodiment, the AD converter of the third embodiment has a 3-bit shift register 32 and an internal clock control circuit (control signal control) in order to repeat the 4-bit comparison operation twice. Circuit) 30. Further, the logic circuit 14 has an 8-bit register that latches an 8-bit comparison result, and generates an 8-bit digital signal DAC1-8. This is different from the AD converter of the first embodiment.

  FIG. 10 is a circuit diagram of the 3-bit shift register 32. The operation waveform diagram is shown in FIG. The 3-bit shift register 32 controls the control signal CONT1 based on the external clock ECLK, the output EOR1_O of the EOR gate EOR1 in the first-stage comparison unit CU1, and the output EOR4_O of the EOR gate EOR4 in the fourth-stage comparison unit CU4. , 2,3 are controlled in order from L level to H level.

  That is, the circuit diagram of FIG. 10 includes three flip-flops 321, 322, and 323. The inverted flip-flop / ECLK is input to the first flip-flop 321 and the flip-flops 322 and 323 in the second and third stages receive data. The data is input to the output Q of the preceding flip-flop. These flip-flops are reset when the external clock ECLK becomes H level and the output Q becomes L level. In response to the rising edge of EOR1_O, the first stage flip-flop 321 fetches the data input D, and in response to the rising edge of EOR4_O, the second and third stage flip-flops input the output Q of the preceding flip-flop as data. Import as D.

  As shown in the operation waveform diagram of FIG. 13, all three flip-flops are reset by the high level of the external clock ECLK, and the control signals CNT1, 2, and 3 that are their outputs all become the L level. When the four-stage comparison unit CU1-4 starts the successive approximation operation, the flip-flop 321 first latches the H level of the inverted external clock / ECLK in response to the rise of the output EOR1_O of the EOR gate of the first-stage comparison unit CU1. Then, the control signal CNT1 becomes H level. Further, in response to the rise of the output EOR4_O of the EOR gate in the fourth-stage comparison unit CU4, the flip-flop 322 latches the control signal CNT1 = H, and the control signal CNT2 becomes H level. This completes the 4-bit comparison operation in the first round.

  Then, during the 4-bit comparison operation in the second round, the flip-flop 323 latches the control signal CNT2 = H in response to the rise of the output EOR4_O of the EOR gate in the fourth-stage comparison unit CU4, Signal CNT3 goes high. Finally, when the external clock ECLK becomes H level, all flip-flops are reset again, and the control signals CNT1, 2, 3 all become L level.

  In the above control signals CNT1, 2, and 3, when the comparison operation of the most significant bit in the first round AD conversion is completed, the control signal CNT1 becomes H level, and the fourth bit comparison in the first round AD conversion is performed. The control signal CNT2 becomes H level when the operation is completed, and the control signal CNT3 becomes H level when the comparison operation of the fourth bit in the AD conversion of the second week is completed. In response to such a control signal, the internal clock control circuit 30 controls the state control signal CLK1, which is an internal clock.

  FIG. 11 is a circuit diagram of the internal clock control circuit 30. The internal clock control circuit 30 controls the state control signal CLK1, which is the internal clock of the first stage, using the control signals CNT1, 2, 3 and the output EOR2_O of the EOR gate of the second stage comparison unit. Specifically, during the external clock ECLK = H, the state control signal CLK1 is set to the H level by the NOR gate 305, and any of the three AND gates 301 to 303 is set to the H level during the external clock ECLK = L. Is output, the NOR gate 304 outputs an L level and the state control signal CLK1 is set to an L level. If all AND gates output an L level, the NOR gate 304 outputs an H level and the state control signal CLK1 is set to an H level. To the level. The control is as shown in FIG.

  FIG. 12 is a circuit diagram of the logic circuit 14. The logic circuit 14 in the third embodiment includes an 8-bit register 14-1 and a SAR logic circuit 14-2 that generates a digital signal DAC1-8 that generates a reference voltage.

  The 8-bit register 14-1 includes four comparison units CU1- in response to the rising edge of the control signal CNT1 generated when the upper 4-bit register RG1-4 completes the first round of DA conversion. Latch 4 judgment result DOUT1-4. Further, the lower 4-bit register RG5-8 responds to the rising edge of the control signal CNT3 generated at the completion of the second round of DA conversion, and the determination results DOUT1 of the four comparison units CU1-4 Latch -4.

  The SAR logic circuit 14-2 is the same as the SAR logic circuit 14-2 of FIG. In other words, the SAR logic circuit 14-2 includes a circuit 14-2 (1) for generating a digital signal DAC1-4 for generating a reference voltage during the determination operation of the upper 4 bits and a lower 4 bits. A circuit 14-2 (2) for generating a digital signal DAC5-8 for generating a reference voltage during the determination operation. The upper circuit 14-2 (1) causes the AND gate of the first stage to respond to the internal clock CLK1-4 by the control signal CNT2 = L inverted signal / CNT2 = H that becomes L level during the first AD conversion operation. Works. This operation is the same as in FIG. Furthermore, in the lower circuit 14-2 (2), the first AND gate operates according to the internal clock CLK1-4 by CNT2 = H of the control signal CNT2 which becomes H level during the second round AD conversion operation. To do. This operation is also the same as in FIG.

  FIG. 13 is an operation waveform diagram of the AD converter according to the third embodiment. Time T1 is the tracking period, time T2-T5 is the first AD conversion operation period, and time T6-T9 is the second AD conversion operation period. The operation will be described in detail below.

At the first round AD conversion operation time T1, the external clock ECLK is at the H level, the track and hold circuit 10 tracks (or samples) the analog input Vin, and Vin = Vin_th. At this time, the internal clocks CLK1 to CLK4 are all set to H level by the OR gate OR1-4, and the comparators COMP1 to COMP4 are reset.

  At time T2, the external clock ECLK changes to L level at time T1, and the output of the AND gate 301 of the internal clock control circuit 30 is at H level, so the output of the internal clock control circuit 30 is CLK1 = L. The comparator COMP1 starts to determine the most significant bit (MSB). At this time, the digital input signal DAC1 of the DAC circuit 16 output from the 8-bit SAR logic circuit 14-2 is changed to DAC1 = H by / CLK1 = H, CLK2 = H, / CNT2 = H, and other lower bit DAC2 -8 is set to L.

  The comparator COMP1 compares the analog input Vin_th with the reference Vdac, and outputs the judgment result to the output pair OP1 and OM1. However, since the internal clocks CLK2 to 4 = H, the other comparators COMP2 to COMP4 are in a reset state.

  After completion of the determination of the comparator COMP1, the determination result of the comparator COMP1 is held by the flip-flop DFF1 at the rising edge of the output EOR1_O of the EOR gate EOR1, and is output to the subsequent 8-bit register circuit 14-1, and the most significant bit MSB ( D1) is determined. At time T2, the output EOR1_O = H of the EOR gate EOR1 is input to the 3-bit shift register circuit 32, and the control signal CNT1 = H. At this time, the control signals CNT1, 2, 3 become H, L, L. As a result, the output of the AND gate 301 becomes L level, but the output of the AND gate 302 becomes H level, and CLK1 = L is maintained.

  At time T3, when the output of the OR gate OR1 changes from the H level to the L level, the state control signal that is the internal clock becomes CLK2 = L, and the comparator COMP2 starts the determination of the second bit. At this time, the first bit digital input signal DAC1 of the DAC circuit 16 is at a level corresponding to the most significant bit COUT1, and the second bit digital input signal DAC2 is / CLK2 = H, CLK3 = H, / CNT2 = H. As a result, it becomes H level and the other lower bits DAC3-8 are set to L level.

  Comparator COMP2 compares analog input Vin_th with reference voltage Vdac, and outputs the judgment result to output pair OP2 and OM2. However, since the internal clocks CLK3 to 4 = H, the comparators COMP3 to COMP4 are in a reset state.

  After completion of the determination of the comparator COMP2, the determination result of the comparator COMP2 is held by the flip-flop DFF2 at the rising edge of the output EOR2_O of the EOR gate EOR2, and is output to the subsequent 8-bit register circuit 14-1 to determine the second bit To do. At the same time, the output EOR2_O of the EOR gate EOR2 rises and is input to the internal clock control circuit 30, the output of the AND gate 302 changes from H to L level, and the internal clock becomes CLK1 = H.

  At time T4, when the output of the OR gate OR2 changes from H to L, the internal clock CLK3 = L, and the comparator COMP3 starts the determination of the third bit. At the same time, the reset operation is started in the comparator COMP1 due to the change of the internal clock CLK1 from L to H at time T3. At this time, the 1st and 2nd bit digital input signals DAC1 and 2 of the DAC circuit 16 are at a level depending on the determination result, and the 3rd bit DAC3 is H when / CLK3 = H, CLK4 = H, and / CNT2 = H. Level, and the other lower bits DAC4-8 are set to L level.

  Then, the comparator COMP3 compares the analog input Vin_th with the reference voltage Vdac, and outputs the determination result to the output pair OP3, OM3. However, because the internal clock CLK4 = H, the comparator COMP4 is in a reset state. After completion of the determination of the comparator COMP3, the determination result of the comparator COMP3 is held by the flip-flop DFF3 at the rising edge of the output of the EOR gate EOR3 and is output to the subsequent 8-bit register circuit.

  Next, at time T5, the output of the OR gate OR3 changes from H to L, whereby the internal clock CLK4 = L, and the comparator COMP4 starts the determination of the fourth bit. At the same time, the internal clock CLK2 changes from H to L, and the reset operation of the second-stage comparator COMP2 is started. At this time, the DAC circuit 16 sets the fourth bit digital input signal DAC4 to H by / CLK4 = H. The upper 3 bits DAC1-3 are at the level according to the respective determination results DOUT1-3, and the lower 4 bits DAC5-8 remain at the L level. The comparator COMP4 compares the input Vin_th with the reference voltage Vdac, and outputs the determination result to the output pair OP4, OM4.

  After completion of the determination of the comparator COMP4, the determination result of the comparator COMP4 is held by the flip-flop DFF4 at the rising edge of the output EOR4_O of the EOR gate EOR4, and is output to the subsequent 8-bit register circuit 14-1.

  Further, after the determination result is held by the flip-flop DFF4, the output signal EOR4_O of the EOR gate EOR4 changes from L to H level, so that the control signal CNT2 = H is output from the 3-bit shift register circuit 32. Thus, the AD conversion operation for the first round is completed, and the AD conversion operation for the second round is started.

Second AD conversion operation In the second AD conversion operation, the control signal CNT2 = H is input to the internal clock control circuit (state control signal control circuit) 30 at time T6, so that the AND gate 303 The output changes from the L level to the H level, the internal clock CLK1 changes to the L level again, and the comparator COMP1 starts judging the fifth bit. Thereafter, the comparators COMP1 to COMP4 sequentially perform the comparison operation of the 5th to 8th bits in the same manner as in the first round, and perform AD conversion up to 8 bits (LSB). This is time T6-T9 in FIG.

  After all bits have been converted, the control signal becomes CNT3 = H or the external clock ECLK becomes H level at the rising edge of the output EOR4_O of the EOR gate EOR4. As a result, the tracking or sampling state at time T1 is entered again. This completes the 8-bit AD conversion. After completion, the output of the AND gate 301 of the internal clock control circuit 30 becomes H level and enters a standby state.

  By repeating the operation during the period of time T1 to T9, 8-bit AD conversion is performed in synchronization with the external clock ECLK. However, the 8-bit determination operation at each time T2-T9 is sequentially performed asynchronously with the external clock ECLK.

  As described above, in the third embodiment, an AD converter having an 8-bit resolution is realized by the four comparison units CU1-4. An AD converter having an 8-bit resolution can be configured by repeating the successive approximation operation by four comparison units twice. By repeating four times, an AD converter having a resolution of 16 bits can be configured. In addition, since it is not necessary to perform an operation of resetting the comparator during the comparison operation of each bit, the time required for 8-bit AD conversion can be shortened.

  FIG. 14 is a configuration diagram of an AD converter of a comparative example corresponding to the present embodiment. This AD converter has one comparator COMP, compares the analog input Vin_th held by the track and hold circuit 10 with the reference voltage Vdac generated by the DAC circuit 16, and outputs the comparison result OUT to the logic circuit 14. Is done.

  As shown in the operation waveform of FIG. 14B, when the external clock ECLK becomes L level, the internal clock ICLK repeats H and L. The comparator COMP enters the reset state R when the internal clock ICLK = L, and enters the determination state when ICLK = H. Then, the logic circuit 14 generates a 4-bit digital signal DAC1-4 according to the determination result and the determination target bit, and the DAC circuit generates a reference voltage Vdac corresponding to the digital signal. Accordingly, one comparator COMP performs the determination operation four times in response to the internal clock ICLK = H, and performs each reset operation in response to ICLK = L during the determination operation.

  FIG. 15 is a diagram illustrating a simulation comparison result between the AD converters of the first and second embodiments and the AD converter of the comparative example. In FIG. 15, the horizontal axis corresponds to the resolution of the AD converter, that is, the number of bits of the digital output, and the vertical axis corresponds to the maximum sampling frequency of the AD converter. The maximum sampling frequency is the frequency of the external clock ECLK, and is the number of times that the AD converter can convert the analog input signal Vin into a digital output signal per second. Therefore, the higher the maximum sampling frequency, the shorter the AD conversion time of the AD converter, that is, the higher the speed.

  FIG. 15 shows a square comparative example and diamond-shaped first and second embodiments. In both examples, as the number of bits of the digital output of the AD converter increases, the time required for one AD conversion becomes longer, so the sampling frequency becomes lower. However, if the number of digital output bits is the same, the first and second embodiments do not require resetting the comparator during the judgment operation, so that the time required for one AD conversion is shorter, and sampling is performed. The frequency is high.

The specific conditions for the simulation are as follows.
The comparator reset operation time and judgment operation time are both 1 [ns]
The duty ratio of the external clock ECLK is 25 [%]
The delay time of the logic circuit 14 other than the comparator is sufficiently smaller than the operation time of the comparator.

The conversion speed is calculated as follows.
(Example) Maximum sampling frequency = 1 / Ts = 1 / (Hw + J * N)
(Conventional example) Maximum sampling frequency = 1 / Ts = 1 / {Hw + J * N + R * (N−1)}
Where Ts is the period of the external clock signal, Hw is the H level width of the external clock signal, J is the judgment operation time of the comparator, R is the reset operation time of the comparator, and N is the resolution of the AD converter.

  From FIG. 15, the present embodiment can improve the maximum AD conversion speed (maximum sampling frequency) by about twice as much as that of the comparative example. The improvement rate tends to increase as the number of AD conversion bits, that is, the resolution increases. On the other hand, in the first and second embodiments, when the resolution is 4 bits, the frequency is improved by about 1.75 times that of the comparative example.

  As described above, according to the AD converter of this embodiment, the time required for AD conversion is shortened by having a plurality of comparison units and sequentially performing the determination operation from the upper bit to the lower bit. be able to.

  The above embodiment is summarized as follows.

(Appendix 1)
An AD converter that converts an analog input signal into a digital output signal,
An N-stage comparison unit that compares the analog input signal with a reference voltage and sequentially outputs each bit of the digital output signal according to the comparison result;
A logic circuit for sequentially generating a reference voltage generation digital signal corresponding to the reference voltage based on each bit of the digital output signal output by the comparison unit;
A DA converter that generates the reference voltage based on the reference voltage generation digital signal,
Each of the N-stage comparison units includes a comparator that changes from a reset state to a determination state in response to a determination state of the state control signal from the previous stage, and a subsequent stage when the comparator outputs a comparison result in the determination state. A state control signal generation unit for making a state control signal to the comparison unit of
An AD converter in which the comparator of the N-stage comparison unit sequentially performs a comparison operation from an upper bit to a lower bit in response to a trigger clock.

(Appendix 2)
In Appendix 1,
All the comparators of the N-stage comparison unit are controlled to the reset state in the initial state,
In response to the trigger clock, the comparator of the first-stage comparison unit transitions from the reset state to the determination state,
The comparator of the N-stage comparison unit is an AD converter that performs a sequential comparison operation asynchronously with the trigger clock.

(Appendix 3)
In Appendix 2,
The state control signal generation unit is an AD converter that puts the comparator of its own stage into a power-down state when the state control signal to the subsequent stage is set to the determination state.

(Appendix 4)
In Appendix 2,
An AD converter in which the N-stage comparison unit repeats the sequential comparison operation K times (K is a plurality).

(Appendix 5)
In Appendix 4,
Further, in response to the trigger clock, the state control signal of the determination state is output to the comparator of the first-stage comparison unit among the N-stage comparison units, and further, the sequential operation from the first time to the K-1th time is performed. In the comparison operation, when the comparator of the final-stage comparison unit transitions to the determination state and outputs a comparison result, an internal control that outputs a state control signal of the determination state to the comparator of the first-stage comparison unit AD converter with signal controller.

(Appendix 6)
In Appendix 5,
Each state control signal generation unit of the N-stage comparison unit sets the state control signal to the subsequent stage when the own comparator enters the determination state, and when the own stage comparator enters the reset state. Reset the state control signal to the subsequent stage,
The state control signal control unit further resets the state control signal to the comparator of the first stage comparison unit after the comparator of the first stage comparison unit transitions to the determination state and outputs a comparison result. AD converter to make.

(Appendix 7)
In any one of supplementary notes 2 to 4,
The trigger clock has a first period and a second period;
In the second period of the trigger clock, all the comparators of the N-stage comparison units are controlled to the reset state in the initial state, and transit from the second period to the first period of the trigger clock. In response, the AD converter in which the comparator of the first-stage comparison unit transitions from the reset state to the determination state.

(Appendix 8)
In Appendix 7,
Further, an AD converter having an output register for outputting a comparison result of the comparator of the N-stage comparison unit when the trigger clock is in the second period.

CU1-4: Comparison unit COMP1-4: Comparator
CLK1-4: internal clock, state control signal ECLK: trigger clock, external clock 10: track and hold circuit 12: external clock generation circuit 14: logic circuit 16: DAC
Vdac: Reference voltage DAC1-4: Reference voltage generation control signal

Claims (4)

An AD converter that converts an analog input signal into a digital output signal,
An N-stage comparison unit that compares the analog input signal with a reference voltage and sequentially outputs each bit of the digital output signal according to the comparison result;
A logic circuit for sequentially generating a reference voltage generation digital signal corresponding to the reference voltage based on each bit of the digital output signal output by the comparison unit;
A DA converter that generates the reference voltage based on the reference voltage generation digital signal,
The N stages are a plurality of stages,
Each of the N-stage comparison units includes a comparator that changes from a reset state to a determination state in response to a determination state of the state control signal from the previous stage, and a subsequent stage when the comparator outputs a comparison result in the determination state. the comparator of the stage with a state control signal to the comparator to determine the state and a state control signal generator for the power-down state,
In response to a trigger clock, a plurality of comparators of the N-stage comparison unit sequentially perform comparison operations while sequentially transitioning from the upper bit to the lower bit from the reset state, the determination state, and the power-down state. AD converter. In claim 1,
All the comparators of the N-stage comparison unit are controlled to the reset state in the initial state,
In response to the trigger clock, the comparator of the first-stage comparison unit transitions from the reset state to the determination state,
The comparator of the N-stage comparison unit is an AD converter that performs a sequential comparison operation asynchronously with the trigger clock. In claim 2,
An AD converter in which the N-stage comparison unit repeats the sequential comparison operation K times (K is a plurality). In claim 3 ,
Further, in response to the trigger clock, the state control signal of the determination state is output to the comparator of the first-stage comparison unit among the N-stage comparison units, and further, the sequential operation from the first time to the K-1th time is performed. In the comparison operation, when the comparator of the final-stage comparison unit transitions to the determination state and outputs a comparison result, an internal control that outputs a state control signal of the determination state to the comparator of the first-stage comparison unit AD converter with signal controller.

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