JP5631179B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A semiconductor device manufacturing method is known in which a semiconductor wafer having a plurality of semiconductor elements or optical devices formed in an array on the surface of a semiconductor substrate is divided into a plurality of chips by cleaving with force from the back side of the substrate. Yes. For example, the cleaving process is for cleaving the adhesive sheet along the planned cleavage line by attaching a pressure-sensitive adhesive sheet to the back surface of the semiconductor wafer and a cover sheet for surface protection on the front surface, and having a recess in the center. This can be done by pressing the blade. By performing cleavage while gradually shifting the stacked body including the semiconductor wafer, the semiconductor wafer can be divided into a plurality of chips.

JP 2010-118401 A

  In the conventional method for manufacturing a semiconductor device, when the semiconductor wafer is cleaved, the semiconductor wafer that is divided by the cleavage and the adjacent semiconductor wafer that has already been divided rub against each other and the semiconductor device is damaged. was there.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing damage accompanying cleavage of a semiconductor wafer.

The method for manufacturing a semiconductor device includes: a first region; a second region adjacent to the first region; and a third region adjacent to the second region. It is made of metal so as to cover at least part of the first boundary line that is the boundary line of the second area and at least part of the second boundary line that is the boundary line of the second area and the third area. A step of forming a coupling layer, a step of cleaving the first region and the second region by cleaving along the first boundary line from the back side of the semiconductor substrate, and the semiconductor substrate Dividing the second region and the third region by cleaving by applying a force along the second boundary line from the back side of the first region, the second region, and Each of the third regions becomes a semiconductor chip after division. A main region, and a region abandoned provided outside of the main area, the connecting layer is formed only on the discarded area. Another method of manufacturing a semiconductor device includes: a first region; a second region adjacent to the first region; and a third region adjacent to the second region. And from the resin so as to cover at least part of the first boundary line that is the boundary line of the second area and at least part of the second boundary line that is the boundary line of the second area and the third area. Forming a connecting layer, dividing the first region and the second region by cleaving by applying a force along the first boundary line from the back side of the semiconductor substrate, and the semiconductor Dividing the second region and the third region by cleaving by applying a force along the second boundary line from the back surface side of the substrate, the first region, the second region, And the third region is divided into a semiconductor chip after division. That a main region, and a region abandoned provided outside of the main area, the connecting layer is formed only on the discarded area.

  The said structure WHEREIN: The said connection layer can be set as the structure extended continuously in the said 1st area | region, the said 2nd area | region, and the said 3rd area | region.

  In the above configuration, a first scribe groove for cleaving the semiconductor substrate is formed on the surface of the semiconductor substrate at the ends of the first boundary line and the second boundary line before the step of dividing by the cleavage. It can be set as the structure provided with a process.

  In the above configuration, the method includes a step of forming a seed metal layer on the back surface side of the semiconductor substrate and a step of forming a back electrode on the seed metal layer, wherein the connection layer forms the seed metal layer. It can be set as the structure which is the said seed metal layer formed at the same process.

  In the above configuration, an optical device of an end face incident type or an end face emission type may be formed in the main region.

  The said structure WHEREIN: The said connection layer can be set as the structure formed on the said semiconductor substrate by the process of any one of plating, vapor deposition, or sputtering including a metal.

  In the above structure, the resin may include at least one of polyimide, benzocyclobutene, and fluorine resin.

  In the above configuration, the step of dividing the first region and the second region and the step of dividing the second region and the third region are performed by applying an adhesive to the back surface of the semiconductor substrate. The step of attaching the adhesive sheet, the step of attaching a cover sheet for surface protection to the surface of the semiconductor substrate, and the cover sheet and the cradle contact each other on a cradle having a recess in the center. As described above, in the state where the semiconductor substrate, the adhesive sheet, and the laminate of the adhesive sheet are installed, and the first boundary line is positioned on the recess, the adhesive sheet along the first boundary line The step of cleaving the semiconductor substrate by pressing a blade for cleavage on the adhesive sheet, and the blade on the adhesive sheet along the second boundary line in a state where the second boundary line is located on the recess Push By applying, it can be configured to include a step of cleaving the semiconductor substrate.

  ADVANTAGE OF THE INVENTION According to this invention, the damage accompanying the cleavage of a semiconductor wafer can be suppressed.

FIG. 1 is a diagram (part 1) illustrating a manufacturing process of a semiconductor device according to a comparative example. FIG. 2 is a diagram (part 2) illustrating the manufacturing process of the semiconductor device according to the comparative example. FIG. 3 is a diagram (part 1) illustrating the manufacturing process of the semiconductor device according to the first embodiment. 4A and 4B are diagrams (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a diagram (No. 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram (part 4) illustrating the manufacturing process of the semiconductor device according to Example 1. FIG. 7 is a diagram (No. 5) illustrating the process for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram (No. 6) illustrating the process for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor device according to the modification of the first embodiment.

(Comparative example)
First, a method for manufacturing a semiconductor device according to a comparative example will be described.

  Dividing by cleaving is known as a method for obtaining semiconductor chips by dividing a semiconductor wafer. Splitting by cleavage is used, for example, in optical devices

  1 to 2 are diagrams illustrating a manufacturing process of a semiconductor device according to a comparative example. 1A is a plan view of a semiconductor wafer, FIG. 1B is a plan view of a wafer block in which a part of FIG. 1A is enlarged, and FIG. 1C is a part of FIG. 1B. It is a top view of the expanded semiconductor chip. As shown in FIG. 1B, the semiconductor wafer 10 is partitioned into a rectangular shape by two boundary lines (planned cleavage lines and planned chip lines) defined in the vertical and horizontal directions. A semiconductor element (for example, an optical device) is formed. In the manufacturing process of the semiconductor device, the semiconductor wafer 10 is first divided into wafer blocks 20 of an appropriate size (FIG. 1B), and then the wafer block 20 is divided into chip sizes of the semiconductor chips 30. Thereby, a plurality of semiconductor chips 30 can be obtained from the semiconductor wafer 10.

  FIG. 2A is a plan view showing a detailed configuration of the wafer block 20 viewed from the back side, and FIG. 2B is a cross-sectional view for explaining a process of dividing the wafer block 20 into semiconductor chips 30. is there. As shown in FIG. 2A, the wafer block 20 is divided into a plurality of semiconductor chips 30 by a planned cleavage line 22 defined in the horizontal direction and a planned chip formation line 24 defined in the vertical direction. Each semiconductor chip 30 is provided with a back electrode 40 that serves as a ground electrode of the semiconductor chip 30.

  As shown in FIG. 2B, when the wafer block 20 is divided, an adhesive sheet 72 (for example, an ultraviolet curable sheet) coated with an adhesive is first attached to the back side of the wafer block 20, A cover sheet 74 for surface protection is attached to the front surface side. And the laminated body 70 containing the wafer block 20, the adhesive sheet 72, and the cover sheet 74 is installed in the cradle 60 which has the recessed part 62 in the center part with the cover sheet 74 side down. Next, the wafer 80 is cleaved and divided into array-shaped wafers by applying a force by pressing the blade 80 from above along the planned cleavage line 22 in FIG. The cleavage of the wafer block 20 is sequentially performed while shifting the stacked body in the direction of the arrow in FIG. When all the cleaving steps are completed, the arrayed wafer is divided (for example, dicing) along the planned chip formation line 24 in FIG. 2A to obtain the semiconductor chip 30 whose end face is cleaved.

  Here, in FIG. 2B, the rightmost region of the wafer block 20 to be an arrayed wafer is the first region 20A, the adjacent region is the second region 20B, and the adjacent region is the third region 20C. And Further, a planned cleavage line between the first region 20A and the second region 20B is a first boundary line 22a, and a planned cleavage line between the second region 20B and the third region 20C is a second boundary line 22b. FIG. 2B shows the second region 20B and the third region along the second boundary line 22b after the first region 20A and the second region 20B are already divided along the first boundary line 22a. A state in which 20C division is performed is illustrated. At this time, the second region 20 </ b> B and the third region 20 </ b> C are pushed downward (the cradle 60 side) by the pressure of the blade 80 via the adhesive sheet 72. On the other hand, the first region 20A that has been divided into an arrayed wafer is peeled off from the adhesive sheet 72, and is in a state that does not link with the second region 20B and the third region 20C. As a result, the corner of the first region 20A may collide with the end surface of the second region 20B (reference numeral 82 in the drawing), and the end surface of the semiconductor chip 30 may be damaged.

  In the following embodiments, a semiconductor device capable of suppressing damage to the semiconductor chip 30 accompanying the cleavage of the semiconductor wafer 10 and a manufacturing method thereof will be described.

  3 to 8 are diagrams illustrating manufacturing steps of the semiconductor device according to the first embodiment. 3A is a plan view of the semiconductor wafer, and FIG. 3B is a plan view of the wafer block obtained by dividing the semiconductor wafer as seen from the back side. As shown in FIG. 3B, the wafer block 20 is partitioned into a main region 12 that becomes a semiconductor chip after division, and a discarding region 14 located outside the main region 12. In addition, a connecting layer 42 is provided in the discard region 14 on the back surface of the wafer block 20. The connection layer 42 is a layer for connecting the discard region 14 so as not to be completely divided in the cleavage step of the wafer block 20 described later.

  FIG. 4A is a plan view showing a detailed configuration of the wafer block 20 as viewed from the back side. As in the comparative example, the main region 12 is partitioned into a rectangular shape by a planned cleavage line 22 and a planned chip formation line 24. The connection layer 42 is formed so as to cover the planned cleavage line 22 continuously in the region that becomes the arrayed wafer after the division. Here, a boundary line between the main region 12 and the discard region 14 is defined as a discard region boundary line 26 (third boundary line).

  FIG. 4B is a plan view showing a detailed configuration of the wafer block 20 as viewed from the front side. A surface electrode 50 that is an electrode on the surface side of the semiconductor chip 30 is formed in each section of the main region 12 partitioned in a rectangular shape. The surface electrode 50 is formed so as not to overlap the planned cleavage line 22. Further, no electrode is formed on the front surface side of the discard region 14 of the wafer block 20.

  Here, the manufacturing process up to FIGS. 3 and 4 will be described. For example, n-type InP having a thickness of 350 μm can be used for the semiconductor wafer 10 used for manufacturing. First, after various semiconductor layers (for example, an active layer and a clad layer) are formed on the semiconductor wafer 10, the surface electrode 50 is formed on the surface of the semiconductor wafer 10. Thereafter, the back surface side of the semiconductor wafer 10 is shaved by a polishing process, and the semiconductor wafer 10 is thinned to a predetermined thickness (for example, 100 μm).

  Next, a seed metal layer (for example, an AuGeNi layer having a thickness of 50 nm, a Ti layer having a thickness of 50 nm, and an Au layer having a thickness of 100 nm are sequentially deposited on the back side of the semiconductor wafer 10. Not shown in FIG. ). Although the thickness of the seed metal layer may be a value other than the above, the total thickness is preferably 150 nm to 500 nm.

  Next, a resist pattern is formed on the back side of the semiconductor wafer 10 by photolithography, and the back electrode 40 and the coupling layer 42 are formed on the seed metal layer by plating. For plating, for example, a non-cyanide gold plating solution containing 10 g of Au per liter can be used. The semiconductor wafer 10 is immersed in the gold plating solution having a liquid temperature of 40 ° C., for example, and a Ti electrode with platinum plating, for example, is immersed in the solution as a counter electrode. Process. Thereafter, the resist pattern is removed and, for example, an alloying process is performed at 320 ° C. for 3 minutes, whereby the back electrode 40 and the coupling layer 42 are completed. The thicknesses of the back electrode 40 and the coupling layer 42 can be set to 3 μm, for example. In addition, you may form the back surface electrode 40 and the connection layer 42 by methods (for example, vapor deposition or sputtering) other than plating.

  For dividing the semiconductor wafer 10 into the wafer block 20, for example, the back surface side of the semiconductor wafer 10 is first attached to an adhesive sheet on a dicing frame, a scribe groove is formed on the front surface side, a cover sheet is applied, and cleavage (brake) is performed. ). Since this process is the same as the process of dividing the wafer block 20 into the arrayed wafer 36, which will be described later, detailed description is omitted here. Note that a method other than the above (for example, dicing using a diamond cutter) may be used for dividing the semiconductor wafer 10 into the wafer blocks 20. For example, two rectangular wafer blocks 20 having a size of 18 mm × 36 mm can be cut out from one semiconductor wafer 10 having a diameter of 2 inches.

  5-8 is a figure which shows the division | segmentation process of the wafer block 20. FIG. First, as shown in FIG. 5A, the back side of the wafer block 20 is attached to the adhesive sheet 72 on the dicing frame 90. For the pressure-sensitive adhesive sheet 72, for example, an ultraviolet-curing pressure-sensitive adhesive sheet made of vinyl chloride having a thickness of 80 μm and having an acrylic pressure-sensitive adhesive having a thickness of about 10 μm and an adhesive strength of 1 N / 20 mm can be used.

  Next, as shown in FIG. 5A, a first scribe groove for cleavage along the planned cleavage line 22 is formed in the discard region 14 that is the end of the front side of the wafer block 20 (the opposite side of the adhesive sheet 72). 32 is formed. At this time, it is preferable that the first scribe groove does not overlap with the discarded region boundary line 26 that is a boundary line between the main region 12 and the discarded region 14. The length of the 1st scribe groove | channel 32 can be 500 micrometers, for example, and a pitch can be 300 micrometers, for example. The first scribe grooves 32 may be formed in the discard regions 14 at both ends of the wafer block 20.

  Next, as shown in FIG. 5B, a second scribing groove 34 for cleavage is formed along a discarded region boundary line 26 that is a boundary line between the main region 12 and the discarded region 14. At this time, it is preferable that the second scribe groove does not overlap with the planned cleavage line 22 (so as to straddle the planned cleavage line 22). The length of the second scribe groove 34 can be set to 150 μm, for example. The first scribe groove 32 and the second scribe groove 34 can be formed by, for example, a diamond cutter.

  Next, as shown in FIG. 6A, a surface protection cover sheet 74 is attached to the wafer block 20. As the cover sheet 74, for example, a transparent PET (Polyethylene Terephthalate) sheet can be used. Thereafter, by applying a force along the planned cleavage line 22 from the back surface side of the wafer block 20, the wafer block 20 is divided into the arrayed wafers 36 by cleavage. The cleavage of the wafer block 20 can be performed by a known braking device.

  Next, as shown in FIG. 6B, a force is applied from the back surface side of the wafer block 20 along the discarded region boundary line 26 to divide the wafer block 20 into the main region 12 and the discarded region 14. Thereafter, the adhesive sheet 72 is irradiated with ultraviolet rays, and the dicing frame 90 is expanded using a known expander. As a result, as shown in FIG. 7, the discard region 14 is divided from the main region 12, and the main region 12 is divided into a plurality of arrayed wafers 36. Thereafter, the semiconductor wafer 30 can be obtained by dividing the arrayed wafer 36 along the planned chip line 24 of FIG. The division from the array-shaped wafer 36 to the semiconductor chip 30 can be performed, for example, by a process similar to the cleavage process from the wafer block 20 to the array-shaped wafer 36.

  FIG. 8 is a diagram illustrating a cleaving process of the wafer block 20 in the manufacturing process of the semiconductor device according to the first embodiment. The wafer block 20 is sequentially divided into the first area 20A to the third area 20C as in the comparative example. The process is shown. Unlike the comparative example (FIG. 2B), since the connection layer 42 (not shown in FIG. 8) is formed on the back surface side (adhesive sheet 72 side) of the wafer block 20, the first region 20A and the second region The back side of 20B is connected without being completely separated (reference numeral 84 in the figure). Thus, even when the second region 20B and the third region 20C are pushed down (the cradle 60 side) by the pressure of the blade 80, the first region 20A moves in synchronization with the second region 20B. The end surfaces of the first region 20A and the second region 20B are not easily damaged. As described above, according to the method for manufacturing a semiconductor device according to the first embodiment, damage to the semiconductor device due to cleavage of the semiconductor wafer 10 can be suppressed.

  FIG. 9A is a diagram illustrating a manufacturing process of the semiconductor device according to the modification of the first embodiment, and corresponds to FIG. 4A of the first embodiment. Unlike the first embodiment, a seed metal layer 44 serving as a base for the back electrode 40 is formed on the entire surface of the main region 12. The coupling layer 42 is not formed. Thereby, the seed metal layer 44 plays a role similar to that of the coupling layer 42, and the back surfaces of the first region 20A to the third region 20C are hardly separated in the cleavage step of FIG. As a result, damage to the semiconductor device accompanying cleavage of the semiconductor wafer 10 can be suppressed. In this case, the seed metal layer 44 may be formed at least across the planned cleavage line 22, but it is more preferably formed on the entire back surface of the wafer block 20. The thickness of the seed metal layer 44 is preferably 150 nm or more from the viewpoint of improving adhesion, but is preferably 500 nm or less from the viewpoint of easily performing the cleavage step.

  FIG. 9B is a diagram illustrating the manufacturing process of the semiconductor device according to the modification of the first embodiment, and corresponds to FIG. 4A of the first embodiment. In the wafer block 20, the coupling layer 42a is formed of resin instead of metal plating. For example, after forming the back electrode 40, a polyimide resin containing a negative photosensitive agent is applied to the entire back surface of the wafer block 20 with a thickness of 3 μm, and then only the discarded region 14 is exposed and developed by an exposure apparatus. Thereafter, a curing process is performed at 300 ° C. for 30 minutes to solidify the polyimide resin, whereby the coupling layer 42a made of resin can be obtained. Even when the coupling layer 42 made of resin is used, damage to the semiconductor device due to cleavage of the semiconductor wafer 10 can be suppressed as in the first embodiment. As the resin, in addition to polyimide, for example, benzocyclobutene, fluorine resin, or the like can be used. The resin may be removed after the wafer block 20 is divided by cleavage.

  The manufacturing method of the semiconductor device according to the first embodiment and the modification thereof can be applied to any semiconductor device having a semiconductor element formed on the surface and the end face being cleaved. It is particularly suitable for optical devices (for example, semiconductor lasers). In these optical devices, the end surface along the planned cleavage line 22 becomes the incident surface or the exit surface of the device.

  Moreover, although Example 1 and its modification demonstrated the example in which the connection layer 42 (42a) was continuously formed in the discard area | region 14, the connection layer 42 (42a) is at least one part of the cleavage line 22 expected. As long as it is formed so as to cover. However, the continuous formation of the coupling layer 42 (42a) as in the above-described example has a higher effect of coupling the discarded region 14, and therefore damage to the semiconductor device in the wall opening process can be further suppressed. .

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 12 Main area 14 Discard area 20 Wafer block 22 Planned cleavage line 24 Planned chip line 26 Discard area boundary line 30 Semiconductor chip, chip area 32 1st scribe groove 34 2nd scribe groove 40 Back electrode 42 Connecting layer 44 Seed Metal layer 50 Surface electrode 60 Base 70 Laminate 72 Adhesive sheet 74 Cover sheet 80 Blade

Claims (9)

On a back surface of a semiconductor substrate having a first region, a second region adjacent to the first region, and a third region adjacent to the second region, a boundary line between the first region and the second region Forming a coupling layer made of metal so as to cover at least a part of the first boundary line and at least a part of the second boundary line that is a boundary line of the second region and the third region;
Dividing the first region and the second region by cleaving by applying a force along the first boundary line from the back side of the semiconductor substrate;
Dividing the second region and the third region by cleavage by applying a force along the second boundary line from the back surface side of the semiconductor substrate ,
Each of the first region, the second region, and the third region has a main region that becomes a semiconductor chip after division, and a discarded region provided outside the main region,
The method for manufacturing a semiconductor device, wherein the connection layer is formed only in the discarded region . On a back surface of a semiconductor substrate having a first region, a second region adjacent to the first region, and a third region adjacent to the second region, a boundary line between the first region and the second region Forming a connecting layer made of a resin so as to cover at least a part of a first boundary line and at least a part of a second boundary line that is a boundary line of the second region and the third region;
Dividing the first region and the second region by cleaving by applying a force along the first boundary line from the back side of the semiconductor substrate;
Dividing the second region and the third region by cleavage by applying a force along the second boundary line from the back surface side of the semiconductor substrate,
Each of the first region, the second region, and the third region has a main region that becomes a semiconductor chip after division, and a discarded region provided outside the main region,
The method for manufacturing a semiconductor device, wherein the connection layer is formed only in the discarded region. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the coupling layer extends continuously in the first region, the second region, and the third region. Before the step of dividing by cleavage,
4. The method according to claim 1, further comprising a step of forming a first scribe groove for cleaving the semiconductor substrate at a surface of the semiconductor substrate at an end of the first boundary line and the second boundary line . A manufacturing method of a semiconductor device given in any 1 paragraph . Forming a seed metal layer on the back side of the semiconductor substrate;
Forming a back electrode on the seed metal layer,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the connection layer is the seed metal layer formed in the same step as the step of forming the seed metal layer. 6. The method of manufacturing a semiconductor device according to claim 1 , wherein an end face incident type or an end face emission type optical device is formed in the main region. 7.   The said connection layer contains a metal, and is formed on the said semiconductor substrate by any process of plating, vapor deposition, or sputtering, The manufacturing of the semiconductor device as described in any one of Claims 1-6 characterized by the above-mentioned. Method. The method for manufacturing a semiconductor device according to claim 2, wherein the resin includes at least one of polyimide, benzocyclobutene, and fluorine-based resin. Dividing the first region and the second region, and dividing the second region and the third region,
A process of attaching a pressure-sensitive adhesive sheet having an adhesive applied to the front surface thereof on the back surface of the semiconductor substrate;
A step of attaching a cover sheet for surface protection to the surface of the semiconductor substrate;
A step of installing the semiconductor substrate, the adhesive sheet, and a laminate of the adhesive sheet so that the cover sheet and the cradle are in contact with each other on a cradle having a recess in the center part;
Cleaving the semiconductor substrate by pressing a blade for cleavage against the adhesive sheet along the first boundary line in a state where the first boundary line is located on the recess;
Cleaving the semiconductor substrate by pressing the blade against the adhesive sheet along the second boundary line in a state where the second boundary line is located on the recess; and
The method for manufacturing a semiconductor device according to claim 1, comprising:

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