JP5629154B2 - Thin film transistor manufacturing equipment - Google Patents

Thin film transistor manufacturing equipment Download PDF

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JP5629154B2
JP5629154B2 JP2010171837A JP2010171837A JP5629154B2 JP 5629154 B2 JP5629154 B2 JP 5629154B2 JP 2010171837 A JP2010171837 A JP 2010171837A JP 2010171837 A JP2010171837 A JP 2010171837A JP 5629154 B2 JP5629154 B2 JP 5629154B2
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electrode
chamber
film transistor
thin film
substrate
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JP2011129870A (en
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秉胄 金
秉胄 金
志洙 安
志洙 安
▲チョル▼浩 劉
▲チョル▼浩 劉
聖哲 金
聖哲 金
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Samsung Display Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67196Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the transfer chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67201Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Description

本発明は、薄膜トランジスタ製造装置に関する。   The present invention relates to a thin film transistor manufacturing apparatus.

平板表示装置(Flat Panel display device)は、軽量及び薄型などの特性を有するため、陰極線管表示装置(Cathode−ray
Tube display device)に代替される表示装置として用いられる。このような平板表示装置の代表的な例として、液晶表示装置(Liquid Crystal
Display device; LCD)と有機電界発光表示装置(Organic Light Emitting Diode
display device; OLED)が知られている。特に有機電界発光表示装置は、液晶表示装置に比べて輝度特性及び視野角特性が優れているため、バックライト(Backlight)を必要とせず、超薄型を実現することができる長所を有する。
Since the flat panel display device has characteristics such as light weight and thin thickness, a cathode-ray tube display device (Cathode-ray) is used.
It is used as a display device that is substituted for a tube display device). A typical example of such a flat panel display is a liquid crystal display (Liquid Crystal).
Display device (LCD) and organic light emitting display (Organic Light Emitting Diode)
display device (OLED) is known. In particular, since the organic light emitting display device has superior luminance characteristics and viewing angle characteristics as compared with a liquid crystal display device, it does not require a backlight, and has an advantage that an ultra-thin shape can be realized.

このような有機電界発光表示装置は、有機薄膜において陰極(Cathode)と陽極(Anode)から注入された電子と正孔とが再結合して励起子を形成し、この励起子からのエネルギーによって特定波長の光が発生する現象を利用した表示装置である。   In such an organic electroluminescent display device, electrons and holes injected from a cathode and an anode are recombined in an organic thin film to form excitons, which are specified by energy from the excitons. This is a display device using a phenomenon in which light of a wavelength is generated.

上記有機電界発光表示装置は、駆動方法によって受動駆動(Passive matrix)方式と能動駆動(Active
matrix)方式とに分類される。上記能動駆動方式の有機電界発光表示装置は、上記有機薄膜を含む有機電界発光ダイオードを駆動するために2つの薄膜トランジスタ(Thin
Film Transistor; TFT)が形成される。すなわち、上記有機電界発光ダイオードに駆動電流を印加するための駆動トランジスタ及び上記駆動トランジスタにデータ信号を伝達して上記駆動トランジスタのオン/オフを決定するスイッチングトランジスタが形成される。しかし、これら2つのトランジスタが形成されるために、能動駆動方式の有機電界発光表示装置は、受動駆動方式の有機電界発光表示装置に比べて製造が複雑であるという短所があった。
The organic light emitting display device has a passive drive method and an active drive method depending on a driving method.
(matrix) method. The active driving organic light emitting display includes two thin film transistors (Thin) for driving an organic light emitting diode including the organic thin film.
A film transistor (TFT) is formed. That is, a driving transistor for applying a driving current to the organic light emitting diode and a switching transistor for transmitting a data signal to the driving transistor to determine on / off of the driving transistor are formed. However, since these two transistors are formed, the active driving type organic light emitting display device has a disadvantage that it is more complicated to manufacture than the passive driving type organic light emitting display device.

しかし、上記受動駆動方式の有機電界発光表示装置は、解像度、駆動電圧の上昇、材料寿命の低下などの問題点で低解像度及び小型ディスプレイの応用分野に制限される。これに対し、上記能動駆動方式の有機電界発光表示装置は、表示領域の各画素に位置するスイッチングトランジスタ及び駆動トランジスタを用いて供給される所定の電流により安定的な輝度を示すことができ、さらに電力消耗も少ないため、高解像度や大型ディスプレイを実現することができるという長所を有する。   However, the organic electroluminescent display device of the passive driving method is limited to low resolution and small display application fields due to problems such as an increase in resolution, a driving voltage, and a decrease in material life. On the other hand, the active driving organic light emitting display device can exhibit stable luminance by a predetermined current supplied using a switching transistor and a driving transistor located in each pixel of the display region. Since it consumes less power, it has the advantage of being able to realize high resolution and large displays.

通常、上記スイッチングトランジスタ及び駆動トランジスタのような薄膜トランジスタは、半導体層、上記半導体層の一側に位置し、上記半導体層を通る電流の流れを制御するゲート電極、及び上記半導体層の両端部にそれぞれ接続されて上記半導体層により所定電流を移動させるソース電極及びドレイン電極を含む。上記半導体層は、多結晶シリコン(polycrystalline silicon; poly-si)または非晶質シリコン(amorphous
silicon; a-si)で形成され得るが、上記多結晶シリコンの電子移動度が非晶質シリコンの電子移動度よりも高いため、現在は多結晶シリコンが主に用いられる。
In general, thin film transistors such as the switching transistor and the driving transistor are located on one side of the semiconductor layer, the gate electrode for controlling the current flow through the semiconductor layer, and both ends of the semiconductor layer. A source electrode and a drain electrode are connected to move a predetermined current through the semiconductor layer. The semiconductor layer may be formed of polycrystalline silicon (poly-si) or amorphous silicon (amorphous).
silicon; a-si), but since the electron mobility of polycrystalline silicon is higher than that of amorphous silicon, polycrystalline silicon is mainly used at present.

ここで、上記多結晶シリコンからなる半導体層を形成する方法は、基板上に非晶質シリコン層を形成し、固相結晶化法(Solid Phase Crystallization: SPC)、急速熱処理方法(Rapid Thermal Annealing: RTA)、金属誘導結晶化法(Metal
Induced Crystallization: MIC)、金属誘導側面結晶化法(Metal Induced Lateral
Crystallization: MILC)、エキシマレーザアニーリング(Excimer Laser Annealing: ELA)結晶化法、及び順次側面固相(Sequential Lateral Solidification: SLS)結晶化法のうちのいずれか1つを用いて結晶化する方法が主に用いられる。
Here, the method for forming the semiconductor layer made of polycrystalline silicon includes forming an amorphous silicon layer on a substrate, solid phase crystallization (SPC), rapid thermal annealing (Rapid Thermal Annealing): RTA), metal-induced crystallization method (Metal
Induced Crystallization (MIC), Metal-Induced Lateral Crystallization (Metal Induced Lateral)
Crystallization: MILC), excimer laser annealing (ELA) crystallization method, and sequential lateral solidification (SLS) crystallization method are mainly used. Used for.

大韓民国出願公開第2005−73076号明細書Korean Application Publication No. 2005-73076 Specification

ここで、上記のような薄膜トランジスタを製造するための製造装置は、通常の工程効率を向上させ、ゲート電極、非晶質シリコン及びソース/ドレイン電極などが外部空気に接触されて腐食または特性変化をすることを防止するために、複数の工程チャンバから成るマルチチャンバを用いて各段階を行う。このような複数のマルチチャンバを含む薄膜トランジスタは、基板上に非晶質シリコンを蒸着した後、該非晶質シリコンが形成された基板を別途のマルチチャンバまたは工程チャンバに移送し、該非晶質シリコンを多結晶シリコンに結晶化し、多結晶シリコンが形成された基板を再び移送して絶縁膜及び電極を形成する。このため、連続的な環境変化による特性の偏差及び基板移送による変形が生じ、工程時間を短縮するのに制限があるという問題があった。   Here, the manufacturing apparatus for manufacturing the thin film transistor as described above improves the normal process efficiency, and the gate electrode, the amorphous silicon, the source / drain electrode, etc. are brought into contact with external air to cause corrosion or change in characteristics. In order to prevent this, each step is performed using a multi-chamber composed of a plurality of process chambers. In such a thin film transistor including a plurality of multi-chambers, after depositing amorphous silicon on a substrate, the substrate on which the amorphous silicon is formed is transferred to a separate multi-chamber or process chamber, and the amorphous silicon is transferred to the thin film transistor. Crystallized into polycrystalline silicon, and the substrate on which the polycrystalline silicon is formed is transferred again to form an insulating film and an electrode. For this reason, there has been a problem that there is a limitation in shortening the process time due to deviation of characteristics due to continuous environmental changes and deformation due to substrate transfer.

そこで、本発明は、上記問題に鑑みてなされたものであり、本発明の目的とするところは、基板上に蒸着された非晶質シリコンを結晶化する方法を改善し、全体の工程チャンバ数を低減させることが可能な、新規かつ改良された薄膜トランジスタ製造装置を提供することにある。   Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to improve a method for crystallizing amorphous silicon deposited on a substrate and to increase the number of process chambers as a whole. It is an object of the present invention to provide a new and improved thin film transistor manufacturing apparatus capable of reducing the above.

上記課題を解決するために、本発明のある観点によれば、基板上に非晶質シリコンを蒸着する第1マルチチャンバと、前記基板上に電極を形成する第2マルチチャンバと、前記第1マルチチャンバと前記第2マルチチャンバとの間に位置するローディング/アンローディングチャンバと、を含み、前記ローディング/アンローディングチャンバは、基板ホルダ及び電源電圧印加部を含むことを特徴とする薄膜トランジスタ製造装置が提供される。   In order to solve the above problems, according to an aspect of the present invention, a first multi-chamber for depositing amorphous silicon on a substrate, a second multi-chamber for forming an electrode on the substrate, and the first And a loading / unloading chamber positioned between the multi-chamber and the second multi-chamber, wherein the loading / unloading chamber includes a substrate holder and a power supply voltage application unit. Provided.

また、前記基板ホルダは、基板が載置される基板支持台と、前記基板支持台を上昇または下降させるホルダ移送部と、前記ホルダ移送部を制御するホルダ駆動部と、を含んでもよい。   The substrate holder may include a substrate support on which the substrate is placed, a holder transfer unit that raises or lowers the substrate support, and a holder drive unit that controls the holder transfer unit.

また、前記基板支持台は、前記基板を固定させる固定手段をさらに含んでもよい。   The substrate support may further include fixing means for fixing the substrate.

また、前記固定手段は、真空ポンプに接続された1つまたは複数の真空ホールであってもよい。   The fixing means may be one or a plurality of vacuum holes connected to a vacuum pump.

また、前記基板支持台の側面に位置し、基板を整列させるアラインメント手段をさらに含んでもよい。   In addition, it may further include alignment means that is positioned on a side surface of the substrate support and aligns the substrates.

また、前記基板支持台は、基板の大きさを検知するための1つまたは複数のセンサをさらに含んでもよい。   The substrate support may further include one or more sensors for detecting the size of the substrate.

また、前記電源電圧印加部は、第1電極と、第2電極と、前記第1電極及び前記第2電極に互いに異なる極性の電源電圧を印加する電源電圧源と、を含んでもよい。   The power supply voltage application unit may include a first electrode, a second electrode, and a power supply voltage source that applies power supply voltages having different polarities to the first electrode and the second electrode.

また、前記電源電圧印加部は、前記第1電極と前記第2電極との間の距離を調節する制御部をさらに含んでもよい。   The power supply voltage application unit may further include a control unit that adjusts a distance between the first electrode and the second electrode.

また、前記電源電圧印加部は、前記第1電極を移動させる第1電極移送部と、前記第2電極を移動させる第2電極移送部と、前記第1電極移送部及び前記第2電極移送部の移動経路が設けられた移動ガイドをさらに含んでもよい。   The power supply voltage application unit includes a first electrode transfer unit that moves the first electrode, a second electrode transfer unit that moves the second electrode, the first electrode transfer unit, and the second electrode transfer unit. A movement guide provided with the movement path may be further included.

また、前記移動ガイドは、前記第1電極移送部の移動経路が設けられた第1移動ガイド及び前記第2電極移送部の移動経路が設けられた第2移動ガイドを含み、前記第1移動ガイドと前記第2移動ガイドとは所定距離離隔されていてもよい。   The movement guide includes a first movement guide provided with a movement path of the first electrode transfer section and a second movement guide provided with a movement path of the second electrode transfer section, and the first movement guide. And the second movement guide may be separated from each other by a predetermined distance.

また、前記第1移動ガイド及び前記第2移動ガイドは、前記移動ガイドの長手方向に形成されたガイドホールを含み、前記第1電極移送部及び前記第2電極移送部は、前記ガイドホームに対応するよう形成された突出部を含んでもよい。   The first movement guide and the second movement guide include a guide hole formed in a longitudinal direction of the movement guide, and the first electrode transfer unit and the second electrode transfer unit correspond to the guide home. Protrusions formed to do so may be included.

また、前記第2マルチチャンバは、スパッタリング工程を行なう工程チャンバを含んでもよい。   The second multi-chamber may include a process chamber for performing a sputtering process.

また、前記薄膜トランジスタ製造装置は、前記第1マルチチャンバと前記ローディング/アンローディングチャンバとの間及び前記ローディング/アンローディングチャンバと前記第2マルチチャンバとの間に位置するゲートバルブをさらに含んでもよい。   The thin film transistor manufacturing apparatus may further include a gate valve positioned between the first multi-chamber and the loading / unloading chamber and between the loading / unloading chamber and the second multi-chamber.

以上説明したように本発明によれば、基板上に蒸着された非晶質シリコンを結晶化する方法を改善し、全体の工程チャンバ数を低減させることができる。   As described above, according to the present invention, the method for crystallizing amorphous silicon deposited on a substrate can be improved and the number of process chambers can be reduced.

本発明の実施形態に係る薄膜トランジスタ製造装置の一部を示す模式図である。It is a schematic diagram which shows a part of thin-film transistor manufacturing apparatus which concerns on embodiment of this invention. 図1の切断線I−I’による断面図である。FIG. 2 is a cross-sectional view taken along a cutting line I-I ′ in FIG. 1. 本発明の実施形態に係る薄膜トランジスタ製造装置の第1マルチチャンバと第2マルチチャンバとの間に位置するローディング/アンローディングチャンバを示す斜視図である。FIG. 5 is a perspective view illustrating a loading / unloading chamber positioned between a first multi-chamber and a second multi-chamber of the thin film transistor manufacturing apparatus according to the embodiment of the present invention. 図2Aの切断線A−A’による断面図である。It is sectional drawing by the cutting line A-A 'of FIG. 2A. 図2Aの切断線B−B’による断面図である。FIG. 2B is a cross-sectional view taken along section line B-B ′ of FIG. 2A.

以下、添付した図面を参照して、本発明の好適な実施形態を詳細に説明する。しかしながら、本発明は、以下で説明する実施形態に限定されるわけではなく、他の形態で具体化することができる。したがって、以下に開示される実施形態は発明の開示を完全なものとすると共に、当業者に本発明の思想を十分に伝えるために提供されるものである。なお、説明の都合上、図面において、層及び領域の厚みは誇張されており、図示する形態が実際とは異なる場合がある。明細書の全体において同一の参照番号は、同一の構成要素を示す。   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, and can be embodied in other forms. Accordingly, the embodiments disclosed below are provided to complete the disclosure of the invention and to fully convey the spirit of the present invention to those skilled in the art. For convenience of explanation, the thickness of layers and regions is exaggerated in the drawings, and the illustrated form may be different from the actual one. Like reference numerals refer to like elements throughout the specification.

本実施形態は、基板上に非晶質シリコンを蒸着する第1マルチチャンバと基板上に電極を形成するための第2マルチチャンバとの間に位置するローディング/アンローディングチャンバを、真空状態でない結晶化装置として用いることで、全体の工程チャンバ数を低減することを特徴とする。   In the present embodiment, a loading / unloading chamber located between a first multi-chamber for depositing amorphous silicon on a substrate and a second multi-chamber for forming an electrode on the substrate is formed in a crystal that is not in a vacuum state. By using it as an apparatus, the number of process chambers as a whole is reduced.

特許文献1は、非晶質シリコン薄膜に所定電源電圧を印加して発生するジュール加熱による高熱を用いて上記非晶質シリコン薄膜を多結晶シリコン薄膜に結晶化することで、工程チャンバを真空状態にしなくても結晶化工程を行うことのできる結晶化方法が開示されている。   In Patent Document 1, the amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by using high heat generated by Joule heating generated by applying a predetermined power supply voltage to the amorphous silicon thin film. There is disclosed a crystallization method capable of performing the crystallization step even if not.

そこで、本発明は、基板上に非晶質シリコンを蒸着するための第1マルチチャンバと上記基板上に電極を形成するための第2マルチチャンバとの間に位置するローディング/アンローディングチャンバで、上記ジュール加熱による結晶化工程が行われるようにし、全体の工程チャンバ数を低減させる。   Accordingly, the present invention provides a loading / unloading chamber positioned between a first multi-chamber for depositing amorphous silicon on a substrate and a second multi-chamber for forming an electrode on the substrate. The crystallization process by the Joule heating is performed, and the total number of process chambers is reduced.

<実施形態>
図1Aは本発明の実施形態に係る薄膜トランジスタ製造装置の一部を示す模式図であり、図1Bは図1Aの切断線I−I’による断面図である。
<Embodiment>
FIG. 1A is a schematic view showing a part of a thin film transistor manufacturing apparatus according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along a cutting line II ′ of FIG. 1A.

図1A及び図1Bに示すように、本発明の実施形態に係る薄膜トランジスタ製造装置は、複数の第1工程チャンバ110を含む第1マルチチャンバ100と、複数の第2工程チャンバ210を含む第2マルチチャンバ200と、第1マルチチャンバ100と第2マルチチャンバ200との間に位置するローディング/アンローディングチャンバ300と、を含む。   As shown in FIGS. 1A and 1B, a thin film transistor manufacturing apparatus according to an embodiment of the present invention includes a first multi-chamber 100 including a plurality of first process chambers 110 and a second multi-chamber including a plurality of second process chambers 210. And a loading / unloading chamber 300 positioned between the first multi-chamber 100 and the second multi-chamber 200.

第1マルチチャンバ100は、基板(図示せず)上に非晶質シリコンを蒸着するものであり、複数の第1工程チャンバ110及び基板を複数の第1工程チャンバ110に搬入/搬出するための第1ロボットアーム125が位置する第1搬送チャンバ120を含む。ここで、複数の第1工程チャンバ110は、基板上に非晶質シリコンを蒸着させるために基板を支持する支持チャック111と、蒸着物質を噴射する複数の噴射ノズル113が形成されたシャワーヘッド112と、を含み、非晶質シリコン蒸着工程を行う。   The first multi-chamber 100 is for depositing amorphous silicon on a substrate (not shown), and is used for loading / unloading the plurality of first process chambers 110 and the substrate into / from the plurality of first process chambers 110. A first transfer chamber 120 in which the first robot arm 125 is located is included. Here, the plurality of first process chambers 110 includes a shower head 112 in which a support chuck 111 that supports a substrate for depositing amorphous silicon on the substrate and a plurality of spray nozzles 113 that spray a deposition material are formed. And performing an amorphous silicon deposition process.

第2マルチチャンバ200は、基板上に電極を形成させるものであって、複数の第2工程チャンバ210と、基板を複数の第2工程チャンバ210に搬入/搬出する第2ロボットアーム225が位置する第2搬送チャンバ220を含む。ここで、複数の第2工程チャンバ210は、ターゲット211、電圧源230に接続される第1電極212aを含むターゲットホルダ212、基準電圧に接続される第2電極221を含む支持台220、及びターゲットホルダ212背面に位置する磁石組立体240を含んでスパッタリング工程を介して電極層を形成する。   The second multi-chamber 200 forms electrodes on a substrate, and a plurality of second process chambers 210 and a second robot arm 225 for loading / unloading the substrates into / from the plurality of second process chambers 210 are positioned. A second transfer chamber 220 is included. Here, the plurality of second process chambers 210 include a target 211, a target holder 212 including a first electrode 212a connected to a voltage source 230, a support base 220 including a second electrode 221 connected to a reference voltage, and a target. An electrode layer is formed through a sputtering process including the magnet assembly 240 located on the back surface of the holder 212.

ここで、第1搬送チャンバ120と第1工程チャンバ110との間及び第2搬送チャンバ220と第2工程チャンバ210との間には、第1工程チャンバ110及び第2工程チャンバ210が工程を行う間に真空状態が維持できるように、ゲートバルブ(図示せず)を含む搬出入口410、440が位置する。   Here, the first process chamber 110 and the second process chamber 210 perform processes between the first transfer chamber 120 and the first process chamber 110 and between the second transfer chamber 220 and the second process chamber 210. In order to be able to maintain a vacuum state therebetween, carry-in / out ports 410 and 440 including gate valves (not shown) are located.

ローディング/アンローディングチャンバ300は、第1マルチチャンバ100から搬出される基板上に蒸着された非晶質シリコンを多結晶シリコンに結晶化させた後、多結晶シリコンが形成された基板を第2マルチチャンバ200に搬入するものである。ローディング/アンローディングチャンバ300は、内部の下側に基板ホルダ310が位置し、内部の上側に互いに異なる極性を有する第1電極321と第2電極322とを含む電源電圧印加部320が位置する。   The loading / unloading chamber 300 crystallizes amorphous silicon deposited on the substrate unloaded from the first multi-chamber 100 into polycrystalline silicon, and then converts the substrate on which polycrystalline silicon is formed into the second multi-chamber. It is carried into the chamber 200. In the loading / unloading chamber 300, the substrate holder 310 is located on the lower side of the interior, and the power supply voltage application unit 320 including the first electrode 321 and the second electrode 322 having different polarities is located on the upper side of the interior.

ここで、第1マルチチャンバ100及び第2マルチチャンバ200とローディング/アンローディングチャンバ300との間には、第1マルチチャンバ100及び第2マルチチャンバ200が工程を行う間に真空状態が維持できるように、ゲートバルブを含む搬出入口420、430が位置する。   Here, a vacuum state may be maintained between the first multi-chamber 100 and the second multi-chamber 200 and the loading / unloading chamber 300 while the first multi-chamber 100 and the second multi-chamber 200 perform a process. In addition, loading / unloading ports 420 and 430 including gate valves are located.

図2Aは本発明の実施形態に係る薄膜トランジスタ製造装置の第1マルチチャンバ100と第2マルチチャンバ200との間に位置するローディング/アンローディングチャンバ300を示す斜視図である。図2Bは図2Aの切断線A−A’による断面図である。図2Cは切断線図2AのB−B’による断面図である。   FIG. 2A is a perspective view illustrating a loading / unloading chamber 300 positioned between the first multi-chamber 100 and the second multi-chamber 200 of the thin film transistor manufacturing apparatus according to the embodiment of the present invention. FIG. 2B is a cross-sectional view taken along section line A-A ′ of FIG. 2A. FIG. 2C is a cross-sectional view taken along line B-B ′ of FIG. 2A.

図2A〜図2Cを参照し、本発明の実施形態に係る薄膜トランジスタ製造装置のローディング/アンローディングチャンバ300をより詳しく説明する。ローディング/アンローディングチャンバ300内部の下側に位置する基板ホルダ310は、ローディング/アンローディングチャンバ300の内側に搬入された基板を支持し、電源電圧印加部320により電源電圧が印加される位置に該基板を移動させて、基板上に蒸着された非晶質シリコンの結晶化工程が行われるようにする。基板ホルダ310は、基板が載置される基板支持台311、該基板支持台311を上昇または下降させるためのホルダ移送部312及び該ホルダ移送部312を制御するためのホルダ駆動部313を含む。   2A to 2C, the loading / unloading chamber 300 of the thin film transistor manufacturing apparatus according to an embodiment of the present invention will be described in more detail. The substrate holder 310 located on the lower side of the loading / unloading chamber 300 supports the substrate loaded inside the loading / unloading chamber 300, and the power supply voltage application unit 320 applies the power supply voltage to the position. The substrate is moved to perform a crystallization process of amorphous silicon deposited on the substrate. The substrate holder 310 includes a substrate support 311 on which a substrate is placed, a holder transfer unit 312 for raising or lowering the substrate support 311, and a holder driving unit 313 for controlling the holder transfer unit 312.

基板支持台311は、載置された基板を固定するための固定手段を含む。例えば、固定手段として、基板と基板支持台311との間の空気を排出させて基板を基板支持台311に密着させる1つまたは複数の真空ホール311aを形成してもよい。かかる1つまたは複数の真空ホール311aは、真空配管345により真空ポンプ340に接続され、1つまたは複数の真空ホール311aを介して基板と基板支持台311との間に存在する空気を強制排気させることによって、基板を基板支持台311に密着固定させることができる。   The substrate support 311 includes fixing means for fixing the placed substrate. For example, as the fixing means, one or a plurality of vacuum holes 311a may be formed so that the air between the substrate and the substrate support 311 is discharged and the substrate is in close contact with the substrate support 311. The one or more vacuum holes 311a are connected to the vacuum pump 340 by a vacuum pipe 345, and the air existing between the substrate and the substrate support 311 is forcibly exhausted through the one or more vacuum holes 311a. As a result, the substrate can be tightly fixed to the substrate support 311.

また、基板支持台311は、基板を整列させるアラインメント手段311b及び基板の大きさを検知する複数のセンサ311cを含む。アラインメント手段311bは、基板支持台311の側面に位置し、基板支持台311からはみ出した基板を基板支持台311の内側に押し込む手段とすることができる。   The substrate support 311 includes alignment means 311b for aligning the substrates and a plurality of sensors 311c for detecting the size of the substrate. The alignment means 311 b can be a means that is located on the side surface of the substrate support table 311 and pushes the substrate protruding from the substrate support table 311 into the substrate support table 311.

電源電圧印加部320は、基板の導電性薄膜に所定電源電圧を印加し、基板に形成された非晶質シリコンの結晶化を行う。電源電圧印加部320は、第1電極321、第2電極322、及び上記第1電極321と第2電極322に互いに異なる極性の電源電圧を印加するための電源電圧源330を含む。   The power supply voltage application unit 320 applies a predetermined power supply voltage to the conductive thin film of the substrate, and crystallizes amorphous silicon formed on the substrate. The power supply voltage application unit 320 includes a first electrode 321, a second electrode 322, and a power supply voltage source 330 for applying power supply voltages having different polarities to the first electrode 321 and the second electrode 322.

そこで、電源電圧印加部320は搬入される基板の大きさとは関係なく、基板の正確な位置に所定電源電圧が印加されることができるように、第1電極321と第2電極322との間の距離を調節するための制御部360及び該制御部360により調節される第1電極321と第2電極322の移動経路が形成された移動ガイド323をさらに含むことができる。   Therefore, the power supply voltage application unit 320 is provided between the first electrode 321 and the second electrode 322 so that a predetermined power supply voltage can be applied to an accurate position of the substrate regardless of the size of the substrate to be loaded. And a movement guide 323 in which a movement path of the first electrode 321 and the second electrode 322 adjusted by the control unit 360 is formed.

また、電源電圧印加部320は、第1電極321及び第2電極322の移動及び整列を容易に調節するために、第1電極321と移動ガイド323との間に結合され、制御部360の制御により第1電極321を移動させる第1電極移送部351と、第2電極322と移動ガイド323との間に結合され、制御部360の制御により第2電極322を移動させるための第2電極移送部352と、をさらに含むことができる。   In addition, the power supply voltage application unit 320 is coupled between the first electrode 321 and the movement guide 323 in order to easily adjust the movement and alignment of the first electrode 321 and the second electrode 322, and is controlled by the control unit 360. The first electrode transfer unit 351 that moves the first electrode 321 by the first electrode 321, and the second electrode transfer unit that is coupled between the second electrode 322 and the movement guide 323 and moves the second electrode 322 under the control of the control unit 360. Part 352 may be further included.

ここで、上記移動ガイド323は、第1電極移送部351の移動経路が形成された第1移動ガイド323a及び第2電極移送部352の移動経路が形成された第2移動ガイド323bと、をそれぞれ含む。なお、第1電極321と第2電極322との衝突を防止させるために、第1移動ガイド323aと第2移動ガイド323bは所定距離離隔させていることが好ましい。   Here, the movement guide 323 includes a first movement guide 323a in which a movement path of the first electrode transfer unit 351 is formed and a second movement guide 323b in which a movement path of the second electrode transfer unit 352 is formed, respectively. Including. In order to prevent a collision between the first electrode 321 and the second electrode 322, the first movement guide 323a and the second movement guide 323b are preferably separated by a predetermined distance.

また、第1移動ガイド323a及び第2移動ガイド323bは、同一方向に所定の長さを有し、第1電極321及び第2電極322を同一方向に移動させることで、第1電極321及び第2電極322の位置をより容易に調節できるようにする。   Further, the first movement guide 323a and the second movement guide 323b have a predetermined length in the same direction, and the first electrode 321 and the second movement guide 323b are moved by moving the first electrode 321 and the second electrode 322 in the same direction. The position of the two electrodes 322 can be adjusted more easily.

本発明の実施形態に係る薄膜トランジスタ製造装置のローディング/アンローディングチャンバ300は、第1移動ガイド323aと第1電極移送部351との間及び第2移動ガイド323bと第2電極移送部352との間をさらに堅く結合させるために、第1移動ガイド323a及び第2移動ガイド323bにY方向に所定の長さを有するガイドホール323cを形成し、第1電極移送部351及び第2電極移送部352にガイドホール323cに対応する突出部351aを形成することもできる。   The loading / unloading chamber 300 of the thin film transistor manufacturing apparatus according to the embodiment of the present invention includes the first movement guide 323a and the first electrode transfer unit 351 and the second movement guide 323b and the second electrode transfer unit 352. In order to make the first and second movement guides 323a and 323b more rigidly coupled to each other, a guide hole 323c having a predetermined length in the Y direction is formed in the first movement guide 323a and the second movement guide 323b. A protrusion 351a corresponding to the guide hole 323c can also be formed.

上記本発明の実施形態に係る薄膜トランジスタ製造装置によれば、別途の工程チャンバまたはマルチチャンバを使用せず、第1マルチチャンバで蒸着された非晶質シリコンを多結晶シリコンに結晶化した後、電極を形成するための第2マルチチャンバに搬入することで、全体の工程チャンバ数を低減させて連続的な環境変化による特性の偏差を最小化し、製造工程効率を向上させることができる。具体的には、基板上に非晶質シリコンを蒸着するために複数の第1工程チャンバを含む第1マルチチャンバと基板上に電極を形成するために複数の第2工程チャンバを含む第2マルチチャンバとの間に位置するローディング/アンローディングチャンバを、ジュール熱を利用した結晶化装置として用いることで、第1マルチチャンバで蒸着された非晶質シリコンを別途のマルチチャンバまたは工程チャンバなしに多結晶シリコンに結晶化した後に、電極形成のための第2マルチチャンバに移送するため、全体の工程チャンバ数を低減させることができる。   According to the thin film transistor manufacturing apparatus according to the embodiment of the present invention, the amorphous silicon deposited in the first multi-chamber is crystallized into polycrystalline silicon without using a separate process chamber or multi-chamber, and then the electrode By carrying it into the second multi-chamber for forming the process chamber, it is possible to reduce the number of process chambers as a whole, minimize characteristic deviation due to continuous environmental changes, and improve manufacturing process efficiency. Specifically, a first multi chamber including a plurality of first process chambers for depositing amorphous silicon on a substrate and a second multi including a plurality of second process chambers for forming electrodes on the substrate. By using the loading / unloading chamber located between the chambers as a crystallization apparatus using Joule heat, the amorphous silicon deposited in the first multi-chamber can be increased without a separate multi-chamber or process chamber. After crystallizing into crystalline silicon, the entire number of process chambers can be reduced because it is transferred to the second multi-chamber for electrode formation.

以上、添付図面を参照しながら本発明の好適な実施形態について詳細に説明したが、本発明はかかる例に限定されない。本発明の属する技術の分野における通常の知識を有する者であれば、特許請求の範囲に記載された技術的思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、これらについても、当然に本発明の技術的範囲に属するものと了解される。   The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field to which the present invention pertains can come up with various changes or modifications within the scope of the technical idea described in the claims. Of course, it is understood that these also belong to the technical scope of the present invention.

100 第1マルチチャンバ
110 第1工程チャンバ
200 第2マルチチャンバ
210 第2工程チャンバ
300 ローディング/アンローディングチャンバ
310 基板ホルダ
320 電源電圧印加部
DESCRIPTION OF SYMBOLS 100 1st multi-chamber 110 1st process chamber 200 2nd multi-chamber 210 2nd process chamber 300 Loading / unloading chamber 310 Substrate holder 320 Power supply voltage application part

Claims (11)

基板上に非晶質シリコンを蒸着する第1マルチチャンバと、
前記基板上に電極を形成する第2マルチチャンバと、
前記第1マルチチャンバと前記第2マルチチャンバとの間に位置するローディング/アンローディングチャンバと、
を含み、
前記ローディング/アンローディングチャンバは、基板ホルダ及び前記基板ホルダに載置される基板に電源電圧を印加する電源電圧印加部を含み、
前記電源電圧印加部は、第1電極と、第2電極と、前記第1電極及び前記第2電極に互いに異なる極性の電源電圧を印加する電源電圧源と、前記第1電極と前記第2電極との間の距離を調節する制御部を含むことを特徴とする薄膜トランジスタ製造装置。
A first multi-chamber for depositing amorphous silicon on a substrate;
A second multi-chamber for forming electrodes on the substrate;
A loading / unloading chamber located between the first multi-chamber and the second multi-chamber;
Including
The loading / unloading chamber saw including a power supply voltage applying unit for applying a power supply voltage to the substrate placed on the substrate holder and the substrate holder,
The power supply voltage application unit includes a first electrode, a second electrode, a power supply voltage source that applies power supply voltages having different polarities to the first electrode and the second electrode, the first electrode, and the second electrode. A thin film transistor manufacturing apparatus comprising: a control unit that adjusts a distance between the first thin film transistor and the second thin film transistor.
前記基板ホルダは、基板が載置される基板支持台と、前記基板支持台を上昇または下降させるホルダ移送部と、前記ホルダ移送部を制御するホルダ駆動部と、を含むことを特徴とする請求項1に記載の薄膜トランジスタ製造装置。   The substrate holder includes a substrate support on which a substrate is placed, a holder transfer unit that raises or lowers the substrate support, and a holder drive unit that controls the holder transfer unit. Item 2. The thin film transistor manufacturing apparatus according to Item 1. 前記基板支持台は、前記基板を固定させる固定手段をさらに含むことを特徴とする請求項2に記載の薄膜トランジスタ製造装置。   The thin film transistor manufacturing apparatus according to claim 2, wherein the substrate support further includes a fixing unit that fixes the substrate. 前記固定手段は、真空ポンプに接続された1つまたは複数の真空ホールであることを特徴とする請求項3に記載の薄膜トランジスタ製造装置。   4. The thin film transistor manufacturing apparatus according to claim 3, wherein the fixing means is one or a plurality of vacuum holes connected to a vacuum pump. 前記基板支持台の側面に位置し、基板を整列させるアラインメント手段をさらに含むことを特徴とする請求項2から4のいずれか1項に記載の薄膜トランジスタ製造装置。   5. The thin film transistor manufacturing apparatus according to claim 2, further comprising alignment means positioned on a side surface of the substrate support and aligning the substrates. 前記基板支持台は、基板の大きさを検知するための1つまたは複数のセンサをさらに含むことを特徴とする請求項2から5のいずれか1項に記載の薄膜トランジスタ製造装置。   The thin film transistor manufacturing apparatus according to claim 2, wherein the substrate support further includes one or more sensors for detecting the size of the substrate. 前記電源電圧印加部は、前記第1電極を移動させる第1電極移送部と、前記第2電極を移動させる第2電極移送部と、前記第1電極移送部及び前記第2電極移送部の移動経路が設けられた移動ガイドをさらに含むことを特徴とする請求項1から6のいずれか1項に記載の薄膜トランジスタ製造装置。 The power supply voltage application unit includes a first electrode transfer unit that moves the first electrode, a second electrode transfer unit that moves the second electrode, and a movement of the first electrode transfer unit and the second electrode transfer unit. producing a thin film transistor device according to any one of 6 claim 1, characterized by further comprising a movement guide path is provided. 前記移動ガイドは、前記第1電極移送部の移動経路が設けられた第1移動ガイド及び前記第2電極移送部の移動経路が設けられた第2移動ガイドを含み、
前記第1移動ガイドと前記第2移動ガイドとは所定距離離隔されていることを特徴とする請求項に記載の薄膜トランジスタ製造装置。
The movement guide includes a first movement guide provided with a movement path of the first electrode transfer section and a second movement guide provided with a movement path of the second electrode transfer section,
8. The thin film transistor manufacturing apparatus according to claim 7 , wherein the first movement guide and the second movement guide are separated from each other by a predetermined distance.
前記第1移動ガイド及び前記第2移動ガイドは、前記移動ガイドの長手方向に形成されたガイドホールを含み、
前記第1電極移送部及び前記第2電極移送部は、前記ガイドホーに対応するよう形成された突出部を含むことを特徴とする請求項に記載の薄膜トランジスタ製造装置。
The first movement guide and the second movement guide include a guide hole formed in a longitudinal direction of the movement guide,
The first electrode transfer unit and the second electrode transfer unit, producing a thin film transistor device according to claim 8, characterized in that it comprises a protruding portion formed so as to correspond to the guide hall.
前記第2マルチチャンバは、スパッタリング工程を行なう工程チャンバを含むことを特徴とする請求項1からのいずれか1項に記載の薄膜トランジスタ製造装置。 It said second multi-chamber, producing a thin film transistor device according to any one of claims 1 to 9, characterized in that it comprises a process chamber for performing the sputtering process. 前記薄膜トランジスタ製造装置は、
前記第1マルチチャンバと前記ローディング/アンローディングチャンバとの間及び前記ローディング/アンローディングチャンバと前記第2マルチチャンバとの間に位置するゲートバルブをさらに含むことを特徴とする請求項1から10のいずれか1項に記載の薄膜トランジスタ製造装置。
The thin film transistor manufacturing apparatus includes:
From claim 1, further comprising a gate valve located between and between the loading / unloading chamber and the second multi-chamber of the first multi-chamber and the loading / unloading chamber 10 of the The thin-film transistor manufacturing apparatus of any one of Claims.
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