JP5622934B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5622934B2
JP5622934B2 JP2013519309A JP2013519309A JP5622934B2 JP 5622934 B2 JP5622934 B2 JP 5622934B2 JP 2013519309 A JP2013519309 A JP 2013519309A JP 2013519309 A JP2013519309 A JP 2013519309A JP 5622934 B2 JP5622934 B2 JP 5622934B2
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lead
mos
fet
solder
semiconductor device
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JPWO2012169044A1 (en
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大賀　琢也
琢也 大賀
一泰 坂元
一泰 坂元
杉原　剛
剛 杉原
加藤政紀
政紀 加藤
中島　大輔
大輔 中島
剛 治田
剛 治田
玄 多田
玄 多田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

この発明は、ＭＯＳ−ＦＥＴ素子を用いたパワー用インバータ回路を構成するための、樹脂封止型半導体装置に関するものである。   The present invention relates to a resin-encapsulated semiconductor device for constituting a power inverter circuit using a MOS-FET element.

車両用回転電機への制御装置一体化や、車載機器の小型化が進められるに伴い、それらに用いられる半導体装置も小型化、軽量化、高信頼性が求められている。
また、車載用のパワー半導体装置においては、小型化する一方で大電流制御への対応も求められる。As control devices are integrated into a vehicular rotating electrical machine and downsizing of in-vehicle devices is progressed, semiconductor devices used for them are also required to be downsized, lightweight, and highly reliable.
In addition, in-vehicle power semiconductor devices are required to cope with large current control while being downsized.

このため、ＭＯＳ−ＦＥＴ素子を用いたパワー用半導体装置は、ＭＯＳ−ＦＥＴ素子の下面電極を絶縁基板配線上にはんだ付けし、上面電極を基板配線へワイヤボンドで接合したものを樹脂ケースに収める形態のものから、ＭＯＳ−ＦＥＴ素子の下面電極を金属リードフレームへはんだ付けし、さらに上面電極とリードフレームを内部リードではんだ付け接合し、トランスファーモールドにより樹脂封止する形態のものが開発されてきている。   For this reason, in a power semiconductor device using a MOS-FET element, the lower electrode of the MOS-FET element is soldered onto the insulating substrate wiring, and the upper electrode bonded to the substrate wiring by wire bonding is housed in a resin case. From the type, a type has been developed in which the lower electrode of the MOS-FET element is soldered to a metal lead frame, the upper electrode and the lead frame are soldered and joined with internal leads, and the resin is sealed by transfer molding. ing.

ＭＯＳ−ＦＥＴ素子の上面電極とリードフレームとの接合が内部リードで接合された、従来の半導体装置は、例えば、特許文献１、特許文献２などで提案されている。
（特許文献１、特許文献２ 参照）。Conventional semiconductor devices in which the upper electrode of the MOS-FET element and the lead frame are joined by an internal lead have been proposed in, for example, Patent Document 1 and Patent Document 2.
(See Patent Document 1 and Patent Document 2).

特開２００６−２１６７３６号公報JP 2006-216736 A 特開２００１−２９８１４２号公報JP 2001-298142 A

従来例のような半導体チップの上面電極とリードフレームを内部リードで接合する構造をさらに小型化しようとすると、はんだ付け工程における半導体チップ、内部リードの位置および姿勢を安定して実装することが課題となる。   In order to further reduce the size of the structure for joining the upper surface electrode of the semiconductor chip and the lead frame with the internal leads as in the conventional example, it is necessary to stably mount the position and orientation of the semiconductor chip and the internal leads in the soldering process. It becomes.

たとえば特許文献１（図１）では、内部リード（フレーム）の接合面が、半導体チップの電極部表面より内側に納まるように小さく形成されているため、電極部と内部リードの位置はセルフアライメントにより位置が決まり保たれるとしている。   For example, in Patent Document 1 (FIG. 1), since the joint surface of the internal lead (frame) is formed small so as to fit inside the surface of the electrode part of the semiconductor chip, the position of the electrode part and the internal lead is self-aligned. The position is supposed to be maintained.

しかし、この例ではリードフレーム（第二リード端子）と内部リードとの位置あわせ手段がないため、内部リード搭載位置のばらつきや、はんだ溶融時の内部リード移動時にリードフレームと内部リードの位置がずれることが懸念される。
半導体装置を小型化するためには、リードフレームも幅の狭いことが必要であるが、内部リードの位置ずれがあると、それを許容して接合を確保するためにリードフレームの接合面を広くする必要があり半導体装置の小型化が難しくなる。However, in this example, since there is no means for aligning the lead frame (second lead terminal) and the internal lead, the position of the lead frame and the internal lead shifts when the internal lead is moved or when the internal lead moves when the solder melts. There is concern.
In order to reduce the size of the semiconductor device, the lead frame also needs to be narrow. However, if there is a misalignment of the internal leads, the lead frame bonding surface is widened to allow it and secure the bonding. It is necessary to reduce the size of the semiconductor device.

また、この例では、溶融したはんだの厚さを規制する手段がないため、セルフアライメント時に半導体チップや内部リードが移動すると、はんだ厚さが変わったり、はんだが偏ったりして半導体チップや内部リードが傾くことが懸念される。   In this example, since there is no means to regulate the thickness of the molten solder, if the semiconductor chip or the internal lead moves during self-alignment, the solder thickness may change or the solder may be biased. There is a concern about the inclination.

半導体チップや内部リードが傾くと、押し出されたはんだが流れ出して上面電極と下面電極のショートを起こしたり、はんだ厚が不均一になるため、温度サイクル環境でのはんだ接合部の信頼性が低下するといった問題がある。
また、この例の構造で半導体チップにＭＯＳ−ＦＥＴ素子を用いたとき、はんだ付け後のＭＯＳ−ＦＥＴ素子が傾いていると、ゲート電極へのワイヤボンド接合が不安定になる問題もある。If the semiconductor chip or internal lead is tilted, the extruded solder will flow out, causing a short circuit between the top and bottom electrodes, and non-uniform solder thickness, reducing the reliability of the solder joint in a temperature cycle environment There is a problem.
Further, when a MOS-FET element is used for a semiconductor chip with the structure of this example, if the MOS-FET element after soldering is inclined, there is a problem that the wire bond bonding to the gate electrode becomes unstable.

また、特許文献２（図１）では、リードフレームと内部リードの接続部に一方に凸部、他方に凹部を設けて嵌合させて位置を決めるとしているが、半導体ペレットと内部リードの位置決めについては手段がなく、半導体ペレットと内部リードの搭載位置ばらつきや、はんだ溶融時のはんだ流れにより接合位置がばらつくことが懸念される。   Further, in Patent Document 2 (FIG. 1), the connecting portion of the lead frame and the internal lead is provided with a convex portion on one side and a concave portion on the other side to be fitted to determine the position. There is no means, and there is a concern that the bonding position varies due to variations in the mounting position of the semiconductor pellet and the internal lead and the solder flow during solder melting.

この例でも溶融したはんだの厚さを規制する手段がないため、半導体ペレットと内部リードの位置がずれると荷重バランスが偏り、はんだ溶融時に内部リードや半導体ペレットが傾くことが懸念される。   Even in this example, there is no means for regulating the thickness of the melted solder. Therefore, when the position of the semiconductor pellet and the internal lead is shifted, the load balance is biased, and there is a concern that the internal lead or the semiconductor pellet may tilt when the solder is melted.

内部リードや半導体ペレットが傾くと、押し出されたはんだが流れ出して上面電極と下面電極のショートを起こしたり、はんだ厚が不均一になるため温度サイクル環境でのはんだ接合部の信頼性が低下するといった問題がある。   If the internal leads or semiconductor pellets are tilted, the extruded solder will flow out, causing a short circuit between the upper and lower electrodes, and the solder thickness will be non-uniform, resulting in reduced solder joint reliability in a temperature cycle environment. There's a problem.

また、この例ではリードフレームと内部リードの接続部に設けた凸部、凹部を嵌合させるとしているが、内部リードの搭載位置にばらつきがあると正しく嵌合されず、位置がずれ、傾いた状態で接合されることも懸念される。
また、この例の構造で半導体ペレットにＭＯＳ−ＦＥＴ素子を用いたとき、はんだ付け後のＭＯＳ−ＦＥＴ素子が傾いていると、ゲート電極へのワイヤボンド接合が不安定になる。Also, in this example, the projections and recesses provided in the connection part between the lead frame and the internal lead are fitted. There is also concern about joining in a state.
In addition, when a MOS-FET element is used for the semiconductor pellet in the structure of this example, if the MOS-FET element after soldering is inclined, the wire bond bonding to the gate electrode becomes unstable.

この発明は上記のような課題を解決するためになされたもので、ＭＯＳ−ＦＥＴ素子とリードフレームを内部リードで電気的接合する半導体装置おいて、リードフレーム、内部リードを小型化しても、リードフレームと内部リード、内部リードとＭＯＳ−ＦＥＴ素子の位置を安定して接合できる構造を提案し、半導体装置を小型化・薄型化することを目的とする。   The present invention has been made to solve the above-described problems. In a semiconductor device in which a MOS-FET element and a lead frame are electrically joined by an internal lead, even if the lead frame and the internal lead are downsized, the lead The present invention proposes a structure in which the position of the frame and the internal lead and the position of the internal lead and the MOS-FET element can be stably bonded to reduce the size and thickness of the semiconductor device.

また、上記小型化された半導体装置を用いて、インバータ回路内蔵回転機械を小型化することを目的とする。     It is another object of the present invention to reduce the size of a rotary machine with a built-in inverter circuit using the miniaturized semiconductor device.

この発明に係る半導体装置は、第１のリードと、一部を変形させて突起部を設けた第２のリードと、第１のリードに下面電極が電気的に接合されたＭＯＳ−ＦＥＴ素子と、ＭＯＳ−ＦＥＴ素子の上面電極と第２のリードとの間に電流を通電する内部リードと、これらを電気的に接合するはんだ材、および、これらの相対位置を固定する封止樹脂からなり、第１のリードと第２のリードは下面が同一平面上にあり、かつ、内部リードはＭＯＳ−ＦＥＴ素子との接合面と第２のリードとの接合面が同一平面であり、第１のリードとＭＯＳ−ＦＥＴ素子の下面電極が第１のはんだで接合され、ＭＯＳ−ＦＥＴ素子の上面電極と内部リードが第２のはんだで接合され、内部リードと第２のリードの突起部が第３のはんだで接合され、第1のリード、第２のリード、ＭＯＳ−ＦＥＴ素子および内部リードが、封止樹脂により一体に成形されている半導体装置であって、少なくとも第１のはんだの内部と第２のはんだ内部に位置する支持部材を設け、前記内部リードの非接合部分に貫通穴を設けたものである。 The semiconductor device according to the present invention includes a first lead , a second lead that is partially deformed to provide a protrusion, a MOS-FET element in which a bottom electrode is electrically joined to the first lead, The internal lead that conducts current between the upper electrode of the MOS-FET element and the second lead, a solder material that electrically joins these, and a sealing resin that fixes their relative positions, The first lead and the second lead have bottom surfaces on the same plane, and the internal lead has a joint surface between the MOS-FET element and the second lead on the same plane, and the first lead And the lower electrode of the MOS-FET element are joined by the first solder, the upper electrode of the MOS-FET element and the internal lead are joined by the second solder, and the protrusion of the internal lead and the second lead is the third solder. Soldered, first lead, second The lead, the MOS-FET element, and the internal lead are integrally formed of a sealing resin, and are provided with a support member positioned at least inside the first solder and inside the second solder , A through hole is provided in a non-joined portion of the internal lead .

この発明の半導体装置によれば、セルフアライメントにより内部リードおよびＭＯＳ−ＦＥＴ素子が移動する際、ＭＯＳ−ＦＥＴ素子および内部リードが水平に保たれ、確実にセルフアライメントが実現できるので、第１のリード、第２のリードおよび、内部リードを必要最小の大きさに設計でき、半導体装置の小型化が可能となる。   According to the semiconductor device of the present invention, when the internal lead and the MOS-FET element are moved by self-alignment, the MOS-FET element and the internal lead are kept horizontal, and the self-alignment can be surely realized. The second lead and the internal lead can be designed to the minimum necessary size, and the semiconductor device can be miniaturized.

また、セルフアライメントが実現できるため、高精度の実装装置は必要ない上、はんだ溶融時に内部リード、ＭＯＳ−ＦＥＴ素子の位置を保持する手段が必要でないので、製造工程の簡略化が可能となる。   In addition, since self-alignment can be realized, a high-accuracy mounting apparatus is not required, and a means for holding the position of the internal lead and the MOS-FET element when the solder is melted is not required, so that the manufacturing process can be simplified.

また、はんだ厚さが安定するので、はんだ流れによるＭＯＳ−ＦＥＴ素子の上面電極と下面電極のショートや、上面電極とゲート電極のショートを防ぐことができる。   Further, since the solder thickness is stabilized, it is possible to prevent a short circuit between the upper electrode and the lower electrode of the MOS-FET element and a short circuit between the upper electrode and the gate electrode due to the solder flow.

上述した、またその他の、この発明の目的、特徴、効果は、以下の実施の形態における詳細な説明および図面の記載からより明らかとなるであろう。   The above-described and other objects, features, and effects of the present invention will become more apparent from the detailed description and the drawings in the following embodiments.

この発明の実施の形態１による半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. この発明の第実施の形態１における内部リードとＭＯＳ−ＦＥＴ素子を示す図である。It is a figure which shows the internal lead and MOS-FET element in Embodiment 1 of this invention. この発明の実施の形態１における半導体装置のはんだ付け工程を説明する図である。It is a figure explaining the soldering process of the semiconductor device in Embodiment 1 of this invention. 薄型化された半導体装置の温度変化による変形を説明する図である。It is a figure explaining the deformation | transformation by the temperature change of the thinned semiconductor device. この発明の実施の形態２による半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device by Embodiment 2 of this invention. この発明の実施の形態２による半導体装置を示す平面図である。It is a top view which shows the semiconductor device by Embodiment 2 of this invention. この発明の実施の形態２におけるＭＯＳ−ＦＥＴ素子を示す図である。It is a figure which shows the MOS-FET element in Embodiment 2 of this invention. この発明の実施の形態３による半導体装置を示す平面図である。It is a top view which shows the semiconductor device by Embodiment 3 of this invention. この発明の実施の形態３による半導体装置の回路図である。It is a circuit diagram of the semiconductor device by Embodiment 3 of this invention. この発明の半導体装置を用いた実施の形態４のインバータ装置を示す図である。It is a figure which shows the inverter apparatus of Embodiment 4 using the semiconductor device of this invention. 図１１のインバータ装置を用いた回転電機の電気回路図である。It is an electric circuit diagram of the rotary electric machine using the inverter apparatus of FIG.

以下、この発明の実施の形態について、図面を参照して説明する。なお、各図中、同一符号は、同一あるいは相当部分を示すものとする。   Embodiments of the present invention will be described below with reference to the drawings. In addition, in each figure, the same code | symbol shall show the same or an equivalent part.

実施の形態１
以下この発明の実施の形態１を図に基づいて説明する。
図１は本発明の実施の形態１の半導体装置の断面構造を示す図、図２は本発明の実施の形態１の半導体装置の平面構造を示す図、図３は実施の形態１における内部リードとＭＯＳ−ＦＥＴ素子を示す図である。Embodiment 1
Embodiment 1 of the present invention will be described below with reference to the drawings.
1 is a diagram showing a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention, FIG. 2 is a diagram showing a planar structure of the semiconductor device according to the first embodiment of the present invention, and FIG. 3 is an internal lead in the first embodiment. It is a figure which shows a MOS-FET element.

図１〜図３において、実施の形態１における半導体装置１は、第１のリード１１の上にＭＯＳ−ＦＥＴ素子２１を配置し、ＭＯＳ−ＦＥＴ素子２１の下面電極２３を第１のはんだ５１を介して第１のリード１１に接合している。
ＭＯＳ−ＦＥＴ素子２１の上面電極２２には、第２のはんだ５２を介して内部リード３１の一方の端部が接合されており、もう一方の端部は、第３のはんだ５３を介して第２のリード１２の突起部６１と接合されている。第２のリード１２の突起部６１はダボ出し加工により第２のリード１２の一部を変形させて形成されている。1 to 3, in the semiconductor device 1 according to the first embodiment, the MOS-FET element 21 is arranged on the first lead 11, and the lower electrode 23 of the MOS-FET element 21 is attached to the first solder 51. To the first lead 11.
One end portion of the internal lead 31 is joined to the upper surface electrode 22 of the MOS-FET element 21 via the second solder 52, and the other end portion is joined to the second electrode via the third solder 53. 2 is joined to the protrusion 61 of the lead 12. The protrusion 61 of the second lead 12 is formed by deforming a part of the second lead 12 by doweling.

ここで第１のリード１１の下面と第２のリード１２の下面は同一平面内にあり、その平面には図示しない放熱グリスや放熱接着剤を介して図示しないヒートシンクが取り付けられる。
また、第１のはんだ５１の内部には第１の支持部材５４、第２のはんだ５２の内部には第２の支持部材５５、第３のはんだ５３の内部には第３の支持部材５６が配置されている。Here, the lower surface of the first lead 11 and the lower surface of the second lead 12 are in the same plane, and a heat sink (not shown) is attached to the plane via heat-dissipating grease or heat-dissipating adhesive (not shown).
The first solder 51 has a first support member 54, the second solder 52 has a second support member 55, and the third solder 53 has a third support member 56. Has been placed.

支持部材５４〜５６は、はんだが濡れて、かつ、はんだ溶融温度で溶融しない金属を材料とする球状部材で、たとえば球状のＮｉ粒子やＣｕ粒子などである。
ゲート電極２４とゲート用リード１３はアルミワイヤ７１で電気的に接続されている。The support members 54 to 56 are spherical members made of a metal which is wet with solder and does not melt at the solder melting temperature, and is, for example, spherical Ni particles or Cu particles.
The gate electrode 24 and the gate lead 13 are electrically connected by an aluminum wire 71.

これらの第１のリード１１、第２のリード１２、はんだ５１〜５３、ＭＯＳ−ＦＥＴ素子２１、内部リード３１、アルミワイヤ７１、ゲート用リード１３を封止樹脂４１で成型し、固定している。ただし、第１のリード１１の一部、第２のリード１２の一部、ゲート用リード１３の一部は封止樹脂４１の外部にあり、外部との電気接続が可能である。   These first lead 11, second lead 12, solders 51 to 53, MOS-FET element 21, internal lead 31, aluminum wire 71, and gate lead 13 are molded and fixed with a sealing resin 41. . However, a part of the first lead 11, a part of the second lead 12, and a part of the gate lead 13 are outside the sealing resin 41 and can be electrically connected to the outside.

なお、図１においては、放熱面となる第１のリード１１のＭＯＳ−ＦＥＴ素子２１接合部裏面、および第２のリード１２の内部リード３１接合部裏面は、封止樹脂４１から露出している構造としたが、これに限るものではなく、たとえば封止樹脂４１で覆われていても、あるいは図示しない伝熱性絶縁部材で覆ってもかまわない。   In FIG. 1, the back surface of the junction part of the MOS-FET element 21 of the first lead 11 and the back surface of the joint part of the internal lead 31 of the second lead 12 are exposed from the sealing resin 41. The structure is not limited to this. For example, the structure may be covered with the sealing resin 41 or may be covered with a heat conductive insulating member (not shown).

次に、内部リード３１と第２のリード１２の突起６１およびＭＯＳ−ＦＥＴ素子２１について説明する。
図３（ａ）は内部リード３１の側面図、図３（ｂ）は接合面から見た平面図を示す。内部リード３１は屈曲加工により第１の接合用平面３２と第２の接合用平面３３が設けられており、第１の接合用平面３２と第２の接合用平面３３は同一平面内にある。
また、第２の接合用平面３３の面内に貫通穴３４、非接合面に貫通穴３５が設けてある。Next, the internal lead 31 and the protrusion 61 of the second lead 12 and the MOS-FET element 21 will be described.
3A is a side view of the internal lead 31, and FIG. 3B is a plan view seen from the joint surface. The internal lead 31 is provided with a first bonding plane 32 and a second bonding plane 33 by bending, and the first bonding plane 32 and the second bonding plane 33 are in the same plane.
Further, a through hole 34 is provided in the plane of the second bonding plane 33, and a through hole 35 is provided in the non-joint plane.

また、図３（ｃ）に示すように、第２のリード１２の一部に設けた突起部６１の上面には、接合面６２が形成されており、図１、図２に示すように、内部リード３１の第１の接合用平面３２は接合面６２と概同形状となっている。
また、図３（ｄ）に示すように、ＭＯＳ−ＦＥＴ素子２１は表面に上面電極２２とゲート電極２４が設けられていて、かつ表面には保護膜２５が備えられている。
保護膜２５の開口形状は円形であり、図１、図２に示すように、内部リード３１の第２の接合用平面３３は、ＭＯＳ−ＦＥＴ素子２１の上面電極２２の開口電極形状に内接する形状となっている。Further, as shown in FIG. 3C, a bonding surface 62 is formed on the upper surface of the protrusion 61 provided on a part of the second lead 12, and as shown in FIGS. The first bonding plane 32 of the internal lead 31 has a shape substantially the same as the bonding surface 62.
Further, as shown in FIG. 3D, the MOS-FET element 21 is provided with a top electrode 22 and a gate electrode 24 on the surface, and a protective film 25 is provided on the surface.
The opening shape of the protective film 25 is circular, and as shown in FIGS. 1 and 2, the second bonding plane 33 of the internal lead 31 is inscribed in the opening electrode shape of the upper surface electrode 22 of the MOS-FET element 21. It has a shape.

なお、図３（ｂ）の内部リード３１の第２の接合用平面３３は概円形としたが、これに限らず図３（ｅ）のような四角形や、あるいはそれ以外の図示しない多角形、楕円、長円などでも構わず、その外形がＭＯＳ−ＦＥＴ素子２１の上面電極２２の形状に３箇所以上で内接する形であれば、セルフアライメントによる位置補正の効果を得ることができる。   Note that the second bonding plane 33 of the internal lead 31 in FIG. 3B has a substantially circular shape, but is not limited to this, and is not limited to a square shape as shown in FIG. An ellipse or an ellipse may be used. If the outer shape is inscribed in the shape of the upper surface electrode 22 of the MOS-FET element 21 at three or more locations, the effect of position correction by self-alignment can be obtained.

図４は実施の形態１における半導体装置のはんだ付け工程を説明する図である。
図４（ａ）は第１のリード１１にＭＯＳ−ＦＥＴ素子２１をはんだ付けした状態を示す。このときＭＯＳ−ＦＥＴ素子２１は実装装置の搭載位置のばらつきのため狙いの位置からずれていることがある。FIG. 4 is a diagram for explaining a soldering process of the semiconductor device according to the first embodiment.
FIG. 4A shows a state in which the MOS-FET element 21 is soldered to the first lead 11. At this time, the MOS-FET element 21 may be displaced from the target position due to variations in the mounting position of the mounting apparatus.

図４（ｂ）は、ＭＯＳ−ＦＥＴ素子２１の上面電極２２と、第２のリード１２の突起部６１にはんだペーストを塗布し、内部リード３１を搭載した状態を示す。
はんだペーストは支持部材を混合したはんだペーストで、第２のはんだ５２、第３のはんだ５３に同一のものを用い同一工程で供給される。FIG. 4B shows a state in which a solder paste is applied to the upper surface electrode 22 of the MOS-FET element 21 and the protrusion 61 of the second lead 12 and the internal lead 31 is mounted.
The solder paste is a solder paste in which a support member is mixed, and the same solder paste is used for the second solder 52 and the third solder 53 and is supplied in the same process.

このとき、内部リード３１は実装装置の搭載位置のばらつきのため狙いの位置からずれていることがある。また、はんだペーストの供給量もばらつくことがある。   At this time, the internal lead 31 may be displaced from the target position due to variations in the mounting position of the mounting apparatus. Also, the amount of solder paste supplied may vary.

次にリフロー工程ではんだが溶融すると図４（ｃ）に示すように、まず第３のはんだ５３の表面張力によるセルフアライメントで、第２のリードの突起部６１の上面接合面６２と内部リード３１の第１の接合用平面３２が合うように内部リード３１が移動する。
このとき、第３のはんだ５３に余剰なはんだがあると突起部６１の側面に流れ落ちるが、突起部の接合面６２上のはんだの外形は変わらないためセルフアライメント位置は保たれる。Next, when the solder is melted in the reflow process, as shown in FIG. 4C, first, the upper surface joint surface 62 of the protrusion portion 61 of the second lead 61 and the internal lead 31 are self-aligned by the surface tension of the third solder 53. The internal lead 31 moves so that the first bonding plane 32 is aligned.
At this time, if there is excess solder in the third solder 53, it flows down to the side surface of the protruding portion 61, but the external shape of the solder on the bonding surface 62 of the protruding portion does not change, so that the self-alignment position is maintained.

さらに、ＭＯＳ−ＦＥＴ素子２１の下面に位置する第１のはんだ５１も再溶融しており、第２のはんだ５２の表面張力によるセルフアライメントで、ＭＯＳ−ＦＥＴ素子２１の上面電極２２の外形に内部リード３１の第２の接合用平面３３が内接する位置になるようにＭＯＳ−ＦＥＴ素子２１が移動する。このとき第２のはんだ５２に余剰なはんだがあると貫通穴３４を通り、内部リード３１の上面に移動し、接合部のはんだ量が調整される。   Furthermore, the first solder 51 located on the lower surface of the MOS-FET element 21 is also remelted, and the self-alignment due to the surface tension of the second solder 52 causes the inner shape of the upper surface electrode 22 of the MOS-FET element 21 to be internal. The MOS-FET element 21 is moved so that the second bonding plane 33 of the lead 31 is inscribed. At this time, if there is excess solder in the second solder 52, it passes through the through hole 34 and moves to the upper surface of the internal lead 31, and the amount of solder at the joint is adjusted.

上記のセルフアライメントの際、第１のはんだ５１の内部に支持部材５４、第２のはんだ５２の内部に支持部材５５、および第３のはんだ５３の内部に支持部材５６があるため、内部リード３１およびＭＯＳ−ＦＥＴ素子２１は円滑に移動できるとともに、移動しても水平に保たれる。   During the above self-alignment, since the support member 54 is inside the first solder 51, the support member 55 is inside the second solder 52, and the support member 56 is inside the third solder 53, the internal lead 31. The MOS-FET element 21 can move smoothly and is kept horizontal even if it moves.

このあと、図示しない工程により、ゲート電極２４とゲート用リード１３をアルミワイヤ７１で接合するが、ＭＯＳ−ＦＥＴ素子２１が傾くことなく接合されているので安定したアルミワイヤ接合が得られる。その後、封止樹脂４１で成形することで半導体装置となる。   Thereafter, the gate electrode 24 and the gate lead 13 are joined by the aluminum wire 71 by a process (not shown). However, since the MOS-FET element 21 is joined without being inclined, a stable aluminum wire joining can be obtained. Thereafter, the semiconductor device is formed by molding with the sealing resin 41.

なお、この例では、金属粒子を混合したはんだペーストを供給するとしたが、支持部材および、はんだの供給方法はこれに限らず、たとえば支持部材を含有する板はんだを必要な形状だけ切り出したものを搭載してもよい。   In this example, the solder paste mixed with the metal particles is supplied. However, the support member and the method of supplying the solder are not limited to this. For example, a plate solder containing the support member is cut out only in a necessary shape. May be installed.

薄型化された半導体装置は温度変化すると封止樹脂とリードフレームの線膨張係数の差で図５に示すような変形が発生する。このような状態でも実施の形態１の半導体装置においては、内部リード３１の非接合部に貫通穴３５を設けて、この貫通穴３５にも封止樹脂４１が充填されるので、内部リード３１に対して封止樹脂４１がずれたり、剥離したりして、はんだクラックやＭＯＳ−ＦＥＴ素子のクラックが発生することを抑えることができる。   When the temperature of the thinned semiconductor device changes, the deformation as shown in FIG. 5 occurs due to the difference between the linear expansion coefficients of the sealing resin and the lead frame. Even in such a state, in the semiconductor device of the first embodiment, the through-hole 35 is provided in the non-joined portion of the internal lead 31 and the through-hole 35 is filled with the sealing resin 41. On the other hand, it is possible to suppress the occurrence of solder cracks and MOS-FET element cracks due to the sealing resin 41 being displaced or peeled off.

以上のように、この発明の実施の形態１の半導体装置１によれば、第１のはんだと第２のはんだの内部に支持部材を配置したことで、内部リードの接合時に第１のはんだと第２のはんだがともに溶融し、セルフアライメントにより内部リードおよびＭＯＳ−ＦＥＴ素子が移動する際、支持部材によりＭＯＳ−ＦＥＴ素子および内部リードが水平に保たれ、確実にセルフアライメントが実現できるので、第１のリード、第２のリードおよび、内部リードを必要最小の大きさに設計でき、半導体装置の小型化が可能となる。
また、セルフアライメントが実現できるため、高精度の実装装置は必要ない上、はんだ溶融時に内部リード、ＭＯＳ−ＦＥＴ素子の位置を保持する手段も必要なく、製造工程の簡略化が可能となる。
また、はんだ厚さが安定するので、はんだ流れによるＭＯＳ−ＦＥＴ素子上面電極と下面電極または上面電極とゲート電極のショートを防ぐことができる。As described above, according to the semiconductor device 1 of the first embodiment of the present invention, since the support member is disposed inside the first solder and the second solder, the first solder and When the second solder is melted together and the internal lead and the MOS-FET element are moved by self-alignment, the MOS-FET element and the internal lead are kept horizontal by the support member, and self-alignment can be reliably realized. The first lead, the second lead, and the internal lead can be designed to the minimum necessary size, and the semiconductor device can be miniaturized.
In addition, since self-alignment can be realized, a high-precision mounting apparatus is not required, and no means for holding the position of the internal lead and the MOS-FET element when the solder is melted is required, and the manufacturing process can be simplified.
Further, since the solder thickness is stabilized, it is possible to prevent a short circuit between the upper electrode and the lower electrode or the upper electrode and the gate electrode due to the solder flow.

また、内部リードの第１の接合用平面形状と第２のリードの突起上面形状を概同形状としたことで、はんだの表面張力により、第２のリードを基準として内部リードの位置がセルフアライメント効果により補正される。   In addition, the first lead planar shape of the internal lead and the top surface of the second lead protrusion are approximately the same, so that the position of the internal lead is self-aligned with respect to the second lead due to the surface tension of the solder. It is corrected by the effect.

また、内部リードの第２の接合用平面形状をＭＯＳ−ＦＥＴ素子の上面電極の開口形状の外形に概内接する形状としたことで、第２のはんだの表面張力により、内部リードとＭＯＳ−ＦＥＴ素子の位置がセルフアライメントにより補正される。   Further, the second planar shape for bonding of the internal lead is formed so as to be substantially inscribed in the outer shape of the opening shape of the upper surface electrode of the MOS-FET element. The position of the element is corrected by self-alignment.

このとき、すでに第２のリードを基準として内部リードの位置が決められているので内部リード位置に合わせるようにＭＯＳ−ＦＥＴ素子が移動し、第２のリード、内部リード、ＭＯＳ−ＦＥＴ素子の位置が補正される。   At this time, since the position of the internal lead has already been determined with reference to the second lead, the MOS-FET element moves to match the internal lead position, and the position of the second lead, internal lead, and MOS-FET element. Is corrected.

また、ＭＯＳ−ＦＥＴ素子上面電極の開口形状を円形としたことで、水平面内でＭＯＳ−ＦＥＴ素子と内部リードに角度ずれがあっても円滑にセルフアライメントされる。また、ＭＯＳ−ＦＥＴ素子と内部リードを角度つける配置に設計したとしても、長軸方向に左右対称の内部リードを用いることができ、内部リードのバランスを保つことができる。   In addition, since the opening shape of the upper surface electrode of the MOS-FET element is circular, even if there is an angle shift between the MOS-FET element and the internal lead in the horizontal plane, the self-alignment is smoothly performed. Even if the MOS-FET element and the internal lead are designed to be arranged at an angle, the internal leads symmetrical in the major axis direction can be used, and the balance of the internal leads can be maintained.

また、支持部材を球状金属としたことで、支持部材が転がりやすく、はんだ溶融時のセルフアライメントによる内部リードおよびＭＯＳ−ＦＥＴ素子の移動を円滑にする。
さらに、ＭＯＳ−ＦＥＴ素子との接触面が球面であるため、熱変形時に支持部材を起点としたＭＯＳ−ＦＥＴ素子のクラック発生を防ぐことができる。Further, since the supporting member is made of a spherical metal, the supporting member is easy to roll, and the internal lead and the MOS-FET element can be moved smoothly by self-alignment when the solder is melted.
Furthermore, since the contact surface with the MOS-FET element is a spherical surface, the occurrence of cracks in the MOS-FET element starting from the support member during thermal deformation can be prevented.

また、第３のはんだ内部にも支持部材を配置することで、第２のはんだと第３のはんだを球状金属を混合した同一のはんだペーストとすることができ、同一工程でのはんだ供給が可能となり、製造工程が簡略化できる。   In addition, by arranging a support member inside the third solder, the second solder and the third solder can be made into the same solder paste in which spherical metal is mixed, and solder can be supplied in the same process. Thus, the manufacturing process can be simplified.

また、ＭＯＳ−ＦＥＴ素子上面電極接合部分に対応する内部リードの第２の接合用平面部に、貫通穴を設けたことにより、セルフアライメントで内部リードとＭＯＳ−ＦＥＴ素子の位置が変化するときに余剰となるはんだや、供給量のばらつきによって余剰となるはんだを貫通穴を通して内部リードの第２の接合用平面の上面に逃がすことができ、ＭＯＳ−ＦＥＴ素子表面へのはんだ流れによるＭＯＳ−ＦＥＴ素子上面電極と下面電極のショートや、上面電極とゲート電極のショートを防ぐことができる。   Further, when the through-hole is provided in the second bonding plane portion of the internal lead corresponding to the MOS-FET element upper surface electrode bonding portion, the position of the internal lead and the MOS-FET element is changed by self-alignment. A surplus solder or a surplus solder due to a supply amount variation can be released to the upper surface of the second bonding plane of the internal lead through the through hole, and the MOS-FET element by the solder flow to the MOS-FET element surface A short circuit between the upper electrode and the lower electrode and a short circuit between the upper electrode and the gate electrode can be prevented.

また、内部リードの非接合部分に貫通穴を設けたことで、内部リードと封止樹脂の密着が向上するので、封止樹脂厚みを薄くしても、温度変化による半導体装置が変形しても内部リードと封止樹脂の剥離を防ぎ、熱変形時のはんだ、ＭＯＳ−ＦＥＴ素子への応力負荷を低減する。   Also, by providing a through hole in the non-joined part of the internal lead, the adhesion between the internal lead and the sealing resin is improved, so even if the thickness of the sealing resin is reduced or the semiconductor device is deformed due to temperature changes. Prevents peeling of internal leads and sealing resin and reduces stress load on solder and MOS-FET elements during thermal deformation.

実施の形態２．
この発明の実施の形態２を図に基づいて説明する。
図６は実施の形態２の半導体装置の断面構造を示す図、図７は実施の形態２の平面構造を示す図、図８は実施の形態２におけるＭＯＳ−ＦＥＴ素子を示す図である。
この実施の形態２の半導体装置２は、図６、図７に示すように、第２のはんだ５２の内部の支持部材を、金属ワイヤの超音波接合により形成した支持部材５７とし、また、第３のはんだ５３の内部には支持部材を設けていない点が異なる以外は、実施の形態１と同様の構造である。Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to the drawings.
6 is a diagram showing a cross-sectional structure of the semiconductor device of the second embodiment, FIG. 7 is a diagram showing a planar structure of the second embodiment, and FIG. 8 is a diagram showing a MOS-FET element in the second embodiment.
In the semiconductor device 2 of the second embodiment, as shown in FIGS. 6 and 7, the support member inside the second solder 52 is a support member 57 formed by ultrasonic bonding of a metal wire, 3 has the same structure as that of the first embodiment except that a support member is not provided inside the solder 53.

ＭＯＳ−ＦＥＴ素子２１の上面電極２２には、図８に示すように、金属ワイヤ５７を複数個所超音波接合することで支持部材を形成している。
また第２のリードの突起部６１の接合面の高さは、支持部材５６を設けていなくても、接合した内部リード３１が水平になるように設定している。As shown in FIG. 8, a support member is formed on the upper surface electrode 22 of the MOS-FET element 21 by ultrasonic bonding a plurality of metal wires 57.
Further, the height of the joint surface of the protrusion 61 of the second lead is set so that the joined internal lead 31 is horizontal even if the support member 56 is not provided.

はんだ付け工程においては実施の形態１と同様に、セルフアライメントにより第２のリード１２に設けた突起部６１を基準に、内部リード３１の位置、ＭＯＳ−ＦＥＴ素子２１の位置が補正される。このとき内部リード３１およびＭＯＳ−ＦＥＴ素子２１が移動しても、支持部材５４および支持部材５７があるため、内部リード３１およびＭＯＳ−ＦＥＴ素子２１は水平に保たれる。また支持部材５７がＭＯＳ−ＦＥＴ素子２１の上面電極２２に超音波接合された金属ワイヤであるので、内部リード３１が移動しても位置がずれることがなく、内部リード３１を安定して水平に保つ。   In the soldering process, as in the first embodiment, the position of the internal lead 31 and the position of the MOS-FET element 21 are corrected based on the protrusion 61 provided on the second lead 12 by self-alignment. Even if the internal lead 31 and the MOS-FET element 21 move at this time, the internal lead 31 and the MOS-FET element 21 are kept horizontal because of the support member 54 and the support member 57. Further, since the support member 57 is a metal wire ultrasonically bonded to the upper surface electrode 22 of the MOS-FET element 21, the position does not shift even if the internal lead 31 moves, and the internal lead 31 can be stably leveled. keep.

支持部材５７である金属ワイヤの材料は、たとえばアルミワイヤである。金属ワイヤの材料としてアルミを用いると、ＮｉやＣｕに比べてやわらかいので、熱応力によりＭＯＳ−ＦＥＴ素子２１がアルミワイヤに押し付けられても、アルミワイヤとの接触部を起点としたＭＯＳ−ＦＥＴ素子のクラックの発生を抑えることができる。   The material of the metal wire that is the support member 57 is, for example, an aluminum wire. When aluminum is used as the material of the metal wire, it is softer than Ni or Cu. Therefore, even if the MOS-FET element 21 is pressed against the aluminum wire due to thermal stress, the MOS-FET element starting from the contact portion with the aluminum wire Generation of cracks can be suppressed.

以上のように、この発明の実施の形態２の半導体装置２によれば、第２のはんだの内部に位置する支持部材を、金属ワイヤをＭＯＳ−ＦＥＴ素子上面電極に超音波接合したものとすることで、セルフアライメントにより内部リードに対してＭＯＳ−ＦＥＴ素子が移動しても、支持部材の位置は固定されているので、内部リードを安定して水平に保つことができる。   As described above, according to the semiconductor device 2 of the second embodiment of the present invention, the support member positioned inside the second solder is obtained by ultrasonically bonding the metal wire to the upper surface electrode of the MOS-FET element. Thus, even if the MOS-FET element moves with respect to the internal lead by self-alignment, the position of the support member is fixed, so that the internal lead can be kept stable and horizontal.

実施の形態３．
この発明の実施の形態３を図に基づいて説明する。
図９は本発明の実施の形態３の半導体装置３の平面構造を示す図、図１０は実施の形態３の半導体装置の回路図である。
図９において、第１のリード１１の上に第１のＭＯＳ−ＦＥＴ素子２１を配置し、第１のＭＯＳ−ＦＥＴ素子２１の下面電極２３を第１のはんだ５１を介して第１のリード１１と接合している。
第１のＭＯＳ−ＦＥＴ素子２１の上面電極２２には、第２のはんだ５２を介して内部リード３１の一端が接合されており、内部リード３１のもう一方の端部は、第３のはんだ５３を介して第２のリード１２に設けた突起部６１と接合されている。
ここで突起部６１は、第２のリード１２の一部にダボ出し加工により形成されたものであり、その上面は内部リード３１の第１の接合用平面３２と概同形状である。Embodiment 3 FIG.
Embodiment 3 of the present invention will be described with reference to the drawings.
FIG. 9 is a diagram showing a planar structure of the semiconductor device 3 according to the third embodiment of the present invention, and FIG. 10 is a circuit diagram of the semiconductor device according to the third embodiment.
In FIG. 9, the first MOS-FET element 21 is disposed on the first lead 11, and the lower electrode 23 of the first MOS-FET element 21 is connected to the first lead 11 via the first solder 51. It is joined with.
One end of the internal lead 31 is joined to the upper surface electrode 22 of the first MOS-FET element 21 via the second solder 52, and the other end of the internal lead 31 is connected to the third solder 53. It is joined to the protrusion 61 provided on the second lead 12 through the via.
Here, the protrusion 61 is formed on a part of the second lead 12 by doweling, and the upper surface thereof is substantially the same shape as the first bonding plane 32 of the internal lead 31.

また、第１のＭＯＳ−ＦＥＴ素子２１の上面電極２２は、保護膜２５により開口部が円形形状を形成し、内部リード３１の第２の接合用平面３３の外形は開口部に内接する形状となっている。ゲート電極２４とゲート用リード１３はアルミワイヤ７１で電気的に接続されている。   Further, the upper surface electrode 22 of the first MOS-FET element 21 has a circular opening formed by the protective film 25, and the outer shape of the second bonding plane 33 of the internal lead 31 is inscribed in the opening. It has become. The gate electrode 24 and the gate lead 13 are electrically connected by an aluminum wire 71.

さらに、第２のリード１２の上に第２のＭＯＳ−ＦＥＴ素子２６を配置し、第２のＭＯＳ−ＦＥＴ素子２６の下面電極を第１のはんだ５１を介して第２のリード１２と接合している。第２のＭＯＳ−ＦＥＴ素子２６の上面電極には、第２のはんだ５２を介して第２の内部リード３６の一端が接合されており、第２の内部リード３６のもう一方の端部は、第３のはんだ５３を介して第３のリード１５に設けた突起部６３と接合されている。
ここで、突起部６３は第３のリード１５の一部にダボ出し加工により形成されたものであり、その上面は内部リード３６の第１の接合用平面と概同形状である。Furthermore, the second MOS-FET element 26 is disposed on the second lead 12, and the lower electrode of the second MOS-FET element 26 is joined to the second lead 12 via the first solder 51. ing. One end of the second internal lead 36 is joined to the upper surface electrode of the second MOS-FET element 26 via the second solder 52, and the other end of the second internal lead 36 is It is joined to a protrusion 63 provided on the third lead 15 through a third solder 53.
Here, the protruding portion 63 is formed on a part of the third lead 15 by doweling, and the upper surface thereof is substantially the same shape as the first bonding plane of the internal lead 36.

また、第２のＭＯＳ−ＦＥＴ素子２６の上面電極は、保護膜３０により開口部が円形形状を形成し、内部リード３６の第２の接合用平面の外形は開口部に内接する形状となっている。
ゲート電極２９とゲート用リード１４はアルミワイヤ７２で電気的に接続されている。Further, the upper electrode of the second MOS-FET element 26 has a circular opening formed by the protective film 30, and the outer shape of the second bonding plane of the internal lead 36 is inscribed in the opening. Yes.
The gate electrode 29 and the gate lead 14 are electrically connected by an aluminum wire 72.

これらの第１〜第３のリード１１、１２、１５、第１〜第３のはんだ５１〜５３、ＭＯＳ−ＦＥＴ素子２１、２６、内部リード３１、３６、アルミワイヤ７１、７２、ゲート用リード１３、１４を封止樹脂４１で一体に成型、固定している。
ただし、第１〜第３のリード１１、１２、１５、ゲート用リード１３、１４の一部は、封止樹脂４１の外部にあり、外部との電気接続が可能である。これにより、インバータ回路の上下アームを一体とした半導体装置を構成している。上下アーム一体の半導体装置の回路図を図１０に示す。These first to third leads 11, 12 and 15, first to third solders 51 to 53, MOS-FET elements 21 and 26, internal leads 31 and 36, aluminum wires 71 and 72, gate lead 13 , 14 are molded and fixed integrally with a sealing resin 41.
However, some of the first to third leads 11, 12, 15 and the gate leads 13, 14 are outside the sealing resin 41 and can be electrically connected to the outside. Thus, a semiconductor device in which the upper and lower arms of the inverter circuit are integrated is configured. A circuit diagram of a semiconductor device integrated with upper and lower arms is shown in FIG.

図９においても、実施の形態１および実施の形態２で説明したものと同様に、第１のはんだ５１、第２のはんだ５２、および第３のはんだ５３の内部にはそれぞれ、第１の支持部材、第２の支持部材、第３の支持部材が設けられている。   Also in FIG. 9, the first support 51, the second solder 52, and the third solder 53 are respectively provided with a first support in the same manner as described in the first and second embodiments. A member, a second support member, and a third support member are provided.

図９に示す実施の形態３の半導体装置３のはんだ付け工程においては、２つのＭＯＳ−ＦＥＴ素子の実装の後、２つのＭＯＳ−ＦＥＴ素子上面電極へのはんだ供給、２つの突起面へのはんだ供給、２つの内部リードの搭載、をそれぞれ同一工程で実施し、リフロー工程によりはんだを溶融する。   In the soldering process of the semiconductor device 3 according to the third embodiment shown in FIG. 9, after the mounting of the two MOS-FET elements, the solder is supplied to the upper electrodes of the two MOS-FET elements, and the solder is applied to the two projecting surfaces. Supplying and mounting of two internal leads are performed in the same process, and the solder is melted by a reflow process.

このようにすれば、２組の内部リード、ＭＯＳ−ＦＥＴ素子を含む半導体装置であっても、実施の形態１で説明したようにセルフアライメントによりそれぞれの内部リード、ＭＯＳ−ＦＥＴ素子の位置が補正される。   In this manner, even in a semiconductor device including two sets of internal leads and MOS-FET elements, the positions of the internal leads and MOS-FET elements are corrected by self-alignment as described in the first embodiment. Is done.

図９、図１０において、上アーム１１１を構成する第１のＭＯＳ−ＦＥＴ素子２１と第１の内部リード３１の結合体と、下アーム１１２を構成する第２のＭＯＳ−ＦＥＴ素子２６と第２の内部リード３６の結合体は逆向きの配置である。
このようにすることで上アーム１１１と下アーム１１２の距離が小さくでき、一対の上下アームを内蔵した半導体装置を小型化できる。9 and 10, a combination of the first MOS-FET element 21 and the first internal lead 31 constituting the upper arm 111, the second MOS-FET element 26 constituting the lower arm 112, and the second The combination of the inner leads 36 is in the reverse orientation.
By doing so, the distance between the upper arm 111 and the lower arm 112 can be reduced, and the semiconductor device incorporating the pair of upper and lower arms can be reduced in size.

以上のように、この発明の実施の形態３によれば、複数の半導体素子を用いる電機機器において、半導体装置の外部の配線を省略することができるので、電機機器を小型化できる。   As described above, according to the third embodiment of the present invention, in the electrical equipment using a plurality of semiconductor elements, wiring outside the semiconductor device can be omitted, so that the electrical equipment can be downsized.

実施の形態４
図１１は本発明の実施の形態４によるインバータ装置１０２を示す平面図、図１２は図１１のインバータ装置を用いた回転電機１００の電気回路図である。
図１１において、半導体装置１の正極端子と負極端子は、封止樹脂によって形成された概長方形の対向面から突出するよう配置されている。また、半数の半導体装置は鏡面対称構造となっている。Embodiment 4
11 is a plan view showing an inverter device 102 according to Embodiment 4 of the present invention, and FIG. 12 is an electric circuit diagram of a rotating electrical machine 100 using the inverter device of FIG.
In FIG. 11, the positive electrode terminal and the negative electrode terminal of the semiconductor device 1 are arranged so as to protrude from a substantially rectangular facing surface formed of a sealing resin. Half of the semiconductor devices have a mirror symmetry structure.

図１１の半導体装置においても、実施の形態１および実施の形態２で説明したものと同様に、図示しない第１のはんだ５１、第２のはんだ５２および第３のはんだ５３の内部にはそれぞれ、第１の支持部材、第２の支持部材、第３の支持部材が設けられ、小型に設計されている。   In the semiconductor device of FIG. 11 as well, as described in the first and second embodiments, the first solder 51, the second solder 52, and the third solder 53 (not shown) A first support member, a second support member, and a third support member are provided and are designed to be small.

半導体装置１は同心円上に配置されインバータ装置１０２を構成している。
ここで半導体装置１の正極端子は、内周に配置された正電圧供給部品８１に電気的に接合されている。正電圧供給部品８１は、図示しない配線で蓄電手段の正極に接続される。The semiconductor device 1 is arranged concentrically and constitutes an inverter device 102.
Here, the positive terminal of the semiconductor device 1 is electrically joined to a positive voltage supply component 81 disposed on the inner periphery. The positive voltage supply component 81 is connected to the positive electrode of the power storage means by a wiring (not shown).

半導体装置１の負極端子は、外周上に配置された負電圧供給部品８２に電気的に接合されている。負電圧供給部品８２は、図示しない配線で蓄電手段の負極に接続される。
電気的接合はたとえば溶接やはんだ付けなどでよい。また、各相の電力出力端子８３は、図示しない配線で回転電機のコイルに接続されている。The negative terminal of the semiconductor device 1 is electrically joined to a negative voltage supply component 82 disposed on the outer periphery. The negative voltage supply component 82 is connected to the negative electrode of the power storage means by a wiring (not shown).
The electrical connection may be, for example, welding or soldering. Further, the power output terminals 83 of each phase are connected to the coil of the rotating electrical machine by wiring not shown.

このように構成することで、半導体装置１と正電圧供給部品８１と負電圧供給部品８２を概同一平面上に配置できるので、インバータ装置１０２の薄型化が可能である。
また、実施の形態４のインバータ装置を内蔵する回転電機を構成することで、インバータ一体型の回転電機を薄型化できる。With this configuration, the semiconductor device 1, the positive voltage supply component 81, and the negative voltage supply component 82 can be arranged on substantially the same plane, so that the inverter device 102 can be thinned.
Further, by configuring the rotating electrical machine incorporating the inverter device of the fourth embodiment, the inverter-integrated rotating electrical machine can be thinned.

なお、図１１では、半導体装置の数を６個（６相）としたが、これに限らない。
また、正電圧供給部品８１は６角形に限らず、多角形や円形でも構わない。
さらに図１１では正電圧供給部品８１を内周側に配置したが、負電圧供給部品８２を内周側に配置しても構わない。この場合、半導体装置１の負電極が内側に向くように半導体装置を配置すればよい。In FIG. 11, the number of semiconductor devices is six (six phases), but is not limited thereto.
Further, the positive voltage supply component 81 is not limited to a hexagon, and may be a polygon or a circle.
Further, in FIG. 11, the positive voltage supply component 81 is disposed on the inner peripheral side, but the negative voltage supply component 82 may be disposed on the inner peripheral side. In this case, the semiconductor device may be arranged so that the negative electrode of the semiconductor device 1 faces inward.

図１２に、図１１で示したインバータ装置１０２を内蔵する回転電機１００の電気回路図を示す。図１２において、回転電機１００は、制御手段１０１とインバータ装置１０２と固定コイル１０３、１０４と可動コイル１０５からなる。   FIG. 12 shows an electric circuit diagram of the rotating electrical machine 100 incorporating the inverter device 102 shown in FIG. In FIG. 12, the rotating electrical machine 100 includes a control unit 101, an inverter device 102, fixed coils 103 and 104, and a movable coil 105.

固定コイル１０３および固定コイル１０４の各相には、ＭＯＳ−ＦＥＴ素子からなる上アーム部１１１と下アーム部１１２を介して蓄電手段１２０と接続されており、これらのＭＯＳ−ＦＥＴ素子に対して制御手段１０１からゲート信号を送ることによって、各ＭＯＳ−ＦＥＴ素子をON／OFF制御し、固定コイル１０３、１０４の各相に流れる電流を切り替える。この回転電機１００は制御手段１０１からの信号により、可動コイル１０５を回転駆動することも、可動コイル１０５の回転から発電することも可能である。   Each phase of the fixed coil 103 and the fixed coil 104 is connected to the power storage means 120 via an upper arm portion 111 and a lower arm portion 112 made of MOS-FET elements, and controls these MOS-FET elements. By sending a gate signal from the means 101, each MOS-FET element is ON / OFF controlled, and the current flowing through each phase of the fixed coils 103, 104 is switched. The rotating electrical machine 100 can drive the movable coil 105 in response to a signal from the control means 101 or can generate electric power from the rotation of the movable coil 105.

以上のように、この発明の実施の形態４によれば、正電圧接続端子と、負電圧接続端子および電圧出力端子を半導体装置の対向する面に配置することで、半導体装置を同心円状に配置してインバータ装置を構成しても、正電圧接続端子と、負電圧接続端子を概同一平面に配置できるので、インバータ装置を内蔵する回転機械を薄型化できる。   As described above, according to the fourth embodiment of the present invention, the positive voltage connection terminal, the negative voltage connection terminal, and the voltage output terminal are arranged on the opposing surfaces of the semiconductor device, whereby the semiconductor device is arranged concentrically. Even if the inverter device is configured, the positive voltage connection terminal and the negative voltage connection terminal can be arranged on substantially the same plane, so that the rotating machine incorporating the inverter device can be thinned.

さらに、上記インバータ装置を構成するにあたり、半導体装置の半数を鏡面対称構造とすることで、外周側接続長を短縮でき、配線の簡素化、電気抵抗の低減が可能となる。   Further, when configuring the inverter device, half of the semiconductor devices have a mirror-symmetric structure, whereby the outer peripheral connection length can be shortened, wiring can be simplified, and electrical resistance can be reduced.

この発明は、ＭＯＳ−ＦＥＴ素子を用いた樹脂封止型半導体装置を用いて、パワー用インバータ装置を構成するのに好適なものである。   The present invention is suitable for constituting a power inverter device using a resin-encapsulated semiconductor device using a MOS-FET element.

１〜３ 半導体装置、１１ 第１のリード、 １２ 第２のリード、
１３、１４ ゲート用リード、１５ 第３のリード、
２１、２６ ＭＯＳ−ＦＥＴ素子、２２ 上面電極、２３ 下面電極、
２４、２９ ゲート電極、２５、３０ 保護膜、３１、３６ 内部リード
３２ 第１の接合用平面、３３ 第２の接合用平面、３４ 貫通穴、
３５ 貫通穴、４１ 封止樹脂、５１〜５３ はんだ、
５４〜５７ 支持部材、 ６１、６３ 突起部、
６２ 突起接合面、７１、７２ アルミワイヤ、
８１ 正電圧供給部品、 ８２ 負電圧供給部品、８３ 電力出力端子、
１００ 回転電機、１０１ 制御手段、１０２ インバータ装置、
１０３、１０４固定コイル、 １０５ 可動コイル、
１１１ 上アーム、１１２ 下アーム、１２０ 蓄電手段。1-3, semiconductor device, 11 first lead, 12 second lead,
13, 14 Gate lead, 15 Third lead,
21, 26 MOS-FET element, 22 upper surface electrode, 23 lower surface electrode,
24, 29 Gate electrode, 25, 30 Protective film, 31, 36 Internal lead 32 First bonding plane, 33 Second bonding plane, 34 Through hole,
35 through hole, 41 sealing resin, 51-53 solder,
54-57 support member, 61, 63 protrusion,
62 projection joint surface, 71, 72 aluminum wire,
81 positive voltage supply component, 82 negative voltage supply component, 83 power output terminal,
100 rotating electrical machine, 101 control means, 102 inverter device,
103, 104 fixed coil, 105 movable coil,
111 Upper arm, 112 Lower arm, 120 Power storage means.

Claims (15)

第１のリードと、一部を変形させて突起部を設けた第２のリードと、前記第１のリードに下面電極が電気的に接合されたＭＯＳ−ＦＥＴと、前記ＭＯＳ−ＦＥＴの上面電極と前記第２のリードとの間に電流を通電する内部リードと、これらを電気的に接合するはんだ材、および、これらの相対位置を固定する封止樹脂からなり、
前記第１のリードと前記第２のリードは下面が同一平面上にあり、かつ、前記内部リードは、前記ＭＯＳ−ＦＥＴとの接合面と、前記第２のリードとの接合面が同一平面であり、
前記第１のリードと前記ＭＯＳ−ＦＥＴの下面電極とが第１のはんだで接合され、
前記ＭＯＳ−ＦＥＴの上面電極と前記内部リードとが第２のはんだで接合され、
前記内部リードと前記第２のリードの突起部とが第３のはんだで接合され、
前記第1のリード、第２のリード、ＭＯＳ−ＦＥＴおよび内部リードが前記封止樹脂により一体に成形されている半導体装置であって、
少なくとも前記第１のはんだの内部と前記第２のはんだの内部に位置する支持部材を設け、前記内部リードの非接合部分に貫通穴を設けたことを特徴とする半導体装置。 A first lead, a second lead that is partially deformed to provide a protrusion, a MOS-FET having a bottom electrode electrically joined to the first lead, and a top electrode of the MOS-FET And an internal lead that conducts current between the second lead, a solder material that electrically joins these, and a sealing resin that fixes their relative positions,
The first lead and the second lead have bottom surfaces on the same plane, and the internal lead has a joint surface with the MOS-FET and a joint surface with the second lead on the same plane. Yes,
The first lead and the lower electrode of the MOS-FET are joined with a first solder,
The top electrode of the MOS-FET and the internal lead are joined with a second solder,
The internal lead and the protrusion of the second lead are joined with a third solder,
A semiconductor device in which the first lead, the second lead, the MOS-FET, and the internal lead are integrally formed of the sealing resin,
A semiconductor device comprising: a support member positioned at least in the first solder and in the second solder; and a through hole provided in a non-joined portion of the internal lead . 前記内部リードの第１の端部に屈曲により区切られた第１の接合用平面を設け、前記第２のリードに設けた突起部がダボ出し加工により形成された突起部であり、かつ前記第１の接合用平面形状と前記突起部の上面形状が実質的に同形状であることを特徴とする請求項１に記載の半導体装置。   The first end of the internal lead is provided with a first joining plane divided by bending, and the protrusion provided on the second lead is a protrusion formed by doweling, and the first 2. The semiconductor device according to claim 1, wherein the bonding planar shape of 1 and the upper surface shape of the protrusion are substantially the same shape. 前記内部リードの第２の端部に屈曲により区切られた第２の接合用水平面を設け、この第２の接合用平面が、前記ＭＯＳ−ＦＥＴの上面電極接合部分に形成された開口電極形状の外形に実質的に内接することを特徴とする請求項１に記載の半導体装置。   A second bonding horizontal plane that is divided by bending is provided at the second end portion of the internal lead, and the second bonding plane has an opening electrode shape formed in the upper surface electrode bonding portion of the MOS-FET. The semiconductor device according to claim 1, wherein the semiconductor device is substantially inscribed in an outer shape. 前記ＭＯＳ−ＦＥＴの上面電極接合部分の開口電極形状が円形であることを特徴とする請求項３に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the shape of the opening electrode at the upper electrode joint portion of the MOS-FET is circular. 前記支持部材が球状金属であることを特徴とする請求項１〜請求項４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the support member is a spherical metal. 前記第３のはんだの内部に位置する支持部材を設けたことを特徴とする請求項１〜請求項４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, further comprising a support member positioned inside the third solder. 6. 第１のリードと、一部を変形させて突起部を設けた第２のリードと、前記第１のリードに下面電極が電気的に接合されたＭＯＳ−ＦＥＴと、前記ＭＯＳ−ＦＥＴの上面電極と前記第２のリードとの間に電流を通電する内部リードと、これらを電気的に接合するはんだ材、および、これらの相対位置を固定する封止樹脂からなり、
前記第１のリードと前記第２のリードは下面が同一平面上にあり、かつ、前記内部リードは、前記ＭＯＳ−ＦＥＴとの接合面と、前記第２のリードとの接合面が同一平面であり、
前記第１のリードと前記ＭＯＳ−ＦＥＴの下面電極とが第１のはんだで接合され、
前記ＭＯＳ−ＦＥＴの上面電極と前記内部リードとが第２のはんだで接合され、
前記内部リードと前記第２のリードの突起部とが第３のはんだで接合され、
前記第1のリード、第２のリード、ＭＯＳ−ＦＥＴおよび内部リードが前記封止樹脂により一体に成形されている半導体装置であって、
少なくとも前記第１のはんだの内部と前記第２のはんだの内部に位置する支持部材を設け、前記第２のはんだの内部に位置する支持部材が、金属ワイヤを前記ＭＯＳ−ＦＥＴ上面電極に超音波接合することで形成されていることを特徴とする半導体装置。 A first lead, a second lead that is partially deformed to provide a protrusion, a MOS-FET having a bottom electrode electrically joined to the first lead, and a top electrode of the MOS-FET And an internal lead that conducts current between the second lead, a solder material that electrically joins these, and a sealing resin that fixes their relative positions,
The first lead and the second lead have bottom surfaces on the same plane, and the internal lead has a joint surface with the MOS-FET and a joint surface with the second lead on the same plane. Yes,
The first lead and the lower electrode of the MOS-FET are joined with a first solder,
The top electrode of the MOS-FET and the internal lead are joined with a second solder,
The internal lead and the protrusion of the second lead are joined with a third solder,
A semiconductor device in which the first lead, the second lead, the MOS-FET, and the internal lead are integrally formed of the sealing resin,
At least a support member positioned inside the first solder and the second solder is provided, and the support member positioned inside the second solder ultrasonically transmits a metal wire to the upper surface electrode of the MOS-FET. A semiconductor device formed by bonding. 前記内部リードの第１の端部に屈曲により区切られた第１の接合用平面を設け、前記第２のリードに設けた突起部がダボ出し加工により形成された突起部であり、かつ前記第１の接合用平面形状と前記突起部の上面形状が実質的に同形状であることを特徴とする請求項７に記載の半導体装置。 The first end of the internal lead is provided with a first joining plane divided by bending, and the protrusion provided on the second lead is a protrusion formed by doweling, and the first 8. The semiconductor device according to claim 7 , wherein the planar shape for bonding and the top surface shape of the protrusion are substantially the same . 前記内部リードの第２の端部に屈曲により区切られた第２の接合用水平面を設け、この第２の接合用平面が、前記ＭＯＳ−ＦＥＴの上面電極接合部分に形成された開口電極形状の外形に実質的に内接することを特徴とする請求項７に記載の半導体装置。A second bonding horizontal plane that is divided by bending is provided at the second end portion of the internal lead, and the second bonding plane has an opening electrode shape formed in the upper surface electrode bonding portion of the MOS-FET. The semiconductor device according to claim 7, wherein the semiconductor device is substantially inscribed in an outer shape. 前記ＭＯＳ−ＦＥＴの上面電極接合部分の開口電極形状が円形であることを特徴とする請求項７に記載の半導体装置。8. The semiconductor device according to claim 7, wherein the shape of the opening electrode at the upper surface electrode junction portion of the MOS-FET is circular. 第１のリードと、一部を変形させて突起部を設けた第２のリードと、前記第１のリードに下面電極が電気的に接合されたＭＯＳ−ＦＥＴと、前記ＭＯＳ−ＦＥＴの上面電極と前記第２のリードとの間に電流を通電する内部リードと、これらを電気的に接合するはんだ材、および、これらの相対位置を固定する封止樹脂からなり、
前記第１のリードと前記第２のリードは下面が同一平面上にあり、かつ、前記内部リードは、前記ＭＯＳ−ＦＥＴとの接合面と、前記第２のリードとの接合面が同一平面であり、
前記第１のリードと前記ＭＯＳ−ＦＥＴの下面電極とが第１のはんだで接合され、
前記ＭＯＳ−ＦＥＴの上面電極と前記内部リードとが第２のはんだで接合され、
前記内部リードと前記第２のリードの突起部とが第３のはんだで接合され、
前記第1のリード、第２のリード、ＭＯＳ−ＦＥＴおよび内部リードが前記封止樹脂により一体に成形されている半導体装置であって、
少なくとも前記第１のはんだの内部と前記第２のはんだの内部に位置する支持部材を設け、前記内部リードの第２の端部に屈曲により区切られた第２の接合用水平面を設け、この第２の接合用平面が、前記ＭＯＳ−ＦＥＴの上面電極接合部分に形成された開口電極形状の外形に実質的に内接するようにし、
前記内部リードの第２の接合用平面部に貫通穴を設けたことを特徴とする半導体装置。 A first lead, a second lead that is partially deformed to provide a protrusion, a MOS-FET having a bottom electrode electrically joined to the first lead, and a top electrode of the MOS-FET And an internal lead that conducts current between the second lead, a solder material that electrically joins these, and a sealing resin that fixes their relative positions,
The first lead and the second lead have bottom surfaces on the same plane, and the internal lead has a joint surface with the MOS-FET and a joint surface with the second lead on the same plane. Yes,
The first lead and the lower electrode of the MOS-FET are joined with a first solder,
The top electrode of the MOS-FET and the internal lead are joined with a second solder,
The internal lead and the protrusion of the second lead are joined with a third solder,
A semiconductor device in which the first lead, the second lead, the MOS-FET, and the internal lead are integrally formed of the sealing resin,
A support member positioned at least in the first solder and in the second solder is provided, and a second joining horizontal plane that is divided by bending is provided at the second end of the internal lead. 2 bonding planes are substantially inscribed in the outer shape of the opening electrode formed in the upper surface electrode bonding portion of the MOS-FET,
A semiconductor device, wherein a through-hole is provided in the second bonding plane portion of the internal lead. 第１のリードと、一部を変形させて突起部を設けた第２のリードと、前記第１のリードに下面電極が電気的に接合されたＭＯＳ−ＦＥＴと、前記ＭＯＳ−ＦＥＴの上面電極と前記第２のリードとの間に電流を通電する内部リードと、これらを電気的に接合するはんだ材、および、これらの相対位置を固定する封止樹脂からなり、
前記第１のリードと前記第２のリードは下面が同一平面上にあり、かつ、前記内部リードは、前記ＭＯＳ−ＦＥＴとの接合面と、前記第２のリードとの接合面が同一平面であり、
前記第１のリードと前記ＭＯＳ−ＦＥＴの下面電極とが第１のはんだで接合され、
前記ＭＯＳ−ＦＥＴの上面電極と前記内部リードとが第２のはんだで接合され、
前記内部リードと前記第２のリードの突起部とが第３のはんだで接合され、
前記第1のリード、第２のリード、ＭＯＳ−ＦＥＴおよび内部リードが前記封止樹脂により一体に成形されている半導体装置であって、
少なくとも前記第１のはんだの内部と前記第２のはんだの内部に位置する支持部材を設け、少なくとも２組のＭＯＳ−ＦＥＴと内部リードを用いて、第１のリード上に第１のＭＯＳ−ＦＥＴを配置して、第１のＭＯＳ−ＦＥＴの下面電極と第１のリードを電気的に接続し、第１のＭＯＳ−ＦＥＴの上面電極と第２のリードを第１の内部リードを介して電気的に接続し、第２のリード上に第２のＭＯＳ−ＦＥＴを配置して、第２のＭＯＳ−ＦＥＴの下面電極と第２のリードを電気的に接続し、第２のＭＯＳ−ＦＥＴの上面電極と第３のリードを第２の内部リードを介して電気的に接続し、これらを一体の封止樹脂で成形したことを特徴とする記載の半導体装置。 A first lead, a second lead that is partially deformed to provide a protrusion, a MOS-FET having a bottom electrode electrically joined to the first lead, and a top electrode of the MOS-FET And an internal lead that conducts current between the second lead, a solder material that electrically joins these, and a sealing resin that fixes their relative positions,
The first lead and the second lead have bottom surfaces on the same plane, and the internal lead has a joint surface with the MOS-FET and a joint surface with the second lead on the same plane. Yes,
The first lead and the lower electrode of the MOS-FET are joined with a first solder,
The top electrode of the MOS-FET and the internal lead are joined with a second solder,
The internal lead and the protrusion of the second lead are joined with a third solder,
A semiconductor device in which the first lead, the second lead, the MOS-FET, and the internal lead are integrally formed of the sealing resin,
A support member positioned at least inside the first solder and inside the second solder is provided, and the first MOS-FET is formed on the first lead by using at least two sets of MOS-FETs and internal leads. To electrically connect the lower surface electrode of the first MOS-FET and the first lead, and electrically connect the upper surface electrode of the first MOS-FET and the second lead via the first internal lead. The second MOS-FET is disposed on the second lead, the lower electrode of the second MOS-FET and the second lead are electrically connected, and the second MOS-FET The semiconductor device according to claim 1, wherein the upper surface electrode and the third lead are electrically connected via the second internal lead, and these are molded with an integral sealing resin. 前記第１のリードと前記第３のリードが前記封止樹脂の対向する面から樹脂外に突出していることを特徴とする請求項１２に記載の半導体装置。 The semiconductor device according to claim 12 , wherein the first lead and the third lead protrude outside the resin from the opposing surfaces of the sealing resin. 請求項１３に記載の半導体装置を複数個、同一平面上かつ同心円上に配置し、内周側の同一平面上に配置した電力供給部品ですべての半導体装置の正極または、すべての半導体装置の負極を結合することを特徴とするインバータ装置。 A plurality of the semiconductor devices according to claim 13 are arranged on the same plane and concentrically, and are power supply components arranged on the same plane on the inner peripheral side, or positive electrodes of all semiconductor devices or negative electrodes of all semiconductor devices. An inverter device characterized by coupling. 半導体装置の半数を鏡面対称構造とし、同一平面上に配置した電力供給部品で、すくなくとも一組の隣り合う半導体装置の外周側の電極を結合したことを特徴とする請求項１４に記載のインバータ装置。 15. The inverter device according to claim 14 , wherein half of the semiconductor devices have a mirror-symmetric structure, and at least one set of electrodes on the outer peripheral side of adjacent semiconductor devices are coupled by power supply components arranged on the same plane. .
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JP2003133497A (en) * 2001-10-29 2003-05-09 Toshiba Components Co Ltd Thin semiconductor device
JP2006287064A (en) * 2005-04-01 2006-10-19 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
JP2010171181A (en) * 2009-01-22 2010-08-05 Renesas Technology Corp Semiconductor device

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JP2003133497A (en) * 2001-10-29 2003-05-09 Toshiba Components Co Ltd Thin semiconductor device
JP2006287064A (en) * 2005-04-01 2006-10-19 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
JP2010171181A (en) * 2009-01-22 2010-08-05 Renesas Technology Corp Semiconductor device

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