JP5621185B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device formed of a wide gap semiconductor such as silicon carbide, gallium nitride, or diamond, and the semiconductor device.

Conventionally, in order to prevent the surface of the SiC substrate from being roughened when the conductive layer is selectively formed by performing a heat treatment on the SiC substrate, the surface of the SiC substrate into which impurity ions are implanted is dense, and A manufacturing method is known in which heat treatment is performed after coating with a heat-resistant material (hereinafter referred to as a cap layer) having a thermal expansion coefficient equivalent to that of an SiC substrate, and the cap layer is removed after the heat treatment is completed (see Non-Patent Document 1). ).
Y. Negoro et al., Materials Science Forum Vols. 457-460 (2004) pp. 933-936

  When the inventors of the present invention heat-treat a substrate formed of a wide gap semiconductor such as SiC by the above-described manufacturing method, a defect occurs in which the substrate is crushed during the heat treatment. It has been found that the value increases as the thickness of the substrate decreases and the thickness of the substrate decreases. For this reason, the inventors have considered that when a semiconductor device formed of a wide gap semiconductor such as SiC is manufactured using the above manufacturing method, the yield may be reduced.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to provide a semiconductor device manufacturing method and a semiconductor device capable of suppressing a decrease in yield when manufacturing a semiconductor device using a wide gap semiconductor. is there.

  In the method for manufacturing a semiconductor device according to the present invention, a first coating layer is formed on a surface of a semiconductor substrate, and a second coating layer having an internal configuration different from the internal configuration of the first coating layer in a part of the first coating layer. The semiconductor substrate on which the first coating layer and the second coating layer are formed is heat-treated to activate the impurity ions, and the first coating layer and the second coating layer are formed from the surface of the semiconductor substrate after the heat treatment. Remove. The semiconductor device according to the present invention has a first coating layer formed on the surface of the semiconductor substrate including the element region, and an internal configuration different from the internal configuration of the first coating layer formed on the surface of the first coating layer. A second coating layer.

  According to the semiconductor device manufacturing method and the semiconductor device of the present invention, it is possible to suppress a decrease in yield when manufacturing a semiconductor device using a wide gap semiconductor.

  Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Note that the drawings referred to below are schematic, and it should be noted that the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. That is, specific thicknesses and plane dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings. The present invention is applicable to all large crystal substrates (diameter 5 cm or more) of all crystal systems such as 4H, 6H, 3C, and 15R (H means hexagonal crystal, C means cubic crystal, and R means rhombohedral crystal). However, in the embodiment, for the sake of convenience, the substrate will be described as a 4H—SiC (0001) substrate having a diameter of 50 mm. Unless otherwise specified, a substrate having an epitaxial layer or other film or electrode formed on the surface of the SiC substrate is referred to as “SiC substrate” or simply “substrate”. Although this embodiment relates to a SiC substrate, the present invention is not limited to a SiC substrate, and crushing occurs when an activation heat treatment is performed with a cap layer at a temperature of 1300 ° C. or higher. It can be applied to all wide gap semiconductors. Specifically, the present invention can be applied to activation heat treatment when manufacturing a semiconductor device formed of a gallium nitride substrate, a zinc oxide substrate, or a diamond substrate having a diameter of 50 mm or more.

[What are continuous layers and discontinuous layers?]
In this specification, the term “continuous layer” means a layer in which lattice bonds are uniformly arranged in a specific direction when the continuous layer is formed of a metal or a semiconductor. In the case where it is formed by, for example, it means a layer in which the internal structure is in a uniform state. In this specification, the term “discontinuous layer” refers to a layer in which lattice bonds are not arranged uniformly in a specific direction or in which lattice bonds are cut when the discontinuous layer is formed of a metal or a semiconductor. In the case where the discontinuous layer is formed of a photoresist or the like, it means a layer in which the internal structure is not uniform. In the discontinuous layer, since the lattice coupling and the internal structure are not uniform, no stress is generated in a specific direction.

[First Embodiment]
First, with reference to FIGS. 1 to 3, an impurity region forming step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. In the following, a case where a high-concentration n-type impurity region used for ohmic contact or the like is formed on a large-diameter substrate by selective ion implantation and high-temperature activation heat treatment will be described as an example for convenience. It may be an impurity region. The impurity concentration of the impurity region may be any value, and a plurality of impurity regions having different conductivity types and impurity concentrations may be formed on the substrate.

In the method of manufacturing a semiconductor device according to the first embodiment of the present invention, first, as shown in FIG. 1A, SiO ₂ or PSG (phosphosilicate) with a film thickness of about 1.5 μm is formed on the entire surface of the SiC substrate 1. An ion implantation mask layer 2 made of glass is formed. Next, as shown in FIG. 1B, the ion implantation mask layer 2 corresponding to the region where the high-concentration n-type impurity region is formed is removed by a photolithography process and an etching process, and an opening of the ion implantation mask layer 2 is formed. Region R1 is formed. Next, as shown in FIG. 1C, an ion-implanted through film 3 is formed on the substrate surface shown in FIG. 1B to adjust the range (depth) of impurity ions implanted in the processing described later. To do. The film thickness of the ion-implanted through film 3 is about 20 to 25 nm under the P (phosphorus) ion implantation conditions described later.

Next, as shown in FIG. 1D, the SiC substrate 1 is exposed so that the SiC substrate 1 exposed in the opening region R1 has a desired impurity ion concentration and the crystallinity of the SiC substrate 1 is not impaired. Impurity ions are implanted into the entire surface to form an impurity ion implantation region I in the SiC substrate 1 exposed in the opening region R1. In order to sufficiently reduce the contact resistance, the impurity ion concentration on the surface of SiC substrate 1 needs to be at least 1 × 10 ⁻²⁰ cm ⁻² or more. When such an impurity ion implantation region I is formed, P ions may be implanted into the SiC substrate 1 heated to 500 ° C. at the following “dose amount / acceleration energy” in multiple stages.
(A) 5 × 10 ¹⁴ cm ⁻² / 40 keV
(B) 5 × 10 ¹⁴ cm ⁻² / 70 keV
(C) 1 × 10 ¹⁵ cm ⁻² / 100 keV
(D) 1 × 10 ¹⁵ cm ⁻² / 150 keV
(E) 2 × 10 ¹⁵ cm ⁻² / 200 keV
(F) 2 × 10 ¹⁵ cm ⁻² / 250 keV

  When the formation of the impurity ion implantation region I is completed, the ion implantation mask layer 2 and the ion implantation through layer 3 are removed with hydrofluoric acid (HF), and then the surface of the SiC substrate 1 is made of the same material as shown in FIG. A continuous layer 4 and a discontinuous layer 5 are formed. The total thickness of the continuous layer 4 and the discontinuous layer 5 is about 0.1 to 5 μm, and the continuous layer 4 and the discontinuous layer 5 function as the cap layer 6. Examples of the material for forming the continuous layer 4 and the discontinuous layer 5 include materials containing carbon as a main component, such as a graphite film, an amorphous carbon film, and a diamond-like carbon (DLC) film. When forming a graphite film or an amorphous carbon film, for example, a photoresist carbonization method or a sputtering film formation method may be used. The DLC film can be formed by various methods. For example, a hot filament chemical vapor deposition (CVD) method using hydrogen and methane as raw materials can be exemplified. Specifically, the DLC film can be grown by microwave plasma CVD using hydrogen and methane as raw materials and a substrate temperature of about 800 ° C. and a pressure of 50 Torr.

  Crushing of the large-diameter substrate during the activation heat treatment can be reliably prevented as the discontinuous layer 5 has a larger film thickness. Specifically, if the film thickness of the discontinuous layer 5 is 100 mm or more, the large-diameter substrate can be prevented from being broken during the activation heat treatment. If the thickness of the discontinuous layer 5 increases and the thickness of the continuous layer 4 (the remaining portion of the cap layer 6 excluding the discontinuous layer 5) becomes too thin, the substrate generated during the activation heat treatment by the cap layer 6 Since the effect of preventing the surface roughness of the surface becomes small, it is necessary to be careful. For this reason, the film thickness of the discontinuous layer 5 must be controlled so that the continuous layer 4 having a minimum film thickness (at least 100 mm or more) necessary for preventing surface roughness of the substrate remains. The minimum value of the thickness of the discontinuous layer 5 depends on the formation conditions of the cap layer 6, but is about 0.2 μm when formed of a graphite film or an amorphous carbon film, and is formed of a DLC film or a diamond film. If it is, it is about 0.1 μm.

  As shown in FIG. 3, the discontinuous layer 5 has three forms of (a) regular depression type, (b) irregular depression type, and (c) bond cutting type. Any of the three forms or a combination of two or more of the three forms can be employed according to the characteristics. Hereinafter, the three forms shown in FIG. 3 will be described in detail.

(A) Regular depression type In this embodiment, a linear groove having a depth and width of submicron or more is formed on the surface as shown in FIG. 3 (a) according to a groove pattern regularly designed in the in-plane direction. The discontinuous layer 5 having regularly formed grooves is formed. For example, a groove pattern (for example, a lattice line or a honeycomb line) is designed so that the density of the groove is 0.2 line / cm ² or more, preferably 0.5 line / cm ² or more, and the discontinuous layer 5 is formed according to the groove pattern. Form. The cross-sectional shape of the groove may be a wedge shape as shown in FIG. 3A or a rectangular shape. Examples of the groove pattern forming method include a photolithography method and an etching method, a photolithography method and a lift-off method, a laser scan processing method using a YAG laser, a discharge scan method, a micro rolling method, a shadow mask vapor deposition method, and the like. Further, the same effect can be obtained even when a dot (dot) -like depression hole (recess) is formed instead of the groove. When forming a dot-shaped depression holes, the density of the recessed hole 100 / cm ² or more, preferably it is desirable to design a recessed hole pattern to be 1,000 / cm ² or more.

(B) Irregularly depressed type In this embodiment, a linear groove having a depth and width of submicron or more is formed according to a groove pattern irregularly designed in the in-plane direction as shown in FIG. A discontinuous layer 5 having irregularly formed grooves is formed thereon. However, also in this case, the groove pattern is designed so that the density of the grooves is 0.2 / cm ² or more, preferably 0.5 / cm ² or more. Examples of the method for forming the groove pattern in this case include hairline processing and rough polishing processing using sandpaper or stainless wool. Also in this case, the same effect can be obtained even if a dot-like depression hole is formed instead of the groove. When forming a dot-shaped depression holes, the density of the recessed hole 100 / cm ² or more, preferably it is desirable to design a recessed hole pattern to be 1,000 / cm ² or more. Examples of the method for forming the recessed hole pattern include sandblasting and sputtering. The present embodiment is extremely easy to process and inexpensive as compared with the embodiment (a), but it is difficult to precisely control the density and depth of the grooves. For this reason, it is desirable to process so that the average density of a groove | channel may become excess about 1 to 4 digits.

(C) Bond cutting type In this embodiment, a large amount of atomic level discontinuities, that is, high-density (1 × 10 ¹⁸ to 10 ²² / cm ³ ) dangling bonds are formed on the surface of the cap layer. As shown in FIG. 3 (c), the discontinuous layer 5 composed of an assembly of high-density unbonded hands is formed. Such a discontinuous layer 5 can be formed by, for example, a plasma bombardment process (including reverse sputtering process) using an inert gas plasma, or an entire surface ion implantation process using inert gas ions.

When the formation of the continuous layer 4 and the discontinuous layer 5 is completed, as shown in FIG. 2B, the SiC substrate 1 is then subjected to rapid heat treatment in an argon atmosphere at atmospheric pressure and 1700 ° C. for 5 minutes. Ions are activated to form impurity regions 7. The depth of the n ⁺ SiC region formed by the aforementioned P ion implantation conditions and heat treatment conditions is about 350 nm. Next, after sufficiently cleaning the SiC substrate 1, the continuous layer 4 and the discontinuous layer 5 are ashed as shown in FIG. 2C by heat-treating in an oxygen atmosphere at 900 ° C. for 60 minutes. Remove from one surface. In addition, after the continuous layer 4 and the discontinuous layer 5 disappear, the surface of the SiC substrate 1 is also exposed to an oxygen atmosphere at 900 ° C. for a short time, but the oxidation of the surface of the SiC substrate 1 hardly proceeds at this temperature. It can be virtually ignored. Thus, a series of impurity region forming steps is completed.

[Experimental example]
A comparative experiment was conducted in which 10 4H-SiC (0001) substrates each having a diameter of 2 inches and a thickness of 0.4 mm were divided into two groups of five, and the P impurity layer was activated by the manufacturing method of the conventional and this embodiment. . As a result, when the P impurity layer was activated by the conventional manufacturing method, crushing was confirmed on all five substrates, whereas when the P impurity layer was activated by the manufacturing method of this embodiment, In all of the five substrates, the crushing did not occur and the activation could be completed. Further, the flatness (degree of roughness) of the substrate surface activated by the manufacturing method of the present embodiment was equivalent to the case where the conventional manufacturing method was used. Further, the activation of the 4H—SiC substrate and the 6H—SiC substrate having the diameters of 75 mm and 100 mm was applied to the manufacturing method of this embodiment, and no crushing was confirmed even in these large diameter substrates. Furthermore, when the manufacturing method of the present embodiment was applied to the activation of the 3C—SiC substrate having a diameter of 150 mm (activation conditions were 1400 ° C. and 5 minutes), the heat treatment was successfully completed without crushing even the 150 mm substrate. From the above experimental facts, according to the present embodiment, it was confirmed that activation heat treatment can be performed on a SiC substrate having a diameter of 50 mm or more without crushing the substrate.

  In general, when a substrate whose surface is covered with a different material film is heated, the substrate is crushed because of the bimetal effect (stress generation) caused by the difference in thermal expansion coefficient between the different material film and the substrate. It is widely known that For this reason, hitherto, the substrate is prevented from being crushed by using a material having a small difference in thermal expansion coefficient from the substrate. However, even if the SiC substrate is heat-treated based on such an idea, the inventors have confirmed through experiments that the substrate is often crushed especially in the activation heat treatment for large-diameter substrates. Contradicts with the above idea.

  The inventors have conducted extensive research on this point, and as a result, have found the following from the results of an experimental heat treatment for a wide gap hand semiconductor such as SiC. First, when the SiC substrate is exposed to a high temperature, stress is not generated in a specific direction with respect to the semiconductor substrate in the SiC substrate like a semiconductor substrate such as Si. Is considered to be distributed. On the other hand, it is considered that stress is generated in a specific direction in the cap layer formed uniformly on the surface of the SiC substrate. For this reason, the stress generated in the uniformly formed cap layer continues to act in a specific direction, but the stress generated in the SiC substrate is difficult to predict and is generated in an unspecified direction. It is considered that the stress in a specific direction increases as a result of canceling in a certain region, and the SiC substrate is crushed without being able to withstand the resultant force.

  Therefore, the inventors intentionally formed the discontinuous layer 5 on the surface of the cap layer so that the direction of stress generated in the cap layer is generated not in a specific direction but in a non-uniform direction. By adopting such a configuration, it is possible to alleviate the deviation in the direction of the stress generated between the SiC substrate and the cap layer, to prevent the stress from concentrating on a specific portion of the substrate, and to predict the occurrence in the SiC substrate. Since it is possible to increase the probability of canceling a part of the difficult and non-uniform internal stress distribution (compression and tension), it is possible to suppress the SiC substrate from being crushed.

  As is clear from the above description, according to the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the continuous layer 4 is formed on the surface of the SiC substrate 1, and the continuous layer 4 is formed on the surface of the continuous layer 4. The discontinuous layer 5 having an internal structure different from the internal structure is formed, and the activation heat treatment is performed on the SiC substrate 1 on which the continuous layer 4 and the discontinuous layer 5 are formed as the cap layer 6. Impurity region 6 is formed by removing continuous layer 4 and discontinuous layer 5 from the surface of SiC substrate 1. And according to such a manufacturing method, as described above, it is possible to alleviate the deviation in the direction of stress generation between the SiC substrate 1 and the cap layer 6, and to prevent stress from concentrating on a specific location of the substrate, In addition, since it is possible to increase the probability of canceling a part of the non-predictable and non-uniform internal stress distribution generated in the SiC substrate 1, the SiC substrate 1 is prevented from being crushed, and the SiC substrate 1 is used for the semiconductor device. When manufacturing, it can suppress that a yield falls.

[Second Embodiment]
Next, with reference to FIG. 4, an impurity region forming step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. In the present embodiment, a cap layer is provided on an element region in accordance with a scribe line when cutting (scribing) between element regions. In such a configuration, since the cap layer can be formed in accordance with the scribe line, it can be considered that the cap layer is equivalent to a state where the cap layer is divided into element regions (element region). Each cap layer provided on top does not have a discontinuous layer as in the first embodiment). Accordingly, the manufacturing process can be simplified by omitting the step of forming the discontinuous layer while calculating the depth of the continuous layer.

  In the method for manufacturing a semiconductor device according to the second embodiment of the present invention, the ion implantation mask layer 2 and the ion implantation through film 3 are removed as shown in FIG. As a result, the impurity ion region I partitioned by the scribe line having the width D is exposed on the surface of the SiC substrate 1. Next, as shown in FIG. 4B, a cap layer 8 having a thickness of 0.1 to 5 μm formed of a material mainly composed of carbon and having a through groove formed along a scribe line is formed on the surface of the SiC substrate 1. Adhere to.

  Specifically, it was designed so that a positive photoresist film having a thickness of about 0.2 to 10 μm was first applied to the surface of the SiC substrate 1 and prebaked, and then selectively irradiated to the inside of the scribe line. By exposing and developing using a photomask and an exposure apparatus, a through groove is formed in the photoresist film on the scribe line. Next, the SiC substrate 1 is heat-treated in an inert gas atmosphere at 750 ° C. for about 20 minutes, whereby the photoresist film is graphitized to form a cap layer 8 having a through groove in the scribe line. The film thickness of the photoresist film is desirably determined in consideration of shrinking to about 1/3 to 2/3 due to graphitization.

  In this embodiment, the cap layer 8 is formed by graphitizing the photoresist film. For example, an amorphous carbon film is deposited by sputtering or the like using a photoresist pattern formed on a scribe line as a deposition mask. Then, the cap layer 8 made of amorphous carbon may be formed on the scribe line by dissolving (lifting off) the photoresist pattern. When the width of the scribe line is large, the cap layer 8 having a groove pattern directly on the substrate surface may be formed using a metallic vapor deposition mask (shadow mask).

  When the formation of the cap layer 8 is completed, as shown in FIG. 4C, impurity ions are activated by rapidly heating the SiC substrate 1 for 5 minutes at 1700 ° C. in an argon atmosphere at atmospheric pressure. Thus, the impurity region 7 is formed. According to the present embodiment, the scribe line region R2 is exceptionally roughened. However, since the scribe line is located outside the element region, the scribe line region R2 has any adverse effect on the characteristics and reliability of the semiconductor device. Absent. Next, the SiC substrate 1 is thoroughly cleaned, and then heat-treated in an oxygen atmosphere at 900 ° C. for 60 minutes, so that the cap layer 8 is ashed and completely removed from the surface of the SiC substrate 1 as shown in FIG. To do. After the cap layer 8 disappears, the surface of the SiC substrate 1 is also exposed to an oxygen atmosphere at 900 ° C. for a short time. However, since the oxidation of the surface of the SiC substrate 1 hardly proceeds at this temperature, it should be ignored. Can do. Thus, a series of impurity region forming steps is completed.

[Experimental example]
4H- and 6H-SiC (0001) substrates having a diameter of 2 inches to 100 mm and a thickness of 0.4 mm, and several 3C-SiC (001) substrates having a diameter of 2 inches to 150 mm and a thickness of 0.3 mm, respectively. Experiments were performed to activate the P impurity layer by the manufacturing method. As a result, the activation was completed without crushing all the substrates. Further, the flatness (roughness degree) of the substrate surface corresponding to the element region was the same as when using the conventional manufacturing method. From this experimental fact, it has been found that according to the present embodiment, activation heat treatment can be performed on a SiC substrate having a diameter of 50 mm or more without crushing the substrate.

  As apparent from the above description, according to the method of manufacturing the semiconductor device according to the second embodiment of the present invention, the cap is formed on the impurity ion implantation region I formed at a predetermined interval on the surface of the SiC substrate 1. The layer 8 is formed, and heat treatment is performed on the SiC substrate 1 on which the cap layer 8 is formed to activate the impurity ions in the impurity ion implantation region I. After the heat treatment is completed, the cap layer 8 is removed from the surface of the SiC substrate 1. By removing, the impurity region 7 is formed. And according to such a manufacturing method, it can suppress that the SiC substrate 1 crushes, and can suppress that a yield falls when manufacturing a semiconductor device with the SiC substrate 1. FIG.

  As mentioned above, although embodiment which applied the invention made by the present inventors was described, this invention is not limited by description and drawing which make a part of indication of this invention by this embodiment. For example, in the above embodiment, the cap layer 6 is formed of a material whose main component is carbon, but the present invention is not limited to this, and can withstand high temperatures, and the thermal expansion coefficient is close to the thermal expansion coefficient of the substrate. The cap layer 6 may be formed of a material such as aluminum nitride that does not react with the substrate. Thus, it is needless to say that all other embodiments, examples, operation techniques, and the like made by those skilled in the art based on the present embodiment are all included in the scope of the present invention.

It is sectional process drawing which shows the flow of the manufacturing method of the semiconductor device used as the 1st Embodiment of this invention. FIG. 2 is a cross-sectional process diagram illustrating a continuation of the cross-sectional process diagram illustrated in FIG. 1. It is a schematic diagram which shows the structure of the cap layer used as embodiment of this invention. It is sectional process drawing which shows the flow of the manufacturing method of the semiconductor device used as the 2nd Embodiment of this invention.

Explanation of symbols

1: SiC substrate 2: Ion implantation mask layer 3: Ion implantation through film 4: Continuous layer 5: Discontinuous layers 6, 8: Cap layer 7: Impurity region I: Impurity ion implantation region R1: Opening region

Claims (20)

Forming an ion implantation mask layer on a surface of a semiconductor substrate formed of a silicon carbide wide gap semiconductor ;
Forming an opening of the mask layer by removing the ion implantation mask layer at a position corresponding to the element region on the surface of the semiconductor substrate;
Forming an ion implantation through layer on the mask layer surface and on the semiconductor substrate surface exposed from the opening;
Implanting impurity ions into the semiconductor substrate through the ion implantation through layer;
Removing the ion implantation mask layer and the ion implantation through layer from the surface of the semiconductor substrate after impurity ion implantation;
A first structure having an internal configuration in which lattice bonds are uniformly arranged in a specific direction on the surface of the semiconductor substrate from which the ion implantation mask layer and the ion implantation through layer have been removed, or in which the internal structure is uniform; Forming a coating layer;
On the surface of the first coating layer, a state in which lattice bonds are not uniformly arranged in a specific direction, a state in which lattice bonds are cut, or an internal tissue structure is uniform so that no stress is generated in a specific direction. Forming a second coating layer having an internal configuration that is not in a state;
Activating the impurity ions by performing a heat treatment on the semiconductor substrate on which the first coating layer and the second coating layer are formed;
And a step of removing the first coating layer and the second coating layer from the surface of the semiconductor substrate after the heat treatment. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the first coating layer remaining after the second coating layer is formed has a thickness of 100 mm or more. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second coating layer has linear grooves regularly formed on the surface according to a predetermined pattern. In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the second coating layer has at least 0.2 linear grooves / cm ² or more. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second coating layer has a dot-like recess regularly formed on the surface according to a predetermined pattern. In the manufacturing method of the semiconductor device according to claim 5,
The method for manufacturing a semiconductor device, wherein the second coating layer has at least 100 dot-like recesses / cm ² or more. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second coating layer has a linear groove irregularly formed on the surface. In the manufacturing method of the semiconductor device according to claim 7,
The method of manufacturing a semiconductor device, wherein the second coating layer has at least 0.2 linear grooves / cm ² or more. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second coating layer has dot-like recesses irregularly formed on the surface. In the manufacturing method of the semiconductor device according to claim 9,
The method for manufacturing a semiconductor device, wherein the second coating layer has at least 100 dot-like recesses / cm ² or more. The method of manufacturing a semiconductor device according to any one of claims 3 to 10,
The groove or the recess is formed by any one of a photolithography method and an etching method, a photolithography method and a lift-off method, a laser scan processing method, a discharge scan method, a micro rolling method, and a shadow mask deposition method. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 7 or claim 8,
A method of manufacturing a semiconductor device, wherein the groove is formed by a hairline process using sand paper or stainless wool, or a rough polishing process. In the manufacturing method of the semiconductor device according to claim 9 or 10,
A method of manufacturing a semiconductor device, wherein the recess is formed by sandblasting or sputtering. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second coating layer is an aggregate of dangling bonds formed at a high density by cutting the atomic structure of the first coating layer. In the manufacturing method of the semiconductor device according to claim 14,
A dangling bond is formed by any one of a plasma bombardment process, a reverse sputtering process, and an entire surface ion implantation process. In the manufacturing method of the semiconductor device according to claim 14 or 15,
A method for manufacturing a semiconductor device, wherein the density of the dangling bonds is in the range of 1 × 10 ¹⁸ pieces / cm ^{3 to} 1 × 10 ²² pieces / cm ³ . The method of manufacturing a semiconductor device according to any one of claims 1 to 16 ,
A method of manufacturing a semiconductor device, wherein a diameter or one side of the semiconductor substrate has a length of 50 mm or more. The method for manufacturing a semiconductor device according to any one of claims 1 to 17 ,
A method of manufacturing a semiconductor device, wherein the first coating layer is formed of a material mainly containing carbon. In the manufacturing method of the semiconductor device according to claim 18 ,
The method for manufacturing a semiconductor device, wherein the material containing carbon as a main component is any one of a graphite film, an amorphous carbon film, a DLC film, and a diamond film. A semiconductor substrate formed of a silicon carbide wide gap semiconductor ;
An element region formed on the surface of the semiconductor substrate and in which the implanted impurity ions are activated by heat treatment ;
A first coating layer formed on the surface of the semiconductor substrate including the element region and having an internal configuration in which lattice bonds are uniformly arranged in a specific direction or an internal structure is uniform;
A state in which lattice bonds are not uniformly arranged in a specific direction, or a state in which lattice bonds are cut, or an internal tissue structure is formed on the surface of the first coating layer so that no stress is generated in the specific direction. And a second coating layer having an internal configuration in a state where is not uniform.

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