JP2018107271A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of facilitating flaking process of a semiconductor substrate that contains SiC as a main material, and of achieving an SiC semiconductor device with good characteristics.SOLUTION: A method of manufacturing a semiconductor device includes the following steps of: bonding a first supporting body 10 formed of SiC with a lower surface of a single crystal wafer 1of SiC; thinning an upper surface of a single crystal wafer 1defined at an opposite side to the first supporting body 10 to obtain a wafer 1 for epitaxial growth; building a device structure on an upper surface of the wafer 1 for epitaxial growth to obtain a device wafer 100; oxidizing a region at an interface bonded with the device wafer 100, of the first supporting body 10 to form an isolation oxide film 18; and removing the isolation oxide film 18 to isolate the remaining first supporting body 10r and the device wafer 100.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a vertical power device (semiconductor device) in which the main current runs in the thickness direction of the substrate, the current conduction distance, that is, the device wafer (semiconductor substrate) is processed thinly in order to reduce loss during conduction and to operate at high speed. Is required. On the other hand, the minimum thickness of the device wafer is determined from the request for the maximum electric field strength and the extension distance of the depletion layer for the desired breakdown voltage specification.

  In order to suppress the extension distance of the depletion layer, a buffer layer or the like may be used in the drift layer of the device wafer. If the buffer layer is used, the wafer can be made thinner. Further, by changing the semiconductor material from silicon (Si) to silicon carbide (SiC), particularly 4H—SiC, the maximum electric field strength is increased about 10 times. Therefore, the wafer thickness required for SiC may be 1/10 of Si. However, in the case of Si, if it is thinned to about 60 μm or less, a wafer that is easy to bend can be realized. However, in the case of SiC, if the wafer is thinned, the mechanical strength is insufficient, and the influence of warping due to breakage or stress increases. .

  As a method for avoiding these problems, there is a technique that uses a structure that supports a thinned substrate, for example, a technique that leaves the outer periphery of a wafer in a rib shape and thins it by cutting other than the rib. There is also a technique for thinning the substrate by attaching a support substrate to the front surface of the wafer using an adhesive and cutting the back surface to avoid breakage and the like. In adhering the front surface of the wafer and the support substrate, a bonding technique such as a surface activation method can be used in addition to the adhesive.

  However, SiC is a harder material than Si, and thinning is very difficult and troublesome. Further, the residual stress due to the thinning process tends to cause warpage or breakage of the wafer. For this reason, in SiC, it is necessary to perform a polishing process for removing residual stress separately. Further, as the wafer becomes thinner, the influence of stress deformation caused by the formation of components such as electrodes cannot be ignored. Such stress deformation occurs at the time of device formation with a certain thickness or less, and is unavoidable. For this reason, the technique of leaving the outer periphery in a rib shape can be applied in the case of Si, but in the case of SiC, the thinned wafer cannot be sufficiently supported, and cracks and the like are generated.

Moreover, in SiC, the high temperature process of about 1000 degreeC is required for formation of an ohmic electrode, and the high temperature process of 1600 degreeC-1700 degreeC is required for activation of a dopant. Therefore, in the case of a technology for attaching a support substrate, even if a resin adhesive using a polyimide material having a high heat resistance temperature is used as an adhesive, the adhesive between the SiC wafer and the support substrate is subjected to high temperature processing. I can't stand it.
Further, when the substrates are bonded to each other by an adhesive or a surface activation method, generally, a bonded state is formed very firmly, and therefore, the substrates are not peeled again. In addition, there arises a problem that the joint surface is rough due to peeling.

  As a technology for bonding a support substrate to a SiC substrate, for example, a technology is disclosed in which a support substrate of a single crystal SiC substrate or a polycrystalline SiC substrate is prepared and directly bonded to a device wafer of a single crystal SiC substrate (Patent Document 1). reference). Further, as a method for peeling the support substrate as easily as possible, a technique is disclosed in which the first substrate and the second substrate are joined via an intervening layer having a high etching rate (see Patent Document 2). .

However, the method of Patent Document 1 does not fully consider the problem of peeling after bonding. Further, since the method of Patent Document 2 uses silicon oxide (SiO ₂ ) as an intervening layer, it is effective for a Si substrate having a low melting point, but cannot withstand activation annealing of SiC at about 1600 ° C. There is a problem.

Japanese Patent No. 5053855 JP 2002-299589 A

  The present invention has been made paying attention to the above-described problems, and is a method for manufacturing a semiconductor device that can easily realize a SiC semiconductor device having good characteristics, which is easy to thin a semiconductor substrate containing SiC as a main material. The purpose is to provide.

  In order to solve the above-described problem, an aspect of the method for manufacturing a semiconductor device according to the present invention includes: (a) a step of bonding a first support to a lower surface of a single crystal wafer mainly composed of silicon carbide; (B) a step of thinning the upper surface side of the single crystal wafer defined on the side opposite to the first support; (c) a step of constructing a device structure on the upper surface side of the single crystal wafer to form a device wafer; (D) oxidizing the region at the interface where the first support and the device wafer are joined to form an isolation oxide film; and (e) removing the isolation oxide film to leave the remaining first support. And a step of separating the body and the device wafer.

  Therefore, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to provide a method for manufacturing a semiconductor device in which a semiconductor substrate containing SiC as a main material can be easily thinned and a SiC semiconductor device having good characteristics can be realized.

1 is a bird's-eye view (perspective view) schematically illustrating an outline of a support used in a method for manufacturing a semiconductor device according to a first embodiment. It is process sectional drawing which illustrates the manufacturing method of the support body shown in FIG. 1 typically in order of FIG. 2 (a)-> FIG. 2 (b). FIG. 4 is a process cross-sectional view schematically illustrating the method of manufacturing the semiconductor device according to the first embodiment in the order of FIG. 3A → FIG. 3B → FIG. 3C → FIG. (Part 1). The manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIG. 4 (a) → FIG. 4 (b) → FIG. 4 (c) → FIG. 4 (d) → FIG. It is process sectional drawing typically demonstrated in order of (2). It is sectional drawing which illustrates typically the outline of the 1st modification of the support body used for the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a top view which illustrates typically the outline of the 2nd modification of the support body used for the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is an enlarged view of A part in FIG. It is a top view which illustrates typically the outline of the 3rd modification of the support body used for the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing seen from the BB line direction in FIG. It is a top view which illustrates typically the outline of the 4th modification of the support body used for the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which illustrates typically the outline of the 5th modification of the support body used for the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which illustrates typically the outline of the 6th modification of the support body used for the manufacturing method of the semiconductor device which concerns on 1st Embodiment. A method of manufacturing a semiconductor device according to the second embodiment is schematically described in the order of FIG. 13A → FIG. 13B → FIG. 13C → FIG. 13D → FIG. It is process sectional drawing (the 1). The manufacturing method of the semiconductor device according to the second embodiment will be described with reference to FIG. 14 (a) → FIG. 14 (b) → FIG. 14 (c) → FIG. 14 (d) → FIG. 14 (e) → FIG. It is process sectional drawing typically demonstrated in order of (2). FIG. 15 is a process cross-sectional view schematically illustrating the manufacturing method of the semiconductor device according to the third embodiment in the order of FIG. 15A → FIG. 15B → FIG. FIG. 17 is a process cross-sectional view schematically illustrating the manufacturing method of the semiconductor device according to the third embodiment in the order of FIG. 16A → FIG. 16B → FIG. 16C → FIG. (Part 2). It is sectional drawing which illustrates typically the outline of the 7th modification of the support body and semiconductor device which are used for the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.

  The first to third embodiments of the present invention will be described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and it should be noted that the relationship between the thickness and the planar dimensions, the ratio of the thickness of each device and each member, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the directions of “left and right” and “up and down” in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. Thus, for example, if the paper is rotated 90 degrees, “left and right” and “up and down” are read interchangeably, and if the paper is rotated 180 degrees, “left” becomes “right” and “right” becomes “left”. Of course. In addition, in this specification and the accompanying drawings, + and − attached to n and p are semiconductor regions having a relatively high or low impurity concentration, respectively, as compared with a semiconductor region not including + and −. Means. Further, the same notation such as n ⁺ and n ⁺ does not necessarily indicate the same impurity concentration.

<First Embodiment>
As a method for manufacturing the semiconductor device according to the first embodiment, a case where a PiN diode whose main material is SiC is manufactured will be described below as an example. It should be noted that the present invention is not limited to the description of the following embodiments, and includes, for example, a Schottky barrier diode (SBD), an insulated gate field effect transistor (MOSFET) such as MISFET or MISSIT, or an insulated gate bipolar transistor ( (IGBT) and the like. Needless to say, this is true even if the polarity of the conductivity type is changed.

(First support)
First, a first support used in the method for manufacturing a semiconductor device according to the first embodiment will be described. The first support 10 is made of a SiC semiconductor substrate, and as shown in FIG. 1, a substantially cylindrical base 11 and a plurality of convex portions provided on the upper surface of the base 11... 12 _i-1 , 12 _i , 12 _{i + 1} .

  As the first support 10, a polycrystalline SiC substrate or a SiC substrate having a polytype crystal structure such as 3c, 4H, or 6H can be adopted. The grain size of polycrystalline SiC is, for example, about 50 μm or less.

The plurality of convex portions 12 _i−1 , 12 _i , 12 _{i + 1} illustrated in FIG. 1 have substantially the same shape, and are provided on the base portion 11 with an island (mesa) structure. . A single crystal wafer is placed on the upper surface of the convex portions 12 _i-1 , 12 _i , 12 _{i + 1} . Grooves are formed between a plurality of adjacent convex portions... 12 _i−1 , 12 _i , 12 _{i + 1} . This groove portion communicates with the outer periphery of the first support 10 and is in an atmosphere in which the first support 10 is disposed in the oxidation process performed after the bonding of the first support 10 and the single crystal wafer. The oxidation process proceeds so that oxygen comes into contact with all of the plurality of projections... 12 _i-1 , 12 _i , 12 _{i + 1} ... through the groove. That is, the groove portion forms an oxidizing atmosphere passage that is a passage through which the oxidizing gas is introduced.

In FIG. 1, a plurality of substantially prismatic projections 12 _i−1 , 12 _i , 12 _{i + 1 1} are arranged in a lattice window at equal intervals in a plane pattern, and adjacent projections 12 _The case where the groove part pinched | interposed into _i-1 , _12i , _{12i + 1} ... appears in a lattice form is illustrated.

As a manufacturing method of the first support 10, first, as shown in FIG. 2A, at least one surface (upper surface in FIG. 2A) of the SiC substrate 10 _{sub serving} as a base is changed as necessary. Then, the surface is planarized by a polishing process such as chemical mechanical polishing (CMP). Alternatively, a SiC substrate 10 _sub with one surface planarized in advance may be purchased from the market and prepared.

As shown in FIG. 2B, the flattened region forms the upper surface of the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} . In order to secure the bonding strength between the upper surfaces of the convex portions 12 _i-1 , 12 _i , 12 _{i + 1} and the lower surface of the single crystal wafer, the flatness of the SiC substrate 10 _sub has an arithmetic average roughness Ra of 1 nm or less. Desirably, 0.5 nm or less is more desirable. If the surface is flattened by polishing or the like, then a predetermined cleaning process is performed to remove residues and damage caused by the flattening process.

Next, a desired etching mask made of a photoresist film or the like is formed on the planarized upper surface of the SiC substrate 10 _sub using a photolithography technique. Then, by the selective etching technique using an etching mask, the groove portions sandwiched between the convex portions... 12 _i−1 , 12 _i , 12 _{i + 1} . As the groove etching technique, reactive ion etching (RIE), thermal etching, wet etching, ion milling, or the like can be appropriately employed.

In the case of RIE, examples of gases include sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), nitrogen trifluoride (NF ₃ ), phosphorus pentafluoride (PF ₅ ), boron trifluoride ( Oxygen (O ₂ ) for each of BF ₃ ), trifluoromethane (CHF ₃ ), chlorine (Cl ₂ ), silicon chloride (SiCl ₄ ), iodine monobromide (IBr), phosphorus trichloride (PCl ₃ ), etc. Or each can be used alone.

In the case of thermal etching, hydrogen (H ₂ ), Cl ₂ and O ₂ , chlorine trifluoride (ClF ₃ ), or the like can be used as the gas. In the case of wet etching, for example, an aqueous potassium hydroxide (KOH) solution at about 500 ° C. can be used.

The height h measured along the vertical direction from the lowermost part to the uppermost part of the convex parts 12 _i-1 , 12 _i , 12 _{i + 1} shown in FIG. In the oxidation treatment performed after joining, the necessary oxidizing gas is introduced, and all the regions from the bottom to the top of the convex portions 12 _i-1 , 12 _i , 12 _{i + 1} are oxidized. Is set to Although the height h as the oxidizing atmosphere passageway depends on the oxidizing conditions, specifically, for example, a value of about 1 μm can be adopted.

The width w measured along the parallel direction of the convex portions 12 _i-1 , 12 _i , 12 _{i + 1} corresponding to one side of the cube of the convex portions 12 _i−1 , 12 _i , 12 _{i + 1} . Are set in consideration of the fact that the regions in the parallel direction of the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} . Specifically, the width w of the convex portions 12 _i-1 , 12 _i , 12 _{i + 1} is desirably about 0.1 μm to 3 μm, and more desirably about 0.5 μm to 1 μm. .

When the width w of the convex portion is less than 0.3 μm, the bonding strength with the single crystal wafer (device substrate) is low, and when the width w of the convex portion exceeds 3 μm, the oxidation and removal processing becomes difficult. The convex portion adjacent _{... 12 i-1, 12 i} , 12 i + 1 ... the width p of the groove between, like the convex part _{... 12 i-1, 12 i} , 12 i + 1 ... width w of, It is preferably about 0.1 μm or more and about 3 μm or less.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device according to the first embodiment using the first support 10 will be described. First, an n-type 4H—SiC single crystal wafer 1 _sub having a disk shape with substantially the same radius as that of the first support 10 and having one surface flattened is prepared. Flattened one surface of the single crystal wafer 1 _sub, as shown in FIG. 3 (a), the lower surface of the single crystal wafer 1 _sub.

The upper surface of the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} of the first support 10 is in contact with the lower surface of the single crystal wafer 1 _sub . To ensure the bonding strength between the lower surface of the convex portion _{... 12 i-1, 12 i} , 12 i + 1 ... of the upper surface and the single-crystal wafer _{1 sub,} flatness of the single-crystal wafer _{1 sub} is an arithmetic mean roughness Ra 1 nm or less is desirable, and 0.5 nm or less is more desirable. Thereafter, when a predetermined cleaning process is performed and planarization is performed by polishing or the like, it is preferable to remove residues and damage caused by the planarization process by wet etching or the like.

Next, as shown in FIG. 3A, the upper surfaces of the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1 of} the first support 10 and the lower surface of the single crystal wafer 1 _sub are joined. For this bonding, a direct bonding method such as a surface activated bonding (SAB) method can be employed. In the direct bonding method, the first support 10 and the single crystal wafer 1 _sub are placed in the same ultra-high vacuum chamber and irradiated with an atomic beam or an ion beam using atoms such as accelerated argon (Ar). A process for forming an amorphous bonding layer can be performed. Specifically, the Ar atomic beam is irradiated to the upper surfaces of the convex portions 12 _i-1 , 12 _i , 12 _{i + 1} , and the lower surface of the single crystal wafer 1 _sub as the bonding surfaces. Do.

Immediately after irradiation with the Ar atom beam, the first support 10 and the single crystal wafer 1 _sub are bonded directly by bringing the bonding surfaces on which the amorphous bonding layers are formed into contact with each other to form a bonded state. Between the first support 10 and the single crystal wafer 1 _sub after the direct bonding, an amorphous bonding layer having a thickness of about several nm is formed. The amorphous bonding layer is a solid layer having no long-range order in an atomic arrangement composed of Si, carbon (C), and adsorbed Ar.

Next, as shown in FIG. 3B, the thinning process is performed on the surface opposite to the direct bonding surface (the upper surface in FIG. 3B) of the directly bonded single crystal wafer 1 _sub . The single crystal wafer 1 _sub having a desired thickness is left. Hereinafter, the thinned single crystal wafer 1 _sub is referred to as an epitaxial growth wafer 1. The 4H—SiC epitaxial growth wafer 1 has a thickness of, for example, about 15 μm. For the thinning, known techniques such as smart cutting by ion irradiation, grinding and polishing can be employed. When thinning is performed by CMP or the like, it is preferable to remove residues and damage generated by thinning by wet etching or the like.

Next, as shown in FIG. 3C, the thinned 4H—SiC epitaxial growth wafer 1 is subjected to wet cleaning using an acid solution or the like, and then the n-type (n ⁻ ) having a low concentration is formed. SiC is epitaxially grown to form an epitaxial growth layer 2 having a desired thickness. For example, when the breakdown voltage of the semiconductor device is 1200 V, the thickness of the epitaxial growth layer 2 is formed to about 15 μm.

Next, a thin film of, for example, SiO ₂ is deposited on the epitaxial growth layer 2 by a CVD method or the like. Then, a photoresist film is applied on the SiO ₂ thin film, a pattern serving as an etching mask for the photoresist film is formed using photolithography technology, and the SiO ₂ thin film is selectively etched using the etching mask for patterning. To remove the photoresist film. A patterned SiO ₂ thin film is used as an ion implantation mask, an epitaxial growth wafer 1 is placed in an atmosphere of room temperature to about 500 ° C., and aluminum (Al) ions are implanted above the epitaxial growth layer 2. Thereafter, the SiO ₂ thin film is removed. Depending on the desired device, further epitaxial growth layers and ion implantation layers may be formed by repeatedly using the same method as that described above.

  Next, activation annealing at a high temperature of about 1600 ° C. is performed on the epitaxial growth wafer 1, so that a plurality of p-type semiconductor layers 3 a to 3 d as shown in FIG. It is formed on the 4H-SiC device. Hereinafter, the epitaxial growth wafers 1 and 2 on which the plurality of p-type semiconductor layers 3 a to 3 d are formed are referred to as a device wafer 100.

  In order to prevent Si from detaching from the surface of the device wafer 100, a thin film of about 20 nm, for example, carbon (C) is formed on the surface of the device wafer 100 in advance before the activation annealing, and after the activation annealing. It may be removed by a process such as ashing.

After the activation annealing, as shown in FIG. 3E, an interlayer insulating film 14 such as a SiO ₂ thin film is deposited by CVD or the like, and a SiN thin film is formed as a barrier layer 15 on the interlayer insulating film 14. .

  Next, as shown in FIG. 4A, the surfaces of the first support 10 and the device wafer 100 are oxidized by, for example, thermal oxidation, and separated and oxidized at the interface between the first support 10 and the device wafer 100. A layer of film 18 is formed. Incidentally, the rectangular shape of the cross section of the groove portion after oxidation illustrated in FIG. 4A and the rectangular shape of the cross section of the groove portion before oxidation illustrated in FIG. 3 are drawn with substantially the same dimensions. Because of the thickening due to oxidation, the rectangular shape of the groove after oxidation becomes smaller.

  Here, the oxidation rate of polycrystalline SiC is, for example, about 200 to 300 nm / h in the case of wet oxidation in the atmosphere of about 1200 ° C. On the other hand, the oxidation rate of single crystal SiC is about 20 nm / h on the (0001) plane and about 120 nm / h on the (11-20) plane in the case of thermal wet oxidation at about 1150 ° C. for 6H-SiC, for example. is there.

Therefore, it is possible to selectively oxidize the first support 10 by performing wet oxidation, for example, using the fact that polycrystalline SiC has a very high oxidation rate compared to single-crystal SiC. it can. The region to be oxidized includes the vicinity of the bonding interface between the first support 10 and the device wafer 100, the convex portion 12 _i-1 , 12 _i , 12 _{i + 1} , and the base 11 of the first support 10. On the side. Since the groove part sandwiched between the convex parts 12 _i-1 , 12 _i , 12 _{i + 1} ... functions as an oxidizing atmosphere passage, and the oxidizing gas is introduced, the first support 10 and the device The side surfaces of the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} ... located at the bonding interface with the wafer 100 are effectively oxidized.

In addition, a fine groove structure is formed by the plurality of convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} ..., And the surface area of oxidation in the upper portion of the first support 10 is increased. Therefore, at the time of oxidation, not only the side surfaces of the protrusions 12 _i−1 , 12 _i , 12 _{i + 1 of} the first support 10 but also the entire surface is more efficiently oxidized to the device wafer 100. It can be selectively oxidized. At this time, the layer of the isolation oxide film 18 may be formed at such a depth that all of the plurality of convex portions... 12 _i-1 , 12 _i , 12 _{i + 1 of} the first support 10 are oxidized. Although desirable, it is desirable that the film is oxidized at an oxidation depth of at least about 0.5 μm and can function as an effective isolation oxide film 18.

  Next, as shown in FIG. 4B, a photoresist film is applied on the interlayer insulating film 14 and the barrier layer 15, and the interlayer insulating film 14 and the barrier layer 15 are selected by using the photolithography technique and the RIE method. Etching is performed to open a contact hole in the interlayer insulating film 14 where a part of the upper surface of the plurality of semiconductor layers 3a to 3d is exposed, and then the photoresist film is removed. Further, a metal thin film made of a refractory metal such as tungsten (W), molybdenum (Mo), titanium (Ti) is formed on the entire surface of the interlayer insulating film 14 and the barrier layer 15 in which the contact holes are opened by a sputtering method, Deposited by vacuum evaporation, CVD or the like. Then, a photoresist film is applied on the refractory metal thin film, and the metal thin film is selectively etched using a photolithography technique and an RIE method. Thereafter, heat treatment is performed to form the main part of the PiN diode structure in which the ohmic contact region patterns 6a to 6d made of refractory metal silicide are formed on the plurality of semiconductor layers 3a to 3d.

  Next, as shown in FIG. 4C, a second support 5 having a disk shape with substantially the same radius as that of the device wafer 100 is bonded to the upper surface side of the device wafer 100 via the adhesive layer 4. As the 2nd support body 5, materials, such as SiC and Si, can be used, for example. The adhesive layer 4 can be formed using a known adhesive such as a resin.

Next, as shown in FIG. 4 (d), for example, with hydrofluoric acid (HF), the vicinity of the bonding interface between the first support 10 and the device wafer 100, the convex portion... 12 _i-1 , 12 _i , 12 _{i + 1} ... The isolation oxide film 18 on the entire surface and the side surface of the base 11 of the first support 10 is removed, and the first support 10 r is separated from the device wafer 100. At this time, the interlayer insulating film 14 formed on the device surface is protected by the barrier layer 15 and the adhesive layer 4 made of SiN.

Next, as shown in FIG. 4E, nitrogen (N) ions are implanted into the lower surface of the separated device wafer 100, which is the back surface side of the device structure, and annealing is performed at an appropriate temperature as a low temperature process. An n ⁺ -type back contact layer 7 having a higher concentration than that of the wafer 100 is formed. Further, a Ni layer is formed and annealed at an appropriate temperature as a low temperature process to form the back electrode layer 8. Hereinafter, the device wafer 100 formed up to the back electrode layer 8 is referred to as a device wafer 101. The “low temperature process” means that, for example, local heating is used so as not to impair the bonding with the second support 5 bonded onto the device structure on the front surface side of the device wafer 100. It refers to a process performed at a process temperature at which the adhesive of the adhesive layer 4 does not decompose.

  Next, as shown in FIG. 4F, after the back surface structure forming process is completed, the second support 5 is removed from the device wafer 101. Furthermore, a device wafer is obtained by forming electrodes on the surface, and the manufacturing method of the semiconductor device according to the first embodiment is completed.

According to the method of manufacturing a semiconductor device according to the first embodiment, the first support 10 of the polycrystalline structure SiC is directly bonded to the lower surface of the single crystal wafer 1 _sub of SiC, a single-crystal wafer 1 _sub A device structure is constructed on the upper surface of the thinned epitaxial growth wafer 1. As the first support 10, direct bonding layer also include a formed at the bonding interface of the direct bonding, since the polycrystalline SiC or the like which is a material that can withstand high temperatures is employed, for example, to dissolve in the SiO ₂ film Even when high-temperature epitaxial growth at about 1500 ° C. to about 1600 ° C. is performed, the bonding state can be maintained and the epitaxial growth wafer 1 can be firmly supported. Similarly, even when activation annealing at a high temperature of about 1600 ° C. or higher is performed, the epitaxial growth wafer 1 can be firmly supported while maintaining the bonding state.

Further, according to the method for manufacturing a semiconductor device according to the first embodiment, it is not necessary to use a resin adhesive or a material having low heat resistance for joining the first support 10 and the single crystal wafer 1 _sub. The bonding is not impaired by the high temperature activation annealing.

Further, according to the method of manufacturing a semiconductor device according to the first embodiment, since the first support 10 is made of polycrystalline SiC, it contains particles of various grain sizes, so that the single crystal wafer 1 _sub Regardless of the crystal orientation of the lower surface, the _bondability with the single crystal wafer 1 _sub can be improved.

  Further, according to the method of manufacturing a semiconductor device according to the first embodiment, the second support 5 is bonded to the upper surface of the epitaxial growth layer 2 to grow on the epitaxial growth wafer 1 or the epitaxial growth wafer 1. The strength of the epitaxial growth layer 2 is improved, and then the first support 10 is removed from the device wafer 100. Therefore, it is possible to prevent damage to the epitaxial growth wafer 1 made of an SiC substrate and the epitaxial growth layer 2 grown on the epitaxial growth wafer 1 where the mechanical strength is insufficient when the thickness is reduced. In addition, if the intensity | strength of the wafer 1 for epitaxial growth and the epitaxial growth layer 2 is ensured appropriately, the 2nd support body 5 is not essential.

  Further, according to the method of manufacturing a semiconductor device according to the first embodiment, after the device structure is constructed, the region on the side of the first support 10 that is bonded to the device wafer 100 is selectively oxidized to separate the oxide film 18. Then, the isolation oxide film 18 is removed to separate the remaining first support 10r from the device wafer 100. Therefore, it is possible to easily and simultaneously realize the execution of the high-temperature process and difficult thinning process unique to SiC and the separation of the first support 10 and the device wafer 100 after the process with good characteristics. The SiC semiconductor device provided with can be provided.

(First modification)
The convex portions of the first support are not limited to the convex portions as shown in FIGS. 1 and 2... 12 _i−1 , 12 _i , 12 _{i + 1} . As shown in the support 10a, convex portions 12a _i-1 , 12a _i , 12a _{i + 1} , etc. whose cross section appears in a trapezoidal shape may be used. In FIG. 5, the isosceles trapezoidal convex portion is sandwiched between 12 a _i-1 , 12 a _i , 12 a _{i + 1} and the convex portion ... 12 a _i-1 , 12 a _i , 12 a _{i + 1} . A reverse isosceles trapezoidal groove is illustrated. Similarly to the groove portion of the first support 10 shown in FIG. 2, the groove portion of the first support 10a shown in FIG. 5 also constitutes an oxidizing atmosphere passage that serves as a passage through which oxidizing gas is introduced. .

In FIG. 5, the width wa of the upper base of the trapezoidal shape of the convex parts 12a _i-1 , 12a _i , 12a _{i + 1} ... is shorter than the width wb of the lower base, The case where the width w1 is longer than the width w2 of the lower bottom is illustrated. In this way, even if the cross-sectional shape of the convex portions 12a _i-1 , 12a _i 12a _{i + 1} is trapezoidal, the upper surface of the convex portions 12a _i-1 , 12a _i 12a _{i + 1} ... The crystal wafer 1 _sub is bonded and supported, and the groove portion communicates with the atmosphere outside the first support 10 a to control the selective oxidation region.

(Second modification)
For example, as shown in FIG. 6 and FIG. 7, the convex portions... 12 b _i−1 , 12 b _i , 12 b _{i + 1} , and so on are formed so as to appear in stripes in a plane pattern when the first support 10 b is viewed from the top. It may be configured. The first support 10b is sandwiched between linearly extending convex portions 12b _i-1 , 12b _i , 12b _{i + 1} and the convex portions 12b _i-1 , 12b _i , 12b _{i + 1} . In addition, a linearly extending groove is illustrated.

Similarly to the groove portion of the first support 10 shown in FIG. 2, the groove portion of the first support 10b shown in FIG. 6 and FIG. Configure. Thus, even if it is the convex part ... 12b _i-1 , 12b _i , 12b _{i + 1} ... each extending linearly, it has an upper surface to be joined to the single crystal wafer 1 _sub, and the groove part is the first support. It can be controlled to form a selective oxidation region in communication with the external atmosphere of 10b.

(Third Modification)
Moreover, as shown in FIG. 8, you may comprise the 1st support body 10c whose upper surface is flat. As shown in FIG. 9, the first support 10 c is provided with a certain distance (thickness t) from the upper surface, and a plurality of holes extending along the upper surface at intervals in the same direction. ... 13 _i-1 , 13 _i , 13 _{i + 1} . The plurality of holes ... 13 _i-1 , 13 _i , 13 _{i + 1} ... are voids communicating with the atmosphere outside the first support 10c.

Similarly to the groove portion of the first support 10 shown in FIG. 2, the groove portion of the first support 10c shown in FIG. 8 and FIG. Configure. The thickness t of the upper region of the holes 13 _i-1 , 13 _i , 13 _{i + 1} ... is set to about 1 μm or less, for example, as a thickness that can be removed by oxidation and etching. As a method for producing the holes 13 _i-1 , 13 _i , 13 _{i + 1} , etc., a stripe resist pattern is formed on the upper surface of the SiC substrate 10 _sub and then as described with reference to FIG. It can be formed by forming a trench-like gap by etching and then backfilling only the opening side of the gap.

Thus, even if the upper surface of the first support 10c does not have an opening, it has an upper surface to be bonded to the single crystal wafer 1 _sub, and the lower hole portion 13 _i-1 , 13 _i , 13 It is possible to control _{i + 1 to} communicate with the atmosphere outside the first support 10c so that a selective oxidation region is formed. If the isolation oxide film 18 is formed by using the holes 13 _i-1 , 13 _i , 13 _{i + 1} as an oxidation atmosphere passage, and then the isolation oxide film 18 is removed by etching, the semiconductor according to the present invention is formed. It can be used in the manufacturing method of the device.

(Fourth modification)
Further, FIG. 10 illustrates a first support 10d according to a fourth modification example in which the upper surface of the base 11 is divided into five regions of a first region 11a to a fifth region 11e in consideration of the plane orientation of SiC. ing. For convenience of explanation, the projections provided on the base 11 are not shown.

  Of the first region 11a to the fifth region 11e, the first region 11a to the fourth region 11d arranged on the outer peripheral side of the first support 10d are all flat and have a blade shape. On the other hand, the fifth region 11e disposed in the center of the first support 10d and surrounded by the first region 11a to the fourth region 11d has a substantially square shape. The first region 11a to the fifth region 11e are separated by a groove provided between adjacent regions.

In the first support 10d shown in FIG. 10, the grooves between the first region 11a to the fifth region 11e and the grooves between the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} . An oxidizing atmosphere passage that serves as a passage through which the active gas is introduced is formed. In this way, the upper surface of the base portion 11 is divided into a plurality of regions by the grooves, and the convex portions... 12 _i-1 , 12 _i , 12 _{i + 1} ... As shown in FIG. The oxidation treatment in the vicinity of the bonding interface between the single support 10d and the single crystal wafer 1 _sub can be performed more easily.

(5th modification)
As the first support 10e, first, a SiC substrate, which is a material that can withstand high temperatures, such as activation annealing, such as a polytype single crystal such as 4H or 6H, is prepared. Then, as shown in FIG. 11, the base 16 is formed by forming the uneven shape similar to FIG. 2B on the top of the SiC substrate, and then the polycrystalline SiC thin film 17 is formed on the uneven shape of the base 16. May be.

(Sixth Modification)
As the first support 10f, for example, a SiC substrate 10 _sub , which is a material that can withstand high temperatures such as activation annealing such as 4H, 6H polytype single crystal, is prepared as shown in FIG. . Then, after a polycrystalline SiC thin film is formed on at least one flat surface of the SiC substrate 10 _sub , convex portions... 19 _i-1 , 19 _i , 19 _{i + 1} . An uneven pattern may be formed by providing.

<Second Embodiment>
A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. The semiconductor device manufacturing method according to the second embodiment is equivalent to the processing shown in FIGS. 3A to 3D using the first support 10 described in the first embodiment. The same processing is the same. However, as shown in FIG. 13A, after the first support 10 is oxidized to form an isolation oxide film, the interlayer insulating film 14 and the barrier layer 15 are formed as shown in FIG. Then, as shown in FIGS. 13 (c) and 13 (d), contact holes that expose a part of the upper surfaces of the plurality of semiconductor layers 3a to 3d are opened by using a photolithography technique and an RIE method, etc. The difference is that a plurality of surface contact electrodes 6 a to 6 d and surface electrodes 21 a to 21 d are provided on the surface of 100 epitaxial growth layers 2.

Specifically, after forming the isolation oxide film 18 on the first support 10, as shown in FIG. 13B, an interlayer insulating film 14 such as a SiO ₂ thin film is grown by n-type epitaxial growth by CVD or the like. Deposit on layer 2. Further, a SiN thin film is formed as a barrier layer 15 on the interlayer insulating film 14, a photoresist film is applied thereon, and the interlayer insulating film 14 is selectively etched using a photolithography technique, an RIE method, etc. After opening a contact hole in the interlayer insulating film 14 and the barrier layer 15 where a part of the upper surface of the p-type semiconductor layers 3a to 3d is exposed, the photoresist film is removed.

  Further, as shown in FIG. 13C, a metal thin film made of Ni, Mo, Ti or the like is formed on the interlayer insulating film 14 and the barrier layer 15 in which the contact holes are opened by a sputtering method, a vacuum evaporation method, a CVD method. Deposit by the method. A photoresist film is applied on the metal thin film, the metal thin film is selectively etched using a photolithography technique, an RIE method, and the like, and appropriate annealing is performed, so that the upper surfaces of the plurality of p-type semiconductor layers 3a to 3d are formed. Ohmic electrodes 6a to 6d that are in ohmic contact are formed.

  Further, as shown in FIG. 13 (d), a metal thin film such as Al or Al alloy is formed on the entire surface of the interlayer insulating film 14 and the barrier layer 15 in which the contact holes are opened, by sputtering, vacuum deposition, or CVD. Etc. If a photoresist film is applied on the metal thin film, and the metal thin film is selectively etched using a photolithographic technique and an RIE method, the patterns of the surface electrodes 21a to 21d are formed. Hereinafter, the device wafer 100 on which the surface electrodes 21a to 21d are formed is referred to as a device wafer 102.

Next, as shown in FIG. 13E, the second support 5 is provided on the insulating film on the epitaxial growth layer 2 and the barrier layer 15 with the adhesive layer 4 interposed therebetween. Thereafter, the vicinity of the bonding interface between the first support 10 and the device wafer 102, the protrusions ... 12 _i-1 , 12 _i , 12 _{i + 1} ... and the side surface of the base 11 of the first support 10 are etched. The isolation oxide film 18 is removed by HF or the like, and the first support 10r and the device wafer 102 are separated as shown in FIG.

Next, as shown in FIG. 14B, an n ⁺ -type back contact layer 7 having a higher concentration than the epitaxial growth wafer 1 is formed below the device wafer 102 as necessary. Further, a Ni layer is formed on the lower surface of the device wafer 102 or the back contact layer 7 and annealed at a necessary temperature. Further, a Ni, Au film or the like is formed on the lower surface of the Ni film to form the back electrode layer 8. Hereinafter, the device wafer 102 on which the back electrode layer 8 is formed is referred to as a device wafer 103. When the formation temperature of the back contact layer 7 and the back electrode layer 8 becomes a problem, the pattern of the surface electrodes 21a to 21d may be composed of a metal thin film of a refractory metal instead of a metal thin film such as Al or Al alloy. Next, as shown in FIG. 14C, the back electrode layer 8 side of the device wafer 103 is attached and fixed to the adhesive tape 9, and the adhesive layer 4 is removed to remove the second on the upper surface side of the device wafer 103. The support 5 is separated.

  According to the method of manufacturing a semiconductor device according to the second embodiment, as in the case of the first embodiment, the high-temperature process unique to SiC and the difficult thinning process are performed, and the first after the process is performed. The support 10 and the device wafer 102 can be easily and simultaneously separated. Furthermore, according to the method for manufacturing a semiconductor device according to the second embodiment, a more complicated semiconductor device having electrodes as the surface structure of the device wafer 100 can be manufactured. The other effects of the semiconductor device manufacturing method according to the second embodiment are the same as the effects of the semiconductor device manufacturing method according to the first embodiment.

<Third Embodiment>
A method for manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS. The method for manufacturing a semiconductor device according to the third embodiment uses the first support body 10 described in the first embodiment, and the steps of FIGS. 3 (a) to 3 (e) and the second embodiment are performed. It is the same in that processing equivalent to the processing shown in FIGS. 13A and 13B described in the embodiment is performed. However, a contact hole in which a part of the upper surface of the semiconductor layers 3a to 3d is exposed is opened in the interlayer insulating film 14 and the barrier layer 15, and a plurality of surface electrodes 6a to 6d are formed on the surface of the device wafer 100, and the device wafer The second support 5 is bonded to the upper surface of the device 100 via the adhesive layer 4, the isolation oxide film 18 is removed to separate the first support 10 r from the device wafer 100, and the lower surface of the device wafer 100 is The third support 20 is bonded via the adhesive layer 4, and further bonded to the fourth support 30 via the oxide film on the upper surface of the device wafer 100, and contact formation on the lower surface of the device wafer 100 is performed by a high temperature process. Thereafter, the fourth support 30 and the device wafer 100 are separated by removing the oxide film with HF. The “fourth support body 30” corresponds to the “second support body” of the present invention.

  Specifically, as shown in FIG. 15A, the contact in which part of the upper surfaces of the plurality of semiconductor layers 3 a to 3 d are exposed on the interlayer insulating film 14 and the barrier layer 15 using photolithography technique, RIE method, or the like. A hole is opened and a plurality of surface electrodes 6 a to 6 d are formed on the surface of the device wafer 100.

  Subsequently, as shown in FIG. 15B, a second support 5 having a disk shape with substantially the same radius as that of the device wafer 100 is bonded to the upper surface of the device wafer 100 via the adhesive layer 4. The adhesive layer 4 can be formed using a known adhesive such as a resin.

  Next, as shown in FIG. 15C, for example, with hydrofluoric acid (HF), the vicinity of the bonding interface between the first support 10 and the device wafer 100, the entire convex portion, and the base 11 of the first support 10. The side separation oxide film 18 is removed, and the first support 10 r is separated from the device wafer 100.

Subsequently, as shown in FIG. 15D, a third disk having a disk shape with substantially the same radius as the device wafer 100 is formed on the lower surface of the device wafer 100 from which the first support 10 r has been separated via the adhesive layer 4. The support 20 is joined. The third support member 20 may be, for example, Si or SiC, a material such as SiO _2. The adhesive layer 4 can be formed using a known adhesive such as a resin.

Next, as shown in FIG. 15 (e), the second support 5 is removed from the device wafer 100. In addition, in FIG.15 (e), the adhesive layer 4 under the removed 2nd support body 5 is removed.
Subsequently, as shown in FIG. 15 (f), a silicon oxide (SiO ₂ ) thin film 23 is formed on the surface of the device wafer 100. Here, the formation temperature of the thin film is a temperature that the adhesive layer 4 with the support 20 can withstand. Subsequently, the upper surface of the silicon oxide thin film 23 may be flattened by a known method such as polishing, and the flatness is preferably 1 nm or less in terms of arithmetic average roughness Ra. Thereafter, it is desirable to remove residues and damage due to processing by a predetermined cleaning process.

Next, as shown in FIG. 16A, the fourth support 30 is bonded to the SiO ₂ thin film 23 formed on the surface of the device wafer 100. Similar to the first support 10, the fourth support 30 has a disk shape having substantially the same radius as the device wafer 100, and has a number of convex portions on one surface on the device wafer 100 side. In addition, a direct legal method such as a surface activation method can be used for bonding. The SiO ₂ thin film 23 formed on the surface of the fourth support 30 and the device wafer 100 is irradiated with an Ar atom beam, and after forming a Si layer on the SiO ₂ thin film 23 by sputtering, the irradiated surfaces are By bringing them into contact, a bonded state is formed through the amorphous layer. Note that the Si layer may be formed on at least one of the fourth support 30 and the SiO ₂ thin film 23.

Then, as shown in FIG.16 (b), the 3rd support body 20 is removed. Subsequently, as shown in FIG. 16C, in order to reduce the contact resistance, an n ⁺ -type back contact layer 7 having a higher concentration than the epitaxial growth wafer 1 is formed on the lower surface of the device wafer 100. Also good. Further, an ohmic contact is formed by forming a Ni layer on the lower surface of the device wafer 100 or the back contact layer 7 and performing a high-temperature annealing process at about 1000 ° C. At this time, since there is no non-heat resistant material such as an adhesive, the entire device wafer 100 can be subjected to a high temperature treatment.

Further, a back electrode layer 8 is formed by forming a thin film of Ni, Al, Au or the like on the heat-treated Ni film. Subsequently, as shown in FIG. 16D, the SiO ₂ thin film 23 in the vicinity of the bonding interface between the fourth support 30 and the device wafer 100 is removed by, for example, hydrofluoric acid, and the fourth support 30 The device wafer 100 is separated. If the necessary strength cannot be maintained in the device wafer 100, the fifth support 40 may be attached to the back electrode layer 8 as shown in FIG. The fifth support 40 may be a tape material other than the disk-like one like the first support 10.

(Seventh Modification)
For example, as shown in FIG. 17, the lower part of the fourth support 30 is flat, and the silicon oxide thin film 23 formed on the upper surface of the device wafer 100 has a concavo-convex shape 24 by a known technique such as photolithography / etching. Other than the above, the same effect can be obtained also in the case similar to the third embodiment.

  According to the method of manufacturing a semiconductor device according to the third embodiment, as in the case of the first embodiment, the high-temperature process unique to SiC and the difficult thinning process are performed, and the first after the process is performed. The support 10 and the device wafer 100 can be easily and simultaneously separated. Furthermore, according to the method for manufacturing a semiconductor device according to the third embodiment, the fourth support 30 and the device wafer 100 can be easily separated even on the surface side of the device wafer 100. Other effects of the semiconductor device manufacturing method according to the third embodiment are the same as the effects of the semiconductor device manufacturing method according to the first embodiment.

(Other embodiments)
Although the present invention has been described by the first to third embodiments disclosed above, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, it should be understood that various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art.

For example, FIG. 1 shows a case in which a plurality of prismatic convex portions 12 _i−1 , 12 _i , 12 _{i + 1 1} are arranged in a lattice at equal intervals, but the convex portions 12 The shape of _i-1 , _12i , _{12i + 1,} ... is not limited to this. For example, the intervals between the plurality of convex portions 12 _i-1 , 12 _i , 12 _{i + 1 1} are not uniform and may be non-uniformly arranged on the upper surface of the base 11 as long as they can be oxidized through the groove. . Moreover, the cross-sectional shape of convex part ... _{12i- 1,12i} , _{12i + 1} ... may be V shape, a semicircle shape, or U shape.

  In addition, as a bonding method, not only direct bonding, but also an intermediate layer is formed on a surface to be bonded to either or both of the support body such as the first support body 10 and the fourth support body 30 and the device wafer 100, You may carry out through this intermediate | middle layer. As the intermediate layer, a very thin film, for example, a thin Si film or SiC film having a thickness of about 20 nm or less can be employed. The intermediate layer may be a film having a thickness of about one molecular layer or a very thin film on the order of several nm such as a monoatomic film.

  Further, for example, as shown in FIG. 4C, after the first support 10 and the device wafer 100 are separated, the unevenness on the surface of the first support 10r from which the oxide film has been removed is removed by a known polishing method or the like. It is possible to use it again as a new first support 10 by removing and flattening it. By reusing an expensive SiC substrate, the manufacturing cost can be reduced.

  Further, as the device wafer 100, the case where single crystal SiC is used has been described as an example. However, if the difference in oxidation rate with respect to the support is taken into consideration, polycrystalline SiC may be used, and any type of SiC crystal may be used. Even so, the present invention can be applied. Also, the semiconductor device manufacturing method according to the present invention can be configured by partially combining the structures shown in FIGS. As described above, the present invention includes various embodiments and the like not described above, and the technical scope of the present invention is defined only by the invention specifying matters according to the appropriate claims from the above description. Is.

DESCRIPTION OF SYMBOLS 1 Epitaxial growth wafer 1 _Sub single crystal wafer 2 Epitaxial growth layer 3a-3d Semiconductor layer 4 Adhesion layer 5 2nd support body 6a-6d Surface electrode 7 Back surface contact layer 8 Back surface electrode layer 9 Tape 10, 10a-10f, 10r 1st Support 10 _Sub SiC substrate 11 Base 11a to 11e First region to fifth region 12 _i , 12a _i , 12b _i Protruding portion 13 _i Hole portion 14 Interlayer insulating film 15 Barrier layer 16 Base portion 17 SiC thin film 18 Isolation oxide film 19 _i protrusion 20 third supporting member 20a body 21a~21d surface electrode 23 SiO ₂ thin film 24 irregularities 30 fourth support member 40 fifth support 100-103 height t distance device wafer h projection (thickness )
w, wa, wb Width of convex part p, w1, w2 Width of groove part

Claims (21)

Bonding the first support to the lower surface of the single crystal wafer mainly composed of silicon carbide;
Thinning the upper surface side of the single crystal wafer defined on the opposite side of the first support;
Building a device structure on the upper surface side of the single crystal wafer to form a device wafer;
Oxidizing the region of the interface where the first support and the device wafer are joined to form an isolation oxide film;
Separating the remaining first support and the device wafer by removing the isolation oxide film;
A method for manufacturing a semiconductor device, comprising: After the thinning step, further comprising the step of growing an epitaxial growth layer on the upper surface side of the thinned single crystal wafer,
The method of manufacturing a semiconductor device according to claim 1, wherein the device structure is constructed in the epitaxial growth layer.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first support is one of polycrystalline silicon carbide and single crystal silicon carbide formed with polycrystalline silicon carbide. 4.   The surface of the first support on the single crystal wafer side is provided with a plurality of protrusions, and a groove serving as an oxidizing gas introduction path is provided between the plurality of protrusions. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The method for manufacturing a semiconductor device according to claim 4, wherein a width of an upper surface of the convex portion is 0.1 μm or more and 3 μm or less.   6. The method of manufacturing a semiconductor device according to claim 4, wherein a width of the groove is 0.1 μm or more and 3 μm or less.   The method of manufacturing a semiconductor device according to claim 4, wherein the groove portion communicates with the outside of the first support.   The first support is provided at a certain distance from the upper surface on the single crystal wafer side, and further includes a hole extending along the upper surface as an introduction path for oxidizing gas. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the hole portion communicates with the outside of the first support.   The method of manufacturing a semiconductor device according to claim 9, wherein the certain distance is 1 μm or less.   The manufacturing method of a semiconductor device according to claim 1, wherein the step of bonding the first support is a direct bonding of the first support and the single crystal wafer. Method. Before the direct bonding of the first support and the single crystal wafer, further comprising the step of forming an amorphous bonding layer on at least one of the surface of the first support and the surface of the device wafer;
The method of manufacturing a semiconductor device according to claim 11, wherein the first support and the single crystal wafer are directly bonded via the amorphous bonding layer. Before the step of bonding the first support, further comprising the step of forming a first intermediate layer on at least one bonding surface of the first support and the single crystal wafer;
The method for manufacturing a semiconductor device according to claim 1, wherein the first support and the single crystal wafer are bonded to each other through the first intermediate layer.   14. The method of manufacturing a semiconductor device according to claim 13, wherein the first intermediate layer includes at least silicon and has a thickness of 20 nm or less. Forming a silicon oxide thin film on the upper surface side of the remaining device wafer by removing the isolation oxide film; and
Bonding the upper surface side of the device wafer formed with the silicon oxide thin film to a second support;
Forming ohmic contacts and electrodes on the lower surface side of the device wafer;
Separating the second support and the device wafer by removing the silicon oxide thin film;
The method of manufacturing a semiconductor device according to claim 1, further comprising:   The method of manufacturing a semiconductor device according to claim 15, wherein the step of bonding to the second support is a direct bonding of the second support and the silicon oxide thin film.   The device wafer side surface of the second support is provided with a plurality of protrusions, and a groove serving as an oxidizing gas introduction path is provided between the plurality of protrusions. Item 16. A method for manufacturing a semiconductor device according to Item 15.   The surface on the second support side of the silicon oxide thin film is provided with a plurality of protrusions, and a groove serving as an oxidizing gas introduction path is provided between the plurality of protrusions. Item 16. A method for manufacturing a semiconductor device according to Item 15. Before the direct bonding of the second support and the device wafer, further comprising forming an amorphous bonding layer on at least one of the surface of the second support and the surface of the device wafer;
The method for manufacturing a semiconductor device according to claim 16, wherein the second support and the device wafer are directly bonded via the amorphous bonding layer. Before the step of bonding the second support, further comprising the step of forming a second intermediate layer on the bonding surface of at least one of the second support and the device wafer;
The method of manufacturing a semiconductor device according to claim 15, wherein the second support body and the device wafer are bonded to each other through the second intermediate layer.   21. The method of manufacturing a semiconductor device according to claim 20, wherein the second intermediate layer includes at least silicon and has a thickness of 20 nm or less.

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