JPH10125905A - Semiconductor substrate, and method for correcting warping of semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the warping of a semiconductor substrate having an epitaxial layer by forming grooves on the surface of the epitaxial layer and carrying out heat-treating to correct the substrate from warping. SOLUTION: Grooves 4 of 30μm wide, 5μm deep are cut into the surface of an SiC substrate by the photolithography in the orientations <11-00> and <112-0> in a shape of a grid with spacings of 5mm. Then the substrate is set in a heater to heat-treat it in an Ar atmosphere at 1500 deg.C for 10min to relax the internal stress caused at the time of forming of epitaxial layers 2, 3, and the grooves serve for correcting the warping of the substrate. After correction of the SiC substrate, a MOSFET is formed as a semiconductor element on this substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate such as a silicon carbide substrate having an epitaxial layer formed on a semiconductor layer, the semiconductor substrate having a corrected warp, and a method for correcting the warp. A method for manufacturing a silicon carbide semiconductor device using a manufactured silicon carbide substrate.

[0002]

2. Description of the Related Art Conventionally, silicon carbide (hereinafter referred to as SiC) has been used.
Semiconductor device is trench gate type SiC power MOSF
The one used for ET is disclosed in Japanese Patent Application Laid-Open No. 7-326755,
Alternatively, it is disclosed in JP-A-8-70124. This SiC power MOSFET has excellent characteristics such as low on-resistance and high withstand voltage. FIG. 13 shows a sectional configuration thereof.

An n ^-- type epitaxial layer (high-resistance layer) 2 is provided on a hexagonal n ⁺ -type single-crystal SiC semiconductor substrate (low-resistance semiconductor layer) 1 having a (0001-) carbon plane. And a p-type epitaxial layer 3 are sequentially stacked,
The SiC substrate 100 is configured. An n ⁺ source region 5 as a semiconductor region is formed in the p-type epitaxial layer 3, and a trench 6 penetrating through the n ⁺ source region 5 and the p-type epitaxial layer 3 to reach the n ⁻ -type epitaxial layer 2 Are formed. A gate thermal oxide film 7 is formed in the trench 6, and a gate electrode layer 8 (8
a, 8b) are formed. Further, an interlayer insulating film 9,
On the surface of the n ⁺ source region 5 and the surface of the p-type epitaxial layer 3, a source electrode layer 10 as a first electrode layer is provided.
Is formed, and a drain electrode layer 11 as a second electrode layer is formed on the back surface of the semiconductor substrate 1.

In the above configuration, the side surface 6a of the trench 6
The surface of the p-type epitaxial layer 3 is a channel, and when a positive voltage is applied to the gate electrode 8 to form a channel, a current flows between the source and the drain.

[0005]

However, when a thin epitaxial layer (epitaxially grown film) is deposited and formed on a semiconductor substrate, the substrate is warped due to internal stress generated during the formation of the epitaxial layer. Such a warp causes a shift in mask alignment when manufacturing a semiconductor element. In particular, as the size of the semiconductor substrate increases, the problem of warpage becomes more pronounced. According to the experiments by the present inventors, when the diameter of the SiC substrate 100 is set to 1 inch or more, the problem of mask misalignment due to the warp of the SiC substrate 100 becomes significant.

The present invention has been made in view of the above problems, and has as its object to reduce warpage of a semiconductor substrate having an epitaxial layer.

[0007]

According to the first aspect of the present invention, there is provided a semiconductor substrate in which an epitaxial layer is formed on a semiconductor layer and before a semiconductor element is formed. A groove is formed on the surface of the epitaxial layer, and the warp is corrected by a heat treatment.

[0008] Since the internal stress generated during the formation of the epitaxial layer is reduced by the heat treatment after the formation of the groove, a semiconductor substrate in which the warp has been corrected can be obtained. in this case,
If a plurality of grooves are formed as described in claim 2, the effect of the warp correction can be increased. In the third aspect, the plane orientation of the surface is substantially (0001).
-) By applying the present invention to a SiC substrate having a carbon surface, a warped SiC substrate can be obtained.

In this case, as in the invention according to the fourth aspect, a lattice formed in the <11-00> and <112-0> directions, or as in the invention according to the fifth aspect, It can be hexagonal. When the grooves are formed in a lattice shape, they can also be used as scribe lines when dicing and cutting the semiconductor chip. In the invention described in claim 6, the semiconductor layer and the epitaxial layer have a 4H-type crystal structure. When applied to a 4H-type crystal structure, the effect of straightening is greater than that of a 6H-type crystal structure.

According to the present invention, the first conductive type epitaxial layer and the second conductive type epitaxial layer are laminated on the first conductive type semiconductor layer, and the second conductive type epitaxial layer is formed on the first conductive type epitaxial layer. Surface orientation is approximately (0001-)
The present invention can be applied to a SiC substrate having a carbon surface to obtain a warped SiC substrate. The SiC substrate thus formed can be used for manufacturing a SiC semiconductor device such as a SiC power MOSFET.

In this case, if the groove has a depth that penetrates the epitaxial layer of the second conductivity type and reaches the epitaxial layer of the first conductivity type, the warpage can be sufficiently corrected. Can be done. According to a ninth aspect of the present invention, there is provided a semiconductor substrate warpage correcting method in which a groove is formed on a surface of a semiconductor substrate, and a heat treatment is performed after the groove is formed to correct the semiconductor substrate.

According to this method, the internal stress generated during the formation of the epitaxial layer by the heat treatment after the formation of the groove can be relaxed, and the warpage of the semiconductor substrate can be corrected. The invention according to claim 10 is characterized in that, after forming a groove on the surface of the semiconductor substrate and chamfering the end of the semiconductor substrate, a heat treatment is performed to correct the warpage of the semiconductor substrate, and the method for correcting warpage of the semiconductor substrate is characterized by this. I have.

By chamfering the edge in addition to forming the groove, the warpage of the semiconductor substrate can be corrected more favorably. According to the eleventh aspect of the present invention, an epitaxial layer is formed on a semiconductor layer of SiC, and a surface orientation of the surface is a (0001-) carbon plane and a diameter of 1 inch or more. The method is characterized in that a groove is formed, and after the groove is formed, a heat treatment is performed to correct the warpage of the SiC substrate.

As described above, even in a SiC substrate having a diameter of 1 inch or more, the warpage can be corrected. Claim 12
In the invention described in (1), the above-described SiC power MOS
In a method for manufacturing a SiC semiconductor device such as an FET,
The heat treatment temperature for correcting the warp of the SiC substrate
The process is performed at a temperature higher than any subsequent process temperature.

Therefore, when a semiconductor element is formed using a warped SiC substrate, the warpage of the SiC substrate does not change, and the problem of mask misalignment does not occur.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is described below with reference to a SiC power MO.
An embodiment when applied to an SFET will be described.
1 to 10 show steps of manufacturing a SiC power MOSFET. First, as shown in FIG. 1, the carrier density is 1 × on the surface of a low-resistance n ⁺ -type single-crystal SiC semiconductor substrate 1 having a (0001−) carbon plane.
An n ⁻ -type epitaxial layer 2 having a thickness of about ³ to 4 μm and about 10 ¹⁶ cm ⁻³ and a p-type epitaxial layer 3 having a carrier density of about 1 × 10 ¹⁷ cm ⁻³ and a thickness of 2 μm are sequentially laminated.
An SiC substrate (wafer) 100 is formed. In this case, since the crystal axis of the semiconductor substrate 1 is inclined about 3.5 ° to 8 ° with respect to the axis perpendicular to the (0001-) carbon plane, the plane orientation of the main surface of the p-type epitaxial layer 3 is substantially (0001
-) It becomes a carbon surface. Note that the SiC substrate 100 has a diameter of 1 inch or more.

Next, a process for correcting the warp of the SiC substrate 100 is performed. First, as shown in FIG.
A plurality of grooves 4 are formed on the surface of the C substrate 100 by using a photolithography technique. The grooves 4 have a width of 30 μm and a depth of 5 μm, and are formed in a lattice pattern at 5 mm intervals in the <11-00> and <112-0> directions as shown in FIG. Since the semiconductor chip of the SiC power MOSFET is formed in a region surrounded by the groove 4, the groove 4 can also be used as a scribe line when the semiconductor chip is cut out by dicing.

After the grooves 4 are formed, as shown in FIG. 3, the SiC substrate 100 is placed in the heater 20 and heat-treated at 1500 ° C. for 10 minutes in an argon atmosphere. By this heat treatment, the internal stress generated during the formation of the epitaxial layers 2 and 3 is relaxed, the surface of the SiC substrate 100 is easily moved by the groove 4, and the warpage of the SiC substrate 100 is corrected.

Thereafter, the MOSFET as a semiconductor element is placed on the SiC substrate 100 whose warpage has been corrected by the above-described process.
To form First, as shown in FIG. 4, the p-type epitaxial layer 3 is ion-implanted with the mask material 12 using a mask material 12 so that the carrier concentration on the surface is about 1 × 10 ¹⁹ cm ⁻³ and the junction depth becomes 0.5 μm. ^{+ A} source region 5 is formed.

Next, after the mask material 12 is removed, the n ⁺ source region 5 and the p-type epitaxial layer 3 are penetrated by reactive ion etching (RIE) using the mask material 13 as shown in FIG. Then, a trench 6 having a depth of 2.7 μm reaching the n ⁻ type epitaxial layer 2 is formed. The trench 6 has a side surface 6 a perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface 6 b parallel to the surface of the p-type epitaxial layer 3.

In this SiC power MOSFET, since the leakage current is minimized when the channel surface is set to the (112-0) plane, the side surface 6a of the trench 6 is approximately <1.
12-0> direction. Thereafter, as shown in FIG. 6, a thermal oxide film 15 as a sacrificial oxide film is formed on the inner wall of the trench by a thermal oxidation method at 1100 ° C. for about 5 hours. This thermal oxidation oxidizes the damaged layer on the inner wall of the trench formed by the RIE method. In addition,
The thermal oxide film 15 has a thickness of 50 n on the side surface 6 a of the trench 6.
m, the thickness at the bottom surface 6b of the trench 6 becomes 500 nm.

Then, as shown in FIG. 7, after removing the thermal oxide film 15 with hydrofluoric acid, the mask material 13 is removed. By removing the thermal oxide film 15, the damaged layer on the inner wall of the trench is removed. Next, as shown in FIG. 8, the gate thermal oxide film 7 is
This is formed by a single thermal oxidation process for about a time.
m thin gate thermal oxide film 7a and bottom surface 6b of trench 6
Gate thermal oxide film 7b having a thickness of 500 nm
Is formed. Further, a thick gate thermal oxide film 7c having a thickness of 500 nm is formed on n ⁺ source region 5.

Subsequently, as shown in FIG. 9, the inside of the trench 6 is sequentially filled with the first and second polysilicon layers 8a and 8b. Thereafter, the first and second polysilicon layers 8a,
On the gate thermal oxide film 7 including on the gate oxide film 8b, an interlayer insulating layer 9 is formed by CVD, and n
^{+ The} gate thermal oxide film 7 and the interlayer insulating layer 9 on the surface of the source region 5 and the p-type epitaxial layer 3 are removed. Then, a source electrode layer 10 is formed on the n ⁺ source region 5, the p-type epitaxial layer 3, and the interlayer insulating layer 9, and
Forming a drain electrode layer 11 on the back surface of the semiconductor substrate 1;
The SiC power MOSFET shown in FIG. 13 is completed.

The above-mentioned SiC power MOSFET
Are formed in an integrated manner in a cell region, and a guard ring is formed on the outer periphery of the cell region. This guard ring is formed as follows. In the outer peripheral portion of the cell region shown in FIG. 10, a groove 16 is formed simultaneously with the formation of the trench 6 shown in FIG. Then, after performing the formation and removal processing of the sacrificial oxide film 15 shown in FIGS. 6 and 7, a mask material 17 is formed and ion implantation is performed, and after removing the mask material 17, a heat treatment at 1300 ° C. is performed. A guard ring 18 is formed.

The heat treatment temperature of 1300 ° C. for forming the guard ring 18 is the highest among the process temperatures in the steps after FIG. 4, but the heat treatment temperature for warp correction shown in FIG. Is higher, the warpage of the SiC substrate 100 does not change in the steps after FIG. Therefore, the problem of misalignment of the mask does not occur in the steps after FIG. Note that FIG.
The heat treatment temperature for warp correction shown in FIG.
A temperature above 2000C and below 2000C is preferred.

In the above-described embodiment, the warp is formed by forming the groove 4 in the SiC substrate 100. However, as shown in FIG. The ends of both sides may be chamfered (end face polished at 0.5 mm C) and the heat treatment shown in FIG. 3 may be performed to correct the warpage. By performing this chamfering, the warpage can be corrected more favorably.

The shape of the groove 4 is not limited to the lattice shape shown in FIG. 2B, but may be a hexagonal shape shown in FIG. Further, as the SiC substrate 100, there is a 6H-type or 4H-type crystal structure.
It was confirmed that the 4H type had a greater effect of warpage correction than the 6H type.

In the present specification, when the plane orientation and the like of a hexagonal single crystal SiC are to be expressed, a bar should be added to a required number as shown in the drawing. However, due to restrictions on the means of expression, a required number is indicated by a "-" instead of a bar over the required number.

[Brief description of the drawings]

FIG. 1 shows a SiC power MO according to an embodiment of the present invention.
FIG. 10 is a cross-sectional view for describing an initial manufacturing step of the SFET.

FIG. 2 is a cross-sectional view for explaining a step of forming a plurality of grooves 4 on the surface of a SiC substrate 100 in a manufacturing step following FIG.

FIG. 3 is a view showing a manufacturing process following FIG.
FIG. 9 is a cross-sectional view for explaining a step of correcting a warp of the substrate 100.

FIG. 4 is a cross-sectional view for explaining a step of forming an n ⁺ source region 5 in a manufacturing step following FIG. 3;

FIG. 5 is a cross-sectional view for explaining a step of forming a trench 6 in a manufacturing step following FIG. 4;

FIG. 6 is a cross-sectional view for describing a step of forming a sacrificial oxide film 15 in a manufacturing step following FIG. 5;

FIG. 7 is a cross-sectional view for explaining a step of removing the sacrificial oxide film 15 in a manufacturing step following FIG. 6;

FIG. 8 is a cross-sectional view for explaining a step of forming a gate thermal oxide film 7 in a manufacturing step following FIG. 7;

FIG. 9 shows a gate electrode layer 8 (8
FIGS. 7A and 7B are cross-sectional views for explaining a step of forming (a, 8b).

FIG. 10 is a cross-sectional view for explaining a step of forming a guard ring 18.

FIG. 11 is a sectional view showing a modification of the step shown in FIG. 2;

FIG. 12 is a view showing a modification of the groove 4 formed on the surface of the SiC substrate 100.

FIG. 13 is a sectional view of a SiC power MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate as a low resistance semiconductor layer, 2 ... N ^- type epitaxial layer as a high resistance semiconductor layer, 3 ... P-type epitaxial layer as a semiconductor layer of the second conductivity type, 4 ... Groove,
5 n ⁺ source region as semiconductor region, 6 trench, 7 gate thermal oxide film, 8 gate electrode layer, 10 source electrode layer as first electrode layer, 11 as second electrode layer Drain electrode layer, 18 ... guard ring, 20 ...
Heater, 100 ... SiC substrate.

Claims (12)

[Claims] 1. A semiconductor substrate in which an epitaxial layer is formed on a semiconductor layer and before a semiconductor element is formed, wherein a groove is formed on a surface of the epitaxial layer, and warpage is corrected by heat treatment. substrate. 2. The semiconductor substrate according to claim 1, wherein a plurality of said grooves are formed. 3. A silicon carbide substrate in which an epitaxial layer is formed on a semiconductor layer of silicon carbide, the surface orientation of which is substantially a (0001-) carbon plane, and before a semiconductor element is formed, A silicon carbide substrate in which a groove is formed in the surface and the warp is corrected by a heat treatment. 4. The groove has <11-00> and <112-
The silicon carbide substrate according to claim 3, wherein the silicon carbide substrate is formed in a 0> direction and has a lattice shape. 5. The silicon carbide substrate according to claim 3, wherein said groove is formed in a hexagonal shape. 6. The silicon carbide substrate according to claim 3, wherein said semiconductor layer and said epitaxial layer have a 4H-type crystal structure. 7. A first conductivity type epitaxial layer and a second conductivity type epitaxial layer are stacked on a first conductivity type semiconductor layer, and the surface orientation of the second conductivity type epitaxial layer is approximately ( 0001-) a carbon surface, which is a silicon carbide substrate before a semiconductor element is formed, wherein a groove is formed on the surface of the second conductivity type epitaxial layer;
A silicon carbide substrate whose warpage has been corrected by heat treatment. 8. The silicon carbide substrate according to claim 7, wherein said groove has a depth penetrating said second conductivity type epitaxial layer and reaching said first conductivity type epitaxial layer. . 9. A semiconductor substrate in which an epitaxial layer is formed on a semiconductor layer and before a semiconductor element is formed, a groove is formed on a surface of the semiconductor substrate, and after forming the groove, a heat treatment is performed. A method for correcting warpage of a semiconductor substrate, comprising correcting the warpage of a semiconductor substrate. 10. A semiconductor substrate in which an epitaxial layer is formed on a semiconductor layer and before a semiconductor element is formed, wherein a groove is formed on a surface of the semiconductor substrate, and an edge of the semiconductor substrate is chamfered. Thereafter, a heat treatment is performed to correct the warpage of the semiconductor substrate. 11. An epitaxial layer is formed on a semiconductor layer of silicon carbide, has a surface orientation of substantially (0001-) carbon plane, and has a diameter of 1 inch or more before a semiconductor element is formed. A method for correcting warpage of a silicon carbide substrate, comprising: forming a groove on the surface of the silicon carbide substrate; and performing a heat treatment after forming the groove to correct the warpage of the silicon carbide substrate. 12. A first hexagonal semiconductor layer having a surface orientation of (0001-) carbon and a first conductivity type semiconductor layer.
A first step of preparing a silicon carbide substrate on which a conductive type epitaxial layer and a second conductive type epitaxial layer are formed; and forming a first conductive type semiconductor region in a predetermined region on the surface of the second conductive type epitaxial layer. A second step of forming; a third step of forming a trench that penetrates the semiconductor region and the epitaxial layer of the second conductivity type and reaches the epitaxial layer of the first conductivity type; and a gate thermal oxide film in the trench. A fourth step of forming a gate electrode layer inside the gate thermal oxide film in the trench, and a sixth step of forming a first electrode layer on at least a surface of the semiconductor region. Forming a second electrode layer on the back surface of the semiconductor substrate;
A method of manufacturing a silicon carbide semiconductor device having the steps of: forming a groove on the surface of the prepared silicon carbide substrate; and forming any of the second to seventh steps after forming the groove. Heat treatment at a temperature higher than the process temperature of
Correcting the warpage of the silicon carbide substrate before the second step.