JP5621153B2 - Game machine - Google Patents

Description

  The present invention relates to a pachislot machine, a pachinko machine, and other gaming machines.

  Conventionally, in a gaming machine such as a pachislot machine or a pachinko machine, a plurality of types of “special game states” that are advantageous to the player based on the “general game state” of the basic game state and satisfying predetermined conditions or lottery results, etc. “Game state” is set, and an effect using a decorative lamp, a liquid crystal display device, a sound generation device, or the like is executed in accordance with these various game states.

  In order to realize the determination of each game state and the execution of the effects, a main control circuit that mainly controls the setting of the game state and the game processing operation is transmitted to the inside of the gaming machine, and is transmitted from the main control circuit. A sub-control circuit for realizing an effect by light, video or audio based on the control signal is arranged.

  For example, the main control circuit of the pachislot machine includes a medal sensor for detecting that a player has inserted a game medium, a bet switch for setting an effective line for determining the success or failure of a winning combination, a start switch for rotating a reel, Stop switch for stopping rotation, other input means, stored number display for displaying the number of medals that have been credited, number-of-functions display, paid-out number display, winning display, other output means, reel rotation A sub-control circuit is connected to a reel motor drive circuit that displays a variation in symbols by performing control, a medal ejecting device that controls payout of game media, and other peripheral devices. The main control circuit performs processing based on information input from each input means, and performs game progress, symbol stop display, game medium payout, control of various output means, and the like.

  In conventional pachislot machines, information related to performance is generally transmitted by communication between a main control circuit and a sub-control circuit. However, each input means, each output means, and peripheral devices are controlled via a dedicated control line. Then, the wiring connecting the I / O of the main control circuit and the sub control circuit (hereinafter referred to as a control circuit when collectively referred to) to each input means, each output means, and peripheral devices is preferably 100. Beyond books.

  If a large number of wires are connected to the control circuit, the heat dissipation efficiency of the heating element in the control circuit placed in the housing of the gaming machine will be reduced, the assembly work efficiency of the gaming machine will be reduced, and maintenance of the gaming machine will be difficult Troubles such as an increase in the rate of failure due to wire breakage, poor connection, etc., and an increase in the manufacturing cost of gaming machines.

  Thus, in order to reduce problems caused by the presence of a large amount of wiring, a relay board for controlling these peripheral devices is provided in the vicinity of peripheral devices such as decorative lamps, liquid crystal display devices, speakers, etc. An invention has been disclosed in which a relay board is connected to a relay board by bidirectional serial communication wiring (see, for example, Patent Document 1).

  According to the invention described in Patent Document 1, by serializing the wiring between the control circuit and the relay board, the number of wires connected to the control circuit is reduced, and the assembly work efficiency is increased. It is said that the manufacturing cost can be reduced, the amount of dust generated can be reduced, and the generation of noise can be further reduced.

JP 2003-164560 A

  However, according to the gaming machine described in Patent Document 1, although the number of wires connected to the control circuit can be reduced, when the distance between the control circuit and the relay board is increased, the capacity between the wires is increased. Therefore, it is necessary to keep the transmission speed of the communication low, and in order to improve noise resistance, a device such as increasing the voltage of the signal line used for communication or flowing a large amount of current is required.

  In addition, when a player emits radio waves or discharges a pachislot machine or a pachinko machine during a game, a malfunction may be induced in the gaming machine, or an illegal program may be installed in a pre-crafted gaming machine. In some cases, illegal acts such as starting up are performed. If a long electric wire is connected between the control circuit and the relay board, electromagnetic waves generated by these goto actions are received, causing problems such as that the control circuit is likely to malfunction and an illegal program is likely to be started.

  Also, not only in the case of goto acts, static electricity is charged to the player's clothing, etc., and when the player touches the gaming machine, the static electricity is discharged to the gaming machine, or a mobile phone carried by the player is issued. An electromagnetic wave may cause a current to flow in the electric wire connecting the control circuit and the relay board, and may cause a malfunction in the control circuit. Therefore, when transmitting commands and statuses by communication, it is necessary to monitor and deal with frame errors, timeout errors, parity errors, code check errors, etc., in order to reduce the influence of noise and the like.

  Also, when selling gaming machines such as pachislot machines and pachinko machines, from the viewpoint of the impact on society, in order to avoid significant reluctance of the player's shooting spirit, it is necessary to establish a prize between consecutive games for a certain period of time. The number of game values that the gaming machine pays out to the player, or the number of game values that the gaming machine pays out to the player due to the establishment of a prize during a continuous game for a certain period of time, and this continuous time It is required that the performance of the gaming machine, such as the difference in the number of game values bet on the game by the player during the game, is designed according to a predetermined standard.

  Therefore, a gaming machine manufacturer, a third party testing organization, etc. intervenes a test relay board between the control boards, reads information from the electric wire that is transmitting information, rewrites the information, etc. We are conducting type tests on machines. In the type test, a short-time play rate, a medium-time play rate, a long-time play rate, an accessory ratio, a continuous accessory ratio, and the like are confirmed by a real-fire test or the like.

  As in the past, when each input means, each output means, and each peripheral device are connected by a dedicated control line, it is for a real test with a dedicated emulator for the gaming machine and a status acquisition means. Alternatively, it was necessary to produce a jig substrate for shipping inspection for each gaming machine.

  The present invention has been made in view of the above problems, and reduces the wiring between boards to improve the heat dissipation efficiency in the housing, and reduces the occurrence rate of failures due to wire breakage, poor connection, etc. Easier machine maintenance, reduced gaming machine manufacturing costs, while maintaining the transfer rate of information while reducing malfunctions in the control circuit due to external noise, making it possible to easily support real-life tests The purpose is to provide.

  Another object of the present invention is to execute status transmission and reception at a time in communication between a control circuit and each input means, each output means, or each peripheral device. Another object of the present invention is to easily perform a real fire test or a shipping inspection on gaming machines of different models.

  Another object of the present invention is to improve the reliability of data when transmitting commands and status by communication, thereby reducing the influence of noise and the like, and more reliably transmitting information such as commands and status. It is said.

A gaming machine according to the present invention includes a master communication device provided in a main control circuit, at least one slave substrate, a slave communication device provided on the slave substrate, and between the master communication device and the slave communication device. a game machine having a communication means for transmitting information by the communication interface and generates a pseudo acknowledgment signal confirming receipt completion in a pseudo manner the transmission of data before SL master communication apparatus at a constant amount is completed characterized by comprising a pseudo-acknowledge signal generating means for.

  According to the present invention, since the acknowledge signal originally generated on the slave communication device side is artificially generated on the master communication device side and output to the transmission means, it is necessary to receive the response of the acknowledge signal. The received data line can be omitted.

  Therefore, according to the present invention, an acknowledge signal receiving wiring required between the substrates is not required, and the circuit on the receiving device side can be simplified. Thereby, the cost of the product can be reduced and the development period can be shortened.

  In addition, the master communication device of the gaming machine according to the present invention converts the transmission information including the command and the status into an electrical transmission signal and outputs the electrical transmission signal, and converts the electrical transmission signal into an optical transmission signal and outputs it. First optical signal output means, first optical signal input means for inputting an optical response signal including a command and status, converting it to an electrical response signal, and outputting the electrical response signal, and a response of the electrical response signal to the command and status Response signal restoring means for converting the information into information and outputting the information, wherein the slave communication device receives the light transmission signal, converts it into an electric transmission signal and outputs it, and outputs the electric signal. A transmission signal restoring means for converting a transmission signal into the transmission information and outputting it, and processing corresponding to the command and status included in the transmission information, and after the command and processing Response information generating means for generating response information including status, response signal converting means for converting the response information into an electrical response signal and outputting the response information, and a second output for converting the electrical response signal into an optical response signal and outputting it And an optical signal output means.

  According to the present invention, optical communication can be performed between a master communication device and a slave communication device. By using optical communication to transmit information between the substrates, the electrical connection between the substrates can be disconnected while reducing the wiring between the substrates.

  Note that by reducing the wiring between the boards, the heat dissipation efficiency in the housing can be improved, the failure rate due to wire breakage, poor connection, etc. can be reduced, and maintenance of the gaming machine can be facilitated. Further, by disconnecting the electrical connection between the substrates, it is possible to reduce malfunctions due to external noise mixed in via a communication line, a power line, or the like while maintaining an information transfer rate.

  In addition, according to the present invention, it is possible to connect the information transmission path between the master communication device and the slave communication device in a ring manner, so that a plurality of slave communication devices can be connected in a daisy chain manner. It becomes. Further, the master communication device transmits transmission information to one or more slave communication devices, and the one or more slave communication devices transmit response information to the master communication device, thereby allowing one or more slaves to transmit. Status writing to the communication device and status reading from one or more slave communication devices can be realized in a single loop. As a result, the status can be written and read in a short time, and the status in one or more slave communication devices is acquired at a time by monitoring the information transmission path immediately before the master communication device. be able to. Therefore, it is possible to easily check input / output at the time of inspection of gaming machines.

Further, the transmission information conversion means according to the present invention outputs data including a command and status and a clock signal for sampling the data as the electric transmission signal, and the transmission signal restoration means outputs the command and status. The electrical transmission signal composed of data including and a clock signal for sampling the data is converted into the transmission information and output, and the response signal conversion means includes the data including the command and the status after processing, The response information consisting of a clock signal for sampling data is converted into an electrical response signal and output, and the response signal restoring means includes data including a command and status and a clock signal for sampling the data The electrical response signal consisting of And outputs the pseudo-acknowledge signal generating means, said clock signal counted by the counter, the count value with a count completion signal output to reach the predetermined number, transmits the data of a predetermined quantity It is characterized in that an acknowledge signal indicating completion is generated in a pseudo manner.

  According to the present invention, since synchronous optical communication can be performed between a master communication device and a slave communication device, high-speed communication can be realized without setting a baud rate or the like in advance. Become.

  In addition, since the acknowledge signal originally generated on the receiving device side is generated and output in a pseudo manner on the communication device on the transmitting side, only the data and clock signals are converted into optical signals and transmitted between the other substrates. Communication can be performed.

  Further, according to the present invention, the clock signal for sampling data is counted, and the acknowledge signal is simulated using the count completion signal of the counter that is output when the count value reaches a predetermined number. Since the data is generated and output to the transmission means, it is possible to immediately respond to the acknowledge signal after data transmission.

  In addition, since the acknowledge signal originally generated on the receiving device side is artificially generated on the communication device side and output to the transmission means, the received data by optical communication required to receive the response of the acknowledge signal Lines can be omitted.

  Therefore, according to the present invention, it is not necessary to provide an optical cable for receiving an acknowledge signal between the substrates when performing optical communication, and the circuit on the receiving device side can be simplified. Thereby, the cost of the product can be reduced and the development period can be shortened.

In addition, the gaming machine according to the present invention provides I ² as a communication interface between the transmission signal conversion unit and the first optical signal output unit and between the response signal conversion unit and the second optical signal output unit. Using the C interface, the first or second optical signal output means converts the data line and clock line of the I ² C interface, which are electrically wired-OR connected, into an optical data signal and an optical clock signal, and outputs them. It is characterized by doing.

According to the present invention, only the data line and clock line of the I ² C interface that are electrically wired-OR connected can be converted into an optical signal to transmit information. Familiar I ² C devices and program modules can be used as they are, and the development time required for communication hardware and software development can be greatly reduced. In addition, by using the I ² C interface, which provides many failure diagnosis tools and debugging tools, it is easy to diagnose and debug between boards using these general-purpose tools, and shorten the time to investigate the defective part. be able to.

  According to the present invention, the wiring between the boards is reduced to improve the heat radiation efficiency in the housing, the failure rate due to the disconnection of the electric wire or the poor connection is reduced, the maintenance of the gaming machine is facilitated, and the gaming machine It is possible to reduce the malfunction of the main control circuit or the sub control circuit due to external noise while suppressing the manufacturing cost and maintaining the information transfer rate.

It is an external appearance perspective view of a pachislot. It is the perspective view which opened the front door of the pachislot and observed the inside of the pachislot. It is a figure explaining the structure of the circuit with which the front door block and cabinet block of a pachislot are equipped. It is a figure which shows the Example which connected the information transmission path | route between a main control circuit and three slave boards in the ring type. It is a block diagram of a master communication apparatus and a slave communication apparatus. It is a figure which shows the data format of 1 byte in the case of using an asynchronous method. It is a block diagram showing other embodiment of a master communication apparatus and a slave communication apparatus. 10 is a timing chart showing logic changes at SDA and SCL used in the I ² C interface and at each check point shown in FIG. 9. It is a circuit example of a pseudo acknowledge response means for generating a pseudo acknowledge signal for an I ² C interface. It is an example of a circuit on the receiving side that converts an optical communication interface into an I ² C interface.

  An embodiment in which the present invention is applied to a pachislot machine 1 will be described below with reference to the drawings. Note that the present invention can also be applied to pachinko and other gaming machines.

  FIG. 1 is an external perspective view of the pachi-slot 1, and FIG. 2 is a perspective view of the interior of the pachi-slot 1 when the front door 9 that is pivotally supported on the front surface of the cabinet 2 is opened.

  The pachi-slot 1 includes a cabinet 2 that houses a reel 3, a circuit board, and the like, and a front door 9 that is attached to the cabinet 2 so as to be openable and closable. Inside the cabinet 2, three reels 3 are provided side by side. Each reel 3 is configured by attaching a belt-like sheet in which a plurality of symbols (for example, 21 pieces) are continuously arranged along the rotation direction to the peripheral surface of a cylindrical frame.

  A liquid crystal display device 5 is provided at the center of the front door 9. The liquid crystal display device 5 includes a display screen including a symbol display area, and is provided so as to be positioned on the near side superimposed on the three reels 3 when viewed from the front. The symbol display area is provided corresponding to each of the three reels 3 and has a configuration capable of transmitting through the reels 3 provided behind the reels 3.

  That is, the symbol display area functions as the display window 4, and the player can visually recognize the rotation and the stop operation of the reel 3 provided behind the display window 4. In the present embodiment, the entire display screen including the symbol display area is used to display an image and execute an effect.

  When the rotation of the reel 3 provided behind the symbol 3 is stopped, the symbol display area (hereinafter referred to as the display window 4) has an upper stage and a middle stage within the frame among a plurality of types of symbols arranged on the surface of the reel 3. In addition, one symbol (three in total) is displayed in each of the lower areas. In addition, a pseudo line formed by combining any one of the three regions including the upper stage, the middle stage, and the lower stage of each display window 4 is a target line for determining whether or not to win ( It is defined as a winning determination line 8).

  In the present embodiment, a top line that combines the upper stages of the display windows 4, a center line that combines the middle stages of the display windows 4, a bottom line that combines the lower stages of the display windows 4, and an upper stage of the left display window. , Winning determination of five cross-down lines that combine the middle stage of the middle display window and the lower stage of the right display window, the lower stage of the left display window, the cross-up line that combines the middle stage of the middle display window and the upper stage of the right display window Line 8 is provided.

  The front door 9 is provided with various devices to be operated by the player. The medal slot 15 arranged on the right side of the pedestal part is provided for receiving medals dropped from the outside by the player. The medals accepted by the medal slot 15 are inserted into one game with a predetermined number (for example, three) as an upper limit, and the amount exceeding the predetermined number can be deposited inside the pachislot 1 ( So-called credit function).

  The bet button 13 disposed on the left side of the pedestal portion is provided for determining the number of coins to be inserted into one game from medals deposited inside the pachislot 1. The checkout button 14 is provided to pull out medals deposited inside the pachislot 1 to the outside.

  A start lever 6 disposed on the left side of the pedestal is provided to start the rotation of all the reels 3. The stop button 7 is associated with each of the three reels 3 and is provided to stop the rotation of the corresponding reel 3.

  The 7-segment indicator 12 arranged on the left side of the reel 3 is made up of 7-segment LEDs, and the number of medals inserted in the current game (hereinafter referred to as the number of medals) and the medal paid out to the player as a privilege. Information such as the number of sheets (hereinafter referred to as payout number) and the number of medals deposited in the pachislot machine 1 (hereinafter referred to as credit number) is digitally displayed to the player.

  A large number of lamps 24 (LEDs, etc.) are arranged on the side and upper side of the liquid crystal display device 5, and depending on the contents of the production, movement of the lighting state, rotation of the lighting state, strobe light emission, and other points Emits light with a light-off pattern. A pair of speakers 21 arranged on the lower left and right sides of the liquid crystal display device 5 outputs sound such as sound effects and music corresponding to the contents of the performance. The medal payout port 16 guides medals discharged by driving a medal payout device described later to the outside. The medals discharged from the medal payout opening 16 are stored in the medal tray 17.

  Below the liquid crystal display device 5 and above the pedestal portion, a payout panel 23 for displaying a symbol combination, a medal payout number, and the like is disposed. Further, below the pedestal portion, a waist panel 25 for displaying a machine name and a character design is provided. A pair of speakers 21 that enhance sound effects such as effects are also provided behind the medal tray 17 below the waist panel 25.

  FIG. 2 is a diagram showing the internal structure of the pachislot machine 1 according to the present embodiment, in which the front door 9 is opened, and the structure on the back side of the front door 9 and the structure inside the cabinet 2 appear. .

  A board (hereinafter referred to as a main board) constituting the main control circuit 55 is provided above the inside of the cabinet 2. The main control circuit 55 is a circuit that controls the main flow of the game in the pachi-slot 1 such as determination of an internal winning combination, rotation and stop of the reel 3, and determination of presence / absence of winning.

  Three reels 3 are provided in the center inside the cabinet 2. A stepping motor is connected to each reel 3 via a gear having a predetermined reduction ratio.

  A medal payout device 43 having a structure capable of accommodating a large number of medals and discharging them one by one is provided below the inside of the cabinet 2. On the left side of the medal payout device 43, a power supply device 54 is provided for supplying necessary power to each device of the pachislot machine 1.

  A substrate (hereinafter referred to as a sub-board) constituting the sub-control circuit 56 is provided on the upper side of the back side of the front door 9. The sub-control circuit 56 is a circuit that controls execution of effects by turning on / off the lamp 24, generating sound, displaying images, and the like. A specific configuration of the sub control circuit 56 will be described later.

  A selector 51 is provided at the center of the back side of the front door 9 and below the display window 4. The selector 51 is a device for selecting whether or not a medal is appropriate in material, shape, and the like, and guides an appropriate medal received in the medal insertion slot 15 to the medal payout device 43. A medal sensor 50 (see FIG. 3), which will be described later, is provided on a path through which the medal passes in the selector 51, and detects that an appropriate medal has passed.

  This completes the description of the structure of the pachislot 1. Next, with reference to FIG. 3, the structure of the circuit provided in the front door block (the back side of the front door 9) and the cabinet block (inside the cabinet 2) of the pachi-slot 1 in the present embodiment will be described. The pachi-slot 1 in the present embodiment includes a main control circuit 55, a sub-control circuit 56, a relay board that is electrically connected to these, and peripheral devices.

  The main control circuit 55 is mainly composed of a microcomputer installed on a circuit board. The microcomputer includes a CPU (hereinafter referred to as a main CPU), a ROM (hereinafter referred to as a main ROM), a RAM (hereinafter referred to as a main RAM), an I / O, a communication circuit, and the like.

  The main ROM stores a control program executed by the main CPU, a data table such as an internal lottery table, data for transmitting various control commands (commands) to the sub control circuit 56, and the like. The main RAM is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program.

  A clock pulse generation circuit, a frequency divider, a random number generator, a sampling circuit, and the like are connected to the main CPU of the main control circuit 55, and the main CPU executes a control program based on the generated clock pulses. . The random number generator generates a random number in a predetermined range (for example, 0 to 65535), and the sampling circuit extracts one value from the generated random number and performs lottery processing relating to the game.

  The main board of the main control circuit 55 includes a power supply device 54 that supplies electric power, a reel motor drive circuit 39 that controls rotation and stop of the reel 3, a medal payout device 43 that performs medal payout control, a door relay board 62, and the like. It is connected to the relay board by communication. In addition, the main board of the main control circuit 55 is connected to an external centralized terminal board 63 that transmits / receives information to / from a host computer or the like of the game arcade so that information can be transmitted / received.

  Further, the main control circuit 55 inserts medals, operates the start lever 6, and stops the sub-control circuit 56 that executes control of the lamp 24, the liquid crystal display device 5, or the sound generator for the purpose of production. Various kinds of information such as operation 7, internal winning combination, display combination, gaming state, etc. are transmitted. For this purpose, the main board of the main control circuit 55 is connected to the sub board of the sub control circuit 56 by communication.

  For example, the main control circuit 55 directly reads the state of each input means connected to the door relay board 62 and controls peripheral devices such as the reel motor drive circuit 39 and the medal payout device 43 to display the number of stored items. It is also possible to proceed with the game by outputting display information to a device, an accessory count display, a payout number display, a win display, and other output means. However, in order for the main CPU to directly read the state of each input means to control each peripheral device and display control of each output means, the main CPU of the main control circuit 55 is required to store information via I / O. Reading and writing must be performed, and a large number of wires must be connected to the main board of the main control circuit 55.

  Then, with the increase in wiring, the occurrence rate of failures due to wire breakage, poor connection, etc. increases, maintenance of the pachislot 1 becomes difficult, and the price of the pachislot 1 increases.

In addition, if a new communication standard is adopted as a communication means between the main control circuit 55 and each peripheral device or the sub-control circuit 56, a great development period and cost are required for the development of communication elements and the establishment of protocols. However, reliable communication can be realized in a short period of time and at a low cost by using a general-purpose communication standard that is familiar to the user. In particular, in order to perform communication between a plurality of boards in one housing, a standard based on RS232 or a simple communication standard by wire such as I ² C is advantageous.

  However, in gaming machines such as pachislot 1 and pachinko machines, it is illegal to cause malfunctions in gaming machines by irradiating radio waves to these gaming machines or discharging them, or illegally in gaming machines that have been crafted in advance. Unauthorized gossip, such as starting a program, always occurs.

  Therefore, when developing these gaming machines, not only the main control circuit 55 but also the sub-control circuit 56 will implement sufficient countermeasures against these goto acts in advance so that new gaming machines can be found in the game hall. From the beginning of the replacement, it is important to reduce the motivation of the goto act by appealing that it is a clean machine against the goto act. In particular, since the front door 9 present at a position directly confronting the player is likely to be a target of goto action, sufficient measures are required.

  Similarly, when a player's clothing is charged with static electricity, and the static electricity is discharged to the gaming machine at the moment when the player touches the gaming machine, or due to electromagnetic waves emitted from the mobile phone carried by the player, It is preferable that no malfunction occurs in the main control circuit 55 or the sub control circuit 56.

However, since simple communication standards such as RS232 and I ² C transmit and receive information using electric wires, communication lines, power lines, ground lines, and the like included in communication cables connecting between boards are used. Picks up electromagnetic waves and is transmitted as noise to the main control circuit 55 and the sub-control circuit 56, which may cause a malfunction in the main control circuit 55 and the sub-control circuit 56.

  In addition, when noise is applied to the communication line connected to the main control circuit 55 or the sub control circuit 56, the transmission of the operation information of each input means may be delayed due to a delay in information transmission due to command retransmission or the like. Problems such as a delay in the display timing of the display means and a delay in the control command for the peripheral device occur.

  Although measures to implement strong shielding measures on the communication cable itself are also conceivable, if a shielded wire is used for the communication line, a large capacity load will be connected in parallel, so it must be used at a reduced communication speed. Troubles such as becoming difficult or difficult to handle wiring with poor flexibility.

  Therefore, in the present invention, by using an optical communication cable instead of an electric wire as a communication cable, the main control circuit 55 and the generation of noise due to the irradiated electromagnetic wave can be prevented while maintaining a predetermined communication speed. A malfunction in the sub control circuit 56 is prevented.

  As shown in FIG. 3, the door relay board 62 connected to the main control circuit 55 is connected to wiring such as various switches arranged in the operation unit of the pachislot machine 1. The medal sensor 50 connected to the door relay board 62 detects that the medal received in the medal slot 15 has passed through the selector 51 described above.

  The bet switch 13S connected to the door relay board 62 detects that the bet button 13 has been operated by the player. The start switch 6S detects that the start lever 6 has been operated by the player.

  The stop switch 46 detects that each of the three stop buttons 7 has been pressed by the player. Input information such as these switches is transmitted from the door relay board 62 to the main board of the main control circuit 55. The main control circuit 55 advances the game based on the input information, and controls operations of peripheral devices such as the reel motor drive circuit 39 and the medal payout device 43.

  The reel motor drive circuit 39 controls driving of a stepping motor arranged for each reel 3. Each reel 3 is connected to a reel position detection circuit. The reel position detection circuit detects a reel index indicating that the reel 3 has made one rotation by an optical sensor having a light emitting part and a light receiving part.

  The driving force of the stepping motor that rotates each reel 3 is transmitted to the reel 3 through a gear having a predetermined reduction ratio. Each time one pulse is output to the stepping motor, the reel 3 rotates at a constant angle.

  The main CPU of the main control circuit 55 detects the reel index and counts the number of times a pulse is output to the stepping motor, thereby rotating the rotation angle of the reel 3 (mainly, how many symbols the reel 3 rotates) The position of each symbol arranged on the surface of the reel 3 is managed.

  The medal payout device 43 is provided with a medal detection unit that detects the number of medals to be paid out and checks whether or not medals discharged from the medal payout device 43 have reached the payout number. be able to.

  Next, the sub-board of the sub-control circuit 56 arranged on the back side of the front door 9, the peripheral devices connected thereto, and various relay boards will be described.

  The sub control circuit 56 is connected to the main control circuit 55 by one-way communication, and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 55. The sub-control circuit 56 basically includes a CPU (hereinafter referred to as sub-CPU), ROM (hereinafter referred to as sub-ROM), RAM (hereinafter referred to as sub-RAM), rendering processor, drawing RAM, driver, DSP (digital signal processor), An audio RAM, an A / D converter, and an amplifier are included.

  In response to the command transmitted from the main control circuit 55, the sub CPU of the sub control circuit 56 controls the output of video, sound, and light according to the control program stored in the sub ROM. The sub-RAM is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 55. The sub ROM basically includes a program storage area and a data storage area.

  The program storage area stores a control program executed by the sub CPU. For example, in the control program, a main board communication task for controlling communication with the main control circuit 55 and an effect registration task for extracting and registering effect contents (effect data) by extracting effect random numbers. A drawing control task for controlling the display of video by the liquid crystal display device 5 based on the determined contents of the production, a lamp control task for controlling the light output by the lamp 24, a voice control task for controlling the sound output by the speaker 21, and the like. included.

  The sub-control circuit 56 is connected to the liquid crystal display device 5, the speaker 21 and the sound board 110, the lamp board 58, the lower plate LED board 61, and the like as peripheral devices whose operations are controlled.

  The sub CPU, the rendering processor, the drawing RAM (including the frame buffer), and the driver of the sub control circuit 56 create a video according to the animation data designated by the contents of the presentation, and transmit the created video to the liquid crystal display device 5. indicate.

  Further, the sub CPU, DSP, audio RAM, A / D converter, and amplifier of the sub control circuit 56 output sounds such as BGM from the upper speaker 21 in accordance with the sound data specified by the production contents. Further, the sub CPU transmits a command of audio information designated by the production contents to the sound board 110. The sound board 110 that has received the voice information command analyzes the command, generates a voice signal using a DSP, an audio RAM, an A / D converter, an amplifier, and the like, and outputs a voice from the lower speaker 21 and the rear speaker 21. Output.

  Further, the sub CPU of the sub control circuit 56 turns on and off the lamp 24 in accordance with the lamp data designated by the contents of the effect.

  Based on the command received from the sub-control circuit 56, the lamp board 58 is a pattern for turning on and off the lamps 24 arranged mainly on the side of the liquid crystal display device 5 at the upper front of the pachi-slot 1 shown in FIG. Can be switched. The sub-control circuit 56 transmits a command according to the contents of effects related to turning on / off the lamp 24 to the lamp board 58. When the lamp board 58 receives the command, the lamp board 58 individually controls lighting and extinguishing of the lamps 24 arranged in large numbers, moving the lighting state, rotating the lighting state, strobe light emission, and other points. Each lamp 24 is caused to emit light in an extinguishing pattern.

  In addition, as described above, optical communication is used to transmit information between the sub control circuit 56 and the lamp substrate 58, and the sub control circuit 56 and the sound substrate 110 are connected between the sub control circuit 56 and the liquid crystal display device 5. Optical communication for communication between the sub control circuit 56 and the lower LED board 61, between the sub control circuit 56 and the main control circuit 55, between the main control circuit 55 and the door relay board 62, etc. Can be used.

  Next, a signal path for transmitting input information from each input means to the main control circuit 55, a signal path for transmitting output information from the main control circuit 55 to each output means such as a display unit, and the main control circuit Signal paths of control signals that are transmitted and received when 55 controls the reel motor drive circuit 39 and the medal payout device 43 will be described with reference to FIG.

  FIG. 4 shows an information transmission path between the main control circuit 55 (which corresponds to the master board 64 side as described below in communication) and the three slave boards 65 using a ring type optical communication. It is a figure which shows the Example connected to. FIG. 4 shows information transmission paths between the main control circuit 55 and each input means, each output means, and each peripheral device. The sub-control circuit 56, the lamp board 58, the sound board 110, and the lower plate LED are shown. A similar ring connection can also be made for the information transmission path to the substrate 61.

  Connected to the bus of the main CPU 31 in the main control circuit 55 is a master communication device 67 for inputting / outputting various information to / from each input means, each output means, and each peripheral device. Here, the board on which the main control circuit 55 and the master communication device 67 are arranged is referred to as a master board 64 in communication.

  The optical signal including the command and status output from the master communication device 67 is input by the first slave communication device 68 disposed on the first slave substrate 65. The first slave communication device 68 shown in FIG. 4 is, for example, a door relay board 62 (see FIGS. 2 and 3). The first slave communication device 68 performs processing corresponding to the received command and status as necessary, and outputs an optical signal including the status and command after processing to the second slave substrate 65.

  The optical signal including the command and status output from the first slave communication device 68 is input by the second slave communication device 68 disposed on the second slave substrate 65. The second slave communication device 68 performs processing corresponding to the received command and status as necessary, and outputs an optical signal including the status and command after processing to the third slave substrate 65.

  For example, the second slave substrate 65 can be disposed on the cabinet 2 side, and the I / O of the slave communication device 68 disposed on the second slave substrate 65 can be connected to the reel motor drive circuit 39. In this way, a drive signal for the reel motor can be transmitted from the main control circuit 55 to the reel motor drive circuit 39, and a reel index detection signal can be transmitted from the reel motor drive circuit 39 to the main control circuit 55. The slave communication device 68 may be disposed on the same substrate as the reel motor drive circuit 39.

  The optical signal including the command and status output from the second slave communication device 68 is input by the third slave communication device 68 of the third slave substrate 65. The third slave communication device 68 performs processing corresponding to the received command and status as necessary, and outputs an optical signal including the processed status and command to the master communication device 67 of the master substrate 64.

  The third slave board 65 can be arranged on the cabinet 2 side in the vicinity of the medal payout device 43. The I / O of the slave communication device 68 arranged in the third slave substrate 65 is connected to the medal discharge device 43. With this configuration, the main control circuit 55 can instruct the medal discharging device 43 to pay out a predetermined number of medals. Further, the medal discharging device 43 can transmit information indicating that the payout of a predetermined number of medals has been completed to the main control circuit 55 based on the information acquired from the main control circuit 55.

  As described above, the optical signal including the command and the status is input to the master communication device 67 of the main control circuit 55 after sequentially passing through one or more slave substrates 65. Further, when performing a real test or a shipping inspection using the pachislot machine 1, it is also possible to insert a jig substrate 66 provided with a jig communication device 69 in the information transmission path of the optical signal.

  Each slave substrate 65 and jig substrate 66 can be configured by the same circuit, or can be configured by a unique circuit. Each slave board 65 and jig board 66 can be set with a unique address for identification, application information indicating that the board is used as the slave board 65, and the board. It is possible to set application information indicating that is used as the jig substrate 66. The master communication device 67 can transmit the address and the command and status specific to the slave board 65 in association with each other, and the command and status data array for each slave board 65 can be determined in advance. .

  The time from when the master communication device 67 transmits an optical signal including a command and status to when the master communication device 67 returns to the master communication device 67 again through one or more slave boards 65 is configured to be 500 μsec or less, for example. . Thereby, it is possible to cope with real-time processing executed by the main control circuit 55.

  In the embodiment shown in FIG. 4, an example is shown in which three slave substrates 65 and one jig substrate 66 are connected in one loop. However, in order to shorten the communication time for one time. In addition to limiting the number of slave substrates 65 to about two, a plurality of master communication devices 67 or a plurality of optical communication ports may be arranged on the master substrate 64 side to form a plurality of information transmission path loops. it can.

  Further, when the jig substrate 66 is inserted into the loop of the information transmission path, the master communication device 67 can detect the presence of the jig substrate 66. When the jig substrate 66 is detected, the master communication device 67 transmits an optical signal including a command and a status, and then again through the one to a plurality of slave substrates 65 and the one to a plurality of jig substrates 66. It is also possible to set a long timeout time until returning to the master communication device 67.

  As shown in FIG. 4, when monitoring an optical signal output from the master board 64 and transferred between the boards, or performing a real test or shipment inspection by rewriting the status corresponding to the command The jig substrate 66 can be inserted into the information transmission path. By inserting the jig substrate 66 into the information transmission path, it is possible to perform the optical signal monitor, the actual test, or the shipping inspection while the other slave substrate 65 is mounted.

  The I / O of the first slave board 65 is connected to a medal sensor 50, a bet switch 13S, a stop switch 46, a start switch 6S and other input means arranged on the front door 9 of the pachislot 1. The information of the input means is read to generate corresponding status response information, and the status response information is added together with the command transmitted from the master communication device 67 and returned. The response information is transmitted to the master communication device 67 via the other slave substrate 65 or the jig substrate 66.

  Further, the I / O of the first slave board 65 includes output means such as a stored number indicator, an accessory number indicator, a payout number indicator, a hit indicator, etc., which are arranged on the front door 9 of the pachislot 1. A display drive circuit 41 is connected, and based on the command and status received from the master communication device 67 of the main control circuit 55, the corresponding I / O state is set, and the lighting display of these output means is displayed. It can be carried out.

  When the slave board 65 receives a command and status from the master communication device 67, the slave board 65 returns information indicating that the command has been received in association with information related to the address unique to the slave board 65. Thereby, it can be confirmed in the master communication device 67 that the slave substrate 65 has received the command.

  In addition to the I / O, the slave substrate 65 is provided with a serial output means COM having a serial port (RS232 or the like) capable of transmitting information to / from other peripheral devices. By making the serial port of this serial output means COM dedicated to transmission, the sub-control circuit 56 can be connected to this serial output means COM.

  Since the sub-control circuit 56 is configured not to be able to transmit information to the main control circuit 55 in order to reduce the influence of the gore action performed on the gaming machine, the main control has been conventionally performed. The command and status transmitted from the circuit 55 to the sub-control circuit 56 cannot be checked and dealt with, such as a frame error, a timeout error, and a code check. However, by disposing the slave board 65 in the vicinity of the sub control circuit 56 and receiving the command and status transmitted from the main control circuit 55 from the serial port dedicated to transmission formed in the slave communication device 68, Checks such as frame errors and code inspections can be performed on the slave substrate 65. Further, by forming the information transmission path in a ring shape, the master communication device 67 can detect a timeout error and retransmit the command and status. Therefore, highly reliable communication can be performed.

  Thus, by applying the present invention to communication between the main control circuit 55 and the sub control circuit 56, it becomes possible to perform communication with higher reliability. Therefore, it is possible to increase the distance between the main control circuit 55 and the sub control circuit 56 such that the main control circuit 55 is arranged on the cabinet 2 side and the sub control circuit 56 is arranged on the front door 9. Become.

  The main control circuit 55 is disposed at a position away from the front door 9 in order to cope with an illegal goto action in which a player irradiates or discharges radio waves to a pachislot machine or a pachinko machine during the game. It is preferable. On the other hand, the sub-control circuit 56 controls a large number of lamps 24, the liquid crystal display device 5, the speaker 21 and the like disposed on the front door 9, so that the sub-control circuit 56 is preferably disposed on the front door 9 from the viewpoint of wiring.

  Conventionally, the main control circuit 55 and the sub control circuit 56 are connected by communication using communication means that allows only one-way information transmission, so that a frame error, a time-out error, an error during code check, etc. The possibility of malfunction due to noise picked up in the information transmission path of the communication was high. Conventionally, since the communication information transmission path is constituted by electric wires, the main control circuit 55 or the sub-control circuit 56 receives the radio wave or discharge irradiated by an unauthorized goto action, and the information transmission path electric wires receive them. The problem of affecting the operation of was caused. However, according to the present invention, by using optical communication in the information transmission path between the main control circuit 55 and the sub control circuit 56, the influence on the radio wave or discharge emitted by an illegal goto action is greatly reduced. It is possible to check the frame error, timeout error, code check, etc. for the command and status transmitted from the main control circuit 55 to the slave board 65, so that more reliable communication is performed. It becomes possible.

  Similar to the slave board 65, the I / O of the jig board 66 has a medal sensor 50, a bet switch 13S, a stop switch 46, a start switch 6S, and other input means arranged on the front door 9 of the pachislot 1. A jig switch 71 corresponding to the above is connected. Thereby, the response information of the corresponding status can be generated by reading the information of each input means, and the response information transmitted from the slave substrate 65 can be rewritten and returned to the master communication device 67. Therefore, the operation of each input means can be emulated with a simple switch or the like without directly operating the medal sensor 50, the bet switch 13S, the stop switch 46, the start switch 6S, and other input means.

  Similarly, for the I / O of the jig substrate 66, output means such as a stored number indicator, an accessory number indicator, a payout number indicator, a hit indicator, etc. arranged on the front door 9 of the pachislot 1 A jig lamp 70 corresponding to the display unit driving circuit 41 is connected. Thereby, based on the command and status received from the master communication device 67 of the main control circuit 55, the corresponding I / O state can be set and the jig lamp 70 can be turned on and off.

  When the jig substrate 66 receives a command and status dedicated to the jig substrate 66 from the master communication device 67, information indicating that the command has been received is returned in association with address information unique to the jig substrate 66. Thus, the master communication device 67 can confirm that the jig substrate 66 has received the command.

  In addition to the I / O, the jig substrate 66 is provided with a serial output means COM having a serial port (RS232 or the like) capable of bidirectional communication. By connecting a computer for a real test or a shipping inspection to the serial output means COM, it is possible to perform a more advanced operation of the gaming machine and a shipping inspection.

  The optical signal output from the master substrate 64 defines a reset command, a connection confirmation command, a setting command, an update command, a control command for the serial output means, and other various commands.

  The reset command returns the program relating to optical communication on the slave substrate 65 or jig substrate 66 side connected to the optical communication path to the initial state, or serial output means provided on the slave substrate 65 or jig substrate 66. This is a command for returning a program related to COM, I / O, and communication to an initial state.

  The connection confirmation command is a command for checking the total number and address of the slave substrate 65 or the jig substrate 66 connected to the optical communication path.

  The setting command is a command for setting a protocol such as a baud rate in the serial output means COM of the slave substrate 65 or the jig substrate 66 connected to the optical communication path, an I / O input / output state, and the like.

  The update command acquires the write status command output to the I / O of each slave substrate 65 or jig substrate 66 and the state input to the I / O of each slave substrate 65 or jig substrate 66. This command includes a read status command.

  The control command for the serial output means is a command for outputting a status from the serial port of the serial output means COM arranged on the slave substrate 65 or the jig substrate 66. For example, the serial port of the serial output means COM arranged on the slave substrate 65 and the sub-control circuit 56 are connected by communication, and the status of the main control circuit 55 is sent from the serial output means COM to the sub-control circuit 56 as a status. The transmitted command for the sub control circuit 56 is transmitted. Commands for the sub control circuit 56 include a start command, a reel stop command, a display combination command, a payout end command, a medal insertion command, a bonus end command, a bonus start command, and other commands. The sub-control circuit 56 that has received these various commands executes effects using video, sound, and light in accordance with each command.

  Next, the configuration of the master communication device 67 and the slave communication device 68 will be described with reference to FIG. FIG. 5 is a block diagram of the master communication device 67 and the slave communication device 68. For ease of explanation, FIG. 5 illustrates a state in which only one slave substrate 65 is connected to one master substrate 64.

  As shown in FIG. 5, the master communication device 67 arranged on the master substrate 64 obtains transmission information including commands and status from the upper main CPU 31 and receives it from the slave communication device 68 or the jig substrate 66. A bus I / F for outputting response information including the command and status is provided.

  The bus I / F also includes a CRC checker 79 (first code check information adding means) that acquires transmission information including a command and status and adds code check information of the command or status, and a command or status. In addition, transmission signal conversion means 72 that converts the transmission information including the code check information into an electric transmission signal and outputs it, and response signal restoration means 76 are connected. The master communication device 67 is provided with optical signal output means PD1 (first optical signal output means) for converting the electrical transmission signal output from the transmission signal conversion means 72 into an optical transmission signal and outputting it.

  On the other hand, to the slave substrate 65, an optical signal input means PD3 (second optical signal input means) for inputting the optical transmission signal output from the master communication device 67 side, converting it into an electric transmission signal and outputting it, A transmission signal restoring means 74 for converting a transmission signal into transmission information and outputting it; a CRC checker 79 (second code inspection means) for performing a code check of a command or status using code check information included in the transmission information; Performs processing (I / O setting, serial port setting, etc.) corresponding to the command and status included in the transmission information, and status after the command and processing (address of the slave board 65, presence of frame error, CRC error) Response information generation means 75 for generating response information including the presence / absence of information, I / O status, serial port status, etc.).

  The CRC checker 79 (second code check information adding means) generates the command or status code check information included in the response information, adds it to the electrical response signal, and outputs it to the response signal converting means 73. Is possible. Further, the slave board 65 converts response information including a command or status and sign inspection information into an electrical response signal and outputs the electrical response signal, and converts the electrical response signal into an optical response signal and outputs it. Optical signal output means PD1 (second optical signal output means).

  The CRC checker 79 generates code check information using, for example, a command or status included in the transmission information, and compares the code check information with the code check information included in the transmission information. If both code check information matches, it is determined that the command or status has been acquired normally. On the other hand, when both code check information does not match, an attempt is made to restore the command or status based on the command or status and the code check information.

  When the restoration of the command or status is successful, the restored command or status is output as an electrical transmission signal to the response information generating means 75, and processing corresponding to the command and status is performed based on the restored transmission information. Execute and generate response information.

  On the other hand, if the command or status cannot be restored, information indicating a CRC error is output to the response information generating means 75. Then, the response information generation unit 75 generates an electrical response signal including a status indicating that a CRC error has occurred without executing processing corresponding to the command and status, and outputs the electrical response signal together with the command to the response signal conversion unit 73. . The electrical response signal is converted into an optical response signal and output to the master communication device 67.

  As the code check, cyclic redundancy check by CRC (Cyclic Redundancy Check) can be used, but SHA, MD5 and other code checks can also be used.

  The optical response signal output from the slave communication device 68 is input by the optical signal input means PD3 (first optical signal input means) of the master communication device 67, converted into an electrical response signal, and output. The response signal restoration unit 76 acquires the electrical response signal output from the optical signal input unit PD3.

  The response signal restoration means 76 converts the acquired electrical response signal into command or status and response information of code check information and outputs it to the bus I / F or the like. The time-out checker 78 measures the time required until the response signal restoration means 76 acquires the electrical response signal after the transmission signal conversion means 72 outputs the electrical transmission signal, and when the required time exceeds the threshold time. Generates a timeout error. In this case, the transmission signal conversion means 72 is instructed to re-output the electric transmission signal including the command or status and the code check information. In this way, when the electrical response signal corresponding to the electrical transmission signal does not return within a predetermined time, the master communication device 67 automatically re-outputs the electrical transmission signal including the command or status and code check information. Therefore, more reliable communication can be realized without depending on the monitoring of the main CPU 31 connected to the upper level via the bus I / F.

  Also, the CRC checker 79 (first code check information adding means) of the master communication device 67 generates code check information using, for example, a command or status included in the response information, and code check information included in the response information. Compare with. If both code check information matches, it is determined that the command or status has been acquired normally. On the other hand, when both code check information does not match, an attempt is made to restore the command or status based on the command or status and the code check information.

  When the restoration of the command or status is successful, the restored command or status is output as an electrical response signal to the response signal restoration means 76, and the response corresponding to the command and status is based on the restored electrical response signal. Information is generated and output to the upper main CPU 31 via the bus I / F.

  On the other hand, if the command or status cannot be restored, information indicating a CRC error is output to the response signal restoring means 76. Then, the response signal restoring unit 76 generates a status indicating that a CRC error has occurred without executing the process of transmitting the command and status to the upper main CPU 31. Then, the transmission signal conversion means 72 is instructed to re-output the electric transmission signal including the command or status and the code check information.

  Note that the CRC checker 79 of the master communication device 67 not only instructs re-output of the electric transmission signal when a CRC error occurs in the electric response signal, but also the slave communication device 68 or the control signal acquired by the response signal restoring means 76. Even when it is determined that the status of the tool board 66 includes information indicating that a CRC error has occurred on the slave communication device 68 or the jig board 66 side, electrical transmission to the transmission signal conversion means 72 is performed. A signal re-output may be instructed.

  As described above, when a CRC error is detected in the master communication device 67, the slave communication device 68, or the jig substrate 66, the master communication device 67 automatically re-outputs the electrical transmission signal including the command or the status and the code inspection information. Therefore, more reliable communication can be realized without depending on the monitoring of the main CPU 31 connected to the upper level via the bus I / F. Information indicating that a time-out error and a CRC error have occurred and information indicating that the electrical transmission signal is being re-outputted may be output to the upper main CPU 31 via the bus I / F. As the master communication device 67, the slave communication device 68, and the jig communication device 69, a CPU, a ROM, a RAM, a communication port, an ASIC having an I / O, or the like can be used.

  Next, the data format when using asynchronous communication in transmitting the electrical transmission signal, the optical transmission signal, the optical response signal, and the electrical response signal shown in FIG. 5 will be described.

  FIG. 6 is a diagram showing a 1-byte data format constituting a part of the electrical transmission signal, optical transmission signal, electrical response signal, and optical response signal shown in FIG. The horizontal axis in FIG. 6 is time t.

  For example, when the master board 64 is powered on and the initial setting is completed and communication is possible, the transmission signal converter 72 sets the electrical transmission signal to Hi and sets the idle state. For example, at this time, the light emitting element of the optical signal output means PD1 is turned off.

  When transmission of transmission information is started, transmission signal conversion means 72 outputs a Lo value as a start bit for a predetermined time before transmitting data. Then, the optical signal output means PD1 turns on the light emitting element for a predetermined time.

  When the optical signal input means PD3 of the slave communication device 68 inputs an optical transmission signal as a start bit, the electric transmission signal is dropped from Hi to Lo. When the transmission signal restoring means 74 recognizes that the electrical transmission signal has dropped from Hi to Lo, it prepares to store the data D7 to D0 that will be sent next in the buffer.

  Subsequently, the transmission signal converter 72 sequentially generates and outputs 8-bit data of D7 to D0 and parity bits for parity check at a time interval corresponding to a predetermined baud rate. When the output of the parity bit is completed, a stop bit consisting of 1, 1.5 or 2 bits is output to fix the electrical transmission signal to the Hi state.

  The optical signal input means PD1 of the master communication device 67 converts the data output from the transmission signal conversion means 72 into an optical transmission signal as it is and outputs it. On the other hand, the optical signal input means PD3 of the slave communication device 68 receives the optical transmission signal output from the optical signal output means PD1, converts the input optical transmission signal into an electric transmission signal, and generates a CRC checker 79, response information. The data is output to the generation means 75 and the like.

  The transmission signal restoration unit 74 of the slave communication device 68 samples the D7 to D0 and parity bit electrical transmission signals obtained from the optical signal input unit PD3 at time intervals corresponding to a predetermined baud rate, and sequentially Store it in the buffer. When the transmission signal restoring means 74 acquires the stop bit, it calculates a parity check value from the data D7 to D0 and compares it with the value of the parity bit transmitted from the master communication device 67. If the values of both parity bits match, it is determined that 1-byte data has been acquired normally.

  Note that if the transmission signal restoration unit 74 cannot acquire the stop bit within a predetermined period, it is determined that a framing error has occurred. If the parity bit values do not match, it is determined that a parity error has occurred. When a framing error or a parity error occurs, the response information generation means 75 of the slave communication device 68 adds response information in which the status of the communication error is added to the bit of the communication error assigned to the slave board. Generate.

  Similar to the transmission signal conversion means 72 of the master communication device 67, when the response signal conversion means 73 of the slave communication device 68 starts transmission of response information, a start bit, a 1-byte data bit, a parity bit, And a stop bit. The electrical response signal is input by the optical signal output means PD1 of the slave communication device 68, converted into an optical response signal, and output to the optical signal input means PD3 of the master communication device 67. The optical signal input means PD3 of the master communication device 67 converts the input optical response signal into an electrical response signal and outputs it to the response signal restoration means 76.

  When the response signal restoring means 76 of the master communication device 67 acquires the start bit, it sequentially stores the data D7 to D0 and the parity bit that are sent in the buffer, and when it acquires the stop bit, it uses the data D7 to D0. Perform a parity check. If the response signal restoration means 76 of the master communication device 67 cannot acquire the stop bit, it is determined that a framing error has occurred. If the parity bit values do not match, it is determined that a parity error has occurred. When this framing error or parity error occurs, the transmission signal conversion means 72 of the master communication device 67 outputs the previously transmitted electrical transmission signal again and retransmits the optical transmission signal.

  Next, a configuration example of the master communication device 67S and the slave communication device 68S in the case where synchronous communication is used in transmitting the electrical transmission signal, the optical transmission signal, the optical response signal, and the electrical response signal will be described with reference to FIG. I will explain.

  FIG. 7 is a block diagram of the master communication device 67S and the slave communication device 68S. For ease of explanation, FIG. 7 illustrates a state in which only one slave substrate 65S is connected to one master substrate 64S. It is also possible to connect the tool substrate 66S in a daisy chain manner. In addition, the same code | symbol is attached | subjected about the component same as the structure of the master communication apparatus 67 shown in FIG. 5, and the slave communication apparatus 68, and the description is abbreviate | omitted.

As shown in FIG. 7, the master communication device 67S and the slave communication device 68S are provided with a transmission signal conversion means 72 and a response signal conversion means 73 compliant with, for example, an I ² C device. The transmission signal conversion means 72 and the response signal conversion means 73 are provided with a terminal of a data line SDA for I ² C interface and a terminal of a clock line SCL that outputs a synchronization signal. The signal timing of the data line SDA and the clock line SCL will be described later with reference to FIG. The communication device for optical communication according to the present invention, but are not limited to for I ² C interface, the case of applying the I ² C interface as an example of the embodiment.

In the normal I ² C interface, every time the slave receives, for example, one byte of data, the master recognizes the response of the acknowledge signal by dropping the signal line of the SDA connected by wired OR connection to Lo. When the master monitors the SDA line and recognizes the response of the acknowledge signal, it is determined that the transmission of a predetermined amount of data has been confirmed, and transmission of the next 1-byte data is started continuously.

  Here, when the master and the slave are wired OR connected by an electric wire, it is possible to recognize the acknowledge signal by monitoring the SDA line after the master transmits 1-byte data. However, if the signal lines of SDA and SCL are simply replaced with optical communication, a wired OR connection cannot be easily realized with optical communication, and an acknowledge signal cannot be returned from the slave to the master. Then, the master cannot transmit the next data, and retransmits the same data again, or executes a communication error routine when a predetermined time has elapsed.

  In the present invention, the pseudo-acknowledge response means 77 is provided in the master side communication device in order to convert the communication between the master and the slave into the optical communication and to make it possible to divert the existing hardware and software relating to the communication. (The details of the pseudo acknowledge response means 77 will be described later with reference to FIG. 9). When optical communication is performed, there is little problem that the slave line receives noise information due to noise on the signal line.Therefore, the pseudo-acknowledge signal is transmitted from the master side transmission device without confirming the response of the acknowledge signal from the slave side. No problem occurs even if communication is continued by generating. In the present invention, since the information transmission path between the master communication device 67S and the slave communication device 68S is connected in a loop, the timeout error and CRC error are checked and the countermeasures are taken. Will not occur.

  The SDA and SCL electrical transmission signals output from the pseudo acknowledge response means 77 of the master communication device 67S are the optical signal output means PD1 (first optical signal output means) and the optical signal output means PD2 (first output) of the master communication device 67S. 1 optical signal output means) converts it into SDA and SCL optical transmission signals and outputs them.

  On the other hand, the slave communication device 68S receives the SDA and SCL light transmission signals output from the master communication device 67S side, converts them into SDA and SCL electrical transmission signals, and outputs them, respectively. A second optical signal input means) and an optical signal input means PD4 (second optical signal input means). Further, the slave communication device 68S includes a transmission signal restoring means 74 that converts the SDA and SCL electrical transmission signals into transmission information and outputs the transmission information.

  Similarly, the slave communication device 68S includes a pseudo acknowledge response unit 77 that outputs a pseudo acknowledge signal to the response signal conversion unit 73. The pseudo acknowledge responding means 77 arranged in the master communication device 67S and the pseudo acknowledge response means 77 arranged in the slave communication device 68S can use the same circuit.

  The SDA and SCL electrical transmission signals output from the pseudo acknowledge response means 77 of the slave communication device 68S are the optical signal output means PD1 (first optical signal output means) and the optical signal output means PD2 (first output) of the slave communication device 68S. 1 optical signal output means) converts it into SDA and SCL optical transmission signals and outputs them.

  The master communication device 67S receives the optical response signals of SDA and SCL output from the slave communication device 68S side, converts them into electrical response signals of SDA and SCL, respectively, and outputs optical signal input means PD3 (second output) Optical signal input means) and optical signal input means PD4 (second optical signal input means). Further, the master communication device 67S includes response signal restoring means 76 that converts the electrical response signals of SDA and SCL into response information and outputs the response information. Note that processing similar to the detection and handling described with reference to FIG. 5 can be executed for timeout errors and CRC errors.

Next, among the signal lines used for the I ² C interface, SDA (represents a data line in the I ² C interface) and SCL (represents a clock line in the I ² C interface) using the timing chart shown in FIG. .) Will be described. In FIG. 8, the logic change at each check point (CP1 to CP10) shown in FIG. 9 described later is shown together with SDA and SCL.

Communication device for optical communication according to the present invention, but are not limited to for I ² C interface, the case of applying the I ² C interface as an example of the embodiment.

The I ² C interface is a communication standard capable of performing multi-node designation serial communication in half duplex within a short distance such as on-board. The I ² C interface is used to transmit and receive various information between peripheral devices such as microcontrollers, PLL synthesizers, serial ROMs, color decoders, sound decoders, audio processors, video processors, image processing devices, and on-screen displays. Can be used for

The I ² C interface using electric wires is composed of only two bus lines, SDA and SCL, and outputs data and clock signals to SDA and SCL, respectively, when the master transmits data or addresses. Each device connected to the I ² C interface bus has a unique address, and each device can be controlled by software based on the unique address. In addition, a simple relationship between a master and a slave is always established between devices, and the device can function as a master transmitter and a master receiver.

As for the communication speed of the I ² C interface, there is a standard for transmitting 8-bit serial data at a standard rate of 100 Kbit / s, fast mode 400 Kbit / s, and high speed mode 3.4 MKbit / s. If the capacitance of the bus is 400 pF or less, a plurality of devices can be connected on one bus.

Since the I ² C interface uses a bus configuration, it is easy to add or delete a plurality of types of devices in the system. In addition, since a large number of I ² C devices and program modules are provided, it is possible to greatly reduce the development time required for hardware and software development related to communication. In addition, the I ² C interface provides a number of failure diagnosis tools and debugging tools. By using these general-purpose tools, failure diagnosis and debugging can be performed easily, so it is very easy to investigate defective parts. There are a number of advantages. With this feature, it is possible to easily provide variations of a plurality of types of gaming machines with one basic configuration.

In the I ² C interface using electric wires, the signal lines of SDA and SCL are pulled up by open collector outputs. Thereby, a wired OR connection is realized between the master and the slave. Accordingly, by monitoring the logic of the SDA and SCL signal lines in each of the master and slave I ² C devices, signals are transmitted and received from both the master and the slave, and weights are set. It is possible.

In the I ² C interface, it is allowed to sample the SDA data at the rising edge of the SCL and change the SDA data only when the SCL is Lo. In the example shown in FIG. 8, the data is fixed to 8 bits. In the bus-free phase in the no-signal state, each device has a signal of SCL (a line indicated as CP1 in FIGS. 8 and 9) and a signal of SDA (a line indicated as CP2 in FIGS. 8 and 9). The line is not used (pulled up). From this state, any device can freely access the I ² C interface bus.

  For example, when the master starts transmitting 8 bits (predetermined quantity) of data, the SDA is lowered to Lo while the SCL is Hi. This state is the start state of the bus start phase (Start Condition). Subsequently, the SDA is dropped to Lo to end the start condition and prepare to transmit a predetermined amount of data.

  In the case of transmitting data, first, after setting the data or address of MSB D7, SCL is raised to Hi. At this timing, the slave acquires the D7 data by sampling. Subsequently, the master drops SCL to Lo and sequentially outputs data or addresses of D6, D5... D0.

In the I ² C interface, when the slave finishes receiving 8-bit data and drops SCL to Lo, the master sets the SDA line to Hi (high impedance state) and enters the acknowledge bit (also called ACK response phase). The master waits for an acknowledge signal response. In the I ² C interface, when SCL rises to Hi in this acknowledge bit, the SDA line is dropped on the slave side in advance so that the SDA line is Lo, so that an acknowledge signal (ACK) is responded to the master. It has become. The master monitors the SDA line, and when the SDA is dropped to Lo at the timing when the SCL line rises to Hi, a response to the acknowledge signal is received.

  When the master monitors the SDA line and receives an acknowledge signal response, it is determined that the transmission of a predetermined amount of data has been confirmed, and the SCL falls in the acknowledge bit (referred to as the end of the acknowledge bit). Subsequently, transmission of the next 8-bit data is started.

  When the master completes a series of data transmission, after the acknowledge bit is finished, SDA is dropped to Lo, and then a state is created in which both SCL and SDA are temporarily Lo. Thereafter, SCL is set to Hi first to start a stop condition, and then SDA is set to Hi to end the stop condition. The period from the start of the stop condition to the end of the stop condition is referred to as a bus end phase (Stop Condition).

  Here, when the master and the slave are wired-OR connected by an electric wire, the slave forcibly drops the SDA line set by the master to Hi in the acknowledge bit to Lo, so that the acknowledge signal Sending a response. However, if the signal lines of SDA and SCL are simply replaced with optical communication, a wired OR connection cannot be easily realized with optical communication, and an acknowledge signal cannot be returned from the slave to the master. Then, the master cannot transmit the next data, and retransmits the same data again, or executes a communication error routine when a predetermined time has elapsed.

  In the present invention, in order to convert the communication between the master and the slave into optical communication and to make it possible to divert the existing hardware and software related to the communication, the master communication device 67S and the slave communication device 68S have a pseudo acknowledge response. Means 77 is provided (see FIG. 9 described later). In the case of optical communication, there is almost no problem that the slave receives wrong information due to noise on the signal line. Therefore, even if the master communication device 67S generates a pseudo acknowledge signal and continues communication without confirming the response of the acknowledge signal from the slave side, almost no problem occurs.

  Next, FIG. 9 shows a circuit diagram of the pseudo acknowledge response means 77 of the master communication device 67S and the slave communication device 68S according to the present invention, and FIG. 10 shows a circuit diagram of the receiving device on the slave side. Is described.

Circuit diagram shown in FIG. 9, I ² C outgoing signal converting means interface is compliant device 72 and the response signal converting means 73, I ² C to convert the interface into an optical communication interface optical signal output means PD1 and an optical signal output This is a circuit example on the transmission side including means PD2, a counter CT for counting a predetermined amount of data, and a pseudo acknowledge signal generating means 3SB.

The circuit diagram shown in FIG. 10 is a circuit diagram on the receiving side mounted on, for example, the master communication device 67S, the slave communication device 68S, or the jig substrate 66, and a receiving device that converts an optical communication interface into an I ² C interface. This is an example of the circuit.

The transmission signal conversion means 72 and the response signal conversion means 73 shown in FIG. 9 are, for example, I ² C devices, and operate with a normal logic power supply despite communication with other peripheral devices. Further, the transmission signal conversion means 72 and the response signal conversion means 73 are provided with a terminal for the data line SDA for the I ² C interface and a terminal for the clock line SCL.

In the embodiment shown in FIG. 9, in order to generate a pseudo acknowledge signal on the communication device side, the logic level (for example, totem pole output) is generated from the SDA and SCL signal lines of the open collector output used in the I ² C interface. Signal lines such as SSDA and SSCL are generated. That is, the signal lines of SDA and SCL of the transmission signal conversion means 72 and the response signal conversion means 73 are once passed through the driver DR1 and then input to the Schmitt trigger type gate G1 for waveform shaping. When the SDA and SCL signals pass through the gate G1, signals of / SSDA and / SSCL logic levels are generated. Note that / SSDA represents the inverse logic of SSDA.

  Further, when the / SSDA and / SSCL signals pass through the gate G2, signals of the logic levels of SSDA and SSCL are generated.

  The SDA and SCL signals output from the driver DR1 are further transmitted to the cathodes of optical signal output means PD1 and PD2 for optical communication (for example, composed of light emitting elements such as LEDs) via the driver DR2. The Then, the converted SDA (optical data signal) and SCL (optical clock signal), which are turned on with negative logic, are output via the optical cable. Note that the anode of the driver DR2 is connected to the power source of + Vc via the current limiting resistor R1. A capacitor C1 connected to GND (0 V potential) in the vicinity of the current limiting resistor R1 is a smoothing and noise reducing capacitor for the current limiting resistor R1 through which an intermittent current flows.

On the other hand, the receiving device on the slave side shown in FIG. 10 inputs SDA (optical data signal) and SCL (optical clock signal) transmitted by the optical cable through optical signal input means PD3 and PD4 and converts them into an open collector output. Are sent to the SDA and SCL of the transmission signal restoring means 74 and the response signal restoring means 76 which are general-purpose I ² C devices.

  Next, the operation of the counter CT that counts that 8-bit data has been transmitted using the falling edge (/ SSCL) of the SCL clock generated by the transmission signal conversion means 72 and the response signal conversion means 73 will be described. The counter CT is a 4-bit ripple carry synchronous counter, and for example, a logic element such as 74161 can be used.

  In the embodiment shown in FIGS. 8 and 9, the preset of the counter CT connected to Hi at the start of the start condition, at the end of the stop condition, and when a carry signal (Carry Output) output from the counter CT is generated. The value inputs A to C are made valid and preparations for presetting the value “7” are made. That is, preparations are made for obtaining a count value when counting a predetermined quantity of data to be transmitted. By actually presetting a value of “7” in the counter CT, an 8-bit count value is set to enable counting. The next time / SSCL rises (that is, at the end of the start condition, Or at the falling edge of SCL in the acknowledge bit. In the embodiment shown in FIG. 9, since a general-purpose counter CT is used as a circuit for counting a predetermined amount of data to be transmitted, preparation and setting for presetting the count value are performed at different timings. It is also possible to simultaneously perform preparation and setting for presetting the count value by assembling this circuit.

  Thereafter, when / SSCL rises, / SSCL is sequentially counted eight times, and the carry signal that is continuously output when the value stored in the counter CT is “15” (so-called Carry Output. FIG. 8 and 9, the SDA of the transmission signal conversion means 72 and the response signal conversion means 73 (the line indicated as CP10 in FIGS. 8 and 9) is forcibly set to Lo. And a pseudo acknowledge signal is generated so that the transmission signal conversion means 72 and the response signal conversion means 73 recognize the ACK. In the embodiment shown in FIG. 9, the carry signal of the counter CT is used as a count completion signal for 8-bit data.

  The pseudo acknowledge signal generating means 3SB connected to the subsequent stage of the carry signal output terminal (Carry Output terminal) of the counter CT is a three-state buffer. After the presetting of the counter CT, when the counter CT receives the eighth / SSCL signal (the falling signal of the SCL of the eighth bit), immediately after that, the value of Hi is output to the CP 9 as a carry signal.

  While the carry signal of the counter CT is Hi, the value (Lo) of the input A is output to the output Y (CP10) of the pseudo acknowledge signal generating means 3SB. Therefore, when the SCL signal of the 8th bit falls, the SDA terminal of the transmission signal conversion means 72 and the response signal conversion means 73 immediately falls to Lo, and a pseudo acknowledge signal is generated.

  The carry signal (Carry Output = CP9) output from the counter CT falls to Lo simultaneously after the fall of the SCL signal at the end of the acknowledge bit (see FIG. 8). Then, since the output Y (CP10) of the pseudo acknowledge signal generating means 3SB is in a high impedance state, the response output of the pseudo acknowledge signal is finished together with the end of the acknowledge bit.

  When the carry signal of the counter CT becomes Hi, the output of the gate G5 (inverter) (the line labeled CP8 in FIGS. 8 and 9) becomes Lo and the output of the gate G3 (3-input AND) ( In FIG. 8 and FIG. 9, the line indicated as CP7) becomes Lo. Accordingly, since the / LOAD terminal of the counter CT falls to Lo, the counter CT is ready to be preset with a value of “7”.

  When / SSCL rises at the end of the acknowledge bit, the value stored in the counter CT is preset to “7” again, and the carry signal (Carry Output = CP9) also becomes Lo. While the carry signal of the counter CT is Lo, the output Y (CP10) of the pseudo acknowledge signal generating means 3SB is in a high impedance state, so that it does not affect the SDA signal line at all.

  Next, the presetting of the counter CT in the start condition will be described.

  At the start of the start condition, if SDA is dropped while SCL is Hi, DF2 (start start detecting means, start detecting means) shown in FIG. 9 detects the state. DF2 is a D-flip flop, and a logic element such as 7474 can be used.

  When DF2 detects the start of the start condition at the rise of / SSDA, the output Q (the line indicated as CP3 in FIGS. 8 and 9) is set to Hi, and the output / Q (CP4 in FIGS. 8 and 9) is set. Is set to Lo.

  Since the output / Q (CP4 = Lo) of DF2 is input to the gate G3, the output (CP7) of the gate G3 becomes Lo, and the counter CT is prepared to preset a value of “7”.

In the I ² C interface, SCL is set to Hi in the bus start phase. However, in order to read data sampling at the rising edge of SCL, it is necessary to temporarily drop SCL to Lo separately from data transmission. In the present invention, the first falling edge of the SCL after the bus start phase is stored, and the value of “7” is preset for the counter CT only at the first falling edge of the SCL. .

  Specifically, a signal for clearing DF2 that has detected the start of the start condition at the falling edge of SCL at the end of the start condition (a line indicated as CP5 in FIGS. 8 and 9) is output. DF3 (start end detection means, start detection means) is arranged. Thereby, the output / Q (CP4) of DF2 can be used as one of the preset conditions of the counter CT. As shown in FIG. 8, the outputs Q (CP3) and / Q (CP4) of DF2 can be configured to operate only during the start condition. The DF2 clear signal (CP5) returns to Hi at the fall of SCL after the first data (D7) transmission. Note that DF3 is a D-flip flop, and a logic element such as 7474 can be used.

  Next, presetting of the counter CT at the break of data bytes will be described.

  In general, in communication, loss of transfer rate is prevented by continuously transmitting data. Therefore, when generating a pseudo acknowledge signal for each piece of data transmitted continuously, it is necessary to preset the counter CT by detecting a break in data. In the present invention, a preset for the counter CT is prepared using the carry signal of the counter CT used for generating the acknowledge bit (Carry Output = CP9).

  Specifically, the carry signal (Carry Output = CP9) is inverted (CP8) using the gate G5, and the preparation of the preset is instructed to the counter CT together with the other conditions of CP4 and CP6. A value of “7” is preset for the counter CT at the falling edge of the SCL signal at the end of the acknowledge bit.

  Next, presetting of the counter CT in the stop condition will be described.

  As shown in FIG. 8, a stop condition is generated by starting up SDA from a state in which SCL is maintained at Hi. In the example shown in FIG. 9, DF1 (stop condition detection means) detects the state. DF1 is a D-flip flop, and a logic element such as 7474 can be used.

  When DF1 detects the end of the stop condition at the rising edge of SSDA, the output / Q of DF1 (a line indicated as CP6 in FIGS. 8 and 9) is set to Lo.

  Since the output / Q (CP6 = Lo) of DF1 is input to the gate G3, the output (CP7) of the gate G3 is also Lo, and the counter CT is ready to be preset with a value of “7”.

With the configuration as described above, it is possible to transmit information by converting the I ² C interface into two optical signals. And the influence of the external noise in the communication between board | substrates can be suppressed, and there exists an advantageous effect also with respect to the goto action using an electromagnetic wave.

DESCRIPTION OF SYMBOLS 1 ... Pachi slot 2 ... Cabinet 3 ... Reel 4 ... Display window 5 ... Liquid crystal display device 6 ... Start lever 6S ... Start switch 7 ... Stop button 8 ... Winning determination line 9 ... Front door 12 ... 7 segment display 13 ... Bet button 13S ... bet switch 15 ... medal slot 16 ... medal payout outlet 17 ... medal tray 21 ... speaker 23 ... payout panel 24 ... lamp 25 ... waist panel 39 ... reel motor drive circuit 43 ... medal payout device 46 ... stop switch 50 ... medal sensor 51 ... Selector 54 ... Power supply 55 ... Main control circuit 56 ... Sub control circuit 58 ... Lamp substrate 61 ... Lower plate LED substrate 62 ... Door relay substrate 63 ... External concentration terminal board 64 ... Master substrate 65 ... Slave substrate 66 ... Jig Substrate 67 ... Master communication device 68 ... Slave communication device 69 ... Jig communication device 70 ... Jig run 71 ... Jig switch 72 ... Transmission signal conversion means 73 ... Response signal conversion means 74 ... Transmission signal restoration means 75 ... Response information generation means 76 ... Response signal restoration means 77 ... Pseudo acknowledge response means 78 ... Timeout checker 79 ... CRC checker 110 ... Sound board 3SB ... Pseudo acknowledge signal generation means DF1 ... Stop condition detection means (D-flip-flop)
DF2 ... start start detection means, start detection means (D-flip-flop)
DF3 ... start end detection means, start detection means (D-flip-flop)
DR1, DR2 ... Drivers G1, G2, G3, G5 ... Gate PD1, PD2 ... Optical signal output means PD3, PD4 ... Optical signal input means

Claims (5)

The master communication device provided in the main control circuit, at least one slave substrate, the slave communication device provided on the slave substrate, and the communication interface between the master communication device and the slave communication device are used to transmit information. A gaming machine equipped with a communication means for performing
Game machine characterized by comprising a pseudo-acknowledge signal generating means for generating a pseudo acknowledge signal to confirm artificially the reception end with the master communication device is transmitting the data at a constant amount to complete. The master communication device is
Transmission signal conversion means for converting transmission information including a command and status into an electrical transmission signal and outputting it,
First optical signal output means for converting the electrical transmission signal into a light transmission signal and outputting the light transmission signal;
First optical signal input means for inputting an optical response signal including a command and a status, converting the optical response signal into an electrical response signal, and outputting the electrical response signal;
Response signal restoring means for converting the electrical response signal into command and status response information and outputting it, and
The slave communication device is
Second optical signal input means for inputting the optical transmission signal, converting it into an electric transmission signal and outputting it;
Transmission signal restoring means for converting the electrical transmission signal into the transmission information and outputting the transmission information;
Response information generating means for performing processing corresponding to the command and status included in the transmission information, and generating response information including the command and status after processing,
Response signal conversion means for converting the response information into an electrical response signal and outputting the electrical response signal;
Second optical signal output means for converting the electrical response signal into an optical response signal and outputting the optical response signal;
The gaming machine according to claim 1, further comprising: The oscillation signal conversion means, and data including a command and status, a clock signal for sampling of the data is output as the electrical oscillation signal,
The transmission signal restoration means converts the electrical transmission signal composed of data including a command and status and a clock signal for sampling the data into the transmission information and outputs the transmission information,
The response signal conversion means converts the response information including data including the command and the status after processing and a clock signal for sampling the data into an electrical response signal and outputs the electrical response signal.
The response signal restoring means converts the electrical response signal composed of data including a command and status and a clock signal for sampling the data into response information of the command and status, and outputs the response information.
The pseudo acknowledge signal generating means, said clock signal counted by the counter indicates that the counted value with a count completion signal output to reach the predetermined quantity, has finished sending the data in a predetermined quantity The gaming machine according to claim 2, wherein the acknowledge signal is generated in a pseudo manner. An I ² C interface is used as a communication interface between the transmission signal conversion means and the first optical signal output means and between the response signal conversion means and the second optical signal output means,
The first or second optical signal output means converts an I ² C interface data line and a clock line that are electrically wired-OR connected to an optical data signal and an optical clock signal, and outputs them. The gaming machine according to claim 3. The gaming machine according to any one of claims 1 to 4, characterized in that a said pseudo acknowledge signal generating means to said slave communication device.

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