JP5605784B2 - Game machine - Google Patents

Description

  The present invention relates to a pachislot machine, a pachinko machine, and other gaming machines.

  Conventionally, in a gaming machine such as a pachislot machine or a pachinko machine, a game that is advantageous to the player by making a transition based on the “general gaming state” of the basic gaming state and satisfying predetermined conditions or lottery results, etc. There are multiple types of “special game states” that can be executed, and depending on these various game states, effects using decoration lamps, liquid crystal display devices, sound generators, etc. are executed It is configured to be.

  In order to realize the determination of each game state and the execution of the production, the inside of the gaming machine is mainly based on a main control circuit for controlling the game processing operation and a control signal transmitted from the main control circuit. A sub-control circuit that performs effects and the like is arranged. The sub-control circuit is connected to a large number of peripheral devices such as decorative lamps, liquid crystal display devices, and sound generators for realizing effects by light, video, or sound.

  Particularly in recent years, there are also gaming machines in which 70 or more decorative lamps, liquid crystal display devices, and 5 or more speakers are arranged in order to realize various effects during the game.

  Of these, for example, in order to control the lighting and extinguishing of 70 or more decorative lamps, the I / O for controlling the decorative lamp lighting is provided in the sub-control circuit, and the electric wires are wired to the decorative lamps. A large amount of electric wires are connected to the sub-control circuit only with the lamp lighting wiring. If a large number of wires are connected to the sub-control circuit, the heat dissipation efficiency of the heating element in the sub-control circuit arranged in the casing of the gaming machine will decrease, the assembly work efficiency of the gaming machine will decrease, and maintenance of the gaming machine will Problems such as difficulty, an increase in the failure rate due to wire breakage or poor connection, and an increase in the manufacturing cost of gaming machines occur.

  Thus, in order to reduce problems caused by the presence of a large amount of wiring, a relay board for controlling these peripheral devices is provided in the vicinity of the peripheral devices such as decorative lamps, liquid crystal display devices, speakers, etc., and the sub-control circuit And a relay board are connected by bidirectional serial communication wiring (for example, see Patent Document 1).

  According to the invention described in Patent Document 1, assembly work can be performed by reducing the number of wires connected to the sub-control circuit by serializing the wiring between the sub-control circuit and the relay board. It is said that efficiency can be increased, manufacturing costs can be reduced, the amount of waste generated can be reduced, and noise generation can be further reduced.

FIG. 7 shows a circuit example in which the sub-control circuit and the relay board are serially communicated using the I ² C interface, and the two boards are communicably connected using a communication cable.

  The master-side communication means COM1 shown in FIG. 7 is a device mounted on the sub-control circuit side, and the slave-side communication means COM2 is a device mounted on the relay board side. The slave-side relay board shown in FIG. 7 is a board that controls turning on and off of a large number of lamps, for example.

The communication means COM1 shown in FIG. 7 is a general-purpose I ² C device that has been frequently used in recent years, and is a device connected to the sub CPU of the sub control circuit. The power supply for the communication means COM1 is a normal power supply for logic (+ Vc), but malfunctions due to receiving noise via a communication cable when connecting to a relay board located at a distant place. A power supply for communication (+ Vdd) is separately prepared and used in order to prevent isolation and to ensure isolation due to the power supply between the relay board.

The SDA (representing the data line in the I ² C interface) and SCL (representing the clock line in the I ² C interface) of the communication means COM1 on the master side convert the logic level and operate at 400 Kbit / s over a long distance. It is connected to the relay board side via a bidirectional buffer DR1 enabling communication and a communication cable.

  Similarly, SDA and SCL of the slave side communication means COM2 are connected to the sub control circuit side via the pull-up resistor R92, the bidirectional buffer DR2 and the communication cable.

  The SDA of the communication means COM1 and COM2 is a data line for transmitting data to be transmitted / received. The SCLs of the communication units COM1 and COM2 are clock lines that transmit a clock signal for sampling data to be transmitted.

  As shown in FIG. 7, in the case where communication is performed between the sub control circuit and the relay board using the wired OR connection using the pull-up resistor R92, the bidirectional buffers DR1 and DR2 are connected to the communication means COM1 and the communication. By inserting between the means COM2, the external noise picked up by the communication cable (also called a communication harness) can be reduced to some extent.

JP 2003-164560 A

  However, according to the gaming machine described in Patent Document 1, although the number of wires connected to the sub-control circuit can be reduced, when the distance between the sub-control circuit and the relay board becomes long, Depending on the capacity, it is necessary to keep the transmission speed of the communication low, and in order to improve the noise resistance, it is necessary to devise other means such as increasing the voltage of the signal line used for communication or flowing a large amount of current.

Also, if the distance between the sub-control circuit and the relay board is long, it will be difficult to comply with the on-board communication interface specifications represented by I ² C, etc. Will have to use a large and difficult to use communication interface.

  Further, as shown in FIG. 7, even when the bidirectional buffers DR1 and DR2 are inserted in the communication line between the sub-control circuit and the relay board, the external noise is still received via the communication cable. It becomes.

  In addition, when a player emits radio waves or discharges a pachislot machine or a pachinko machine during a game, a malfunction may be induced in the gaming machine, or an illegal program may be installed in a pre-crafted gaming machine. In some cases, illegal acts such as starting up are performed. When long wires are connected between the main control circuit, sub control circuit, and relay board, electromagnetic waves generated by these goto actions are received, and the sub control circuit and main control circuit are more likely to malfunction, and unauthorized programs are started. This causes problems such as being easy to do.

  Also, not only in the case of goto acts, static electricity is charged to the player's clothing, etc., and when the player touches the gaming machine, the static electricity is discharged to the gaming machine, or a mobile phone carried by the player is issued. An electromagnetic wave may cause a current to flow through the electric wires connecting the main control circuit, the sub control circuit, and the relay board, and may cause a malfunction in the main control circuit and the sub control circuit.

  The present invention has been made in view of the above problems, and reduces the wiring between boards to improve the heat dissipation efficiency in the housing, and reduces the occurrence rate of failures due to wire breakage, poor connection, etc. To provide a gaming machine capable of facilitating machine maintenance, reducing the manufacturing cost of a gaming machine, and reducing malfunctions of a main control circuit or a sub-control circuit due to external noise while maintaining an information transfer rate. It is an object.

A gaming machine according to the present invention includes a main control circuit, a sub control circuit, a liquid crystal display device, and various substrates, between the main control circuit and the sub control circuit, and between the sub control circuit, the liquid crystal display device, and the various substrates. during a game machine having a communication means for communicating with the communication interface of said main control circuit, the sub-control circuit, a liquid crystal display device and various substrates have a transmitting means and receiving means, respectively, before Symbol transmission means where and generating a pseudo acknowledge signal to confirm artificially the reception end and the transmission of the constant amount of data is completed.
According to the present invention, since the acknowledge signal originally generated on the receiving means side and transmitted to the transmitting means side is generated on the transmitting means side in a pseudo manner, the wiring between the substrates can be reduced.

Further, the transmission means according to the present invention includes an optical signal output means for converting the data and clock signal into an optical data signal and an optical clock signal and outputting the optical signal and an optical clock signal, and counts the clock signal. a counter for outputting a count completion signal upon reaching, by using the count completion signal the counter is output, and having a a pseudo acknowledge signal generating means for generating the pseudo acknowledge signal.

  According to the present invention, the acknowledge signal originally generated on the receiving device side is artificially generated on the transmitting device side and output to the transmitting means. Therefore, only the data and the clock signal are converted into optical signals, and the like. Optical communication can be performed between the substrates. By using optical communication for the transmission of information between the substrates, the electrical connection between the substrates can be disconnected while reducing the wiring between the substrates.

  Further, according to the present invention, the clock signal for sampling data is counted, and the acknowledge signal is simulated using the count completion signal of the counter that is output when the count value reaches a predetermined number. Since the data is generated and output to the transmission means, it is possible to immediately respond to the acknowledge signal after data transmission.

  Further, according to the present invention, it is possible to reduce the wiring between the boards by using communication for the transmission of information between the boards, improve the heat radiation efficiency in the housing, and break down due to the disconnection or poor connection of the wires. Can be reduced, and maintenance of the gaming machine can be facilitated. Further, by performing optical communication, it is possible to reduce malfunctions due to external noise mixed in via a communication line, a power line, or the like while maintaining an information transfer rate.

  In addition, since the acknowledge signal originally generated on the receiving device side is artificially generated on the transmitting device side and output to the transmission means, the received data by optical communication required to receive the response of the acknowledge signal Lines can be omitted.

  Therefore, according to the present invention, it is not necessary to provide an optical cable for receiving an acknowledge signal between the substrates when performing optical communication, and the circuit on the receiving device side can be simplified. Thereby, the cost of the product can be reduced and the development period can be shortened.

According to another aspect of the invention, an I ² C interface is used as the communication interface, and the optical signal output means converts a data line and a clock line that are electrically wired-OR connected into an optical data signal and an optical clock signal. It is converted and output.

According to the present invention, only the data line and clock line of the I ² C interface that are electrically wired-OR connected can be converted into an optical signal to transmit information. Familiar I ² C devices and program modules can be used as they are, and the development time required for communication hardware and software development can be greatly reduced. In addition, by using the I ² C interface, which provides many failure diagnosis tools and debugging tools, it is easy to diagnose and debug between boards using these general-purpose tools, and shorten the time to investigate the defective part. be able to.

  According to the present invention, it is possible to transmit information by connecting the main control circuit, the sub-control circuit, and the relay board by the communication interface, and therefore, the wiring between the boards is reduced to reduce the heat dissipation in the housing. Improve efficiency, reduce the rate of failure due to wire breakage or poor connection, facilitate maintenance of gaming machines, reduce gaming machine manufacturing costs, maintain information transfer rate, It is possible to reduce malfunctions of the main control circuit or the sub control circuit.

It is an external appearance perspective view of a pachislot. It is the perspective view which opened the front door of the pachislot and observed the inside of the pachislot. It is a figure explaining the structure of the circuit with which the front door block and cabinet block of a pachislot are equipped. 6 is a timing chart showing logic changes at SDA and SCL used in the I ² C interface and at each check point shown in FIG. It is an example of a circuit of a transmission device that converts an I ² C interface into an optical communication interface and generates a pseudo acknowledge signal. It is a circuit example of the receiver which converts an optical communication interface into an I ² C interface. FIG. 6 is a circuit diagram of a conventional example using an I ² C interface in which a bidirectional buffer is inserted for communication between a sub control circuit and a relay board.

  An embodiment in which the present invention is applied to a pachislot machine 1 will be described below with reference to the drawings. Note that the present invention can also be applied to pachinko and other gaming machines.

  FIG. 1 is an external perspective view of the pachi-slot 1, and FIG. 2 is a perspective view of the interior of the pachi-slot 1 when the front door 9 that is pivotally supported on the front surface of the cabinet 2 is opened.

  The pachi-slot 1 includes a cabinet 2 that houses a reel 3, a circuit board, and the like, and a front door 9 that is attached to the cabinet 2 so as to be openable and closable. Inside the cabinet 2, three reels 3 are provided side by side. Each reel 3 is configured by attaching a belt-like sheet in which a plurality of symbols (for example, 21 pieces) are continuously arranged along the rotation direction to the peripheral surface of a cylindrical frame.

  A liquid crystal display device 5 is provided at the center of the front door 9. The liquid crystal display device 5 includes a display screen including a symbol display area, and is provided so as to be positioned on the near side superimposed on the three reels 3 when viewed from the front. The symbol display area is provided corresponding to each of the three reels 3 and has a configuration capable of transmitting through the reels 3 provided behind the reels 3.

  That is, the symbol display area functions as the display window 4, and the player can visually recognize the rotation and the stop operation of the reel 3 provided behind the display window 4. In the present embodiment, the entire display screen including the symbol display area is used to display an image and execute an effect.

  When the rotation of the reel 3 provided behind the symbol 3 is stopped, the symbol display area (hereinafter referred to as the display window 4) has an upper stage and a middle stage within the frame among a plurality of types of symbols arranged on the surface of the reel 3. In addition, one symbol (three in total) is displayed in each of the lower areas. In addition, a pseudo line formed by combining any one of the three regions including the upper stage, the middle stage, and the lower stage of each display window 4 is a target line for determining whether or not to win ( It is defined as a winning determination line 8).

  In the present embodiment, a top line that combines the upper stages of the display windows 4, a center line that combines the middle stages of the display windows 4, a bottom line that combines the lower stages of the display windows 4, and an upper stage of the left display window. , Winning determination of five cross-down lines that combine the middle stage of the middle display window and the lower stage of the right display window, the lower stage of the left display window, the cross-up line that combines the middle stage of the middle display window and the upper stage of the right display window Line 8 is provided.

  The front door 9 is provided with various devices to be operated by the player. The medal slot 15 arranged on the right side of the pedestal part is provided for receiving medals dropped from the outside by the player. The medals accepted by the medal slot 15 are inserted into one game with a predetermined number (for example, three) as an upper limit, and the amount exceeding the predetermined number can be deposited inside the pachislot 1 ( So-called credit function).

  The bet button 13 disposed on the left side of the pedestal portion is provided for determining the number of coins to be inserted into one game from medals deposited inside the pachislot 1. The checkout button 14 is provided to pull out medals deposited inside the pachislot 1 to the outside.

  A start lever 6 disposed on the left side of the pedestal is provided to start the rotation of all the reels 3. The stop button 7 is associated with each of the three reels 3 and is provided to stop the rotation of the corresponding reel 3.

  The 7-segment indicator 12 arranged on the left side of the reel 3 is made up of 7-segment LEDs, and the number of medals inserted in the current game (hereinafter referred to as the number of medals) and the medal paid out to the player as a privilege. Information such as the number of sheets (hereinafter referred to as payout number) and the number of medals deposited in the pachislot machine 1 (hereinafter referred to as credit number) is digitally displayed to the player.

  A large number of lamps 24 (LEDs, etc.) are arranged on the side and upper side of the liquid crystal display device 5, and depending on the contents of the production, movement of the lighting state, rotation of the lighting state, strobe light emission, and other points Emits light with a light-off pattern. A pair of speakers 21 arranged on the lower left and right sides of the liquid crystal display device 5 outputs sound such as sound effects and music corresponding to the contents of the performance. The medal payout port 16 guides medals discharged by driving a medal payout device described later to the outside. The medals discharged from the medal payout opening 16 are stored in the medal tray 17.

  Below the liquid crystal display device 5 and above the pedestal portion, a payout panel 23 for displaying a symbol combination, a medal payout number, and the like is disposed. Further, below the pedestal portion, a waist panel 25 for displaying a machine name and a character design is provided. A pair of speakers 21 that enhance sound effects such as effects are also provided behind the medal tray 17 below the waist panel 25.

  FIG. 2 is a diagram showing the internal structure of the pachislot machine 1 according to the present embodiment, in which the front door 9 is opened, and the structure on the back side of the front door 9 and the structure inside the cabinet 2 appear. .

  A board (hereinafter referred to as a main board) constituting the main control circuit 55 is provided above the inside of the cabinet 2. The main control circuit 55 is a circuit that controls the main flow of the game in the pachi-slot 1 such as determination of an internal winning combination, rotation and stop of the reel 3, and determination of presence / absence of winning.

  Three reels 3 are provided in the center inside the cabinet 2. A stepping motor is connected to each reel 3 via a gear having a predetermined reduction ratio.

  A medal payout device 43 having a structure capable of accommodating a large number of medals and discharging them one by one is provided below the inside of the cabinet 2. On the left side of the medal payout device 43, a power supply device 54 is provided for supplying necessary power to each device of the pachislot machine 1.

  A substrate (hereinafter referred to as a sub-board) constituting the sub-control circuit 56 is provided on the upper side of the back side of the front door 9. The sub-control circuit 56 is a circuit that controls execution of effects by turning on / off the lamp 24, generating sound, displaying images, and the like. A specific configuration of the sub control circuit 56 will be described later.

  A selector 51 is provided at the center of the back side of the front door 9 and below the display window 4. The selector 51 is a device for selecting whether or not a medal is appropriate in material, shape, and the like, and guides an appropriate medal received in the medal insertion slot 15 to the medal payout device 43. A medal sensor 50 (see FIG. 3), which will be described later, is provided on a path through which the medal passes in the selector 51, and detects that an appropriate medal has passed.

  This completes the description of the structure of the pachislot 1. Next, with reference to FIG. 3, the structure of the circuit provided in the front door block (the back side of the front door 9) and the cabinet block (inside the cabinet 2) of the pachi-slot 1 in the present embodiment will be described. The pachi-slot 1 in the present embodiment includes a main control circuit 55, a sub-control circuit 56, a relay board that is electrically connected to these, and peripheral devices.

  The main control circuit 55 is mainly composed of a microcomputer installed on a circuit board. The microcomputer includes a CPU (hereinafter referred to as a main CPU), a ROM (hereinafter referred to as a main ROM), a RAM (hereinafter referred to as a main RAM), an I / O, a communication circuit, and the like.

  The main ROM stores a control program executed by the main CPU, a data table such as an internal lottery table, data for transmitting various control commands (commands) to the sub control circuit 56, and the like. The main RAM is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program.

  A clock pulse generation circuit, a frequency divider, a random number generator, a sampling circuit, and the like are connected to the main CPU of the main control circuit 55, and the main CPU executes a control program based on the generated clock pulses. . The random number generator generates a random number in a predetermined range (for example, 0 to 65535), and the sampling circuit extracts one value from the generated random number and performs lottery processing relating to the game.

  The main board of the main control circuit 55 includes a power supply device 54 that supplies electric power, a reel motor drive circuit 39 that controls the rotation and stop of the reel 3, a medal payout device 43 that controls the payout of medals, a host computer of the game hall, and the like It is connected to each relay board such as an external concentration terminal board 63 and a door relay board 62 for transmitting and receiving information.

  Further, the main control circuit 55 inserts medals, operates the start lever 6, operates the stop button 7 with respect to the sub-control circuit 56 that executes control of the lamp 24, the liquid crystal display device 5, or the sound generation device for production. Various information such as operation, internal winning combination, display combination, gaming state, etc. is transmitted. For this purpose, the main board of the main control circuit 55 is connected to the sub board of the sub control circuit 56 by communication.

  The door relay board 62 connected to the main control circuit 55 is connected to wires such as various switches arranged in the operation unit of the pachislot machine 1. The medal sensor 50 connected to the door relay board 62 detects that the medal received in the medal slot 15 has passed through the selector 51 described above.

  The bet switch 13S connected to the door relay board 62 detects that the bet button 13 has been operated by the player. The start switch 6S detects that the start lever 6 has been operated by the player.

  The stop switch 46 detects that each of the three stop buttons 7 has been pressed by the player. Input information such as these switches is transmitted from the door relay board 62 to the main board of the main control circuit 55. The main control circuit 55 advances the game based on the input information, and controls operations of peripheral devices such as the reel motor drive circuit 39 and the medal payout device 43.

  The reel motor drive circuit 39 controls driving of a stepping motor arranged for each reel 3. Each reel 3 is connected to a reel position detection circuit. The reel position detection circuit detects a reel index indicating that the reel 3 has made one rotation by an optical sensor having a light emitting part and a light receiving part.

  The driving force of the stepping motor that rotates each reel 3 is transmitted to the reel 3 through a gear having a predetermined reduction ratio. Each time one pulse is output to the stepping motor, the reel 3 rotates at a constant angle.

  The main CPU of the main control circuit 55 detects the reel index and counts the number of times a pulse is output to the stepping motor, thereby rotating the rotation angle of the reel 3 (mainly, how many symbols the reel 3 rotates) The position of each symbol arranged on the surface of the reel 3 is managed.

  The medal payout device 43 is provided with a medal detection unit that detects the number of medals to be paid out and checks whether or not medals discharged from the medal payout device 43 have reached the payout number. be able to.

  Next, the sub-board of the sub-control circuit 56 arranged on the back side of the front door 9, the peripheral devices connected thereto, and various relay boards will be described.

  The sub control circuit 56 is connected to the main control circuit 55 by communication, and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 55. The sub-control circuit 56 basically includes a CPU (hereinafter referred to as sub-CPU), ROM (hereinafter referred to as sub-ROM), RAM (hereinafter referred to as sub-RAM), rendering processor, drawing RAM, driver, DSP (digital signal processor), An audio RAM, an A / D converter, and an amplifier are included.

  In response to the command transmitted from the main control circuit 55, the sub CPU of the sub control circuit 56 controls the output of video, sound, and light according to the control program stored in the sub ROM. The sub-RAM is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 55. The sub ROM basically includes a program storage area and a data storage area.

  The program storage area stores a control program executed by the sub CPU. For example, in the control program, a main board communication task for controlling communication with the main control circuit 55 and an effect registration task for extracting and registering effect contents (effect data) by extracting effect random numbers. A drawing control task for controlling the display of video by the liquid crystal display device 5 based on the determined contents of the production, a lamp control task for controlling the light output by the lamp 24, a voice control task for controlling the sound output by the speaker 21, and the like. included.

  The sub-control circuit 56 is connected to the liquid crystal display device 5, the speaker 21 and the sound board 110, the lamp board 58, the lower plate LED board 61, and the like as peripheral devices whose operations are controlled.

  The sub CPU, the rendering processor, the drawing RAM (including the frame buffer), and the driver of the sub control circuit 56 create a video according to the animation data designated by the contents of the presentation, and transmit the created video to the liquid crystal display device 5. indicate.

  Further, the sub CPU, DSP, audio RAM, A / D converter, and amplifier of the sub control circuit 56 output sounds such as BGM from the upper speaker 21 in accordance with the sound data specified by the production contents. Further, the sub CPU transmits a command of audio information designated by the production contents to the sound board 110. The sound board 110 that has received the voice information command analyzes the command, generates a voice signal using a DSP, an audio RAM, an A / D converter, an amplifier, and the like, and outputs a voice from the lower speaker 21 and the rear speaker 21. Output.

  Further, the sub CPU of the sub control circuit 56 turns on and off the lamp 24 in accordance with the lamp data designated by the contents of the effect.

  Based on the command received from the sub-control circuit 56, the lamp board 58 is a pattern for turning on and off the lamps 24 arranged mainly on the side of the liquid crystal display device 5 at the upper front of the pachi-slot 1 shown in FIG. Can be switched. The sub-control circuit 56 transmits a command according to the contents of effects related to turning on / off the lamp 24 to the lamp board 58. When the lamp board 58 receives the command, the lamp board 58 individually controls lighting and extinguishing of the lamps 24 arranged in large numbers, moving the lighting state, rotating the lighting state, strobe light emission, and other points. Each lamp 24 is caused to emit light in an extinguishing pattern.

  Here, the sub-control circuit 56 can directly control the lighting / extinguishing of a large number of lamps 24. However, in order to directly control the lighting / extinguishing of a large number of lamps 24, the sub-CPU of the sub-control circuit 56 uses I The driver for the lamp 24 must be directly controlled via / O, and a large amount of wires must be connected to the sub-board of the sub-control circuit 56.

  Then, with the increase in wiring, the occurrence rate of failures due to wire breakage, poor connection, etc. increases, maintenance of the pachislot 1 becomes difficult, and the price of the pachislot 1 increases. In addition, when a plurality of types of model variations are provided in the pachislot machine 1, it is naturally preferable to change the appearance of the front door 9 and the arrangement of the lamps 24 used for effects and the lighting-on / off state for each model. However, if the sub-control circuit 56 directly controls turning on / off of the individual lamps 24, it is necessary to prepare a significantly different production program for each model, which requires a huge development period, This will cause problems such as an increase in product price.

  Therefore, the sub-control circuit 56 generates and outputs only the command for turning on / off, and executes the control for turning off the individual lamps 24 on the lamp substrate 58 side, thereby shortening the development period and reducing the product price. The rise can be suppressed.

Furthermore, if a new communication standard is adopted as a communication means between the sub-control circuit 56 and the lamp substrate 58, a great development period and cost are required to develop a communication element and establish a protocol. By using a familiar general-purpose communication standard, reliable communication can be realized in a short period of time and at a low cost. In particular, a simple communication standard such as I ² C is convenient for performing communication between a plurality of substrates in one housing.

  However, in gaming machines such as pachislot 1 and pachinko machines, it is illegal to cause malfunctions in gaming machines by irradiating radio waves to these gaming machines or discharging them, or illegally in gaming machines that have been crafted in advance. Unauthorized gossip, such as starting a program, always occurs.

  Therefore, when developing these gaming machines, not only the main control circuit 55 but also the sub-control circuit 56 will implement sufficient countermeasures against these goto acts in advance so that new gaming machines can be found in the game hall. From the beginning of the replacement, it is important to reduce the motivation of the goto act by appealing that it is a clean machine against the goto act. In particular, since the front door 9 present at a position directly confronting the player is likely to be a target of goto action, sufficient measures are required.

  Similarly, when a player's clothing is charged with static electricity, and the static electricity is discharged to the gaming machine at the moment when the player touches the gaming machine, or due to electromagnetic waves emitted from the mobile phone carried by the player, It is preferable that no malfunction occurs in the main control circuit 55 or the sub control circuit 56.

However, in simple communication standards such as I ² C, information is transmitted and received using electric wires, so communication lines, power lines, ground lines, etc. included in communication cables connecting between boards are electromagnetic waves. May be transmitted to the lamp substrate 58, the sub control circuit 56, and further to the main control circuit 55 as noise. If noise is applied to the communication line between the lamp board 58 and the sub-control circuit 56, there is a possibility that the timing of turning on / off the lamp 24 may be delayed or a malfunction may be caused due to a delay in information transmission due to command retransmission or the like. Arise.

  In addition, if a power line or a ground line included in the communication cable picks up a strong electromagnetic wave, a malfunction may be induced in the sub control circuit 56 or the main control circuit 55. Although measures to implement strong shielding measures on the communication cable itself are also conceivable, if a shielded wire is used for the communication line, a large capacity load will be connected in parallel, so it must be used at a reduced communication speed. Troubles such as becoming difficult or difficult to handle wiring with poor flexibility.

  Therefore, in the present invention, by using an optical communication cable instead of an electric wire as a communication cable, the occurrence of noise due to the irradiated electromagnetic wave is prevented while maintaining a predetermined communication speed, and the lamp substrate 58 and the sub-cable are connected. A malfunction in the control circuit 56 and the main control circuit 55 is prevented.

  In addition, as described above, optical communication is used to transmit information between the lamp substrate 58 and the sub control circuit 56, and the sub control circuit 56 and the sound substrate 110 are connected between the sub control circuit 56 and the liquid crystal display device 5. Optical communication is also used for communication between the sub-control circuit 56 and the lower LED board 61, between the sub-control circuit 56 and the main control circuit 55, and between the main control circuit 55 and the door relay board 62. Can be used.

Next, among the signal lines used for the I ² C interface, SDA (represents a data line in the I ² C interface) and SCL (represents a clock line in the I ² C interface) using the timing chart shown in FIG. ) Will be described. In FIG. 4, the logic change at each checkpoint (CP1 to CP10) shown in FIG. 5 described later is shown together with SDA and SCL.

Communication device for optical communication according to the present invention, but are not limited to for I ² C interface, the case of applying the I ² C interface as an example of the embodiment.

The I ² C interface is a communication standard capable of performing multi-node designation serial communication in half duplex within a short distance such as on-board. The I ² C interface is used to transmit and receive various information between peripheral devices such as microcontrollers, PLL synthesizers, serial ROMs, color decoders, sound decoders, audio processors, video processors, image processing devices, and on-screen displays. Can be used for

The I ² C interface using electric wires is composed of only two bus lines, SDA and SCL, and outputs data and clock signals to SDA and SCL, respectively, when the master transmits data or addresses. Each device connected to the I ² C interface bus has a unique address, and each device can be controlled by software based on the unique address. In addition, a simple relationship between a master and a slave is always established between devices, and the device can function as a master transmitter and a master receiver.

As for the communication speed of the I ² C interface, there is a standard for transmitting 8-bit serial data at a standard rate of 100 Kbit / s, fast mode 400 Kbit / s, and high speed mode 3.4 MKbit / s. If the capacitance of the bus is 400 pF or less, a plurality of devices can be connected on one bus.

Since the I ² C interface uses a bus configuration, it is easy to add or delete a plurality of types of devices in the system. In addition, since a large number of I ² C devices and program modules are provided, it is possible to greatly reduce the development time required for hardware and software development related to communication. In addition, the I ² C interface provides a number of failure diagnosis tools and debugging tools. By using these general-purpose tools, failure diagnosis and debugging can be performed easily, so it is very easy to investigate defective parts. There are a number of advantages. With this feature, it is possible to easily provide variations of a plurality of types of gaming machines with one basic configuration.

In the I ² C interface using electric wires, the signal lines of SDA and SCL are pulled up by open collector outputs. Thereby, a wired OR connection is realized between the master and the slave. Accordingly, by monitoring the logic of the SDA and SCL signal lines in each of the master and slave I ² C devices, signals are transmitted and received from both the master and the slave, and weights are set. It is possible.

In the I ² C interface, it is allowed to sample the SDA data at the rising edge of the SCL and change the SDA data only when the SCL is Lo. In the example shown in FIG. 4, the data is fixed to 8 bits. In the no-signal state of the bus-free phase, any device has a signal of SCL (a line indicated as CP1 in FIGS. 4 and 5) and a signal of SDA (a line indicated as CP2 in FIGS. 4 and 5). The line is not used (pulled up). From this state, any device can freely access the I ² C interface bus.

  For example, when the master starts transmitting 8 bits (predetermined quantity) of data, the SDA is lowered to Lo while the SCL is Hi. This state is the start state of the bus start phase (Start Condition). Subsequently, the SDA is dropped to Lo to end the start condition and prepare to transmit a predetermined amount of data.

  In the case of transmitting data, first, after setting the data or address of MSB D7, SCL is raised to Hi. At this timing, the slave acquires the D7 data by sampling. Subsequently, the master drops SCL to Lo and sequentially outputs data or addresses of D6, D5... D0.

In the I ² C interface, when the slave finishes receiving 8-bit data and drops SCL to Lo, the master sets the SDA line to Hi (high impedance state) and enters the acknowledge bit (also called ACK response phase). The master waits for an acknowledge signal response. In the I ² C interface, when SCL rises to Hi in this acknowledge bit, the SDA line is dropped on the slave side in advance so that the SDA line is Lo, so that an acknowledge signal (ACK) is responded to the master. It has become. The master monitors the SDA line, and when the SDA is dropped to Lo at the timing when the SCL line rises to Hi, a response to the acknowledge signal is received.

  When the master monitors the SDA line and receives an acknowledge signal response, it is determined that the transmission of a predetermined amount of data has been confirmed, and the SCL falls in the acknowledge bit (referred to as the end of the acknowledge bit). Subsequently, transmission of the next 8-bit data is started.

  When the master completes a series of data transmission, after the acknowledge bit is finished, SDA is dropped to Lo, and then a state is created in which both SCL and SDA are temporarily Lo. Thereafter, SCL is set to Hi first to start a stop condition, and then SDA is set to Hi to end the stop condition. The period from the start of the stop condition to the end of the stop condition is referred to as a bus end phase (Stop Condition).

  Here, when the master and the slave are wired-OR connected by an electric wire, the slave forcibly drops the SDA line set by the master to Hi in the acknowledge bit to Lo, so that the acknowledge signal Sending a response. However, if the signal lines of SDA and SCL are simply replaced with optical communication, a wired OR connection cannot be easily realized with optical communication, and an acknowledge signal cannot be returned from the slave to the master. Then, the master cannot transmit the next data, and retransmits the same data again, or executes a communication error routine when a predetermined time has elapsed.

  In the present invention, in order to convert communication between a master and a slave into optical communication and to make it possible to divert existing communication hardware and software as they are, a pseudo-acknowledge signal generating means is provided in the master-side communication device. (See FIG. 5 described later). When optical communication is performed, noise does not appear on the signal line and the slave receives wrong information, so there is no need to confirm the response of the acknowledge signal from the slave side. Even if the signal is generated and the communication is continued, no problem occurs.

  Next, FIG. 5 shows a circuit diagram of the master-side transmitting apparatus according to the present invention, and FIG. 6 shows a circuit diagram of the slave-side receiving apparatus.

The master-side transmission device shown in FIG. 5 is a circuit mounted on, for example, a sub-board of the sub-control circuit 56. The counter CT converts the I ² C interface into an optical communication interface and counts a predetermined amount of data. And a pseudo acknowledge signal generating means 3SB.

6 is, for example, a circuit mounted on the lamp board 58, and is a circuit example of a receiving apparatus that converts an optical communication interface into an I ² C interface.

The communication unit COM1 (transmission unit) illustrated in FIG. 5 is, for example, a general-purpose I ² C device, and is a device connected to the sub CPU of the sub control circuit 56. The communication means COM1 can use a normal power supply for logic, and is provided with a terminal for the data line SDA for the I ² C interface and a terminal for the clock line SCL.

In the embodiment shown in FIG. 5, the logic level (for example, totem pole output) is generated from the SDA and SCL signal lines of the open collector output used in the I ² C interface in order to generate a pseudo acknowledge signal on the transmission device side. Signal lines such as SSDA and SSCL are generated. That is, the signal lines SDA and SCL of the communication means COM1 are once inputted through the driver DR1 and then inputted to the Schmitt trigger type gate G1 for waveform shaping. When the SDA and SCL signals pass through the gate G1, signals of / SSDA and / SSCL logic levels are generated. Note that / SSDA represents the inverse logic of SSDA.

  Further, when the / SSDA and / SSCL signals pass through the gate G2, signals of the logic levels of SSDA and SSCL are generated.

  The SDA and SCL signals output from the driver DR1 are further transmitted to the cathodes of optical signal output means PD1 and PD2 for optical communication (for example, composed of light emitting elements such as LEDs) via the driver DR2. The Then, the converted SDA (optical data signal) and SCL (optical clock signal), which are turned on with negative logic, are output via the optical cable. Note that the anode of the driver DR2 is connected to the power source of + Vc via the current limiting resistor R1. A capacitor C1 connected to GND (0 V potential) in the vicinity of the current limiting resistor R1 is a smoothing and noise reducing capacitor for the current limiting resistor R1 through which an intermittent current flows.

On the other hand, the receiving device on the slave side shown in FIG. 6 receives the SDA (optical data signal) and SCL (optical clock signal) transmitted by the optical cable by the light receiving elements PD3 and PD4 and converts them into an open collector output for general use. input to the SDA and SCL of I ² C devices in which the communication means COM2 (receiving means).

  Next, the operation of the counter CT that counts that 8-bit data has been transmitted using the falling edge of the SCL clock (/ SSCL) generated by the communication means COM1 will be described. The counter CT is a 4-bit ripple carry synchronous counter, and for example, a logic element such as 74161 can be used.

  In the embodiment shown in FIGS. 4 and 5, the preset value of the counter CT connected to Hi at the start of the start condition, at the end of the stop condition, and at the occurrence of a carry signal (CarryOutput) output from the counter CT. The inputs A to C are made valid and preparations are made to preset the value “7”. That is, preparations are made for obtaining a count value when counting a predetermined quantity of data to be transmitted. By actually presetting a value of “7” in the counter CT, an 8-bit count value is set to enable counting. The next time / SSCL rises (that is, at the end of the start condition, Or at the falling edge of SCL in the acknowledge bit. In the embodiment shown in FIG. 5, since a general-purpose counter CT is used as a circuit for counting a predetermined quantity of data to be transmitted, preparation and setting for presetting the count value are performed at different timings. It is also possible to simultaneously perform preparation and setting for presetting the count value by assembling this circuit.

  Thereafter, when / SSCL rises, / SSCL is sequentially counted eight times, and a carry signal that is continuously output when the value stored in the counter CT is “15” (so-called CarryOutput. FIG. 4). And the line indicated by CP9 in FIG. 5), the SDA of the communication means COM1 (the line indicated by CP10 in FIGS. 4 and 5) is forcibly dropped to Lo to generate a pseudo acknowledge signal. Thus, the communication unit COM1 is made to recognize ACK. In the embodiment shown in FIG. 5, the carry signal of the counter CT is used as a count completion signal for 8-bit data.

  The pseudo acknowledge signal generating means 3SB connected to the subsequent stage of the carry signal output terminal (CarryOutput terminal) of the counter CT is a three-state buffer. After the presetting of the counter CT, when the counter CT receives the eighth / SSCL signal (the falling signal of the SCL of the eighth bit), immediately after that, the value of Hi is output to the CP 9 as a carry signal.

  While the carry signal of the counter CT is Hi, the value (Lo) of the input A is output to the output Y (CP10) of the pseudo acknowledge signal generating means 3SB. Therefore, as soon as the 8th bit SCL signal falls, the SDA terminal of the communication means COM1 falls to Lo, and a pseudo acknowledge signal is generated.

  The carry signal (CarryOutput = CP9) output from the counter CT falls to Lo simultaneously after the fall of the SCL signal at the end of the acknowledge bit (see FIG. 4). Then, since the output Y (CP10) of the pseudo acknowledge signal generating means 3SB is in a high impedance state, the response output of the pseudo acknowledge signal is finished together with the end of the acknowledge bit.

  When the carry signal of the counter CT becomes Hi, the output of the gate G5 (inverter) (the line indicated by CP8 in FIGS. 4 and 5) becomes Lo and the output of the gate G3 (3-input AND) ( In FIG. 4 and FIG. 5, the line indicated as CP7) becomes Lo. Accordingly, since the / LOAD terminal of the counter CT falls to Lo, the counter CT is ready to be preset with a value of “7”.

  When / SSCL rises at the end of the acknowledge bit, the value stored in the counter CT is preset to “7” again, and the carry signal (CarryOutput = CP9) also becomes Lo. While the carry signal of the counter CT is Lo, the output Y (CP10) of the pseudo acknowledge signal generating means 3SB is in a high impedance state, so that it does not affect the SDA signal line at all.

  Next, the presetting of the counter CT in the start condition will be described.

  At the start of the start condition, if SDA is dropped while SCL is Hi, DF2 (start start detecting means, start detecting means) shown in FIG. 5 detects the state. DF2 is a D-flip flop, and a logic element such as 7474 can be used.

  When DF2 detects the start of the start condition at the rise of / SSDA, the output Q (the line indicated as CP3 in FIGS. 4 and 5) is set to Hi, and the output / Q (CP4 in FIGS. 4 and 5) is set. Is set to Lo.

  Since the output / Q (CP4 = Lo) of DF2 is input to the gate G3, the output (CP7) of the gate G3 becomes Lo, and the counter CT is prepared to preset a value of “7”.

In the I ² C interface, SCL is set to Hi in the bus start phase. However, in order to read data sampling at the rising edge of SCL, it is necessary to temporarily drop SCL to Lo separately from data transmission. In the present invention, the first falling edge of the SCL after the bus start phase is stored, and the value of “7” is preset for the counter CT only at the first falling edge of the SCL. .

  Specifically, a signal for clearing DF2 that has detected the start of the start condition at the falling edge of SCL at the end of the start condition (a line indicated as CP5 in FIGS. 4 and 5) is output. DF3 (start end detection means, start detection means) is arranged. Thereby, the output / Q (CP4) of DF2 can be used as one of the preset conditions of the counter CT. Then, as shown in FIG. 4, the outputs Q (CP3) and / Q (CP4) of DF2 can be configured to operate only during the start condition. The DF2 clear signal (CP5) returns to Hi at the fall of SCL after the first data (D7) transmission. Note that DF3 is a D-flip flop, and a logic element such as 7474 can be used.

  Next, presetting of the counter CT at the break of data bytes will be described.

  In general, in communication, loss of transfer rate is prevented by continuously transmitting data. Therefore, when generating a pseudo acknowledge signal for each piece of data transmitted continuously, it is necessary to preset the counter CT by detecting a break in data. In the present invention, a preset for the counter CT is prepared by using a carry signal (CarryOutput = CP9) of the counter CT used to generate an acknowledge bit.

  Specifically, the carry signal (CarryOutput = CP9) is inverted (CP8) using the gate G5, and the preparation of the preset is instructed to the counter CT together with the other conditions of CP4 and CP6. A value of “7” is preset for the counter CT at the falling edge of the SCL signal at the end of the acknowledge bit.

  Next, presetting of the counter CT in the stop condition will be described.

  As shown in FIG. 4, a stop condition is generated by starting up SDA from a state in which SCL is maintained at Hi. In the example shown in FIG. 5, DF1 (stop condition detection means) detects the state. DF1 is a D-flip flop, and a logic element such as 7474 can be used.

  When DF1 detects the end of the stop condition at the rise of SSDA, the output / Q of DF1 (a line indicated as CP6 in FIGS. 4 and 5) is set to Lo.

  Since the output / Q (CP6 = Lo) of DF1 is input to the gate G3, the output (CP7) of the gate G3 is also Lo, and the counter CT is ready to be preset with a value of “7”.

With the configuration as described above, it is possible to transmit information by converting the I ² C interface into two optical signals. And the influence of the external noise in the communication between board | substrates can be suppressed, and there exists an advantageous effect also with respect to the goto action using an electromagnetic wave.

DESCRIPTION OF SYMBOLS 1 ... Pachi slot 2 ... Cabinet 3 ... Reel 4 ... Display window 5 ... Liquid crystal display device 6 ... Start lever 6S ... Start switch 7 ... Stop button 8 ... Winning determination line 9 ... Front door 12 ... 7 segment display 13 ... Bet button 13S ... bet switch 15 ... medal slot 16 ... medal payout outlet 17 ... medal tray 21 ... speaker 23 ... payout panel 24 ... lamp 25 ... waist panel 39 ... reel motor drive circuit 43 ... medal payout device 46 ... stop switch 50 ... medal sensor 51 ... Selector 54 ... Power supply 55 ... Main control circuit 56 ... Sub control circuit 58 ... Lamp substrate 61 ... Lower plate LED substrate 62 ... Door relay substrate 63 ... External concentration terminal board 110 ... Sound substrate 3SB ... Pseudo acknowledge signal generation means DF1 ... Stop condition detection means (D-flip-flop)
DF2 ... start start detection means, start detection means (D-flip-flop)
DF3 ... start end detection means, start detection means (D-flip-flop)
DR1, DR2 ... Drivers G1, G2, G3, G5 ... Gate PD1, PD2 ... Optical signal output means PD3, PD4 ... Light receiving element

Claims (3)

Communication comprising a main control circuit, a sub control circuit, a liquid crystal display device and various substrates, and communicating via the communication interface between the main control circuit and the sub control circuit, and between the sub control circuit and the liquid crystal display device and the various substrates. A gaming machine equipped with means,
The main control circuit, the sub-control circuit, a liquid crystal display device and various substrates have a respective transmission means and receiving means,
Before Symbol transmitting means gaming machine and generates a pseudo acknowledgment signal confirming artificially the reception end to the transmission of data at constant volume completed. The transmission means includes
An optical signal output means for converting the data and the clock signal into an optical data signal and an optical clock signal and outputting them;
A counter that counts the clock signal and outputs a count completion signal when the count value reaches the predetermined quantity;
A pseudo acknowledge signal generating means using a count completion signal the counter output, generates the pseudo acknowledge signal,
The gaming machine according to claim 1, further comprising: An I ² C interface is used as the communication interface,
3. The gaming machine according to claim 2, wherein the optical signal output means converts the data line and the clock line that are electrically wired-OR connected into an optical data signal and an optical clock signal and outputs the optical data signal and the optical clock signal.

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