JP5616257B2 - Decoding circuit and node - Google Patents

Description

  The present invention relates to a decoding circuit for decoding a received waveform of a serial signal encoded with a binary code, and a node configured using the decoding circuit.

  Conventionally, CAN (Controller Area Network) has been standardized as an in-vehicle LAN protocol for realizing communication between a plurality of nodes mounted on a vehicle (ISO11898-1).

  In CAN, a binary code is used as a transmission code on a communication path, and dominant and recessive are defined as signal levels of the binary code. When any one node outputs a dominant signal, the signal level on the communication path is set to be dominant.

  In addition, in order to enable clock error correction from a signal received via a communication path, it is also defined that a stuff bit having an inverted signal level is inserted when the same signal level continues for 5 bits.

  Furthermore, in CAN, a physical layer having a sleep / wake-up function is also defined (ISO11898-5). Specifically, a node in the sleep mode, which is an operation mode for stopping the communication function for power saving, wakes up when detecting a dominant on the communication path, and is a normal mode in which the communication function can be used. It is specified to transition to.

  In a communication system having such a wake-up / sleep function, when there is a node in the sleep mode (hereinafter referred to as a dormant node), the normal mode that is the normal operation mode is set while the dormant node is in the sleep state. There has been a problem that it is not possible to communicate between only certain nodes (hereinafter referred to as startup nodes) or to selectively wake up only necessary nodes.

That is, performing communication means that a dominant appears on the communication path, and therefore, if the activation nodes communicate with each other, all the dormant nodes are activated.
On the other hand, when the transceiver detects that the bus is not in an idle state, the protocol controller that analyzes the received frame is activated (resumption of power supply) and received when the transceiver of the dormant node monitors the bus. A technique is described that activates (wakes up) the entire ECU when the protocol controller determines that the completed frame is a frame for waking up its own node (see, for example, Patent Document 1).

JP 2005-529393 A

  By the way, since the protocol controller must individually identify each bit constituting the frame by decoding the waveform of the received signal, usually, for the decoding operation, the clock signal from a high-accuracy clock source is used. It is necessary to receive supply. That is, in order to start the protocol controller, a high-accuracy clock source must be started at the same time.

  In a situation where the start node and the dormant node coexist, if the communication between the start nodes (that is, the non-idle state of the bus) continues, during that time, the dormant node has a protocol controller and a high-accuracy clock source. There has been a problem that power that cannot be ignored continues to be consumed despite being a dormant node (not functioning as an ECU).

  In order to solve the above problems, the present invention provides a decoding circuit that decodes serial data encoded by a binary code without using a clock signal, and a node configured using the decoding circuit. With the goal.

The decoding circuit according to claim 1, which is an invention made to achieve the above object, includes a normal mode that is an operation mode that operates according to a clock signal and a sleep that is an operation mode that reduces power consumption by stopping the clock signal. Applies to nodes with mode and operates in sleep mode. In addition, a serial signal encoded using a binary code whose signal level changes in units of preset unit time so that the same signal level does not continue for N (N is an integer of 3 or more) units or more. Is the target of decryption.

  In the decoding circuit according to the present invention, the edge detection circuit detects the edge of the serial signal, and the time signal generation circuit resets the value every time the edge detection circuit detects the edge, and the value with time elapses. Generates a time signal that increases.

  In addition, the determination circuit compares the time signal generated by the time signal generation circuit with one or a plurality of predetermined determination threshold values, so that the interval between the edges detected by the edge detection circuit is equal to the unit time. The level acquisition circuit determines the signal level of the serial signal corresponding to the edge interval determined by the determination circuit.

  Then, when the bit conversion circuit sets a state in which the edge interval is determined to be N times or more of the unit time by the determination circuit as a standby state, and an edge is detected by the edge detection circuit after the standby state is detected. Until the standby state is detected again, every time an edge is detected by the edge detection circuit, multiple bit data having the signal level acquired by the level acquisition circuit is determined by the determination circuit. Only generate.

The bit conversion circuit outputs the data string generated during the non-standby state as decoded data.
In the decoding circuit of the present invention configured as described above, the protocol controller is activated by determining, using a time signal, how many times the edge interval corresponds to the unit time, that is, how many bits the length corresponds to. Without decoding, the serial data encoded by the binary code is decoded.

  Therefore, according to the decoding circuit of the present invention, decoding can be performed without using an accurate clock signal synchronized with each bit of the serial signal, so that power consumption can be reduced. As a result, for example, it can be suitably used as a decoding circuit that is operated by a dormant node to detect a startup frame.

When the binary code is an NRZ code, the unit time is the same as the length of the 1-bit width of the code, and when the binary code is an RZ code whose signal level changes in the middle of the bit, the unit time is , It may be set so as to coincide with the half length of 1-bit width of the code.
Further, in the present invention, the time signal generating circuit charges the capacitive element capable of charging / discharging the charge with a constant current, and sets the charging voltage every time an edge is detected by the edge detection circuit. It consists of a charging circuit that resets to the initial voltage, and outputs the charging voltage of the capacitive element as a timing signal. Therefore, according to the present invention, the time signal can be generated by the analog circuit without using the clock signal.

  By the way, the determination circuit, for example, when the determination threshold generation circuit continues the edge interval for a period corresponding to k (2 ≦ k ≦ N, k is an integer) times the unit time. N-1 determination threshold values respectively set to the magnitudes of the signal levels of the time measurement signals are generated, and the comparison circuit determines each determination threshold value generated by the determination threshold value generation circuit and the signal level of the time measurement signal. You may be comprised so that a size may be compared.

  In this case, the determination threshold corresponding to k times the unit time is set as a k-bit determination threshold, and when the signal level of the timing signal is larger than the k-bit determination threshold and smaller than the k + 1-bit determination threshold, the edge interval to be determined is What is necessary is just to determine that it is k times the unit time.

  Further, in this case, as described in claim 3, the comparison circuit compares the signal level of the time measurement signal with the N−1 determination threshold values generated by the determination threshold value generation circuit individually. Selection may be made up of a plurality of comparators, and selection may be made to select and output any one of the N-1 determination threshold values generated by the determination threshold value generation circuit as claimed in claim 4. You may be comprised by the circuit and the single comparator which compares the magnitude of the output of a selection circuit, and the signal level of a timing signal.

  In the case of the former (Claim 3), since the comparison result for each determination threshold value can be obtained at the same time, the subsequent processing can be simplified. In the case of the latter (Claim 4), the number of comparators can be reduced. The circuit can be simplified and can be configured at low cost.

  In addition, as described in claim 5, the determination circuit has a determination threshold set to a signal level magnitude of the time measurement signal when the determination threshold generation circuit continues the edge interval for a period corresponding to the unit time. The comparison circuit compares the determination threshold generated by the determination threshold generation circuit with the signal level of the timing signal, and the counter counts the number of times that the signal level of the timing signal is determined to be greater than the determination threshold. It may be configured to.

  However, the time signal generation circuit resets the value of the time signal when the comparison circuit determines that the signal level of the time signal is greater than the determination threshold, and the counter detects an edge by the edge detection circuit. Each time the count value is reset, the count value before the reset is output as a multiple of the determination result.

In this case, every time a period corresponding to a unit time elapses, a count operation by a counter is executed, and the count value is reset every time an edge is detected.
In addition, as described in claim 6, the determination circuit includes the signal level of the time measurement signal when the determination threshold generation circuit continues the edge interval for a period corresponding to k (1 ≦ k ≦ N) times the unit time. N determination threshold values each set to the size of the threshold value are generated, and the selection circuit selects and outputs any one of the N determination threshold values generated by the determination threshold value generation circuit. Even if the one comparator is configured to compare the output of the selection circuit with the signal level of the timing signal, and the counter counts the number of times that the signal level of the timing signal is determined to be greater than the determination threshold. Good.

  However, each time the selection circuit determines that the signal level of the timing signal is higher than the output of the selection circuit by the comparator, the selection circuit switches the setting so that the determination threshold is selected in order from the smaller value, and the edge Each time the edge is detected by the detection circuit, the selection setting is reset. The counter resets the count value every time an edge is detected by the edge detection circuit, and outputs the count value of the counter before the reset as a multiple of the determination result.

  In this case, every time the elapsed time after the edge detection reaches a period corresponding to k (1, 2,... N) times the unit time, the counting operation by the counter is executed, and the edge is detected as the count value. It will be reset every time.

  By the way, as described in claim 7, the level acquisition circuit determines an inverted value of the signal level of the serial signal detected after the edge is detected by the edge detection circuit and before the unit time elapses. You may be comprised so that it may acquire as a signal level in the edge space | interval used as object.

  That is, the signal level of the edge interval that is the determination target is the signal level before edge detection, and is inverted from the signal level detected after edge detection (until the unit time elapses). Therefore, the signal level of the serial signal can be correctly grasped from such a configuration.

  The level acquisition circuit is initialized to a preset standby signal level when a standby state is detected, and detects an edge after a change from the standby state to the non-standby state. The storage signal level set so that the signal level is inverted every time an edge is detected by the circuit may be acquired as the signal level of the edge interval that is the determination target.

  That is, the signal level in the standby state is known, and in the binary code, the signal level is inverted every time an edge is detected, so these pieces of information (whether it is in a standby state or whether an edge is detected) Is obtained, it is possible to correctly grasp the signal level of the serial signal without directly detecting the signal level.

To the next node according to claim 9, a receiver for receiving the serial signals from the channel for performing communication using the binary code, of claims 1 to 9 for decoding the signal received via the receiver Decoding circuit according to any one of the above, and a process execution means for executing a specific process associated with the command when the data string decoded by the decoding circuit represents a preset command; It is constituted by.

  The node configured as described above can extract the command addressed to the node without using the clock signal from the received serial signal, so that the command can be received in a low power consumption state where the clock signal is stopped. I can wait.

In addition, the specific process can execute communication via the communication path from the sleep mode, which is an operation mode for stopping the communication via the communication path and suppressing power consumption, as described in claim 10 , for example. It may be a process for transitioning to the normal mode, which is a normal operation mode. However, the present invention is not limited to this, and any process may be used as the specific process.

The block diagram containing the circuit diagram which shows the structure of the decoding circuit of 1st Embodiment. The circuit diagram which shows the structure of an edge detection circuit, and the timing diagram which shows the operation | movement. The timing diagram which shows the operation example of a duration determination circuit. The flowchart which shows the content of the process implement | achieved by operation | movement of a bit conversion circuit. The block diagram which shows the structural example of the node comprised using the decoding circuit. The block diagram which shows the structural example of the node comprised using the decoding circuit. The block diagram which shows the structural example of the node comprised using the decoding circuit. The block diagram which shows the structure of the decoding circuit of 2nd Embodiment. The flowchart which shows the content of the process implement | achieved by operation | movement of a bit conversion circuit. The block diagram containing the circuit diagram which shows the structure of the decoding circuit of 3rd Embodiment. The flowchart which shows the content of the process implement | achieved by operation | movement of a bit conversion circuit. The block diagram containing the circuit diagram which shows the structure of the decoding circuit of 4th Embodiment. The timing diagram which shows the operation example of a duration determination circuit. The flowchart which shows the content of the process implement | achieved by operation | movement of a bit conversion circuit. The block diagram containing the circuit diagram which shows the structure of the decoding circuit of 5th Embodiment. The timing diagram which shows the operation example of a duration determination circuit.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
<Overall configuration>
FIG. 1 is a block diagram including a circuit diagram showing a configuration of a decoding circuit 1 that decodes a received waveform of a serial signal SI encoded with a binary code.

  It is assumed that the decoding circuit 1 is used for a node constituting a vehicle-mounted communication system using CAN (Controller Area Network) as a communication protocol. Therefore, an NRZ code is used as the binary code. Also, here, a dominant signal level in the communication path is represented by 0 (low level), and a recessive signal level inferior in the communication path is represented by 1 (high level). A state in which recessive continues for 6 bits or more in the communication path is called a standby state. At the beginning of the communication frame, there is an SOF consisting of a 1-bit dominant that appears after the standby state. Further, in the communication frame, in order to prevent the same signal level from continuing for 6 bits or more, if the same signal level continues for 5 bits, a 1-bit stuff bit in which the signal level is inverted is inserted.

  As shown in FIG. 1, the decoding circuit 1 includes an edge detection circuit 10 that generates an edge detection signal EG that indicates the timing of a rising edge and a falling edge at which the signal level of the serial signal SI changes, and an edge detection circuit 10. Determination signals J2 to J5 for determining how many times the interval between detected edges (ie, the duration of the same signal level in the serial signal SI) has a preset unit time. Based on the duration determination circuit 20 that generates JW, the serial signal SI, the edge detection signal EG, and the determination signals J2 to J5 and JW, the serial signal SI is converted into a bit data string without using a clock signal, and parallel And a bit conversion circuit 30 that outputs the data PO.

<Edge detection circuit>
2A is a circuit diagram showing a detailed configuration of the edge detection circuit 10, and FIG. 2B is a timing diagram showing signal waveforms of respective parts of the edge detection circuit 10. As shown in FIG.

  As shown in FIG. 2A, the edge detection circuit 10 includes an inverting circuit (NOT gate) 11 for inverting the signal level of the serial signal SI, and outputs of the serial signal SI and the NOT gate 11, that is, the serial signal SI. A negative OR circuit (NOR gate) 12 that takes an inverted signal DSI as an input and outputs both at a low level, and a serial signal SI and an inverted signal DSI as inputs, and outputs when both are at a high level. A logical product circuit (AND gate) 13 that becomes a high level, a falling edge signal DE that is the output of the NOR gate 12, and a rising edge signal UE that is the output of the AND gate 13 are input, and at least one of them is a high level. An OR gate 14 (OR gate) 14 whose output is sometimes at a high level. Is configured to output an output as an edge detection signal EG.

  In the edge detection circuit 10 configured in this way, as shown in FIG. 2B, the inverted signal DSI is delayed from the serial signal SI by the delay in the NOT gate 11, so that the falling edge of the serial signal SI Then, the falling edge signal DE having the pulse width corresponding to the delay is generated by the NOR gate 12, and the rising edge signal having the pulse width corresponding to the delay is generated by the AND gate 13 at the rising edge of the serial signal SI. A UE is generated. As a result, every time the signal level of the serial signal SI changes, the OR gate 14 generates an edge detection signal EG that becomes high level by the delay.

<Configuration of duration determination circuit>
Returning to FIG. 1, the duration determination circuit 20 is configured such that the capacitor 211 is configured so as to be able to charge and discharge electric charge and one end is grounded, and the non-grounded end of the capacitor 211 is set to the ground level or constant current source according to the clear signal SC described later. The time signal generating circuit 21 includes a switch 213 connected to any one of 212 and generates a time signal ST having a signal level of a voltage (hereinafter referred to as “charge voltage”) VC of a non-grounded end of the capacitor 211. The switch 213 is configured to connect the non-grounded end of the capacitor 211 to the ground side when the clear signal SC is high level and to the constant current source 212 side when the clear signal SC is low level.

  The duration determination circuit 20 includes a voltage dividing circuit 221 that includes a pair of resistors that divide the power supply voltage VDD and generates a reference voltage Vrefi (i = 2, 3, 4, 5, 6), and a reference at an inverting input terminal. A comparator 222 having a voltage Vrefi applied thereto and a timing signal ST applied to a non-inverting input terminal, and configured to output the output of the comparator 222 as an i-bit determination signal Ji, respectively. (22a-22e).

  Note that the reference voltage Vrefi has a unit length (1 bit width in this embodiment) at which the signal level changes in the serial signal SI as a unit time, and corresponds to the magnitude of the current supplied by the constant current source 212 and the capacitance of the capacitor 211. On the basis of this, when the period of continuous charging of the capacitor 211 is not longer than a period that is i-1 times the unit time, the charging voltage VC does not reach the reference voltage Vrefi, i.e., a length exceeding that, i.e., i When the bit length is reached, the charging voltage VC is set so as to exceed the reference voltage Vrefi.

  Further, the duration determination circuit 20 receives the 6-bit determination signal J6 from the multiple determination circuit 22a as a set input, the edge detection signal EG from the edge detection circuit 10 as a reset input, and the 6-bit determination signal J6 changes from low level to high level. The SR flip-flop circuit 23 that generates a standby state signal JW that is high until the pulse of the edge detection signal EG is input after the change, and the edge detection signal EG and the standby state signal JW are input. There is provided an OR circuit (OR gate) 26 for generating a clear signal SC that becomes a high level when at least one of them is at a high level.

<Operation of duration determination circuit>
FIG. 3 is a timing chart showing an operation example of the duration determination circuit 20.
As shown in FIG. 3, when the standby state signal JW is at a high level (the communication path for transmitting the serial signal SI is in a standby state), the serial signal SI changes to a low level and a pulse of the edge detection signal EG is generated (time t1) The standby state signal JW changes to the low level (the communication path is in the non-standby state), and the value of the timing signal ST (charge voltage VC) starts increasing at a constant rate.

  Thereafter, when the serial signal SI changes to the high level in a time corresponding to 1 bit width (one time of the unit time) (time t2), the charging voltage VC is smaller than the reference voltage Vref2 at this time, so the times t1 to t2 None of the determination signals J2 to J6 changes to a high level in the meantime, and the charging voltage VC is reset by the edge detection signal EG.

  Thereafter, when the serial signal SI changes to a high level in a time corresponding to a 4-bit width (four times the unit time) (time t3), the charging voltage VC is larger than the reference voltage Vref4 (smaller than Vref5) at this time. During the time t2 to t3, the determination signals J2, J3, and J4 sequentially change to the high level as the charging voltage VC increases, and the charging voltage VC is reset by the edge detection signal EG at time t3. Accordingly, the determination signals J2, J3, and J4 also return to the low level.

  Further, after the serial signal SI changes from the low level to the high level (time t4), a time corresponding to a 6-bit width (six times the unit time) elapses, and the charging voltage VC reaches the reference voltage Vref6 (time). t5) When the determination signal J6 changes to the high level, the standby state signal JW changes to the high level. As a result, the clear signal SC changes to the high level, so that the charging voltage VC is held in the reset state. The

  In this way, the duration determination circuit 20 has a signal level (charge voltage VC) corresponding to the elapsed time from the timing at which the edge is detected only in the non-standby state (standby state signal JW is low level). And an i-bit determination signal Ji and a standby state signal JW corresponding to the signal level are supplied to the bit conversion circuit 30.

<Operation of bit conversion circuit>
Next, the contents of processing realized by the operation of the bit conversion circuit 30 will be described with reference to the flowchart shown in FIG.

  Note that the bit conversion circuit 30 is configured by a combination of logic circuits. However, those skilled in the art can easily implement the processing based on the contents of processing, and have a feature in the combination of logic circuits. Therefore, the description of the circuit details is omitted here.

  However, the bit conversion circuit 30 includes a reception register having a size capable of storing the maximum transmission frame allowed in the system to which the decoding circuit 1 is applied, and a pointer for designating the write position of the reception register. Assume that at least a storage area for storing a set bit value to be described later is prepared.

The bit conversion circuit 30 first determines whether or not the communication path for transmitting the serial signal SI is in a standby state depending on whether or not the standby state signal JW is at a high level (S110).
If the communication path is in a standby state (S110: YES), it is next determined whether or not the reception register has been cleared (S120). If it has been cleared (S120: YES), the process returns to S110.

  Note that whether or not the reception register has been cleared may be determined, for example, if the pointer indicates the beginning of the reception register, or may be determined when the reception register is cleared. The determination may be made using a flag that is reset once writing to the reception register is performed.

  On the other hand, if the reception register has not been cleared (S120: NO), the contents of the reception register are output as parallel data PO by a predetermined number of bits (for example, 8 bits) (S130). The contents and the pointer value are cleared (S140), and the process returns to S110. In S130, the contents of the reception register may be moved to a storage area accessible from the outside of the bit conversion circuit 30, instead of being output as parallel data PO.

  If it is determined in S110 that the communication path is not in the standby state (S110: NO), it is determined whether the edge is detected by the edge detection circuit 10 (S150), and the edge must be detected. If this is the case (S150: NO), the process returns to S110 and waits until it changes to a standby state or an edge is detected.

  On the other hand, if an edge is detected (S150: YES), it is determined whether or not it is the first edge detected after the reception register or pointer is cleared in S140 (S160). (S160: YES) Since the determination result of the edge interval has not been obtained yet, the process directly returns to S110.

If the detected edge is not the first edge (S160: NO), the signal level of the serial signal SI is acquired, and its inverted value is stored as a set bit value (S170).
Then, it is determined whether or not the determination signal J5 is at a high level (S180). If the determination signal J5 is at a high level (S180: YES), the set bit value is written to the reception register by 5 bits from the position indicated by the pointer (S190). ).

  If the determination signal J5 is not at a high level (S180: NO), it is determined whether or not the determination signal J4 is at a high level (S200). If the determination signal J4 is at a high level (S200: YES), 4 from the position indicated by the pointer. The set bit value is written into the reception register by the amount of bits (S210).

  If the determination signal J4 is not at a high level (S200: NO), it is determined whether or not the determination signal J3 is at a high level (S220). If the determination signal J3 is at a high level (S220: YES), 3 is determined from the position indicated by the pointer. The set bit value is written into the reception register by the amount of bits (S230).

  If the determination signal J3 is not at a high level (S220: NO), it is determined whether or not the determination signal J2 is at a high level (S240). If the determination signal J3 is at a high level (S240: YES), 2 is determined from the position indicated by the pointer. The set bit value is written into the reception register by the amount of bits (S250).

If the determination signal J2 is not at the high level (NO in S240), the set bit value is written into the reception register by one bit from the position indicated by the pointer (S260).
When the reception register is written in any of S190, S210, S230, S250, and S260, the pointer is advanced by the number of bits written (S270), and the process returns to S110.

The bit conversion circuit 30 is configured to execute the processing of S160 to S270 in a time shorter than the shortest time (that is, unit time) of the assumed edge interval.
<Effect>
As described above, the decoding circuit 1 generates the time signal ST whose signal level increases in accordance with the elapsed time after edge detection, and the signal level (charge voltage VC) of the time signal ST and a preset reference. By comparing the voltages Vref2 to Vref6, it is determined how many times the edge interval corresponds to the unit time, that is, how many bits the length corresponds to, and the set bit value is set by the number of bits (multiple) of the determination result. By sequentially writing to the receiving register and repeating this every time an edge is detected, a bit string obtained by decoding the serial signal SI is generated.

  Therefore, according to the decoding circuit 1, since the serial signal SI encoded with the binary code is decoded without using the clock signal, the decoding is performed using a protocol controller or the like that operates according to the clock signal. Compared with the case, power consumption can be significantly reduced.

<Application to node>
Here, FIGS. 5 to 7 are block diagrams illustrating configuration examples of nodes configured using the decoding circuit 1.

<Application example 1>
The node 100 shown in FIG. 5A is configured around a microcomputer (microcomputer), and performs control processing assigned to the own node, communication processing with other nodes, processing for controlling the operation mode of the own node, and the like. The main processing circuit 2 to be executed is connected to a communication path LN that performs communication according to the CAN protocol, and data (transmission frame) TxD given from the main processing circuit 2 is encoded into a transmission code suitable for the communication path LN and output. And a transceiver 3 for supplying the main processing circuit 2 with data (received frame) RxD received and decoded via the communication path LN.

  Note that the operation mode of the node 100 includes a sleep mode which is an operation mode in which power consumption is reduced by stopping the operation of the main processing circuit 2 and the transceiver 3 by stopping the clock signal, and the node 100 as a whole. The normal mode, which is the operating mode to operate, is set. Note that the transceiver 3 is configured to be started / stopped by a start / stop signal supplied from the main processing circuit 2.

  In addition, after stopping the transceiver 3, the main processing circuit 2 executes a process for stopping the operation of the clock signal generation source to stop the operation of the microcomputer, thereby shifting to the sleep mode. When a wake-up signal WU, which will be described later, is input to the main processing circuit 2 in the sleep mode, the microcomputer is started by starting the clock signal generation source, and the transceiver 3 is started by the processing of the started microcomputer. By doing so, it is configured to transition to the normal mode.

  The node 100 operates when the operation of the transceiver 3 is stopped (in the sleep mode), and decodes the receiver 4 that captures a signal on the communication path LN and the signal (serial signal SI) that the receiver 4 captures. Based on the decoding circuit 1 and the decoding result (parallel data PO) in the decoding circuit 1, it is determined whether or not the captured signal is an activation frame for activating the own node. A frame determination circuit 5 that outputs a wake-up signal WU to the processing circuit 2, and a power supply circuit 6 that supplies power to the main processing circuit 2, the transceiver 3, the receiver 4, the decoding circuit 1, and the frame determination circuit 5. I have.

  In the node 100 configured as described above, in the sleep mode in which the main processing circuit 2 and the transceiver 3 are stopped, the decoding circuit 1 decodes the serial signal SI received via the receiver 4, and based on the decoding result, The frame determination circuit 5 determines whether or not a startup frame has been received.

  Therefore, the node 100 does not require a clock signal when determining whether or not to receive a start-up frame in the sleep mode, so that power consumption in the sleep mode can be reduced.

<Application example 2>
The node 101 shown in FIG. 5 (b) is different from the node 100 shown in FIG. 5 (a) only in a part of the configuration, so that the description will focus on the different parts of the configuration.

  The node 101 includes a power switch 7 inserted in the power supply line to the main processing circuit 2 and a power switch 8 inserted in the power supply line to the transceiver 3. It is turned on by a start signal (wake-up signal WU) from the frame determination circuit 5 and turned off by a stop signal from the main processing circuit 2.

  Note that when the power supply to the main processing circuit 2 or the like is stopped, the generation source of the clock signal is also stopped at the same time as the microcomputer, so the main processing circuit 2 performs only the process of outputting the stop signal when shifting to the sleep mode. There is no need to perform processing for stopping the generation source of the clock signal. Further, when the power supply to the main processing circuit 2 is started, the clock signal generation source is also activated, so that it is not necessary to supply the wakeup signal WU to the main processing circuit 2.

  In the node 101 configured as described above, not only the same effect as the node 100 can be obtained, but also the processing to be executed by the main processing circuit 2 can be simplified when the operation mode is changed.

<Application example 3>
The node 102 shown in FIG. 6A differs from the node 100 shown in FIG. 5A only in a part of the configuration, and therefore, the description will focus on the different parts of the configuration.

  The node 102 uses only the transmission function of the transceiver 3, the receiver 4 and the decoding circuit 1 operate not only in the sleep mode but also in the normal mode, and the main processing circuit 2 further performs the decoding result (that is, the decoding circuit 1). , Received frames).

  In the node 102 configured in this way, not only the same effects as the node 100 can be obtained, but also the circuit configuration (particularly the transceiver 3 and the like) can be simplified by effectively using the reception function of the receiver 4 and the decoding circuit 1. Can be

<Application example 4>
The node 103 shown in FIG. 6B is different from the node 101 shown in FIG. 5B only in a part of the configuration, and therefore the description will focus on the different parts of the configuration.

  Similarly to the node 102, the node 103 uses only the transmission function of the transceiver 3, and the receiver 4 and the decoding circuit 1 are operated not only in the sleep mode but also in the normal mode, and the main processing circuit 2 further includes the decoding circuit 1 The decoding result (received frame) at is obtained.

  In the node 103 configured as described above, not only the same effects as the node 101 can be obtained, but also the reception function of the receiver 4 and the decoding circuit 1 can be effectively used to simplify the circuit configuration (particularly the transceiver 3). Can be

<Application example 5>
A node 104 illustrated in FIG. 7A is a reception-only node that does not serve as a transmission source, and has a configuration in which the transceiver 3 is omitted from the node 102 illustrated in FIG. However, the main processing circuit 2a is configured without using a microcomputer.

<Application example 6>
The node 105 illustrated in FIG. 7B is a reception-only node that does not serve as a transmission source, and has a configuration in which the transceiver 3 and the power switch 8 are omitted from the node 103 illustrated in FIG. 6B. ing. However, like the node 104, the main processing circuit 2a is configured without using a microcomputer.

<Application example 7>
The node 106 illustrated in FIG. 7C is configured by identifying the frame determination circuit 5 in the node 104 illustrated in FIG. 7A so that a plurality of commands (which may include a start frame) can be identified. A command corresponding to the command is supplied to the main processing circuit 2a, and the main processing circuit 2a is configured to execute a plurality of types of control according to the command.

<Application example 8>
The node 107 shown in FIG. 7D configures the frame determination circuit 5 in the node 105 shown in FIG. 7B so that a plurality of commands other than the activation frame can be identified. A corresponding command is supplied to the main processing circuit 2a, and the main processing circuit 2a is configured to execute a plurality of types of control according to the command.

<Correspondence with Invention>
In this embodiment, the multiple determination circuit 22 is a determination circuit, the voltage dividing circuit 221 in each multiple determination circuit 22 is a determination threshold value generation circuit, the comparator 222 is a comparison circuit, and the circuit that implements the processing of S170 is a level acquisition circuit and a capacitor 211. The capacitive element, the constant current circuit 212, and the switch 213 correspond to a charging circuit. The frame determination circuit 5 and the main processing circuits 2 and 2a correspond to processing execution means.

[Second Embodiment]
Next, the decoding circuit 1a of 2nd Embodiment is demonstrated.
Since the decoding circuit 1a of the present embodiment is different only in part of the configuration and part of the processing realized by the operation of the bit conversion circuit 30, these differences will be mainly described.

FIG. 8A is a block diagram showing the configuration of the decoding circuit 1a, and FIG. 8B shows the decoding circuit 1 according to the first embodiment, which is shown again with the details of the duration determination circuit 20 omitted. It is.
As can be seen from FIG. 8, the decoding circuit 1a is configured in the same manner as the decoding circuit 1 except that the supply of the serial signal SI to the bit conversion circuit 30 is omitted.

FIG. 9 is a flowchart showing the contents of processing realized by the operation of the bit conversion circuit 30.
As shown in FIG. 9, as compared with the flowchart shown in FIG. 4, S145 is added after S140, and S175 is provided in place of S170.

  That is, when the communication path is in a standby state (S110: YES) and the register has not been cleared (S120: NO), the contents of the reception register are output (S130), and the reception register and the pointer are cleared ( In addition to (S140), a process of initializing the set bit value to “1” representing the signal level in the standby state (S145) is executed, and the process returns to S110.

  If the edge is not in the standby state (S110: NO), an edge is detected (S150: YES), and the edge is not the first edge after clearing (S160: NO), the set bit value is inverted (S175), and the following , S180 to S270 are executed.

  In other words, the setting bit value is not set based on the actually detected signal level of the serial signal SI, but a known standby signal level is set as the initial value of the setting bit value, and then an edge is detected. The value is inverted every time it is used.

<Effect>
The decoding circuit 1a configured in this way is different from the decoding circuit 1 only in the method of obtaining the set bit value, and otherwise operates in exactly the same manner, and thus can obtain the same effect as the decoding circuit 1. it can.

In addition, the circuit configuration can be simplified to the extent that it is not necessary to detect the signal level of the serial signal SI.
[Third Embodiment]
Next, the decoding circuit 1b of 3rd Embodiment is demonstrated.

<Overall configuration>
FIG. 10 is a block diagram including a circuit diagram showing the overall configuration of the decoding circuit 1b.
The decoding circuit 1b of the present embodiment is different from the decoding circuit 1 of the first embodiment in the processing realized by the configuration of the duration determination circuit 20a, the signals input to and output from the bit conversion circuit 30a, and the operation of the bit conversion circuit 30a. Since only the contents of are different, these differences will be mainly described.

  As shown in FIG. 10, the duration determination circuit 20 a includes a timing signal generation circuit 21, an SR flip-flop circuit 23, and an OR gate 24 similar to those in the duration determination circuit 20. However, the pulse-like standby state detection signal DW that is a set input of the SR flip-flop circuit 23 is configured to be supplied from the bit conversion circuit 30a.

<Multiple determination circuit>
In the duration determination circuit 20a, a multiple determination circuit 25 provided in place of the multiple determination circuit 22 includes five voltage dividing circuits that are composed of a pair of resistors for dividing the power supply voltage VDD and generate reference voltages Vref2 to Vref6. 251 to 255 and a selection circuit 256 for selecting any one of the reference voltages Vref2 to Vref6 according to the selection signal SEL, and a reference voltage Vrefk (k = 2, 3, 4, 5, 6) selected by the selection circuit 256 ) Is applied to the inverting input terminal and the timing signal ST is applied to the non-inverting input terminal, and the output of the comparator 257 is supplied to the bit conversion circuit 30a as the k-bit determination signal Jk. Yes.

<Bit conversion circuit>
In addition to the serial signal SI and the edge detection signal EG, the bit conversion circuit 30a receives a k-bit determination signal Jk instead of the determination signals J2 to J5 and JW. Then, the bit conversion circuit 30a is based on the k-bit determination signal Jk, the serial signal SI, and the edge detection signal EG acquired by controlling the operation of the duration determination circuit 20a by the selection signal SEL and the standby state detection signal DW. The serial signal SI is decoded and output as parallel data PO.

The contents of processing realized by the operation of the bit conversion circuit 30a will be described below with reference to the flowchart shown in FIG.
In the bit conversion circuit 30a, first, the selection signal SEL is set so that the selection circuit 256 selects the determination threshold Vref6 (S410), and the k-bit determination signal Jk (here, the 6-bit determination signal J6) is at a high level. Whether or not the communication path for transmitting the serial signal SI is in a standby state is determined based on whether or not (S420).

  If the communication path is in a standby state (S410: YES), it is determined whether the reception register has been cleared (S430), and if it has been cleared (S430: YES), the process returns to S420.

  On the other hand, if the reception register has not been cleared (S430: NO), the content of the reception register is output as parallel data PO by a predetermined number of bits (for example, 8 bits) (S440).

Thereafter, the contents of the reception register and the pointer value are cleared (S450), and a pulse-like standby state detection signal DW is output (S460), and the process returns to S420.
Due to the output of the standby state detection signal DW, the standby state signal JW, which is the output of the SR flip-flop circuit 23, becomes high level.

  If it is determined in S420 that the communication path is not in the standby state (S420: NO), it is determined whether the edge is detected by the edge detection circuit 10 (S470), and the edge must be detected. If this is the case (S470: NO), the process returns to S420 and waits until the state changes to a standby state or an edge is detected.

  On the other hand, if an edge is detected (S470: YES), it is determined whether or not it is the first edge detected after the reception register or pointer is cleared in S450 (S480). (S480: YES) Since the determination result of the edge interval has not been obtained yet, the process directly returns to S420.

  If the detected edge is not the first edge (S480: NO), the signal level of the serial signal SI is acquired, the inverted value thereof is stored as the set bit value (S490), and the determination threshold value for causing the selection circuit 256 to select it. Is set to k = 5 (S500).

  Then, according to the parameter k, the selection signal SEL is set so that the selection circuit 256 selects the determination threshold value Vrefk (S510), and it is determined whether or not the k-bit determination signal Jk is at a high level (S520).

  If the k-bit determination signal Jk is not high level (S520: NO), the parameter k is decreased by 1 (S530), it is determined whether or not the parameter k is 1 (S540), and the parameter k must be 1 If (S540: NO), the process returns to S510.

  On the other hand, when the k-bit determination signal Jk is at the high level (S520: YES) or the parameter k is 1 (S540: YES), the set bit value is written to the reception register by k bits from the position indicated by the pointer. (S550), the pointer is advanced by the number of bits written (S560), and the process returns to S410.

  The bit conversion circuit 30a is configured to execute the processing of S480 to S560 in a time shorter than the shortest time (that is, unit time) of the assumed edge interval. Further, the processes of S420 to S450 and S470 to S490 are the same as the processes of S110 to S170 in the bit conversion circuit 30.

<Effect>
In the decoding circuit 1b configured as described above, the number of the comparators 257 constituting the multiple determination circuit 25 can be reduced as compared with the multiple determination circuit 22 in the decoding circuit 1, so that the decoding circuit 1b can be reduced in size. Can be

[Fourth Embodiment]
Next, the decoding circuit 1c of 4th Embodiment is demonstrated.
<Overall configuration>
FIG. 12 is a block diagram including a circuit diagram showing the overall configuration of the decoding circuit 1c.

  The decoding circuit 1c of this embodiment differs from the decoding circuit 1 of the first embodiment in the processing realized by the configuration of the duration determination circuit 20b, the signals input to and output from the bit conversion circuit 30b, and the operation of the bit conversion circuit 30b. Since only the contents of are different, these differences will be mainly described.

  As shown in FIG. 12, the duration determination circuit 20 b includes a timing signal generation circuit 21 and an OR gate 24 similar to those in the duration determination circuit 20. However, the OR gate 24 is configured such that a 1-bit determination signal J1, which will be described later, is input instead of the standby state signal JW.

<Multiple determination circuit>
In the duration determination circuit 20b, a multiple determination circuit 26 provided in place of the multiple determination circuit 22 includes a voltage dividing circuit 261 that includes a pair of resistors for dividing the power supply voltage VDD and generates a reference voltage Vref1, and a voltage dividing circuit 261. The reference voltage Vref1 generated by the circuit 261 is applied to the inverting input terminal, and the comparator 262 is applied with the timing signal ST applied to the non-inverting input terminal. The output of the comparator 262 is output as the 1-bit determination signal J1. It is configured.

  The reference voltage Vref1 is set based on the magnitude of the current supplied by the constant current source 212 and the capacitance of the capacitor 211. When the capacitor 211 is continuously charged for a time shorter than the unit time by a predetermined time, the charge voltage VC becomes the reference voltage. The size is set to reach the voltage Vref1. The predetermined time is set to be shorter than at least the time obtained by dividing the unit time by N, where N (here, 6) is the number of bits used for determining the standby time.

  The duration determination circuit 20b is composed of a plurality of negative logic circuits (NOT gates), a delay circuit 27 that delays the edge detection signal EG, and a delay edge detection that the 1-bit determination signal J1 is input to the clock and the delay circuit 27 outputs. And a count circuit 28 composed of a 3-bit synchronous counter that operates using the signal DEG as a clear input, and is configured to supply outputs (count values) Q0 to Q2 of the count circuit 28 to the bit conversion circuit.

  When the count value reaches the upper limit value (Q0 = Q1 = Q2 = 1, ie, “7”), the count circuit 28 thereafter increases the upper limit value until the value is cleared by the delayed edge detection signal DEG. Is held (or the count operation is stopped). The delay circuit 27 is for operating the count circuit 28 reliably when the timing at which the 1-bit determination signal J1 changes to the high level and the timing at which the edge detection signal EG goes to the high level are close to each other. The time from when the count value is determined until the count value is cleared is set so as to secure a time during which the bit conversion circuit 30b can reliably recognize the count value.

<Operation of duration determination circuit>
FIG. 13 is a timing chart showing an operation example of the duration determination circuit 20b.
As shown in FIG. 13, when the serial signal SI changes to a low level and a pulse of the edge detection signal EG is generated (time t11) in the standby state where the count values Q0 to Q1 indicate 6 or more, the count values Q0 to Q1. Is cleared and the charging voltage VC is also reset to the ground level.

  Thereafter, the charging voltage VC increases with the passage of time, and when the reference voltage Vref1 is reached (time t12), the 1-bit determination signal J1 becomes a high level, whereby the count values Q0 to Q1 are counted up and the charging voltage is increased. VC is reset. Further, when the charging voltage VC is reset, the 1-bit determination signal J1 returns to the low level. Therefore, the 1-bit determination signal J1 is a pulse signal.

  Thereafter, when the serial signal SI changes to a high level in a time corresponding to 1-bit width (one time per unit time) (time t13), the count values Q0 to Q1 are cleared and the charging voltage VC is reset. At this time, the bit conversion circuit 30b takes in the count values Q0 to Q2 (here, 1) held at the timing of the edge detection signal EG longer than the timing by the delay time in the delay circuit 27.

  Thereafter, when the serial signal SI changes to a high level in a time corresponding to a 4-bit width (four times the unit time) (time t14), the charging voltage VC reset every time the reference voltage Vref1 is reached is from the time t13. Since the reference voltage Vref1 has been reached four times during t14, the count value Q0 to Q2 is 4, and this value is taken into the bit conversion circuit 30b, and the count value Q0 to Q2 is cleared and charged. The voltage VC is reset.

  Further, after the serial signal SI changes from the low level to the high level (time t15), the high level is maintained and the state continues, and the charging voltage VC reaches the reference voltage Vref1 seven times (t16). As long as the high level of SI is held, the count values Q0 to Q2 are also held at the upper limit of 7.

<Bit conversion circuit>
Returning to FIG. 12, in addition to the serial signal SI and the edge detection signal EG, the count value Q0 to Q2 of the count circuit 28 is input to the bit conversion circuit 30b instead of the determination signals J2 to J5 and JW. Then, the bit conversion circuit 30b decodes the serial signal SI based on the serial signal SI and the edge detection signal EG, and outputs it as parallel data PO.

The contents of processing realized by the operation of the bit conversion circuit 30b will be described below with reference to the flowchart shown in FIG.
In the bit conversion circuit 30b, first, it is determined whether or not the communication path for transmitting the serial signal SI is in a standby state depending on whether or not the count values Q0 to Q2 are 6 or more (S610).

  If the communication path LN is in the standby state (S610: YES), it is determined whether or not the reception register has been cleared (S620). If it has been cleared (S620: YES), the process returns to S610.

  On the other hand, if the reception register has not been cleared (S620: NO), the contents of the reception register are output as parallel data PO by a predetermined number of bits (for example, 8 bits) (S630). The contents and the pointer value are cleared (S640), and the process returns to S610.

  If it is determined in S610 that the communication path is not in a standby state (S610: NO), it is determined whether or not an edge is detected by the edge detection circuit 10 (S650), and the edge must not be detected. If this is the case (S650: NO), the process returns to S610 and waits until the state changes to a standby state or an edge is detected.

On the other hand, when an edge is detected (S650: YES), the count values Q0 to Q2 captured before the count values Q0 to Q2 are cleared are stored as the set number of bits (S660).
Then, in S640, it is determined whether or not it is the first edge detected after the reception register and the pointer are cleared (S670). If it is the first edge (S670: YES), the edge interval determination result is still present. Is not obtained, the process directly returns to S610.

If the detected edge is not the first edge (S670: NO), the signal level of the serial signal SI is acquired, and its inverted value is stored as a set bit value (S680).
Then, the set bit value is written into the reception register by the set bit number (S690), the pointer is advanced by the set bit number (S700), and the process returns to S610.

<Effect>
As described above, according to the decoding circuit 1c, since the count values Q0 to Q2 supplied from the duration determination circuit 20b can be used as they are as the number of bits of the edge interval, the configuration of the bit conversion circuit 30b is simplified. can do.

In the present embodiment, the OR gate 24 that generates the clear signal SC based on the 1-bit determination signal J1 corresponds to the reset circuit.
[Fifth Embodiment]
Next, a decoding circuit 1d according to the fifth embodiment will be described.

<Overall configuration>
FIG. 15 is a block diagram showing the overall configuration of the decoding circuit 1d.
The decoding circuit 1d of the present embodiment is different from the decoding circuit 1c of the fourth embodiment only in the configuration of the duration determination circuit 20b, and therefore this difference will be mainly described.

As shown in FIG. 15, the duration determination circuit 20 c includes a time signal generation circuit 21, a delay circuit 27, and a count circuit 28 similar to those in the duration determination circuit 20.
However, the OR gate 24 is omitted, and the switch 213 of the timing signal generation circuit 21 is configured to operate only by the edge detection signal EG.

<Multiple determination circuit>
In the duration determination circuit 20c, a multiple determination circuit 29 provided in place of the multiple determination circuit 26 is composed of a pair of resistors for dividing the power supply voltage VDD, and six voltage dividing circuits for generating reference voltages Vref1 to Vref6. 291 to 296, a selection circuit 297 for selecting any one of the reference voltages Vref1 to Vref6, and a reference voltage Vrefk (k = 1, 2, 3, 4, 5, 6) selected by the selection circuit 297 is inverted. The comparator 298 is applied to the input terminal and the timing signal ST is applied to the non-inverting input terminal. The judgment signal Jx, which is the output of the comparator 298, is supplied as the clock of the count circuit 28 and the selection signal of the selection circuit 297. It is configured as follows.

  In addition, every time the determination signal Jx changes from the low level to the high level, the selection circuit 297 switches the setting in order from the reference voltage Vref1 having a small value to the reference voltage Vref6 having a large value, and the edge detection signal EG is high. When the level is reached, the setting is initialized to the reference voltage Vref1.

<Operation of duration determination circuit>
FIG. 16 is a timing chart showing an operation example of the duration determination circuit 20c.
As shown in FIG. 16, when the count value Q0 to Q1 is in the standby state where the serial signal SI changes to low level and the edge detection signal EG pulse is generated (time t21), the count values Q0 to Q1 are changed. In addition to being cleared, the charging voltage VC is also reset to the ground level, and the selection circuit 297 is initialized to a setting for selecting the reference voltage Vref1.

  Thereafter, when the charging voltage VC increases with the passage of time and reaches the reference voltage Vref1 (time t22), the determination signal Jx becomes a high level, thereby counting up the count values Q0 to Q1, and the selection circuit 297. Is switched to the reference voltage Vref2 that is one greater, and the determination signal Jx returns to the low level accordingly. Therefore, the determination signal Jx is a pulse signal.

  Thereafter, when the serial signal SI changes to a high level in a time corresponding to 1 bit width (one time of unit time) (time t23), the count values Q0 to Q1 are taken into the bit conversion circuit 30b and the charge voltage VC is changed. Reset and initialization of the setting of the selection circuit 297 are performed, and the count values Q0 to Q1 are cleared at a timing delayed by the delay time in the delay circuit 27.

  Thereafter, when the serial signal SI changes to a high level in a time corresponding to a 4-bit width (four times the unit time) (time t24), the charging voltage VC exceeds the reference voltage Vref4. That is, every time the charging voltage VC reaches the reference voltages Vref1, Vref2, Vref3, and Vref4 between times t23 and t24, the pulse-shaped determination signal Jx is output, so the count values Q0 to Q2 become 4. This value is taken into the bit conversion circuit 30b at time t24.

  Further, after the serial signal SI changes from the low level to the high level (time t25), the high level is maintained and the state continues and when the charging voltage VC reaches the reference voltage Vref6 (t26), the count value Q0 is reached at this time. ... Q2 becomes 6. Thereafter, as long as the high level of the serial signal SI is held, the count values Q0 to Q2 are held at 6.

<Effect>
As described above, according to the decoding circuit 1d, since determination is performed using different reference voltages Vref1 to Vref6 for each bit width to be determined, a stable determination result can be obtained for any bit width. it can.

  That is, when the bit width is determined using only the reference voltage Vref1 as in the decoding circuit 1c, the reference voltage Vref1 is such that the charging voltage VC reaches when the capacitor 211 is continuously charged for a time shorter than the unit time by a predetermined time. Therefore, the more times this is used (that is, the wider the edge interval), the more the error for a predetermined time is accumulated, the timing at which the judgment signal Jx becomes high level, that is, the count value. Although the timing of counting up Q0 to Q2 is deviated, the decoding circuit 1d can eliminate such inconvenience.

[Other Embodiments]
As mentioned above, although several embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects. .

For example, the decoding circuit 1 configuring the nodes 100 to 107 described in the first embodiment may be replaced with any of the decoding circuits 1a to 1d of the second to fifth embodiments.
In the decoding circuits 1b to 1d of the third to fifth embodiments, instead of detecting and setting the setting bit value by detecting the signal level of the serial signal SI, the standby state is set as in the case of the decoding circuit 1a of the second embodiment. The signal may be set from the known signal level and the edge detection result.

  In the decoding circuits 1c and 1d of the fourth and fifth embodiments, the time signal generating circuit 21 is configured to perform the charging operation even in the standby state, but like the decoding circuit 1a of the second embodiment. The bit conversion circuit 30b may be configured to output a signal indicating that the standby state has been detected, and the signal 213 may be configured to hold the switch 213 of the bit conversion circuit 21 on the ground side during the standby state. .

  In the above embodiment, the number of reference voltages Vrefk and the number of bits of the count circuit 28 are set on the premise that the same level does not continue for 6 bits or more in the serial signal SI. Needless to say, it may be changed in accordance with the regulation of the serial signal SI.

  DESCRIPTION OF SYMBOLS 1,1a-1d ... Decoding circuit 2, 2a ... Main processing circuit 3 ... Transceiver 4 ... Receiver 5 ... Frame determination circuit 6 ... Power supply circuit 7, 8 ... Power switch 10 ... Edge detection circuit 20, 20a-20c ... Duration determination Circuit 21 ... Timekeeping signal generation circuit 22, 22a ... Multiple determination circuit 23 ... SR flip-flop circuit 24 ... OR gate 25, 26, 29 ... Multiple determination circuit 27 ... Delay circuit 28 ... Count circuit 30, 30a, 30b ... Bit conversion circuit 100-107 ... node

Claims (10)

Applied to a node having a normal mode that is an operation mode that operates according to a clock signal and a sleep mode that is an operation mode that reduces power consumption by stopping the clock signal, and operates in the sleep mode and has a preset unit time. A decoding circuit that decodes a received waveform of a serial signal that uses a binary code whose signal level changes in units of 1 and is encoded so that the same signal level does not continue for N (N is an integer of 3 or more) units or more Because
An edge detection circuit for detecting an edge of the serial signal;
A time signal generating circuit that generates a time signal that is reset each time an edge is detected by the edge detection circuit and that increases as time elapses;
By comparing the time signal generated by the time signal generation circuit with one or more predetermined threshold values, the edge interval detected by the edge detection circuit corresponds to how many times the unit time. A determination circuit for determining whether to
A level acquisition circuit that acquires the signal level of the serial signal corresponding to the edge interval that is the determination target in the determination circuit;
When the determination circuit determines that the interval between the edges is N times or more of the unit time as a standby state, and after the standby state is detected, the edge detection circuit detects the edge again. Until the standby state is detected, each time an edge is detected by the edge detection circuit, the bit data having the signal level acquired by the level acquisition circuit is a multiple determined by the determination circuit. A bit conversion circuit that only generates,
A data string generated by the bit conversion circuit is output as decoded data ,
The time signal generating circuit is:
A capacitive element capable of charging and discharging electric charge;
A charging circuit that charges the capacitive element with a constant current and resets a charging voltage to an initial voltage each time an edge is detected by the edge detection circuit;
A decoding circuit comprising: a charge voltage of the capacitive element that is output as the time signal . The determination circuit includes:
N−1 determinations each set to the magnitude of the signal level of the timing signal when the edge interval continues for a period corresponding to k times the unit time (2 ≦ k ≦ N, k is an integer). A determination threshold generation circuit for generating a threshold;
A comparison circuit that compares each determination threshold value generated by the determination threshold value generation circuit with the signal level of the timing signal;
The decoding circuit according to claim 1, comprising:   The comparison circuit includes N-1 comparators that individually compare the signal level of the time measurement signal with the N-1 determination thresholds generated by the determination threshold generation circuit. Item 3. A decoding circuit according to Item 2. The comparison circuit is
A selection circuit that selects and outputs any one of the N-1 determination thresholds generated by the determination threshold generation circuit;
A single comparator for comparing the output level of the selection circuit and the signal level of the timing signal;
The decoding circuit according to claim 2, comprising: The determination circuit includes:
A determination threshold value generation circuit for generating a determination threshold value set to the magnitude of the signal level of the time measurement signal when the edge interval continues for a period corresponding to the unit time;
A comparison circuit that compares the determination threshold generated by the determination threshold generation circuit with the signal level of the timing signal;
A reset circuit that resets the value of the time signal generated by the time signal generation circuit when the comparison circuit determines that the signal level of the time signal is greater than a determination threshold;
A counter that counts the number of times that the signal level of the timing signal is determined to be greater than a determination threshold, and that resets the count value each time an edge is detected by the edge detection circuit;
2. The decoding circuit according to claim 1, wherein a count value of the counter before being reset by an edge detected by the edge detection circuit is output as a multiple of a determination result. The determination circuit includes:
Determination threshold value for generating N determination threshold values respectively set to the magnitude of the signal level of the time measurement signal when the edge interval continues for a period corresponding to k (1 ≦ k ≦ N) times the unit time A generation circuit;
A selection circuit that selects and outputs any one of the N determination thresholds generated by the determination threshold generation circuit;
A single comparator for comparing the output level of the selection circuit and the signal level of the timing signal;
A counter that counts the number of times that the signal level of the timing signal is determined to be greater than a determination threshold, and that resets the count value each time an edge is detected by the edge detection circuit;
With
Each time the selection circuit determines that the signal level of the timing signal is higher than the output of the selection circuit by the comparator, the setting is switched so that the value is selected in ascending order, and the edge detection circuit Every time an edge is detected at
2. The decoding circuit according to claim 1, wherein a count value of the counter before being reset by an edge detected by the edge detection circuit is output as a multiple of a determination result.   The level acquisition circuit is configured to obtain an inverted value of the signal level of the serial signal detected until the unit time elapses after an edge is detected by the edge detection circuit, as an edge interval that is the determination target. The decoding circuit according to any one of claims 1 to 6, wherein the decoding circuit acquires the signal level at (1).   The level acquisition circuit is initialized to a preset standby signal level when the standby state is detected, and an edge is detected by the edge detection circuit after a change from the standby state to the non-standby state. 7. The storage signal level set so that the signal level is inverted each time is acquired as the signal level of the edge interval that is the determination target. The decoding circuit as described. A receiver that receives a serial signal from a communication path that performs communication using a binary code;
The decoding circuit according to any one of claims 1 to 8 , which decodes a signal received via the receiver;
A process execution means for executing a specific process associated with the command when the data sequence decoded by the decoding circuit represents a preset command;
A node characterized by comprising: The specific process transitions from a sleep mode, which is an operation mode for stopping communication via the communication path and suppressing power consumption, to a normal mode, which is an operation mode capable of executing communication via the communication path. The node according to claim 9 , wherein the node is a process for performing the process.

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