JP5615180B2 - エアギャップ構造の作製方法 - Google Patents
エアギャップ構造の作製方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67115—Apparatus for thermal treatment mainly by radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Micromachines (AREA)
Description
Claims (17)
- 基板上にエアギャップ構造を形成する方法であって:
350℃よりも高い熱分解温度で熱分解する熱分解可能な材料を有する犠牲層を前記基板上に形成する工程;
前記犠牲層の熱分解温度よりも低い基板温度で前記犠牲層上にキャップ層を形成する工程;
紫外(UV)放射線への前記基板の第1曝露を実行し、かつ前記犠牲層の熱分解温度よりも低い第1温度にまで前記基板を加熱することによって、前記犠牲層をUV支援分解する工程;
前記キャップ層を介して前記の分解した犠牲層を除去する工程;及び、
UV放射線への前記基板の第2曝露を実行し、かつ前記第1温度よりも高い第2温度にまで前記基板を加熱することによって、前記キャップ層を硬化させる工程;
を有する方法。 - 前記第1温度は、前記のキャップ層内での第1UV曝露の光化学反応速度を遅くさせる、請求項1に記載の方法。
- 前記犠牲層は375℃よりも高い熱分解温度で熱分解する、請求項1に記載の方法。
- 前記犠牲層は425℃よりも高い熱分解温度で熱分解する、請求項1に記載の方法。
- 前記第1温度は350℃よりも低温である、請求項1に記載の方法。
- 前記第1温度は300℃よりも低温である、請求項1に記載の方法。
- 前記UV支援分解する工程は、前記基板上の特定領域での前記犠牲層の分解を、前記犠牲層の前記第1曝露を前記の基板上の特定領域で選択的に実行することによって行う工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する犠牲層の選択的曝露は、1つ以上のUVランプから、若しくは、1つ以上のUVレーザーから、又は前記の2つ以上の組合せからのUV放射線に対して前記犠牲層を選択的に曝露する工程を有し、
前記のUV放射線に対する犠牲層の選択的曝露はマスクを介してUV放射線を前記犠牲層に照射する工程を有し、かつ
前記マスク内のパターンは前記の基板上の特定領域の1つ以上をそれぞれ異なる状態にする、
請求項7に記載の方法。 - 前記のUV放射線に対する基板の第1曝露は、1つ以上のUVランプ及び/又は1つ以上のUVレーザーからのUV放射線に対して前記基板を曝露する工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第1曝露は100nm乃至600nmの範囲のUV放射線に対して前記基板を曝露する工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第1曝露は170nm乃至320nmの範囲のUV放射線に対して前記基板を曝露する工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第2曝露は、1つ以上のUVランプ及び/又は1つ以上のUVレーザーからのUV放射線に対して前記基板を曝露する工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第2曝露は100nm乃至600nmの範囲のUV放射線に対して前記基板を曝露する工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第2曝露は170nm乃至240nmの範囲のUV放射線に対して前記基板を曝露する工程を有する、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第1曝露及び前記のUV放射線に対する基板の第2曝露は同一の処理チャンバ内で実行される、請求項1に記載の方法。
- 前記のUV放射線に対する基板の第1曝露が、第1UV波長範囲のUV放射線に対して前記基板を曝露する工程を有し、かつ
前記のUV放射線に対する基板の第2曝露が、第2UV波長範囲のUV放射線に対して前記基板を曝露する工程を有する、
請求項1に記載の方法。 - 前記犠牲層がP(npMA-co-EGDA)を有し、かつ
前記キャップ層が有孔性材料を有する、
請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/874,461 US7666754B2 (en) | 2007-10-18 | 2007-10-18 | Method and system for forming an air gap structure |
US11/874,461 | 2007-10-18 | ||
PCT/US2008/079877 WO2009052117A1 (en) | 2007-10-18 | 2008-10-14 | Method and system for forming an air gap structure |
Publications (2)
Publication Number | Publication Date |
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JP2011503840A JP2011503840A (ja) | 2011-01-27 |
JP5615180B2 true JP5615180B2 (ja) | 2014-10-29 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2010530067A Expired - Fee Related JP5615180B2 (ja) | 2007-10-18 | 2008-10-14 | エアギャップ構造の作製方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7666754B2 (ja) |
JP (1) | JP5615180B2 (ja) |
KR (1) | KR20100074239A (ja) |
CN (1) | CN101828249B (ja) |
TW (1) | TWI451528B (ja) |
WO (1) | WO2009052117A1 (ja) |
Families Citing this family (26)
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JP4929254B2 (ja) * | 2008-09-02 | 2012-05-09 | 株式会社東芝 | 半導体装置の製造方法 |
DE102009010845B4 (de) * | 2009-02-27 | 2016-10-13 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung eines Mikrostrukturbauelements mit einer Metallisierungsstruktur mit selbstjustierten Luftspalten und wieder aufgefüllten Luftspaltausschließungszonen |
US7855123B2 (en) * | 2009-03-31 | 2010-12-21 | Tokyo Electron Limited | Method of integrating an air gap structure with a substrate |
US7790601B1 (en) * | 2009-09-17 | 2010-09-07 | International Business Machines Corporation | Forming interconnects with air gaps |
US8456009B2 (en) | 2010-02-18 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having an air-gap region and a method of manufacturing the same |
US8765573B2 (en) | 2010-09-20 | 2014-07-01 | Applied Materials, Inc. | Air gap formation |
US8778749B2 (en) * | 2011-01-12 | 2014-07-15 | Sandisk Technologies Inc. | Air isolation in high density non-volatile memory |
CN103137551B (zh) * | 2011-12-05 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | 沟槽间形成孔洞的方法 |
CN103187362B (zh) * | 2011-12-31 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 具有空气间隙的双镶嵌大马士革结构器件的制作方法 |
US9105634B2 (en) | 2012-06-29 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Voids in interconnect structures and methods for forming the same |
US20140138790A1 (en) * | 2012-11-21 | 2014-05-22 | Spansion Llc | Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same |
JP2014157123A (ja) * | 2013-02-18 | 2014-08-28 | Toshiba Corp | 試料、試料作成装置および試料観察方法 |
US8921235B2 (en) | 2013-03-04 | 2014-12-30 | Applied Materials, Inc. | Controlled air gap formation |
US9312168B2 (en) * | 2013-12-16 | 2016-04-12 | Applied Materials, Inc. | Air gap structure integration using a processing system |
TWI555119B (zh) * | 2014-03-21 | 2016-10-21 | 力晶科技股份有限公司 | 具有氣隙的結構的形成方法 |
JP6237429B2 (ja) | 2014-04-14 | 2017-11-29 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
US9401304B2 (en) | 2014-04-24 | 2016-07-26 | Sandisk Technologies Llc | Patterning method for low-k inter-metal dielectrics and associated semiconductor device |
KR102380774B1 (ko) | 2014-11-14 | 2022-04-04 | 삼성전자주식회사 | 슬러리 화합물 이를 이용한 반도체 소자의 제조 방법 |
US9553019B1 (en) | 2016-04-15 | 2017-01-24 | International Business Machines Corporation | Airgap protection layer for via alignment |
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WO2020014352A1 (en) * | 2018-07-11 | 2020-01-16 | Tokyo Electron Limited | Methods to reduce gouging for core removal processes using thermal decomposition materials |
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JP7192588B2 (ja) * | 2019-03-12 | 2022-12-20 | 東京エレクトロン株式会社 | 基板処理装置及び基板処理方法 |
JP7193729B2 (ja) * | 2019-03-22 | 2022-12-21 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
CN115552573A (zh) | 2020-05-12 | 2022-12-30 | 朗姆研究公司 | 刺激响应聚合物膜的受控降解 |
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US6815329B2 (en) | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
US6380106B1 (en) * | 2000-11-27 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures |
JP4574145B2 (ja) * | 2002-09-13 | 2010-11-04 | ローム・アンド・ハース・エレクトロニック・マテリアルズ,エル.エル.シー. | エアギャップ形成 |
WO2004047166A2 (en) | 2002-11-15 | 2004-06-03 | E.I. Du Pont De Nemours And Company | Process for using protective layers in the fabrication of electronic devices |
TWI273671B (en) | 2004-03-18 | 2007-02-11 | Imec Inter Uni Micro Electr | Method of manufacturing a semiconductor device having damascene structures with air gaps |
EP1632956A1 (en) | 2004-09-07 | 2006-03-08 | Rohm and Haas Electronic Materials, L.L.C. | Compositions comprising an organic polysilica and an arylgroup-capped polyol, and methods for preparing porous organic polysilica films |
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JP2011503840A (ja) | 2011-01-27 |
KR20100074239A (ko) | 2010-07-01 |
US7666754B2 (en) | 2010-02-23 |
CN101828249B (zh) | 2012-05-23 |
WO2009052117A1 (en) | 2009-04-23 |
TWI451528B (zh) | 2014-09-01 |
US20090130863A1 (en) | 2009-05-21 |
CN101828249A (zh) | 2010-09-08 |
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