JP5613810B2 - Display device - Google Patents

Description

The present invention relates to a display device having a pixel portion and a drive circuit for transmitting a signal to the pixel portion on the same insulator. In particular, the present invention relates to a liquid crystal display device in which a liquid crystal material is sandwiched between electrodes, or a self-luminous display device in which a luminescent material is sandwiched between electrodes. An element in which a luminescent material is sandwiched between electrodes (hereinafter,
The present invention relates to a device having a light-emitting element (hereinafter referred to as a light-emitting device). The present invention can also be used for an apparatus (hereinafter referred to as a liquid crystal display device) having an element (hereinafter referred to as a liquid crystal element) in which a liquid crystal material is sandwiched between electrodes. Note that in this specification, a liquid crystal display device and a self-luminous display device are collectively referred to as a display device.

In recent years, an active matrix display device in which a pixel portion is formed using a thin film transistor (hereinafter referred to as a TFT) has been developed. A typical example of the active matrix display device is a liquid crystal display device, and each pixel is provided with a TFT as a switching element in order to control a voltage applied to the liquid crystal layer. In addition, in a self-luminous display device using an EL (Electro Luminescence) material, a TFT is provided in each pixel provided in the pixel portion, and the amount of light emitted from each pixel is controlled by controlling the amount of current flowing through the EL element by the TFT. Control. Such a feature of the active matrix display device is suitable for obtaining a high-definition image because a voltage can be uniformly supplied to each pixel even when the number of pixels increases.

In addition, an advantage of the active matrix display device is that a circuit such as a shift register, a latch, or a buffer is formed on the same insulator as a driver circuit for transmitting a signal to the pixel portion.
This is a point that can be formed. As a result, it is possible to realize a display device that has a very small number of contacts with an external circuit and is capable of high-definition image display.

Here, an equivalent circuit diagram of a pixel of the active matrix self-luminous display device is shown in FIG. 10A, reference numeral 1001 denotes a source wiring, 1002 denotes a gate wiring, 1003 denotes a TFT functioning as a switching element (hereinafter referred to as a switching TFT), 1004
Is a capacitor electrically connected to the drain of the switching TFT 1003.

Further, the gate electrode of the current control TFT 1005 is electrically connected to the drain of the switching TFT 1003. The source of the current control TFT 1005 is electrically connected to the current supply line 1006, and the drain is electrically connected to the EL element 1007. That is, the current control TFT 1005 functions as an element that controls the current flowing through the EL element 1007.

In this way, the pixel has two TFTs, and the light emission luminance of the EL element can be controlled with different roles. As a result, the light emission period is approximately one frame period, and an image can be displayed while suppressing the light emission luminance even in a high-definition pixel portion. Further, an advantage of the active matrix type is that a shift register and a sampling circuit can be formed using TFTs over the same substrate as a driver circuit that transmits a signal to the pixel portion. This makes it possible to manufacture a very compact self-luminous display device.

FIG. 10B is an equivalent circuit diagram of a pixel of the liquid crystal display device.
Gate wiring 1012, switching TFT 1013, storage capacitor 1015, capacitor line 1014
, A liquid crystal layer 1016.

An alternative liquid crystal display device is provided with one TFT or a multi-gate TFT in a pixel. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. The TFT functions as a switching element, and is required to have a small leakage current in order to maintain a voltage applied to the liquid crystal layer. The charge transferred from the source wiring to the pixel when the TFT is on is held for the field period. The resistance of the liquid crystal must be high. The characteristics required for TFT include a sufficiently large on-current that can charge a pixel capacitor (liquid crystal itself) during a scanning period, a sufficiently small off-current that can hold a charge during a field period, and a sufficiently small gate-drain parasitic capacitance. It is. Retention capacity is
Since the pixel capacitance is small, the holding operation is insufficient, so that this is compensated for and the effect of parasitic capacitance is provided.

On the other hand, since a high drive voltage is applied to the buffer circuit of the drive circuit, it is necessary to increase the withstand voltage so that it does not break even when a high voltage is applied. In order to increase the current driving capability, it is necessary to secure a sufficient on-current value (drain current that flows when the TFT is on).

However, in the active matrix display device, if the TFT manufacturing process is complicated,
There was a problem of high manufacturing costs. In addition, since a plurality of TFTs are formed at the same time, it is difficult to secure a yield if the manufacturing process becomes complicated. In particular, when there is a malfunction in the drive circuit, there may be a linear defect in which one column of pixels does not operate.

An object of the present invention is to reduce the manufacturing cost of an active matrix display device,
It is an object to provide an inexpensive display device. It is another object of the present invention to provide an inexpensive electronic device using the display device of the present invention for a display portion.

In the present invention, in order to reduce the manufacturing cost of an active matrix display device, all TFTs used in a pixel portion are one conductivity type TFTs (here, p-channel type TFTs or n-channel type TFTs).
FT indicates any one of FT), and the drive circuit is all the same conductivity type TFT as the pixel portion
It is characterized by forming in. As a result, the manufacturing process can be greatly reduced, and the manufacturing cost can be reduced.

A particularly important point is that a drive circuit is formed with only one conductivity type TFT. In other words, a general driving circuit is a CMO that complementarily combines an n-channel TFT and a p-channel TFT.
Although designed based on S circuit, in the present invention, p-channel TFT or n-channel TF is used.
A drive circuit is formed by combining only T.

With this configuration, the number of masks used when doping impurities for controlling the conductivity type in the TFT manufacturing process can be reduced by one. As a result, the manufacturing process can be shortened and the manufacturing cost can be reduced.

As described above, in the display device in which the pixel portion and the driver circuit are formed over the same insulator, all the TFTs of the pixel portion and the driver circuit are formed in a p-channel type. The p-channel TFT in the pixel portion has an offset gate structure.

According to another aspect of the present invention, in the display device in which the pixel portion and the driving circuit are formed over the same insulator, all TFTs of the pixel portion and the driving circuit are formed in a p-channel type, and the p of the pixel portion is formed. The channel type TFT has an LDD region outside the gate electrode, and the p-channel type TFT of the driving circuit has an LDD region overlapping with the gate electrode.

According to another aspect of the present invention, in the display device in which the pixel portion and the driver circuit are formed over the same insulator, all TFTs of the pixel portion and the driver circuit are formed of a p-channel type, and the source of the pixel portion The wiring and the gate electrode are formed on the first insulating film, and the gate wiring connected to the gate electrode intersects with the source wiring through the second insulating film.

The drive circuit includes an EEMOS circuit or an EDMOS circuit, or the drive circuit includes a decoder including a plurality of NAND circuits.

In the method for manufacturing a display device of the present invention, a first semiconductor film for forming a TFT of a driver circuit and a second semiconductor film for forming a TFT of a pixel portion are formed over an insulator. 1 and a gate electrode formed of a first conductive film and a second conductive film inside the first conductive film on each of the first semiconductor film and the second semiconductor film. A second step of forming, and a first p overlapping the first conductive film on each of the first semiconductor film and the second semiconductor film.
A third step of forming a p-type semiconductor region, and a fourth step of forming a second p-type semiconductor region that does not overlap the first conductive film in each of the first semiconductor film and the second semiconductor film And the process of
And a fifth step of removing, by etching, a portion where the first conductive film overlaps the first p-type semiconductor region.

Another example of the method for manufacturing a display device of the present invention is a first semiconductor film for forming a TFT of a driver circuit over an insulator and a second semiconductor film for forming a TFT of a pixel portion. And a first conductive film and a second conductive film inside the first conductive film on each of the first semiconductor film and the second semiconductor film. A second step of forming a gate electrode, and a third p-type semiconductor region that overlaps the first conductive film in each of the first semiconductor film and the second semiconductor film. Forming a second p-type semiconductor region that does not overlap the first conductive film in each of the first semiconductor film and the second semiconductor film;
And a fifth step of forming an offset region by removing a portion where the first conductive film on the second semiconductor film overlaps with the first p-type semiconductor region by etching. It is a feature.

Another example of the method for manufacturing a display device of the present invention is a first semiconductor film for forming a TFT of a driver circuit over an insulator and a second semiconductor film for forming a TFT of a pixel portion. A first step of forming a first insulating film, a second step of forming a first insulating film on the first semiconductor film and the second semiconductor film, and a step of forming the first insulating film on the first insulating film. Corresponding to the first semiconductor film and the second semiconductor film, a gate electrode made up of a first conductive film and a second conductive film inside the first conductive film, and a source wiring are formed. 3, a fourth step of forming a first p-type semiconductor region overlapping with the first conductive film in each of the first semiconductor film and the second semiconductor film, and the first A second layer that does not overlap the first conductive film on each of the semiconductor film and the second semiconductor film
A fifth step of forming the p-type semiconductor region, a sixth step of removing the portion where the first conductive film overlaps the first p-type semiconductor region by etching, the gate electrode and the source wiring And a seventh step of forming a second insulating film, and an eighth step of forming a gate wiring on the second insulating film.

As described above, according to the present invention, a reflective display device can be realized with four photomasks, and the manufacturing cost of an active matrix display device can be reduced.

The figure which shows the structure of a gate side drive circuit. The figure which shows the timing chart of a decoder input signal. The figure which shows the structure of a source side drive circuit. The figure which shows the structure of an EEMOS circuit and an EDMOS circuit. FIG. 6 illustrates a structure of a shift register. Sectional drawing explaining the structure of the pixel part of the self-light-emitting device formed of PTFT. The top view explaining the structure of the pixel part of the self-light-emitting device formed of PTFT. Sectional drawing explaining the structure of the pixel part of the self-light-emitting device formed of PTFT. Sectional drawing explaining the manufacturing process of E-type PTFT and D-type PTFT. The equivalent circuit diagram of a pixel part. FIG. 6 is a cross-sectional view illustrating a structure of a pixel portion of a liquid crystal display device formed using PTFT. FIG. 10 is a top view illustrating a structure of a pixel portion of a liquid crystal display device formed using PTFT. FIG. 6 is a cross-sectional view illustrating a structure of a pixel portion of a liquid crystal display device formed using PTFT. The figure explaining the detail of an offset gate structure. FIG. 6 is a cross-sectional view illustrating a structure of a pixel portion of a liquid crystal display device formed using PTFT. FIG. 6 is a cross-sectional view illustrating a structure of a pixel portion of a transmissive liquid crystal display device formed using PTFT. Sectional drawing explaining the structure of the transmissive | pervious liquid crystal display device formed with PTFT. The assembly drawing of the main components of a liquid crystal display device. The figure explaining the structure of a terminal part. FIG. 11 is a block diagram illustrating a structure of an electronic device. 10A and 10B illustrate a method for manufacturing a crystalline semiconductor film. FIG. 6 illustrates an example of an electronic device. FIG. 6 illustrates an example of an electronic device. The graph which shows the characteristic of the gate voltage (VG) vs. drain current (ID) of PTFT.

Here, a driving circuit used in the present invention will be described with reference to FIGS. FIG. 1 shows an example of a gate side driving circuit. In the present invention, a decoder using a p-channel TFT as shown in FIG. 1 is used instead of a general shift register.

In FIG. 1, 100 is a decoder of the gate side driving circuit, and 101 is a buffer section of the gate side driving circuit. The buffer unit refers to a part where a plurality of buffers (buffer amplifiers) are integrated. In addition, the buffer refers to a circuit that performs driving without affecting the preceding stage.

In the decoder 100 on the gate side, reference numeral 102 denotes an input signal line (hereinafter referred to as a selection line) of the decoder 100. Here, A1, A1 bar (a signal in which the polarity of A1 is inverted), A2, A
2 bars (signal with reversed polarity of A2), ..., An, An bars (signal with reversed polarity of An)
Is shown. That is, it can be considered that 2n selection lines are arranged.

The number of selection lines is determined by the number of gate lines output from the gate side driving circuit. For example, in the case of having a pixel portion for VGA display, there are 480 gate wirings.
A total of 18 selection lines are required for 9 bits (corresponding to n = 9). The selection line 102 is shown in FIG.
The signal shown in the timing chart is transmitted. As shown in FIG. 2, when the frequency of A1 is 1, the frequency of A2 is 2 ⁻¹ times, the frequency of A3 is 2 ⁻² times, and the frequency of An is 2 ^{− (n−1)} times.

Reference numeral 103a denotes a first-stage NAND circuit (also referred to as a NAND cell), 103b denotes a second-stage NAND circuit, and 103c denotes an n-th stage NAND circuit. The NAND circuit requires the number of gate wirings, and n pieces are required here. That is, in the present invention, the decoder 100 includes a plurality of N
It consists of an AND circuit.

The NAND circuits 103a to 103c are combined with p-channel TFTs 104 to 109 to form a NAND circuit. In practice, 2n TFTs are connected to the NAND circuit 1.
03. Each gate of the p-channel TFTs 104 to 109 is connected to one of the selection lines 102 (A1, A1 bar, A2, A2 bar... An, An bar).

At this time, in the NAND circuit 103a, the p-channel TFTs 104 to 106 having gates connected to any one of A1, A2,... An (referred to as positive selection lines) are connected in parallel to each other and are common. _Is connected to the positive power supply line (V _DH ) 110 as a source of the signal, and connected to the output line 111 as a common drain. Also, a p-channel type T having a gate connected to any of A1 bar, A2 bar... An bar (these are called negative selection lines)
The FTs 107 to 109 are connected in series with each other, and are p-channel type Ts located at the circuit ends.
The source of the FT 109 is connected to the negative power supply line (V _DL ) 112, and the drain of the p-channel TFT 107 located at the other circuit end is connected to the output line 111.

As described above, in the present invention, the NAND circuit includes n one-conductivity TFTs connected in series.
(Here, p-channel type TFT) and n one-conductivity type TFTs (here, p-channel type TFTs) connected in parallel. However, in the n NAND circuits 103a to 103c,
All combinations of p-channel TFTs and selection lines are different. In other words, only one output line 111 is always selected, and a signal for selecting the output line 111 in order from the end is input to the selection line 102.

Next, the buffer 101 is formed of a plurality of buffers 113a to 113c corresponding to each of the NAND circuits 103a to 103c. However, the buffers 113a to 113c may all have the same structure.

The buffers 113a to 113c are p-channel TFTs 114 to 114 as one conductivity type TFTs.
116. The output line 111 from the decoder is a p-channel TFT 114 (
It is input as the gate of the first one conductivity type TFT). The p-channel TFT 114 has a ground power supply line (GND) 117 as a source and a gate wiring 118 as a drain. The p-channel TFT 115 (second one-conductivity type TFT) is always on with the ground power supply line 117 as a gate, the positive power supply line (V _DH ) 119 as a source, and the gate wiring 118 as a drain.

That is, in the present invention, the buffers 113a to 113c are connected in series to the first one-conductivity type TFT (p-channel TFT 114) and the first one-conductivity type TFT, and the drain of the first one-conductivity type TFT is connected. Second one-conductivity type TFT as a gate (p-channel type TFT 115)
including.

The p-channel TFT 116 (third one-conductivity type TFT) is connected to a reset signal line (Reset
) As a gate, the positive power supply line 119 as a source, and the gate wiring 118 as a drain. Note that the ground power supply line 117 may be a negative power supply line (however, a power supply line that supplies a voltage that turns on a p-channel TFT used as a switching element of a pixel).

At this time, the channel width (W1) of the p-channel TFT 115 and the p-channel TF
There is a relationship of W1 <W2 with the channel width (W2) of T114. Note that the channel width is the length of a channel formation region in a direction perpendicular to the channel length.

The operation of the buffer 113a is as follows. First, when a positive voltage is applied to the output line 111, the p-channel TFT 114 is turned off (a state in which no channel is formed). On the other hand, the p-channel TFT 115 is always in an on state (a state in which a channel is formed).
Therefore, the voltage of the positive power supply line 119 is applied to the gate wiring 118.

However, when a negative voltage is applied to the output line 111, the p-channel TFT 114 is turned on. At this time, the channel width of the p-channel TFT 114 is p-channel TFT 1.
Since the channel width is larger than 15, the potential of the gate wiring 118 is p-channel TFT 11.
As a result, the voltage of the ground power supply line 117 is applied to the gate wiring 118.

Therefore, when a negative voltage is applied to the output line 111, the gate wiring 118 outputs a negative voltage (a voltage at which a p-channel TFT used as a pixel switching element is turned on) and outputs a positive voltage to the output line 111. When a voltage is applied, a positive voltage (a voltage at which a p-channel TFT used as a pixel switching element is turned off) is output.

Note that the p-channel TFT 116 is used as a reset switch for forcibly raising the gate wiring 118 to which a negative voltage is applied to a positive voltage. That is, when the selection period of the gate wiring 118 ends. A reset signal is input to apply a positive voltage to the gate wiring 118. However, the p-channel TFT 116 can be omitted.

The gate lines are sequentially selected by the gate side driving circuit operating as described above. Next, FIG. 3 shows the configuration of the source side driver circuit. The source side driver circuit shown in FIG. 3 includes a decoder 301, a latch 302, and a buffer 303. Note that the configurations of the decoder 301 and the buffer 303 are the same as those of the gate-side driver circuit, and thus description thereof is omitted here.

In the case of the source side driver circuit shown in FIG. 3, the latch 302 includes a first-stage latch 304 and a second-stage latch 305. Further, the first-stage latch 304 and the second-stage latch 305 each have a plurality of unit units 307 formed of m p-channel TFTs 306a to 306c. An output line 308 from the decoder 301 is input to the gates of m p-channel TFTs 306 a to 306 c forming the unit unit 307. Note that m is an arbitrary integer.

For example, in the case of VGA display, the number of source lines is 640. NA if m = 1
640 ND circuits are required, and 20 selection lines (corresponding to 10 bits) are required.
However, if m = 8, the number of necessary NAND circuits is 80, and the number of necessary selection lines is 14 (7
equivalent to bit). That is, if the number of source wirings is M, the necessary NAND circuits are (M / m).

The sources of the p-channel TFTs 306a to 306c are video signal lines (V1, V
2... Vk) 309. That is, when a negative voltage is applied to the output line 308, the p-channel TFTs 306a to 306c are turned on at the same time, and video signals corresponding to the p-channel TFTs 306a to 306c are captured. In addition, the video signals thus captured are converted into p-channel TFTs 306a to 306a-30.
6c is held by capacitors 310a to 310c connected to each of 6c.

The second-stage latch 305 also includes a plurality of unit units 307b, and unit unit 3
07b is formed of m p-channel TFTs 311a to 311c. p-channel TFT
All the gates 311a to 311c are connected to the latch signal line 312, and the latch signal line 312 is connected.
When a negative voltage is applied to the p-channel TFTs 311a to 311c, they are turned on simultaneously.

As a result, the signals held in the capacitors 310a to 310c are converted into p-channel TFTs.
It is held in capacitors 313a to 313c connected to each of 311a to 311c and simultaneously output to the buffer 303. Then, as described in FIG. 1, the data is output to the source wiring 314 through the buffer. The source lines are selected in order by the source side driving circuit operating as described above.

As described above, by forming the gate side driver circuit and the source side driver circuit with only the p-channel TFT, the pixel portion and the driver circuit can all be formed with the p-channel TFT. Therefore, in manufacturing an active matrix display device, the yield and throughput of the TFT process can be greatly improved, and the manufacturing cost can be reduced.

Note that the present invention can also be implemented when either the source side driver circuit or the gate side driver circuit is an external IC chip.

Further, in the PMOS circuit, an EEMOS circuit formed by enhancement type TFTs;
There is an EDMOS circuit formed by combining an enhancement type and a depletion type.

Here, FIG. 4A shows an example of an EEMOS circuit, and FIG. 4B shows an example of an EDMOS circuit.
In FIG. 4A, 401 and 402 are both enhancement-type p-channel TFs.
T (hereinafter referred to as E-type PTFT). In FIG. 4B, 403 is an E-type PT.
FT and 404 are depletion type p-channel TFTs (hereinafter referred to as D-type PTFTs).

4A and 4B, V _DH is a power supply line to which a positive voltage is applied (positive power supply line).
V _DL is a power supply line (negative power supply line) to which a negative voltage is applied. The negative power source line may be a ground potential power source line (ground power source line).

Further, FIG. 5 shows an example in which a shift register is manufactured using the EEMOS circuit shown in FIG. 4A or the EDMOS circuit shown in FIG. In FIG. 5, reference numerals 500 and 501 denote flip-flop circuits. Reference numerals 502 and 503 denote E-type PTFTs, which are E-type PTFs.
A clock signal (CL) is input to the gate of T502, and a clock signal (CL bar) with an inverted polarity is input to the gate of the E-type PTFT 503. The symbol 504 is an inverter circuit, and as shown in FIG. 5B, the EEMOS circuit shown in FIG. 4A or the EDMOS circuit shown in FIG. 4B is used.

As described above, n-channel type TF can be obtained by making all TFTs p-channel type TFTs.
Since the process of forming T is reduced, the manufacturing process of the active matrix display device can be simplified. Accordingly, the yield of the manufacturing process is improved, and the manufacturing cost of the active matrix display device can be reduced.

The present invention is characterized in that all the drive circuits are formed of p-channel TFTs.
All the pixel portions are also formed by p-channel TFTs. Therefore, in this embodiment, an example of a structure of a pixel portion for displaying an image by a signal transmitted by the driving circuit shown in FIGS. 1 and 3 will be described.

Here, the pixel structure of the active matrix self-luminous display device of the present invention is shown in FIGS. FIG. 6 shows a cross-sectional view of one pixel, and FIG. 7 shows a top view of the pixel. FIG. 6 is a cross-sectional view taken along line AA ′ of FIG. 7, and the same reference numerals are given to the same portions in the respective drawings.

In FIG. 6, 601 is a substrate transparent to visible light, and 602a and 602b are base coat layers. As the substrate 601 that is transparent to visible light, a glass substrate, a quartz substrate, a crystallized glass substrate, or a plastic substrate (including a plastic film) can be used. The base coat layer is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film (expressed as SiO _x N _y ), or the like. The thickness is 50 to 200 nm. For example, a silicon oxynitride film made of SiH ₄ , NH _3, and N ₂ O by plasma CVD is used to form a silicon oxynitride film 602a at 50 nm, 6
02b is a two-layer structure in which a silicon oxynitride film made of SiH ₄ and N ₂ O is laminated to 100 nm, or a silicon oxide film made by using a silicon nitride film and TEOS (Tetraethyl Ortho Silicate) is laminated. A two-layer structure.

In the preferred embodiment of the present invention, the TFT is formed on an insulator. The insulator may be an insulating film (typically an insulating film containing silicon) or a substrate made of an insulating material (typically a quartz substrate). Therefore, “on an insulator” means on an insulating film or on a substrate made of an insulating material.

A switching TFT 651 and a current control TFT 652 are formed of p-channel TFTs on the insulating film 602b containing silicon.

The switching TFT 651 includes a region made of a p-type semiconductor (hereinafter, p-type semiconductor) in the semiconductor film 603.
605 and 607, and regions (hereinafter referred to as channel formation regions) 608 and 609 made of intrinsic or substantially intrinsic semiconductor. The current control TFT 652 includes a semiconductor region including p-type semiconductor regions 610 and 611 and a channel formation region 612 in the semiconductor film 604.

Note that the p-type semiconductor region 605 or 607 becomes a source region or a drain region of the switching TFT 651. The p-type semiconductor region 611 becomes a source region of the current control TFT 652, and the p-type semiconductor region 610 becomes a drain region of the TFT.

The semiconductor films 603 and 604 are covered with a gate insulating film 613, and a power line 614,
619, a source wiring 615, a gate electrode 616, and a gate electrode 617 connected to the p-type semiconductor region 607 are formed. These are formed simultaneously with the same material. These wiring and electrode materials include tantalum (Ta), tungsten (W), and molybdenum (Mo).
Niobium (Nb), titanium (Ti), or nitrides of these metals may be used. Also,
An alloy combining these metals may be used, or a silicide of these metals may be used.

In FIG. 6, reference numeral 620 denotes a passivation film made of a silicon nitride oxide film or a silicon nitride film, and an interlayer insulating film 621 is provided thereon. As the interlayer insulating film 620,
An insulating film containing silicon or an organic resin film is used. As the organic resin film, polyimide, polyamide, acrylic resin, or BCB (benzocyclobutene) may be used.

Contact holes are formed in the passivation film 620 and the interlayer insulating film 621, a connection wiring connecting the source wiring 615 and the p-type semiconductor region 605 of the semiconductor film 603, a gate wiring 618 connecting to the gate electrode 616, and a p-type semiconductor region 607 A connection wiring 623 for connecting the gate electrode 617, a connection wiring 625 for connecting the power supply line 619 and the p-type semiconductor region 611, and a connection wiring 624 for connecting the pixel electrode 626 and the p-type semiconductor region 610 are formed. These wirings are formed of a material mainly composed of aluminum (Al).

As shown in the top view of FIG. 7, with such a structure, the channel formation regions 608 and 609 of the semiconductor film 603 can be covered with the gate wiring 618 to be shielded from light. In addition, it is desirable that the p-type semiconductor regions 605 to 607 of the semiconductor film 603 be shielded from light.
Furthermore, since the end portion of the pixel electrode 626 can be formed so as to overlap with the source wiring 615 and the power supply line 619, the pixel electrode can be made large and the aperture ratio can be improved. Further, the source wiring 615 and the power supply line 619 can have a function as a light-shielding film.

Here, a cross-sectional view taken along line BB ′ in FIG. 7 is shown in FIG. FIG. 8A is a diagram for explaining a contact portion between the gate wiring 618 and the gate electrode 616.
3 is a gate wiring 618 in a region outside the semiconductor film 603.
And electrical connection is formed.

Further, FIG. 8B shows a cross-sectional view taken along CC ′ in FIG. FIG. 8B illustrates a cross-sectional structure of a region where a capacitor is formed. The semiconductor film 604 formed over the base coat layer 602b is used as one electrode, the gate insulating film 613 is a dielectric, and the gate electrode 617 is used. A capacitor is formed as the other electrode.

An equivalent circuit diagram of such a pixel is FIG. 10A, and a TF formed of a semiconductor film 603 is used.
T functions for switching, and the TFT formed of the semiconductor film 604 functions for current control.

Next, as shown in FIG. 6B, insulators 650 and 651 made of resin are formed so as to hide the end portion and the concave portion (the depression caused by the contact hole) of the pixel electrode 626. In this case, an insulating film made of resin may be formed and then formed in a predetermined pattern in accordance with the pixel electrode.
At this time, the height from the surface of the pixel electrode 626 to the top of the insulator 650 is desirably 300 nm or less (preferably 200 nm or less). The insulators 650 and 651 can be omitted.

The insulators 650 and 651 are formed for the purpose of hiding the end portion of the pixel electrode 626 and avoiding the influence of electric field concentration at the end portion. Thereby, deterioration of the EL layer can be suppressed. In addition, the insulators 650 and 651 are formed for the purpose of filling the recesses of the pixel electrodes formed due to the contact holes. Accordingly, it is possible to prevent the EL layer formed later from being poorly covered and to prevent a short circuit between the pixel electrode and the cathode formed later.

Next, an EL layer 652 having a thickness of 70 nm and a cathode 653 having a thickness of 300 nm are formed by an evaporation method. In this embodiment, a structure in which 20 nm thick copper phthalocyanine (hole injection layer) and 50 nm thick Alq ₃ (light emitting layer) are stacked is used as the EL layer 652. Of course, a hole injection layer in the light emitting layer,
Other known structures combining hole transport layers, electron transport layers, or electron injection may be used.

In this embodiment, first, copper phthalocyanine is formed so as to cover all the pixel electrodes, and then
A red light emitting layer, a green light emitting layer, and a blue light emitting layer are formed for each pixel corresponding to red, green, and blue. The regions to be formed may be distinguished using a shadow mask during vapor deposition. In this way, color display is possible.

When the green light emitting layer is formed, Alq ₃ (Tris-8-
Quinolinolato aluminum complex) and quinacridone or coumarin 6 is added as a dopant. When a red light emitting layer is formed, Alq _{3 is} used as a base material of the light emitting layer.
And DCJT, DCM1 or DCM2 is added as a dopant. Further, when forming a blue light emitting layer, BAlq ₃ (a pentacoordinate complex having a mixed ligand of 2-methyl-8-quinolinol and a phenol derivative) is used as a base material of the light emitting layer, and perylene is used as a dopant. Add as

Of course, in the present invention, it is not necessary to limit to the above organic material, and it is possible to use a known low molecular organic EL material, high molecular organic EL material or inorganic EL material. Moreover, it is also possible to use these materials in combination. In the case of using a polymer organic EL material, a coating method can also be used.

As described above, E composed of the pixel electrode (anode) 836, the EL layer 839, and the cathode 840.
An L element is formed. Further, the auxiliary electrode 654 may be formed using Al or the like on the cathode 653.

Thus, an active matrix self-luminous device is completed. A known technique may be used to form the EL layer and the cathode. With the above pixel structure, the manufacturing process of the active matrix self-luminous device can be significantly reduced, and an inexpensive active matrix self-luminous device can be produced. In addition, an electronic device using it for the display portion can be made inexpensive.

In this embodiment, a process of manufacturing an E-type PTFT and a D-type PTFT on the same insulator will be described with reference to FIGS.

First, as shown in FIG. 9A, a base coat film (insulator) is formed over a glass substrate 901. In this embodiment, a first silicon nitride oxide film 902a having a thickness of 50 nm and a second silicon nitride oxide film 902b having a thickness of 200 nm are sequentially stacked from the glass substrate 901 side to form a base coat film. In addition, the first silicon nitride oxide film 902a is the second silicon nitride oxide film 902b.
Compared to the above, the content of nitrogen is increased, and the diffusion of alkali metal from the glass substrate 901 is suppressed.

Next, an amorphous semiconductor film 903 is formed to a thickness of 40 nm on the base coat film by a plasma CVD method. As the amorphous semiconductor film, a material such as silicon or silicon germanium is used. Then, the amorphous semiconductor film 903 is crystallized by irradiating with laser light to form a polycrystalline semiconductor film (polysilicon film). Further, the crystallization method is not limited to the laser crystallization method, and other known crystallization methods can also be used.

Next, as shown in FIG. 9B, the polycrystalline semiconductor film is etched into a predetermined shape through a light exposure process using a first photomask to form individually isolated semiconductor films 904 and 905. To do. Note that the semiconductor film indicated by 904 and 905 forms a channel formation region and a source or drain region of the TFT when completed.

In order to form a D-type PTFT, a step of doping an acceptor with a semiconductor film in advance is performed. First, a mask insulating film 906 made of a silicon oxide film is formed. This is provided in order to control the concentration of the acceptor to be doped using an ion doping method or an ion implantation method. The concentration of the acceptor to be injected is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ . This doping is performed on the channel formation region of the D-type PTFT. In FIG. 9C,
The entire surface of the semiconductor film 905 is doped, and the semiconductor film 904 for forming the E-type PTFT is covered with a resist mask 907 so that the acceptor is not doped.
This process is applied when a D-type PTFT is formed.

In FIG. 9D, the gate insulating film 909 is formed to a thickness of 80 nm by plasma CVD. The gate insulating film 909 is formed using a silicon oxide film, a silicon oxynitride film, or the like. Then, a first conductive film 910 formed using tantalum nitride or titanium nitride is formed to a thickness of 20 to 40 nm, preferably 30 nm. A second conductive film 911 is formed thereover. As the second conductive film, Ta, W, Mo, Nb, Ti or a nitride of these metals is used, and 300 to 40 is used.
It is formed to a thickness of 0 nm.

As shown in FIG. 9E, a resist mask 912 is formed by a light exposure process using a second photomask, and the conductive film is etched to form gate electrodes 913 and 914.
This step can be combined with a doping step to form a self-aligned LDD region and a source and drain region of a p-type semiconductor region in a semiconductor film. In the first etching process performed first, an ICP (Inductively Coupled Plasma) etching method is used as a suitable technique. Mix CF ₄ and Cl ₂ in the etching gas, and
500 W RF (13.56 M) applied to the coil-type electrode at a pressure of 5-2 Pa, preferably 1 Pa.
Hz) Power is applied to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. C
When F ₄ and Cl ₂ are mixed, etching can be performed at the same rate even in the case of a tungsten film, a tantalum nitride film, and a titanium film.

Under the above etching conditions, the end portion can be tapered by the shape of the resist mask and the effect of the bias voltage applied to the substrate side. The angle of the taper part is 15-4
Set to 5 °. In order to etch without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the overetching process.

Further, a second etching process is performed. The etching uses ICP etching method, and CF ₄ , Cl ₂ and O ₂ are mixed in the etching gas, and 500 W is applied to the coil type electrode at a pressure of 1 Pa.
RF power (13.56 MHz) is supplied to generate plasma. Substrate side (sample stage)
Is supplied with 50 W RF (13.56 MHz) power and applied with a lower self-bias voltage than in the first etching process. Under such conditions, the tungsten film is anisotropically etched to leave the tantalum nitride film or titanium film as the first conductive layer. Thus, as shown in FIG. 9E, gate electrodes 913 and 914 are formed from the first conductive layers 913a and 914a whose end portions are located outside the second conductive layers 913b and 914b.

Next, first p-type semiconductor regions 915 and 916 are formed in the semiconductor films 904 and 905 by ion doping using the second conductive layers 913b and 914b as a mask. Doping is performed by applying an accelerating voltage to such an extent that it can pass through the first conductive layers 913a and 914a and the gate insulating film 909, and an acceptor of 1 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ is doped. . The acceptor is typically boron, and other elements belonging to Group 13 of the periodic table may be added. In the ion doping method, B ₂ H ₆ or BF ₃ is used as a source gas.

Further, the first conductive layers 913a and 914a and the second conductive layer 9 are formed by ion doping.
Second p-type semiconductor regions 917 and 918 are formed outside the first p-type semiconductor region using 13b and 914b as a mask. The second p-type semiconductor region is a source or drain region, and is doped with an acceptor of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

In addition, channel formation regions 919 and 920 are formed in regions where the semiconductor film overlaps with the second conductive layers 913b and 914b of the gate electrode. An acceptor is added to the channel formation region 920 at a lower concentration than the first p-type semiconductor region 916.

Next, heat treatment is performed to activate the acceptor of the p-type semiconductor region. This activation may be performed by furnace annealing, laser annealing or lamp annealing, or a combination thereof. In this embodiment, the heat treatment at 500 ° C. for 4 hours is performed in a nitrogen atmosphere. At this time, it is desirable to reduce oxygen in the nitrogen atmosphere as much as possible.

When the activation is completed, as shown in FIG. 9F, a silicon nitride oxide film is formed to a thickness of 200 nm as the passivation film 921, and then the semiconductor layer is hydrogenated. For the hydrogenation treatment, a known hydrogen annealing technique or plasma hydrogenation technique may be used. Further, an interlayer insulating film 922 made of resin is formed to a thickness of 800 nm. As the resin, polyimide, polyamide, acrylic resin, epoxy resin, or BCB (benzocyclobutene) may be used. An inorganic insulating film may be used.

Next, a contact hole is formed in the interlayer insulating film 922 using a third photomask.
Then, wirings 923 to 926 are formed using a fourth photomask. In this embodiment, a laminate of Ti and Al is formed as the wirings 923 to 926. The contact with the p-type semiconductor region is made of Ti in order to improve heat resistance.

Thus, an E-type PTFT 930 and a D-type PTFT 931 are completed. When only the E-type PTFT is formed, it can be completed with four photomasks.
Forming the mold PTFT on the same substrate can be completed with five photomasks.

Each TFT has an LDD that overlaps with the gate electrode, so that deterioration due to the hot carrier effect or the like can be prevented. Such E-type PTFT or D-type PT
Various circuits based on a PMOS circuit can be formed by FT. For example, as described in the embodiment, the EEMOS circuit and the EDMOS circuit described in FIG. 4 can be formed.

An example of a reflective display device using the E-type PTFT or the D-type PTFT shown in Embodiment 2 will be described. An example of the pixel structure is shown in FIG. 12, and a cross-sectional structure is shown in FIG.
FIG. 11 shows a cross-sectional view along AA ′ in FIG.

In FIG. 11, the E-type PTFT 440 and the D-type PTFT 441 of the driving circuit 444 are manufactured by the same process as that of the second embodiment, and the difference is that the first conductive layer is formed after the doping process for forming the second p-type semiconductor region. The film is selectively etched to form the structure shown in FIG. Etching is performed using a mixed gas of Cl ₂ and SF ₆ .

That is, a channel formation region 424, a first p-type semiconductor region 425 (LDD region) that does not overlap with the gate electrode 410, and a second p-type semiconductor region 426 that forms a source or drain region are formed in the semiconductor film 403. ing. Further, in the semiconductor film 404, a channel formation region 427 doped with an acceptor, a first p-type semiconductor region 428 (LDD region) that does not overlap with the gate electrode 411, and a second p for forming a source or drain region. A type semiconductor region 429 is formed. In addition, the base coat films 402a and 402b, the semiconductor films 403 and 404, the gate electrode 407, and the gate electrode 4 are formed on the substrate 401.
10, 411, a passivation film 414, an interlayer insulating film 415, and wirings 417 to 420 are formed. The wiring 408 under the interlayer insulating film is formed in the same layer as the gate electrode, and the wiring 41
6 together with the wiring in the drive circuit.

On the other hand, the pixel TFT 442 of the pixel portion 445 is formed of an E-type PTFT, and is provided as a switching element that controls a voltage applied to the pixel electrode. The pixel TFT 442 and the storage capacitor 443 are formed by the same process as the TFT of the driver circuit 444. The pixel TFT 442 includes a channel formation region 430, a first p-type semiconductor region 431 (LDD region) that does not overlap the gate electrode 412, and a second region that forms a source or drain region in the semiconductor film 405.
P-type semiconductor regions 432 to 434, a gate electrode 412, a source wiring 409, and a connection wiring 42.
1, a pixel electrode 422 and the like are formed. As described above, the off-current is reduced by providing the first p-type semiconductor region 431 (LDD region) that does not overlap with the gate electrode.

In the step of selectively etching the first conductive film to form the first p-type semiconductor region that does not overlap with the gate electrode, the offset region can be formed by adjusting the etching conditions. FIG. 14 is a diagram for explaining this state, in which both ends of the gate electrode 1403 made of the first conductive film and the second conductive film are retreated, and the end of the gate electrode 1403 (or the channel formation region 1306). An offset region 1407 to which no acceptor is added can be formed between the first p-type semiconductor region 1405 and the end portion of the first p-type semiconductor region 1405. The offset region 1407 can be adjusted in a range of about 10 to 1000 nm. PTF due to offset area
The off-current value of T can be reduced. In particular, this region is preferably provided in the pixel TFT.

The storage capacitor 443 includes a semiconductor film 406 having a substantially intrinsic semiconductor region 432 and a p-type semiconductor region 433, a dielectric formed of the same layer as the gate insulating film 407, a capacitor electrode 413,
The capacitor wiring 423 is formed.

FIG. 12 is a top view illustrating the structure of a pixel. A storage capacitor is formed of a semiconductor film 406 and a capacitor electrode 413 using an insulating film formed of the same layer as the gate insulating film over the semiconductor film 406 as a dielectric. ing. Note that the capacitor electrode 413 is connected to the capacitor wiring 423. Capacitance wiring is
The pixel electrode 422, the connection electrode 421, and the gate wiring 424 are simultaneously formed on the same insulating film. The pixel electrode is formed so that the end portion of the source wiring 409 overlaps. With such a structure, the pixel electrode can be made large and the aperture ratio can be improved. Further, the source wiring 409 can have a function as a light shielding film. Such an arrangement of the pixel electrodes can exert an effect of improving the aperture ratio particularly in a reflective liquid crystal display device.

By the way, the size of the storage capacitor provided in the pixel can be determined by the liquid crystal material to be used and the off-current value of the pixel TFT. The holding capacitor C _S also shown in the equivalent circuit of FIG.
The ratio of the liquid crystal capacitance C _LC is C _S / C _LC = 2.7 to 4.5 when nematic liquid crystal is used.
Thus, in the antiferroelectric liquid crystal (AFLC), C _S / C _LC = 7.5.

FIG. 24 shows the gate voltage (VG) versus drain current (ID) characteristics of a single drain, multi-gate PTFT having a channel length of 6.8 μm and a channel width of 4 μm. Focusing on the value of the drain current (VD) = 14 V and the gate voltage (VG) = 4.5 V as the off-current value, the off-current value (I _off ) at that time is 0.4 pA / μm when normalized by the channel width. It is done. This value can be used practically.

  From the above numerical values, the relationship between the off-current value and the storage capacity is defined by the following equation.

Therefore, in the case of nematic liquid crystal, it is 0.08 to 0.1 pA / μm, and in the case of AFLC, it is about 0.05 to 0.07 pA / μm.

The drive circuit shown in FIGS. 1 and 3 can be formed using the E-type PTFT 440 or the D-type PTFT of the drive circuit 444 shown in FIG. An equivalent circuit of the pixel portion 445 is shown in FIG.
Same as (B). Thus, one substrate (referred to as an element substrate in this specification) for forming an active matrix liquid crystal display device can be formed.

In the element substrate shown in FIG. 11, in consideration of deterioration of the PTFT, L of the PTFT of the drive circuit
An example in which the DD structure is changed will be described with reference to FIG. In the element substrate shown in FIG. 13, the configuration of the pixel TFT 442 and the storage capacitor 443 of the pixel portion 445 is the same as that of the third embodiment.
The description is omitted here.

In FIG. 13, an E-type PTFT 540 and a D-type PTFT 541 are formed in the drive circuit 544. These TFTs can be manufactured in the same manner as in FIG. In the E-type PTFT 540, the semiconductor film 503 has a channel formation region 524, a first p-type semiconductor region 525 (LDD) overlapping with the gate electrode 510, and a second p-type semiconductor region 526 forming a source or drain region. Is formed. D type P
The semiconductor film 504 of the TFT 541 includes a channel formation region 527 doped with an acceptor and a first p-type semiconductor region 528 (LDD) overlapping with the gate electrode 511.
), A second p-type semiconductor region 529 forming a source or drain region is formed.

In order to change the LDD structure between the driver circuit 544 and the pixel portion 455, a light exposure process is additionally performed after the doping step. A resist mask that covers the drive circuit 544 is formed, and the pixel portion 4
The configuration shown in FIG. 13 can be realized by selectively etching the first conductive film of the 55 pixel TFTs 442. By forming an LDD region overlapping with the gate electrode in each TFT of the driver circuit 544, deterioration of the TFT due to a hot carrier effect or the like can be prevented. In particular, it can be suitably used for a buffer circuit, a level shifter circuit, and the like.

As an application of the active matrix liquid crystal display device, considering a television receiver,
Large screen size and high definition are required. However, since the number of scanning lines (gate wirings) is increased and the length of the scanning lines (gate wirings) is increased due to the enlargement and high definition of the screen, the resistance of the gate wirings and the source wirings must be further reduced. That is, as the number of scanning lines increases, the charging time for the liquid crystal becomes shorter, and it is necessary to reduce the time constant (resistance × capacitance) of the gate wiring and to respond at high speed. For example, when the specific resistance of the material forming the gate wiring is 100 μΩcm, the screen size is almost limited to the 6-inch class, but when it is 3 μΩcm, it is possible to display up to the 27-inch class.

Considering the resistivity, the wiring material selected includes Al and Cu. FIG. 15 shows an example in which the source wiring is manufactured using Al or the like in the same structure as the pixel portion shown in FIG. In the pixel portion 745, the pixel TFT 442 has the same configuration as that of the third embodiment or the fourth embodiment. The source wiring 709 is formed on the gate insulating film 707 and connected to the connection wiring 42.
1 is contacted. The source wiring 709 is formed of a material mainly composed of Al or Cu and has a resistivity of 10 μΩcm or less, preferably 3 μΩcm or less. Since such a material has a problem in heat resistance, the source wiring 709 is preferably formed after the activation step.

Similarly, in the storage capacitor 443, the capacitor electrode 710 can be formed using a material mainly containing Al or Cu. By forming the capacitor electrode 710 later, the storage capacitor 4
A semiconductor film 406 which is the other electrode of 43 can be formed of the p-type semiconductor region 733.

Since the gate wiring is formed of a material containing Al as a main component, it becomes possible to reduce the resistance together with the source wiring, and the pixel structure shown in FIG. 15 solves the problem of wiring delay and enlarges the screen. It can correspond to. The structure of this embodiment can be combined with Embodiments 1, 3, 4, and 6 to form an active matrix display device.

In Example 3 or Example 4, the pixel electrode may be formed of a transparent conductive film in order to form a transmissive liquid crystal display device. FIG. 16 shows an example, and the pixel electrode 701 is formed on the interlayer insulating film 415 using a transparent conductive film material selected from indium tin oxide (ITO), zinc oxide (ZnO), zinc oxide to which gallium is added, and the like. . The contact with the source or drain region of the pixel TFT may be made by the transparent electrode 701 or may be formed by using the connection electrode 702 as shown in FIG.

It is to be noted that such a configuration of this embodiment can be combined with Embodiments 3, 4, and 5 to form an active matrix display device.

In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an element substrate manufactured using any of the structures of Embodiments 3 to 6 will be described. FIG. 17 shows an element substrate and a counter substrate 710.
Are attached to each other with a sealant 715. Columnar spacers 7 on the element substrate
13 is formed. The pixel portion is preferably formed in accordance with the contact portion on the pixel electrode. Although the spacer depends on the liquid crystal material to be used, the spacer has a height of 3 to 10 μm. Since the concave portion corresponding to the contact hole is formed in the contact portion, disorder of the alignment of the liquid crystal can be prevented by forming a spacer in accordance with this portion. Thereafter, an alignment film 714 is formed and a rubbing process is performed. A transparent conductive film 711 and an alignment film 712 are formed on the counter substrate 710. After that, the element substrate and the counter substrate are bonded to each other, and liquid crystal is injected to form a liquid crystal layer 716.

FIG. 18 schematically shows a state in which an element substrate and a counter substrate are bonded together and assembled. The element substrate 750 is provided with a pixel portion 753, a scanning line side driver circuit 752, a signal line side driver circuit 751, an external input terminal 754, a wiring 759 for connecting the external input terminal to the input portion of each circuit, and the like. A counter electrode 756 is formed on the counter substrate 755 corresponding to a region where the pixel portion and the driving circuit of the active matrix substrate 750 are formed. Such an element substrate 7
50 and the counter substrate 755 are bonded to each other through a sealant 757 and liquid crystal is injected to provide a liquid crystal layer 758 inside the sealant 757. Further, an FPC (Flexible Printed Circuit) 760 is attached to the external input terminal 754 of the element substrate 750. In order to increase the adhesive strength of the FPC 760, a reinforcing plate 759 may be provided.

A cross-sectional view of the external input terminal 754 to which the FPC is attached is shown in FIG. A terminal 762 is formed over the base coat film 761 of the substrate 750 by using the same layer as the gate electrode formed of the first conductive film and the second conductive film. A passivation film 763 and an interlayer insulating film 764 are formed on this upper layer. An opening is formed on the electrode 762, and an electrode 765 which is preferably formed of a transparent conductive film material is formed to integrally form a terminal. Terminal width is 100-1
000 μm, and the pitch is about 50 to 200 μm.

The active matrix liquid crystal display device manufactured as described above can be used as a display device for various electronic devices.

An example of an electronic device using the display device shown in Embodiments 1 to 7 will be described with reference to FIG. The display device in FIG. 20 includes a pixel portion 821 including pixels 820 by TFTs formed on a substrate.
A data signal side driving circuit 815 and a gate signal side driving circuit 814 used for driving the pixel portion are formed. The data signal side driving circuit 815 shows an example of digital driving, but includes a shift register 816, latch circuits 817 and 818, and a buffer circuit 819. The gate signal side driver circuit 814 includes a shift register, a buffer, and the like (none of which are shown).

The system block diagram shown in FIG. 20 shows the form of a portable information terminal such as a PDA. In the display device, a pixel portion 821, a gate signal side driver circuit 814, and a data signal side driver circuit 815 are formed.

The configuration of the external circuit connected to this display device is as follows: a power supply circuit 801 composed of a stabilized power supply and a high-speed high-precision operational amplifier, an external interface port 802 having a USB terminal, CP
U803, a pen input tablet 810 used as input means, a detection circuit 811, a clock signal oscillator 812, a control circuit 813, and the like.

The CPU 803 includes a video signal processing circuit 804, a tablet interface 805 for inputting signals from the pen input tablet 810, and the like. Also, VRAM 806,
A DRAM 807, a flash memory 808, and a memory card 809 are connected.
Information processed by the CPU 803 is converted into a video signal (data signal) as a video signal processing circuit 80.
4 to the control circuit 813.
The control circuit 813 has a function of converting the video signal and the clock into timing specifications of the data signal side driving circuit 815 and the gate signal side driving circuit 814.

Specifically, the function of distributing the video signal to the data corresponding to each pixel of the display device, the horizontal synchronization signal and the vertical synchronization signal input from the outside, the drive circuit start signal and the built-in power supply circuit AC timing Has the function of converting to control signals.

It is desired that a portable information terminal such as a PDA can be used for a long time outdoors or in a train with a rechargeable battery as a power source without being connected to an AC outlet. In addition, such electronic devices are required to be lighter and smaller at the same time with emphasis on ease of carrying. Batteries that occupy most of the weight of electronic devices increase in weight when the capacity is increased.
Therefore, in order to reduce the power consumption of such an electronic device, it is necessary to take measures from the software side, such as controlling the lighting time of the backlight or setting the standby mode.

For example, when an input signal from the pen input tablet 810 does not enter the tablet interface 805 for a certain period of time with respect to the CPU 803, the standby mode is set, and the operation surrounded by the dotted line in FIG. Alternatively, each pixel is provided with a memory and measures such as switching to a still image display mode are taken. Thus, the power consumption of the electronic device is reduced.

In order to display a still image, the video signal processing circuit 804 of the CPU 803 and the VRAM 80
The function such as 6 can be stopped to reduce power consumption. In FIG. 20, the part that performs the operation is indicated by a dotted line. In addition, the controller 813 uses an IC chip, and COG
It may be mounted on the element substrate by the method, or may be integrally formed inside the display device.

In Examples 1 to 8, an organic resin material can be used for the substrate on which the PTFT is formed. As the organic resin material, polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, polycarbonate, polyimide, aramid and the like can be employed. Since the specific gravity of the organic resin material is smaller than that of the glass material, a display device using the organic resin substrate can contribute to weight reduction of the electronic device. For example, considering that a 5-inch class display device is mounted, when a glass substrate is used, the weight is about 60 g, whereas a display device using an organic resin substrate can achieve 10 g or less.

However, since the organic resin material has poor heat resistance, a laser annealing method is actively applied to form a polycrystalline silicon film and activate the acceptor. Laser annealing method has a wavelength of 4
An excimer laser of 00 nm or less or a second harmonic (wavelength 532 nm) to a fourth harmonic (wavelength 266 nm) of a YAG or YVO ₄ laser is used as a light source. These laser beams are condensed into a linear or spot shape by an optical system, and the energy density is 100 to 700 m.
Irradiation is performed as J / cm ² , and processing is performed by scanning the laser beam condensed as described above over a predetermined region of the substrate. By doing so, the annealing process can be performed with little heating of the substrate.

Further, since the organic resin material is inferior in wear resistance, the surface is preferably covered with a DLC film. The surface hardness increases, so-called scratches are difficult to make, and a beautiful display screen can be obtained forever. Thus, by applying the organic resin substrate to the configurations of Examples 1 to 8, extremely excellent effects can be exhibited in electronic devices such as portable information terminals.

Another example of a method for manufacturing a semiconductor film used for forming PTFTs in Examples 1 to 6 will be described with reference to FIGS.

The semiconductor film manufacturing method described with reference to FIG. 21 is a method of performing crystallization by adding an element that promotes crystallization of silicon to the entire surface of an amorphous silicon film. First, in FIG. 21A, a substrate 2101 is a glass substrate typified by Corning # 1773 glass substrate. On the surface of the substrate 2101, a silicon oxynitride film is formed to a thickness of 100 nm using SiH ₄ and N ₂ O as a base coat film 2102 by a plasma CVD method. The base coat film 2102 is provided so that alkali metal contained in the glass substrate does not diffuse into the semiconductor film formed in the upper layer.

An amorphous semiconductor film 2103 mainly composed of silicon is formed by a plasma CVD method, and SiH
₄ is introduced into the reaction chamber, decomposed by intermittent discharge or pulse discharge, and deposited on the substrate 2101. The condition is that high frequency power of 27 MHz is modulated and deposited to a thickness of 54 nm by intermittent discharge with a repetition frequency of 5 kHz and a duty ratio of 20%. In order to reduce as much as possible impurities such as oxygen, nitrogen, and carbon in the amorphous semiconductor film 2103 mainly containing silicon, SiH ₄ having a purity of 99.9999% or more is used. In addition, as a specification of the plasma CVD apparatus, for a reaction chamber having a reaction chamber volume of 13 L, a complex molecular pump having a pumping speed of 300 L / sec is provided in the first stage, and a dry pump having a pumping speed of 40 m ³ / hr is provided in the second stage. In addition to preventing back diffusion of organic vapor from the exhaust system side, the ultimate vacuum of the reaction chamber is increased, and impurity elements are prevented from being taken into the film as much as possible when the amorphous semiconductor film is formed.

Although an example of the plasma CVD method using pulse discharge is shown here, it is needless to say that an amorphous semiconductor film may be formed by plasma CVD method using continuous discharge.

Then, as shown in FIG. 7B, a nickel-containing layer 2104 is formed by applying a nickel acetate salt solution containing 10 ppm of nickel in terms of weight with a spinner. In this case, in order to improve the familiarity of the solution, as the surface treatment of the amorphous semiconductor film 2103 containing silicon as a main component, an extremely thin oxide film is formed with an aqueous solution containing ozone, and the oxide film is mixed with hydrofluoric acid. After etching with a mixed solution of hydrogen oxide water to form a clean surface, treatment with ozone-containing aqueous solution is performed again to form an extremely thin oxide film. Since the surface of silicon is inherently hydrophobic, the nickel acetate solution can be uniformly applied by forming an oxide film in this way.

Next, heat treatment is performed at 500 ° C. for 1 hour to release hydrogen in the amorphous semiconductor film containing silicon as a main component. Then, crystallization is performed by heat treatment at 580 ° C. for 4 hours. Thus, a crystalline semiconductor film 2105 shown in FIG. 21C is formed.

Further, in order to increase the crystallization rate (ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, laser treatment is performed on the crystalline semiconductor film 2105 with laser light 2106. The laser uses excimer laser light that oscillates at 30 Hz with a wavelength of 308 nm. The laser light is condensed to 100 to 300 mJ / cm ² by an optical system, and is 90 to
Laser treatment is performed without melting the semiconductor film with an overlap ratio of 95%.
Thus, a crystalline semiconductor film 2107 mainly containing silicon shown in FIG. 21D can be obtained.

The crystalline semiconductor film 2107 thus manufactured is etched into a predetermined shape to form individually isolated semiconductor films. The semiconductor film manufactured by the method of this example has excellent crystallinity,
Also in the PTFT, field effect mobility and S value (subthreshold coefficient) can be improved.

In Example 10, an amorphous semiconductor film containing silicon and germanium as components can be used. Such an amorphous semiconductor film can be typically manufactured by a plasma CVD method using SiH ₄ and GeH ₄ as source gases. By using an amorphous semiconductor film containing silicon and germanium as components, and employing the crystallization method described in Example 10, {101}
A crystalline semiconductor film having a plane orientation ratio of 30% or more can be obtained. In this case, the germanium content of the amorphous semiconductor film containing silicon and germanium as components is 10 atomic% or less, preferably 5 atomic% or less.

In this embodiment, an electronic device incorporating the active matrix display device of the present invention is shown. Examples of such electronic devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers, televisions, and the like. The electronic devices listed here may be connected to an external circuit as shown in the eighth embodiment. Examples of these are shown in FIGS.

FIG. 22A illustrates a mobile phone, which includes a main body 2901, an audio output unit 9002, and an audio input unit 29.
03, a display device 2904, an operation switch 2905, and an antenna 2906. The present invention can be applied to the display device 2904. In particular, the reflective liquid crystal display device shown in Embodiment 3 or Embodiment 4 is suitable from the viewpoint of reducing power consumption.

FIG. 22B illustrates a video camera, which includes a main body 9101, a display device 9102, and an audio input unit 9.
103, an operation switch 9104, a battery 9105, and an image receiving unit 9106.
The present invention can be applied to the display device 9102. In particular, the reflective liquid crystal display device shown in Example 3 or Example 4 is suitable from the viewpoint of reducing power consumption.

FIG. 22C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, an operation switch 9204, and a display device 9205. The present invention can be applied to the display device 9205. In particular, the reflective liquid crystal display device shown in Example 3 or Example 4 is suitable from the viewpoint of reducing power consumption.

FIG. 22D illustrates a television receiver, which includes a main body 9401, a speaker 9402, and a display device 9.
403, a receiving device 9404, an amplifying device 9405, and the like. The present invention provides a display device 940.
3 can be applied. In particular, the reflective liquid crystal display device shown in Example 3 or Example 4 is suitable from the viewpoint of reducing power consumption.

FIG. 22E illustrates a portable book which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, an operation switch 9505, and an antenna 9506. Data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The direct-view display devices 9502 and 9503 are particularly suitable for the reflective liquid crystal display device shown in Embodiment 3 or Embodiment 4 from the viewpoint of reducing power consumption.

FIG. 23A illustrates a personal computer, which includes a main body 9601, an image input portion 9602,
A display device 9603 and a keyboard 9604 are included. The present invention can be applied to the display device 9603. In particular, the reflective liquid crystal display device shown in Example 3 or Example 4 is suitable from the viewpoint of reducing power consumption.

FIG. 23B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded.
4 and operation switch 9705. This apparatus uses a DVD (Di as a recording medium).
gial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 9702. In particular, the reflective liquid crystal display device shown in Example 3 or Example 4 is suitable from the viewpoint of reducing power consumption.

FIG. 23C illustrates a digital camera, which includes a main body 9801, a display device 9802, and an eyepiece unit 98.
03, an operation switch 9804, and an image receiving unit (not shown). The present invention is a display device 9.
802 can be applied. In particular, the reflective liquid crystal display device shown in Example 3 or Example 4 is suitable from the viewpoint of reducing power consumption.

Claims (2)

A first transistor; a second transistor; a first conductive layer; a second conductive layer; a third conductive layer; a fourth conductive layer; a fifth conductive layer; A conductive layer, an insulating film, a storage capacitor, and a pixel electrode;
The pixel electrode functions as an anode of the EL element,
The first conductive layer, the gate electrode of the first transistor, and the gate electrode of the second transistor have any one of tantalum, tungsten, molybdenum, niobium, and titanium,
The insulating film is provided above the first conductive layer, above the gate electrode of the first transistor, and above the gate electrode of the second transistor,
The second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer are provided above the insulating film,
The first conductive layer has a function of transmitting a video signal,
The first conductive layer extends in a first direction;
The second conductive layer has a function of electrically connecting the first conductive layer and one of a source and a drain of the first transistor,
The third conductive layer has a function of electrically connecting the gate electrode of the second transistor and the other of the source and the drain of the first transistor,
The fourth conductive layer has a function of electrically connecting one of a source and a drain of the second transistor and the pixel electrode,
A gate electrode of the first transistor is electrically connected to the fifth conductive layer;
The fifth conductive layer has a function of transmitting a signal for selecting on or off of the first transistor;
The fifth conductive layer is arranged extending in a second direction intersecting the first direction,
The other of the source and the drain of the second transistor is electrically connected to the sixth conductive layer;
The sixth conductive layer has a function of supplying current to the pixel electrode through the second transistor,
One of the pair of electrodes of the storage capacitor includes a semiconductor layer of the second transistor and a continuous semiconductor layer;
The semiconductor layer comprises a polycrystalline semiconductor;
The other of the pair of electrodes of the storage capacitor includes a gate electrode of the second transistor and a continuous conductive layer. In claim 1,
In the pixel portion, the first conductive layer has a region overlapping with the pixel electrode,
In the pixel portion, the sixth conductive layer has a region overlapping with the pixel electrode,
In the pixel portion, the fifth conductive layer does not overlap with the pixel electrode.

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