JP5602638B2 - フォーマット制御を有する動的アドレス変換 - Google Patents

フォーマット制御を有する動的アドレス変換 Download PDF

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Publication number
JP5602638B2
JP5602638B2 JP2010541762A JP2010541762A JP5602638B2 JP 5602638 B2 JP5602638 B2 JP 5602638B2 JP 2010541762 A JP2010541762 A JP 2010541762A JP 2010541762 A JP2010541762 A JP 2010541762A JP 5602638 B2 JP5602638 B2 JP 5602638B2
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address
bit
translation
entry
region
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Japanese (ja)
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JP2011509469A5 (enExample
JP2011509469A (ja
Inventor
グライナー、ダン
ヘラー、リサ
オシセック、ダミアン
スレゲル、ティモシー
プフェッファー、エルビン
ウェブ、チャールズ
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2010541762A 2008-01-11 2009-01-05 フォーマット制御を有する動的アドレス変換 Active JP5602638B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/972,706 US8037278B2 (en) 2008-01-11 2008-01-11 Dynamic address translation with format control
US11/972,706 2008-01-11
PCT/EP2009/050049 WO2009087132A1 (en) 2008-01-11 2009-01-05 Dynamic address translation with format control

Publications (3)

Publication Number Publication Date
JP2011509469A JP2011509469A (ja) 2011-03-24
JP2011509469A5 JP2011509469A5 (enExample) 2011-05-06
JP5602638B2 true JP5602638B2 (ja) 2014-10-08

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Family Applications (1)

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JP2010541762A Active JP5602638B2 (ja) 2008-01-11 2009-01-05 フォーマット制御を有する動的アドレス変換

Country Status (12)

Country Link
US (1) US8037278B2 (enExample)
EP (1) EP2229630B1 (enExample)
JP (1) JP5602638B2 (enExample)
KR (1) KR101419578B1 (enExample)
CN (1) CN101911022B (enExample)
CY (1) CY1113979T1 (enExample)
DK (1) DK2229630T3 (enExample)
ES (1) ES2406056T3 (enExample)
PL (1) PL2229630T3 (enExample)
PT (1) PT2229630E (enExample)
SI (1) SI2229630T1 (enExample)
WO (1) WO2009087132A1 (enExample)

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US8417916B2 (en) * 2008-01-11 2013-04-09 International Business Machines Corporation Perform frame management function instruction for setting storage keys and clearing blocks of main storage
US8677098B2 (en) 2008-01-11 2014-03-18 International Business Machines Corporation Dynamic address translation with fetch protection
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US8117417B2 (en) 2008-01-11 2012-02-14 International Business Machines Corporation Dynamic address translation with change record override
US8041923B2 (en) 2008-01-11 2011-10-18 International Business Machines Corporation Load page table entry address instruction execution based on an address translation format control field
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US8086811B2 (en) 2008-02-25 2011-12-27 International Business Machines Corporation Optimizations of a perform frame management function issued by pageable guests
US8095773B2 (en) 2008-02-26 2012-01-10 International Business Machines Corporation Dynamic address translation with translation exception qualifier
US8239667B2 (en) * 2008-11-13 2012-08-07 Intel Corporation Switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory
US8782434B1 (en) 2010-07-15 2014-07-15 The Research Foundation For The State University Of New York System and method for validating program execution at run-time
US9753860B2 (en) 2012-06-14 2017-09-05 International Business Machines Corporation Page table entry consolidation
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US9811472B2 (en) * 2012-06-14 2017-11-07 International Business Machines Corporation Radix table translation of memory
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US9069782B2 (en) 2012-10-01 2015-06-30 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
US10445229B1 (en) 2013-01-28 2019-10-15 Radian Memory Systems, Inc. Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies
US11249652B1 (en) 2013-01-28 2022-02-15 Radian Memory Systems, Inc. Maintenance of nonvolatile memory on host selected namespaces by a common memory controller
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EP3033682A4 (en) * 2013-08-14 2017-04-05 Skyera, LLC Address translation for a non-volatile memory storage device
US9542118B1 (en) 2014-09-09 2017-01-10 Radian Memory Systems, Inc. Expositive flash memory control
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US9658792B2 (en) * 2015-06-11 2017-05-23 International Business Machines Corporation Reserving a storage area and building page frame table entries
US11379371B2 (en) 2019-11-07 2022-07-05 Research & Business Foundation Sungkyunkwan University Method and system with improved memory input and output speed
US11175984B1 (en) 2019-12-09 2021-11-16 Radian Memory Systems, Inc. Erasure coding techniques for flash memory

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US8037278B2 (en) 2008-01-11 2011-10-11 International Business Machines Corporation Dynamic address translation with format control
US8041922B2 (en) 2008-01-11 2011-10-18 International Business Machines Corporation Enhanced dynamic address translation with load real address function
US8677098B2 (en) 2008-01-11 2014-03-18 International Business Machines Corporation Dynamic address translation with fetch protection
US8335906B2 (en) * 2008-01-11 2012-12-18 International Business Machines Corporation Perform frame management function instruction for clearing blocks of main storage
US8082405B2 (en) 2008-01-11 2011-12-20 International Business Machines Corporation Dynamic address translation with fetch protection
US8103851B2 (en) 2008-01-11 2012-01-24 International Business Machines Corporation Dynamic address translation with translation table entry format control for indentifying format of the translation table entry
US8019964B2 (en) * 2008-01-11 2011-09-13 International Buisness Machines Corporation Dynamic address translation with DAT protection
US8151083B2 (en) 2008-01-11 2012-04-03 International Business Machines Corporation Dynamic address translation with frame management
US8417916B2 (en) 2008-01-11 2013-04-09 International Business Machines Corporation Perform frame management function instruction for setting storage keys and clearing blocks of main storage
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Also Published As

Publication number Publication date
EP2229630B1 (en) 2013-04-03
CN101911022A (zh) 2010-12-08
PL2229630T3 (pl) 2013-07-31
EP2229630A1 (en) 2010-09-22
KR101419578B1 (ko) 2014-07-25
US20090182964A1 (en) 2009-07-16
DK2229630T3 (da) 2013-05-06
ES2406056T3 (es) 2013-06-05
SI2229630T1 (sl) 2013-06-28
JP2011509469A (ja) 2011-03-24
US8037278B2 (en) 2011-10-11
WO2009087132A1 (en) 2009-07-16
PT2229630E (pt) 2013-05-13
CN101911022B (zh) 2012-10-10
KR20100095629A (ko) 2010-08-31
CY1113979T1 (el) 2016-07-27

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