JP5589836B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5589836B2
JP5589836B2 JP2010505586A JP2010505586A JP5589836B2 JP 5589836 B2 JP5589836 B2 JP 5589836B2 JP 2010505586 A JP2010505586 A JP 2010505586A JP 2010505586 A JP2010505586 A JP 2010505586A JP 5589836 B2 JP5589836 B2 JP 5589836B2
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circuit board
semiconductor element
semiconductor device
recess
manufacturing
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JPWO2009119427A1 (en
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雄己 藤村
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NEC Corp
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Description

本発明は、半導体装置およびその製造方法に関し、特に半導体素子が回路基板上にフリップチップ接続された半導体装置の実装構造およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a mounting structure of a semiconductor device in which a semiconductor element is flip-chip connected on a circuit board and a manufacturing method thereof.

半導体素子の電極が配置される面と回路基板とが対面するように配置されるフリップチップ実装タイプの半導体装置は、厚みが薄いという特長を生かし携帯機器へ数多く採用されているが、機器の薄型化や半導体装置の積層化（PoP : Package on Package）に対応するため、更に薄型化されることが強く求められている。
半導体装置の薄型化は、半導体素子の回路面と反対側にあるシリコン面の研削や、基板の絶縁層を構成するプリプレグ材を薄くすることで実現される。しかし、このような方法によっては半導体装置は薄型化に伴い剛性が低下し、パッケージ内に実装されている半導体素子と回路基板との線膨張係数の差異で生じる応力によって生じる半導体装置の反りが顕著となる。この場合に、回路基板が半導体素子側に向って凸に反るため、半導体素子と回路基板との距離が短くなる。Flip chip mounting type semiconductor devices that are arranged so that the surface on which the electrodes of the semiconductor element are arranged and the circuit board face each other are widely used in portable devices, taking advantage of their thin thickness. There is a strong demand for further reduction in thickness in order to cope with the trend toward semiconductor devices and the stacking of semiconductor devices (PoP: Package on Package).
Thinning of a semiconductor device can be realized by grinding a silicon surface opposite to the circuit surface of a semiconductor element or by thinning a prepreg material that constitutes an insulating layer of a substrate. However, according to such a method, the rigidity of the semiconductor device is reduced as the thickness is reduced, and the warpage of the semiconductor device caused by the stress caused by the difference in the linear expansion coefficient between the semiconductor element mounted in the package and the circuit board is remarkable. It becomes. In this case, since the circuit board warps convexly toward the semiconductor element side, the distance between the semiconductor element and the circuit board becomes short.

而して、今後の半導体素子の開発動向によれば、適用されるアプリケーションの高速化、高機能化、多機能化が考えられる。このため、半導体素子で扱われる信号の周波数は高くなり、並行して処理された複数の信号が、高密度に形成された配線を介して半導体素子の内／外で授受される態様の半導体装置の開発が進むことになる。
これらを実現するためには、半導体素子内の配線ルールは微細化されるとともに回路規模は拡大され、外部回路との間で授受される信号数が増し、これに伴い信号の入出力端である電極数を増す必要がある。電極についてはこれらを狭い半導体素子上へ配置するため、電極サイズの小サイズ化および電極ピッチの狭ピッチ化が進み、これら半導体素子上の電極と、これらに合わせて形成された回路基板上の微細電極とを接続する導電性の接続部材（バンプやはんだボールなど）は、電極に合わせて微細化される必要があり、これに伴い導電性の接続材料の高さも縮小されることとなる。したがって、半導体装置に反りが生じ、半導体素子−回路基板間の距離が短縮されると、半導体素子と回路基板の回路間で生じるクロストークが増大し、信号品質の維持が困難になる。Thus, according to the development trend of the semiconductor element in the future, it is conceivable that the application to be applied is increased in speed, function, and function. For this reason, the frequency of the signal handled by the semiconductor element becomes high, and the semiconductor device in a mode in which a plurality of signals processed in parallel are exchanged inside / outside the semiconductor element via wiring formed at high density Development will progress.
In order to realize these, the wiring rule in the semiconductor element is miniaturized and the circuit scale is enlarged, and the number of signals transferred to and from the external circuit is increased. It is necessary to increase the number of electrodes. Since the electrodes are arranged on a narrow semiconductor element, the electrode size is reduced and the electrode pitch is narrowed. The electrodes on these semiconductor elements and the circuit board formed in accordance with these electrodes Conductive connection members (bumps, solder balls, and the like) that connect the electrodes need to be miniaturized in accordance with the electrodes, and accordingly, the height of the conductive connection material is also reduced. Accordingly, when the semiconductor device is warped and the distance between the semiconductor element and the circuit board is shortened, crosstalk generated between the circuit of the semiconductor element and the circuit board increases, and it becomes difficult to maintain the signal quality.

この反りの対策として、回路基板に生じる反りと逆向きの撓みを予め回路基板に与えておいてから、フリップチップボンディングを行なう手法が提案されている（例えば、特許文献１参照）。図７Ａ〜図７Ｄは、特許文献１にて開示された半導体装置の製造方法を示す工程順の断面図である。まず、凹部１０６を有するボンディングステージ１０５上に、基板側電極１０３ａを有する回路基板１０３を載置し、吸着孔１０５ａ、排気孔１０５ｂより排気する。これにより、凹部１０６上の回路基板が吸引され、弾性変形して下方に凸に撓む。次いで、回路基板１０３上に接着用樹脂１０４を滴下する。チップ側電極１０１ａ、バンプ１０１ｂを有する半導体チップ１０１を、加熱されたボンディングツール１０２により、吸着孔１０２ａを通して吸着し、保持する〔図７Ａ〕。位置合わせ後、ボンディングツール１０２を降下させ、半導体チップ１０１を押圧して、ボンディングを行なうとともに接着用樹脂１０４を硬化させる〔図７Ｂ〕。このとき、接着用樹脂１０４は収縮し、回路基板１０３は、半導体チップ１０１側に引き付けられ、回路基板１０３の撓みは小さくなる。ボンディングツール１０２が上昇し、冷却が進行すると接着用樹脂１０４はさらに収縮し、回路基板１０３の撓みは一層小さくなる〔図７Ｃ〕。ボンディングステージ１０５から取り外すと、図７Ｄに示されるように、反りの小さい半導体装置が得られる。
特開２００６−２０２７８３号公報 As a countermeasure against this warp, there has been proposed a technique of performing flip-chip bonding after preliminarily giving a circuit board a bending in a direction opposite to the warp generated in the circuit board (see, for example, Patent Document 1). 7A to 7D are cross-sectional views in the order of steps showing the method for manufacturing the semiconductor device disclosed in Patent Document 1. FIG. First, the circuit board 103 having the substrate-side electrode 103a is placed on the bonding stage 105 having the recess 106, and exhausted through the suction hole 105a and the exhaust hole 105b. As a result, the circuit board on the concave portion 106 is sucked, elastically deformed, and bent downward. Next, an adhesive resin 104 is dropped on the circuit board 103. The semiconductor chip 101 having the chip-side electrode 101a and the bump 101b is sucked and held through the suction hole 102a by the heated bonding tool 102 [FIG. 7A]. After alignment, the bonding tool 102 is lowered and the semiconductor chip 101 is pressed to perform bonding and cure the adhesive resin 104 [FIG. 7B]. At this time, the adhesive resin 104 contracts, the circuit board 103 is attracted to the semiconductor chip 101 side, and the flexure of the circuit board 103 is reduced. When the bonding tool 102 is raised and the cooling proceeds, the adhesive resin 104 is further contracted, and the flexure of the circuit board 103 is further reduced [FIG. 7C]. When removed from the bonding stage 105, a semiconductor device with small warpage is obtained as shown in FIG. 7D.
JP 2006-202783 A

特許文献１に開示された半導体装置の製造方法では、回路基板を強制的に撓ませており、基板側電極に位置ずれが発生するため、チップ側電極との位置合わせが困難になる。特に、回路基板上に半導体素子の搭載箇所が複数個ある場合、回路基板が複数の凹部で吸引されるため、回路基板のボンディングステージの平坦面に接する部分の形状が変形してしまうので、位置合わせが一層困難になる。
また、特許文献１の製造方法では、排気孔による排気によって、回路基板を撓ませるものであるため、配線やソルダーレジストの凹凸によって吸引ができなくなる可能性があり、またリジットな回路基板には適用が困難になるなど、適用可能な基板が限定されるという問題もあった。
一方、特許文献１によると、半導体装置の反りが低減され、図７Ｄに示されるように、半導体チップと回路基板とがほぼ平行になされるため、従前の半導体素子で課題となっていた、反りによって半導体素子−回路基板間の距離が狭まってクロストークが増大するという問題はある程度緩和される。しかし、今後、半導体素子の小型化、信号の高速化が一層進行することを考慮すると、特許文献１による対策では不十分である。
本発明の課題は、上述した技術の問題点を解決することであって、その目的は、半導体装置の反りを低減すると共に、半導体素子上の回路と回路基板上の回路とのクロストークの低減できるようにすることである。In the method of manufacturing a semiconductor device disclosed in Patent Document 1, the circuit board is forcibly bent, and positional displacement occurs in the substrate side electrode, so that alignment with the chip side electrode becomes difficult. In particular, when there are a plurality of mounting locations of semiconductor elements on the circuit board, the circuit board is sucked by the plurality of recesses, so that the shape of the portion of the circuit board that contacts the flat surface of the bonding stage is deformed. Matching becomes more difficult.
Further, in the manufacturing method of Patent Document 1, since the circuit board is bent by exhausting through the exhaust hole, there is a possibility that suction may not be possible due to the unevenness of the wiring and solder resist, and it is applicable to a rigid circuit board. However, there is a problem that applicable substrates are limited.
On the other hand, according to Patent Document 1, the warpage of the semiconductor device is reduced, and as shown in FIG. 7D, the semiconductor chip and the circuit board are made substantially parallel, so that the warpage that has been a problem in the conventional semiconductor element is present. This alleviates the problem that the distance between the semiconductor element and the circuit board is reduced and crosstalk is increased to some extent. However, in consideration of further progress in miniaturization of semiconductor elements and higher speed of signals in the future, the countermeasure according to Patent Document 1 is insufficient.
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems of the technology, and the object thereof is to reduce warpage of a semiconductor device and to reduce crosstalk between a circuit on a semiconductor element and a circuit on a circuit board. Is to be able to do it.

上記の目的を達成するため、本発明によれば、第１電極を有する回路基板と、前記回路基板に回路形成面が対向するように配置され、前記第１電極と電気的に接続された第２電極を有する半導体素子と、前記半導体素子と前記回路基板との間隙に充填された充填樹脂とを備え、実装されている前記半導体素子の外周部での厚みよりも該半導体素子の中央部での厚みの方が厚い半導体装置、が提供される。   In order to achieve the above object, according to the present invention, a circuit board having a first electrode and a circuit board that is disposed so that a circuit forming surface faces the circuit board and electrically connected to the first electrode are provided. A semiconductor element having two electrodes, and a filling resin filled in a gap between the semiconductor element and the circuit board; A semiconductor device having a larger thickness is provided.

また、上記の目的を達成するため、本発明によれば、
（ａ）回路基板をボンディングステージ上に載置し、
（ｂ）前記回路基板の中央部上の半導体素子搭載領域に充填用の樹脂を供給し、
（ｃ）ツールヘッドにて半導体素子を把持し、半導体素子−回路基板間の位置合わせを行ない、前記半導体素子の回路形成面が前記回路基板に対向するようにして、前記回路基板上に前記半導体素子を配置し、
（ｄ）前記ツールヘッドにより、前記半導体素子を加熱すると共に、半導体素子−回路基板間に圧力を加えて、前記半導体素子の第１電極と前記回路基板の第２電極間に電気的接続が行なわれるようにし、
前記（ｄ）においては、半導体素子搭載領域の前記回路基板が、熱膨張により半導体素子−回路基板間の距離が広がるように湾曲する、
半導体装置の製造方法であって、前記（ａ）においては、
前記ボンディングステージには、第１凹部及び第２凹部を有する段付き凹部が形成されており、
前記第１凹部は、前記回路基板の半導体素子搭載領域下に形成されており、
前記第２凹部は、前記第１凹部の外側に、前記第１凹部より浅く形成されており、
前記第２凹部の前記第１凹部側は平坦面となっており、
前記第２凹部の前記第１凹部と反対側は傾斜面となっている、
ことを特徴とする、半導体装置の製造方法、が提供される。


In order to achieve the above object, according to the present invention,
(A) Place the circuit board on the bonding stage,
(B) supplying a filling resin to the semiconductor element mounting region on the center of the circuit board;
(C) A semiconductor element is gripped by a tool head, alignment between the semiconductor element and the circuit board is performed, and a circuit forming surface of the semiconductor element is opposed to the circuit board so that the semiconductor is placed on the circuit board. Place the elements,
(D) The tool head is used to heat the semiconductor element and apply a pressure between the semiconductor element and the circuit board to make an electrical connection between the first electrode of the semiconductor element and the second electrode of the circuit board. And
In (d), the circuit board in the semiconductor element mounting region is curved so that the distance between the semiconductor element and the circuit board is widened by thermal expansion .
A method of manufacturing a semiconductor device, wherein in (a),
In the bonding stage, a stepped recess having a first recess and a second recess is formed,
The first recess is formed under a semiconductor element mounting region of the circuit board,
The second recess is formed outside the first recess and shallower than the first recess.
The first recess side of the second recess is a flat surface,
The opposite side of the second recess to the first recess is an inclined surface.
A method for manufacturing a semiconductor device is provided.


本発明によると、半導体素子が回路基板へフリップチップ実装されている半導体装置について、半導体素子と回路基板の回路間で発生するクロストークを低減することが可能になり、かつ、反りを低減させることが可能になる。   According to the present invention, for a semiconductor device in which a semiconductor element is flip-chip mounted on a circuit board, it is possible to reduce crosstalk generated between the semiconductor element and the circuit board, and to reduce warpage. Is possible.

本発明の半導体装置の第１の実施の形態を示す断面図。Sectional drawing which shows 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第１の実施の形態の製造方法を示す工程順の断面図。Sectional drawing of the order of a process which shows the manufacturing method of 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第１の実施の形態の製造方法を示す工程順の断面図。Sectional drawing of the order of a process which shows the manufacturing method of 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第１の実施の形態の製造方法を示す工程順の断面図。Sectional drawing of the order of a process which shows the manufacturing method of 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第１の実施の形態の製造方法を示す工程順の断面図。Sectional drawing of the order of a process which shows the manufacturing method of 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第１の実施の形態の製造方法を示す工程順の断面図。Sectional drawing of the order of a process which shows the manufacturing method of 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第１の実施の形態の製造方法を示す工程順の断面図。Sectional drawing of the order of a process which shows the manufacturing method of 1st Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第２の実施の形態を示す断面図。Sectional drawing which shows 2nd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第２の実施の形態の製造方法を説明するための断面図。Sectional drawing for demonstrating the manufacturing method of 2nd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第３の実施の形態を示す断面図。Sectional drawing which shows 3rd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第３の実施の形態の製造方法を説明するための回路基板の断面図。Sectional drawing of the circuit board for demonstrating the manufacturing method of 3rd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第４の実施の形態を示す断面図。Sectional drawing which shows 4th Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第４の実施の形態の製造方法を説明するための断面図。Sectional drawing for demonstrating the manufacturing method of 4th Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第４の実施の形態の製造方法を説明するための断面図。Sectional drawing for demonstrating the manufacturing method of 4th Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第５の実施の製造方法を説明するための断面図。Sectional drawing for demonstrating the manufacturing method of 5th implementation of the semiconductor device of this invention. 本発明の半導体装置の第５の実施の製造方法を説明するための断面図。Sectional drawing for demonstrating the manufacturing method of 5th implementation of the semiconductor device of this invention. 関連する半導体装置の製造方法を示す工程順の断面図。Sectional drawing of the order of the process which shows the manufacturing method of a related semiconductor device. 関連する半導体装置の製造方法を示す工程順の断面図。Sectional drawing of the order of the process which shows the manufacturing method of a related semiconductor device. 関連する半導体装置の製造方法を示す工程順の断面図。Sectional drawing of the order of the process which shows the manufacturing method of a related semiconductor device. 関連する半導体装置の製造方法を示す工程順の断面図。Sectional drawing of the order of the process which shows the manufacturing method of a related semiconductor device.

符号の説明Explanation of symbols

１ 回路基板
１ａ 基板電極
２ 半導体素子
２ａ 素子電極
３ 接続部材
４ ソルダーレジスト
４ａ ソルダーレジスト開口
５ ソルダーレジストパタン
６ アンダーフィル樹脂
７ ステージ
７ａ 吸着孔
７ｂ 凹部
７ｃ 第２の凹部
８ ツールヘッド
８ａ 吸着孔
９ 絶縁性樹脂層
１０１ 半導体チップ
１０１ａ チップ側電極
１０１ｂ バンプ
１０２ ボンディングツール
１０２ａ 吸着孔
１０３ 回路基板
１０３ａ 基板側電極
１０４ 接着用樹脂
１０５ ボンディングステージ
１０５ａ 吸着孔
１０５ｂ 排気孔
１０６ 凹部DESCRIPTION OF SYMBOLS 1 Circuit board 1a Substrate electrode 2 Semiconductor element 2a Element electrode 3 Connection member 4 Solder resist 4a Solder resist opening 5 Solder resist pattern 6 Underfill resin 7 Stage 7a Adsorption hole 7b Recess 7c Second depression 8 Tool head 8a Adsorption hole 9 Insulation Resin layer 101 Semiconductor chip 101a Chip side electrode 101b Bump 102 Bonding tool 102a Adsorption hole 103 Circuit board 103a Substrate side electrode 104 Adhesive resin 105 Bonding stage 105a Adsorption hole 105b Exhaust hole 106 Recess

（第１の実施の形態）
図１は、本発明による半導体装置の第１の実施の形態を示す断面図である。本実施の形態の半導体装置の形状の一例を示すと、以下の通りである。回路基板１は、厚み０．３ｍｍで１５ｍｍ□のガラスクロスへ樹脂を含浸させたプリプレグを基板材料として形成された６層配線の基板である。厚み０．０２５ｍｍのソルダーレジスト４の、回路基板１の中央にある８ｍｍ□のソルダーレジスト開口４ａの領域内に、厚み０．１ｍｍで７ｍｍ□の半導体素子２が半導体素子の回路面が回路基板１に対向するようにフリップチップ実装されている。すなわち、半導体素子２の回路面の６．８ｍｍ□の領域にペリフェラルで配置されている素子電極２ａと、回路基板１上に形成された基板電極１ａが、接続部材３を介して電気的に接続されている。回路基板１は下側に凸形で半導体素子２は上側に凸形となっている。回路基板１と半導体素子２との間には０．０４〜０．１０ｍｍの一様ではない厚みでアンダーフィル樹脂６が充填されている。素子電極２ａと基板電極１ａが接続部材３を介して接続されている部分付近において、アンダーフィル樹脂６は最も薄い０．０４ｍｍの膜厚となっている。また、回路基板１中央付近に存在するアンダーフィル樹脂の最も厚い０．１０ｍｍの部分は、半導体素子２の中央付近である。半導体素子２のフリップチップ搭載工程において、回路基板１のチップ側が凹となって、アンダーフィル樹脂６を厚み０．１０ｍｍに確保できるようにするために、ソルダーレジスト開口４ａの中央に、１ｍｍ□、厚み３０μmのソルダーレジストパタン５を配置している。これにより、逆向きの湾曲が抑制される。(First embodiment)
FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. An example of the shape of the semiconductor device of this embodiment is as follows. The circuit board 1 is a six-layer wiring board formed by using a prepreg obtained by impregnating a glass cloth having a thickness of 0.3 mm and 15 mm □ with a resin as a substrate material. In the region of the solder resist opening 4a of 8 mm □ in the center of the circuit board 1 of the solder resist 4 having a thickness of 0.025mm, the semiconductor element 2 having a thickness of 0.1mm and 7mm □ is the circuit surface of the semiconductor element. It is flip-chip mounted so as to face the surface. That is, the element electrode 2 a arranged as a peripheral in the region of 6.8 mm □ on the circuit surface of the semiconductor element 2 and the substrate electrode 1 a formed on the circuit board 1 are electrically connected via the connection member 3. Has been. The circuit board 1 has a convex shape on the lower side, and the semiconductor element 2 has a convex shape on the upper side. Underfill resin 6 is filled between circuit board 1 and semiconductor element 2 with a non-uniform thickness of 0.04 to 0.10 mm. In the vicinity of the portion where the element electrode 2a and the substrate electrode 1a are connected via the connection member 3, the underfill resin 6 has the thinnest film thickness of 0.04 mm. The thickest part of the underfill resin existing in the vicinity of the center of the circuit board 1 is 0.10 mm near the center of the semiconductor element 2. In the flip-chip mounting process of the semiconductor element 2, the chip side of the circuit board 1 is concave, so that the underfill resin 6 can be secured to a thickness of 0.10 mm, in the center of the solder resist opening 4a, A solder resist pattern 5 having a thickness of 30 μm is disposed. As a result, reverse bending is suppressed.

次に、本実施の形態の半導体装置の製造方法について説明する。図２Ａ〜図２Ｆは、本実施の形態の半導体装置の製造方法を示す工程順の断面図である。図２Ａに示すように、凹部７ｂを有するフリップチップマウンターのステージ７上へ回路基板を搭載する。このとき、回路基板のソルダーレジスト開口４ａの中心がステージ７の凹部７ｂの中心上に位置するようにする。凹部７ｂのサイズは、６ｍｍ□で深さ０．１ｍｍである。凹部７ｂの平面形状は、基板電極１ａに掛からない範囲で極力大きくなるようにする。ボンディング時に膨張する回路基板の範囲を広くして回路基板が大きく湾曲できるようにするためである。理想的には、凹部７ｂの内壁面を含む平面内に、基板電極１ａの内側の辺が存在するようにすることであるが、基板電極１ａが凹部７ｂ上に掛かるとボンディングの信頼性が損なわれるので、若干のアロワンスを設けてもよい。回路基板１のステージ７上への搭載後、ステージ７の吸着孔７ａの吸引により回路基板をステージに固定する。
次に、図２Ｂに示すように、固定された回路基板のソルダーレジスト開口部へ、熱硬化性のアンダーフィル樹脂６を適量塗布する。この場合に、アンダーフィル樹脂の供給量は、回路基板が下に向って湾曲することを見込んでおり、反り対策の行なわれていない場合に比較して増量されている。次いで、図２Ｃに示すように、回路基板よりも上にあるツールヘッド８へ吸着孔８ａにより半導体素子２を吸着し、水平方向のＸ方向とＹ方向について回路基板１の基板電極１ａと半導体素子２の素子電極２ａとの位置が一致するように相対的に移動させる。そして、図２Ｄに示すように、ツールヘッド８に具備されたヒータにより、吸着された半導体素子２を適度に加熱しながら、回路基板１に対し押し付けて荷重をかけ、半導体素子の素子電極上に形成された接続部材３と回路基板１の基板電極１ａとを接触させる。Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 2A to 2F are cross-sectional views in order of steps showing the method for manufacturing the semiconductor device of the present embodiment. As shown in FIG. 2A, a circuit board is mounted on a stage 7 of a flip chip mounter having a recess 7b. At this time, the center of the solder resist opening 4 a of the circuit board is positioned on the center of the recess 7 b of the stage 7. The size of the recess 7b is 6 mm □ and a depth of 0.1 mm. The planar shape of the concave portion 7b is made as large as possible within a range that does not hit the substrate electrode 1a. This is to widen the range of the circuit board that expands at the time of bonding so that the circuit board can be greatly bent. Ideally, the inner side of the substrate electrode 1a exists in a plane including the inner wall surface of the recess 7b. However, if the substrate electrode 1a is placed on the recess 7b, the reliability of bonding is impaired. Therefore, a slight allowance may be provided. After mounting the circuit board 1 on the stage 7, the circuit board is fixed to the stage by suction of the suction holes 7 a of the stage 7.
Next, as shown in FIG. 2B, an appropriate amount of thermosetting underfill resin 6 is applied to the solder resist opening of the fixed circuit board. In this case, the supply amount of the underfill resin is expected to bend the circuit board downward, and is increased compared to the case where no warp countermeasures are taken. Next, as shown in FIG. 2C, the semiconductor element 2 is sucked by the suction holes 8a to the tool head 8 above the circuit board, and the substrate electrode 1a and the semiconductor element of the circuit board 1 in the horizontal direction X and Y direction. The two element electrodes 2a are relatively moved so as to coincide with each other. Then, as shown in FIG. 2D, while the adsorbed semiconductor element 2 is appropriately heated by the heater provided in the tool head 8, it is pressed against the circuit board 1 to apply a load, and is applied onto the element electrode of the semiconductor element. The formed connection member 3 is brought into contact with the substrate electrode 1a of the circuit board 1.

半導体素子２の加熱を続けると、これに伴い回路基板１も加熱され回路基板１は、図２Ｅに示すように、膨張によりステージ７の凹部７ｂ側へ湾曲する。これと共に半導体素子２と回路基板１との間隙に充填されている熱硬化性のアンダーフィル樹脂６が硬化し、半導体素子２と回路基板１が固定される。このとき、回路基板１は膨張により、半導体素子２の回路面へ向けて凸形に変形する可能性がある。ここでは、ソルダーレジスト開口４ａの中央部に形成した１ｍｍ□、０．０３ｍｍ厚のソルダーレジストパタン５がスペーサの役割を果たすことにより、回路基板はステージ７の凹部７ｂに向けて湾曲するように誘導される。
樹脂硬化後は、ツールヘッド８を半導体素子２から離脱させ、半導体素子２と回路基板１は常温にまで冷却され、それぞれの線膨張率で収縮する。半導体素子２として例えばシリコンの線膨張係数は約３ｐｐｍ／℃で、回路基板１として例えばガラスクロスへエポキシ樹脂を含浸させたプリプレグにより形成された基板の線膨張係数は約１５ｐｐｍ／℃である。半導体素子２よりも回路基板１の方が線膨張率が大きいので、回路基板１の方がより大きく収縮し、図２Ｆに示すように、半導体素子２が上向きに凸形、回路基板１が下向きに凸形となった半導体装置が作製される。
これらの工程によって製造された半導体装置は関連するフリップチップの半導体装置よりも、半導体素子の回路面と回路基板の回路面を離すことが可能であるので、相互間の電磁的なアイソレーションを拡大できクロストークを小さくすることが可能である。
また、ツール離脱後の冷却時に半導体装置に反りを発生させようとする応力（反り発生応力）を、主たる応力発生箇所である、半導体素子と回路基板とが積層された箇所において、厚み増加による剛性強化と、この部分の半導体装置が有する湾曲形状とによって、分散させることができ、反り抑制効果が得られる。As the semiconductor element 2 continues to be heated, the circuit board 1 is also heated accordingly, and the circuit board 1 is curved toward the concave portion 7b side of the stage 7 due to expansion, as shown in FIG. 2E. At the same time, the thermosetting underfill resin 6 filled in the gap between the semiconductor element 2 and the circuit board 1 is cured, and the semiconductor element 2 and the circuit board 1 are fixed. At this time, the circuit board 1 may be deformed into a convex shape toward the circuit surface of the semiconductor element 2 due to expansion. Here, the 1 mm □ and 0.03 mm thick solder resist pattern 5 formed at the center of the solder resist opening 4 a serves as a spacer, so that the circuit board is guided to bend toward the concave portion 7 b of the stage 7. Is done.
After the resin is cured, the tool head 8 is detached from the semiconductor element 2, and the semiconductor element 2 and the circuit board 1 are cooled to room temperature and contract at their respective linear expansion rates. For example, silicon as the semiconductor element 2 has a linear expansion coefficient of about 3 ppm / ° C., and the circuit board 1 has a linear expansion coefficient of, for example, a substrate formed of a prepreg obtained by impregnating a glass cloth with an epoxy resin at about 15 ppm / ° C. Since the linear expansion coefficient of the circuit board 1 is larger than that of the semiconductor element 2, the circuit board 1 contracts more greatly, and the semiconductor element 2 is convex upward and the circuit board 1 is downward as shown in FIG. 2F. A semiconductor device having a convex shape is manufactured.
Since the semiconductor device manufactured by these processes can separate the circuit surface of the semiconductor element and the circuit surface of the circuit board from the related flip-chip semiconductor device, the electromagnetic isolation between them is expanded. It is possible to reduce crosstalk.
Also, the stress due to warpage (warping stress) that causes the semiconductor device to warp when cooled after tool separation is the main stress generating location, where the semiconductor element and the circuit board are stacked, the rigidity due to increased thickness The strengthening and the curved shape of the semiconductor device in this portion can be dispersed and a warp suppressing effect can be obtained.

（第２の実施の形態）
図３Ａは、本発明による半導体装置の第２の実施の形態を示す断面図であり、図３Ｂは、第２の実施の形態の半導体装置の製造方法を説明するための断面図である。図３Ａ及び図３Ｂにおいて、図１、図２Ａ〜図２Ｆに示した第１の実施の形態の部分と同等の部分には同一の参照符号を付し、重複する説明は適宜省略する（この点は、以下の実施の形態についても同様である）。本実施の形態の半導体装置の製造工程は一部を除き、先に示された第１の実施の形態の製造工程と同じである。製造工程で異なる点は、図３Ｂに示すように、回路基板を加熱、膨張させ、ステージの凹み側へ湾曲させる工程において、ステージの凹部７ｂの底部と回路基板１の湾曲部とを接触させ、湾曲部の変位量を任意に制限している点である。この凹部７ｂの深さを調整することによって回路基板１の湾曲による変形を制御できる。この制御によって、フリップチップ実装が完了した後の常温での形状を、図３Ａに示すように、回路基板についてはほぼ平坦で、半導体素子については上側が凸形となる構造とすることができる。
この構造は第１の実施の形態と同様に、半導体素子２の回路と回路基板の回路とのノイズ干渉を小さくでき、反りを抑制する効果を得ることが出来る。(Second Embodiment)
FIG. 3A is a cross-sectional view showing a second embodiment of the semiconductor device according to the present invention, and FIG. 3B is a cross-sectional view for explaining a method for manufacturing the semiconductor device of the second embodiment. 3A and 3B, parts equivalent to those of the first embodiment shown in FIGS. 1 and 2A to 2F are denoted by the same reference numerals, and redundant description is omitted as appropriate (this point) The same applies to the following embodiments). The manufacturing process of the semiconductor device of the present embodiment is the same as the manufacturing process of the first embodiment shown previously except for a part. The difference in the manufacturing process is that, as shown in FIG. 3B, in the step of heating and expanding the circuit board and bending it toward the concave side of the stage, the bottom of the concave part 7b of the stage and the curved part of the circuit board 1 are brought into contact with each other. The amount of displacement of the bending portion is arbitrarily limited. By adjusting the depth of the recess 7b, the deformation of the circuit board 1 due to bending can be controlled. With this control, the shape at room temperature after flip-chip mounting is completed can be structured such that the circuit board is substantially flat and the semiconductor element has a convex shape as shown in FIG. 3A.
Similar to the first embodiment, this structure can reduce the noise interference between the circuit of the semiconductor element 2 and the circuit of the circuit board, and can obtain an effect of suppressing warpage.

（第３の実施の形態）
図４Ａは、本発明による半導体装置の第３の実施の形態を示す断面図であり、図４Ｂは、第３の実施の形態の半導体装置の製造方法を説明するための回路基板の断面図である。本実施の形態の半導体装置の、先の第１の実施の形態のそれと異なる点は、回路基板の半導体素子搭載部に、上に凸形状の絶縁性樹脂層９が形成されていることであって、本実施の形態の半導体装置の製造工程は、先の第１の実施の形態の製造工程と同じである。本実施の形態において使用されている回路基板１に形成されている絶縁性樹脂層９の高さは、約０．０４ｍｍであり、第１の実施の形態で示された半導体素子の素子電極２ａと回路基板の基板電極１ａとの接続部付近の回路基板−半導体素子間の間隙幅に概略等しい。
従来の方法によれば、半導体素子を回路基板へ押し当てるときにこれらの隙間にアンダーフィル樹脂を流動させることになるため、樹脂物性は流動性の良い粘度が低い材料を選定する必要であったが、第３の実施の形態では回路基板上へ予め絶縁性の樹脂層を形成しておけばよく、樹脂選定の自由度が拡大される。半導体素子搭載時に絶縁性樹脂層９は硬化前であっても硬化された状態であってもよい。本実施の形態では、ヤング率が１０ＧＰａ以上、膨張率が３０ｐｐｍ／℃の硬化樹脂層を半導体素子搭載前に形成した。
また、この絶縁性樹脂層として、高弾性で低線膨張率の材料の適用も可能である。これにより、パッケージの高剛性化と膨張率低下の実現が容易となる。剛性強化によっては、半導体装置を湾曲させようとする応力に対し変形する量を小さくすることができる。膨張率低下によっては、樹脂と密着している回路基板の膨張が抑制され、半導体装置を湾曲させようとする応力自体を小さくすることができる。
また、アンダーフィル樹脂を無機材料との組み合わせに置き換えることも可能である。例えば厚み０．０２ｍｍのシリコン板を回路基板に接着層０．０１ｍｍを設けて貼り付け半導体素子を搭載した場合、回路基板の特性として剛性を大幅に高めることができ、また膨張を低く抑えることができるので、反り低減への寄与は大きい。(Third embodiment)
FIG. 4A is a cross-sectional view showing a third embodiment of the semiconductor device according to the present invention, and FIG. 4B is a cross-sectional view of a circuit board for explaining the method for manufacturing the semiconductor device of the third embodiment. is there. The semiconductor device of this embodiment is different from that of the first embodiment in that a convex insulating resin layer 9 is formed on the semiconductor element mounting portion of the circuit board. Thus, the manufacturing process of the semiconductor device according to the present embodiment is the same as the manufacturing process of the first embodiment. The height of the insulating resin layer 9 formed on the circuit board 1 used in the present embodiment is about 0.04 mm, and the element electrode 2a of the semiconductor element shown in the first embodiment. Is substantially equal to the gap width between the circuit board and the semiconductor element in the vicinity of the connection portion between the circuit board and the substrate electrode 1a of the circuit board.
According to the conventional method, when the semiconductor element is pressed against the circuit board, the underfill resin is caused to flow in these gaps. Therefore, it is necessary to select a material having good fluidity and low viscosity for the resin physical properties. However, in the third embodiment, an insulating resin layer may be formed on the circuit board in advance, and the degree of freedom in resin selection is expanded. When the semiconductor element is mounted, the insulating resin layer 9 may be in a cured state before or after curing. In this embodiment, a cured resin layer having a Young's modulus of 10 GPa or more and an expansion coefficient of 30 ppm / ° C. is formed before mounting a semiconductor element.
Further, as this insulating resin layer, a material having high elasticity and low linear expansion coefficient can be applied. As a result, it is easy to achieve a high rigidity package and a low expansion coefficient. Depending on the rigidity enhancement, it is possible to reduce the amount of deformation with respect to the stress to bend the semiconductor device. Depending on the decrease in the expansion coefficient, the expansion of the circuit board that is in close contact with the resin is suppressed, and the stress itself that causes the semiconductor device to bend can be reduced.
It is also possible to replace the underfill resin with a combination with an inorganic material. For example, when a semiconductor element is mounted by attaching a silicon plate having a thickness of 0.02 mm to a circuit board with an adhesive layer of 0.01 mm, the rigidity of the circuit board can be greatly increased, and the expansion can be kept low. Because it can, the contribution to warpage reduction is great.

（第４の実施の形態）
図５Ａは、本発明による半導体装置の第４の実施の形態を示す断面図であり、図５Ｂ及び図５Ｃは、第４の実施の形態の半導体装置の製造方法を説明するための断面図である。図５Ａに示される本実施の形態の半導体装置の、図１に示される第１の実施の形態のそれと異なる点は、半導体素子２がほぼ平坦になっている点である。また、本実施の形態の半導体装置の製造方法の、第１の実施の形態のそれと異なる点は、半導体素子を把持するツールヘッド８の形状が異なっていることである。第１〜第３までの実施の形態で用いられていたツールヘッドの形状は、半導体素子と接触する部分が平坦面であるが、本第４の実施の形態では、図５Ｂに示されるように、ツールヘッド８の下面は曲面となっており、半導体素子と接触する部分は吸着孔８ａ付近のみとなっている。このツールヘッドを使って半導体素子へ荷重と熱を加えると、半導体素子２と回路基板１は双方ともに湾曲し図５Ｃに示す形状になる。この後ツールヘッド８を半導体素子２から離脱させ、組みあがった半導体装置を常温まで冷却させると、図５Ａに示されるように、半導体素子２の湾曲は小さく、回路基板の半導体素子搭載面とは反対側の面が凸形となる。第４の実施の形態によっても、第１の実施の形態と同様の効果を得ることができる。(Fourth embodiment)
FIG. 5A is a cross-sectional view showing a fourth embodiment of a semiconductor device according to the present invention, and FIGS. 5B and 5C are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the fourth embodiment. is there. The semiconductor device of the present embodiment shown in FIG. 5A is different from that of the first embodiment shown in FIG. 1 in that the semiconductor element 2 is substantially flat. The semiconductor device manufacturing method of the present embodiment is different from that of the first embodiment in that the shape of the tool head 8 that grips the semiconductor element is different. The shape of the tool head used in the first to third embodiments has a flat surface in contact with the semiconductor element, but in the fourth embodiment, as shown in FIG. 5B. The lower surface of the tool head 8 is a curved surface, and the portion in contact with the semiconductor element is only near the suction hole 8a. When a load and heat are applied to the semiconductor element using this tool head, both the semiconductor element 2 and the circuit board 1 are bent into the shape shown in FIG. 5C. Thereafter, when the tool head 8 is detached from the semiconductor element 2 and the assembled semiconductor device is cooled to room temperature, the curvature of the semiconductor element 2 is small as shown in FIG. The opposite surface is convex. According to the fourth embodiment, the same effect as that of the first embodiment can be obtained.

（第５の実施の形態）
図６Ａ及び図６Ｂは、第５の実施の形態の半導体装置の製造方法を説明するための断面図である。本実施の形態の製造方法の、他の実施の形態のそれと異なる点は、回路基板の載置されるステージ７の構造である。本実施の形態において用いられるステージ７は、第１〜４の実施の形態において用いられていたステージといずれについても置き換え可能である。ここでは、第１の実施の形態に対しステージを代替した場合についてのみ述べる。本実施の形態において用いられるチップマウンターのステージ７では、図６Ａに示されるように、元々あった凹部７ｂの外側に第２の凹部７ｃが形成されている。元々あった凹部７ｂは、回路基板の中央部を下に凸形状に湾曲させるためのものであり、本実施の形態において追加された第２の凹部７ｃは、回路基板の周辺部を湾曲させるためのものである。
回路基板１は第２の凹部７ｃよりも外側にある吸着孔７ａで固定され、半導体素子が搭載される位置にアンダーフィル樹脂６が塗布され、ツールヘッド８に吸着された半導体素子２が回路基板１の搭載位置へ位置合わせされる。次に、ツールヘッド８を降下させ半導体素子に形成された接続部材３と回路基板１の基板電極１ａとを接触させる。そして、荷重を増していくに従い、回路基板周辺が第２の凹部７ｃにより変形し、次いで回路基板が第２の凹部７ｃの底部に接触すると、より大きな荷重が半導体素子の素子電極に形成された接続部材３と回路基板の基板電極１ａとに加わる。このとき、予め塗布されていたアンダーフィル樹脂６は、半導体素子と回路基板との隙間から上方向に湾曲した回路基板上へ流れ出て、半導体素子２を囲むように湾曲した回路基板上にフィレットを形成する。この状態で、ツールヘッド８による半導体素子への加熱が続けられると、回路基板も加熱され膨張し第２の凹部７ｃ側に湾曲する。また、回路基板１の中央部も凹部７ｂ内へ湾曲する。加熱により半導体素子と回路基板との間隙にあるアンダーフィル樹脂６が周辺のフィレットとともに硬化され、図６Ｂに示すように、回路基板の周辺部は上方に湾曲した形で固定される。常温まで冷却される際、先の回路基板における上方向の湾曲は、常温に冷却される際に発生する反りの向きとは逆であったので、回路基板周辺は水平に近づくことになる。(Fifth embodiment)
6A and 6B are cross-sectional views for explaining the method for manufacturing the semiconductor device of the fifth embodiment. The difference between the manufacturing method of this embodiment and that of the other embodiments is the structure of the stage 7 on which the circuit board is placed. The stage 7 used in the present embodiment can be replaced with any of the stages used in the first to fourth embodiments. Here, only the case where the stage is substituted for the first embodiment will be described. In the stage 7 of the chip mounter used in this embodiment, as shown in FIG. 6A, a second recess 7c is formed outside the original recess 7b. The original concave portion 7b is for curving the central portion of the circuit board into a convex shape downward, and the second concave portion 7c added in the present embodiment is for curving the peripheral portion of the circuit board. belongs to.
The circuit board 1 is fixed by the suction hole 7a outside the second recess 7c, the underfill resin 6 is applied to the position where the semiconductor element is mounted, and the semiconductor element 2 sucked by the tool head 8 is attached to the circuit board. 1 is aligned to the mounting position. Next, the tool head 8 is lowered to bring the connection member 3 formed on the semiconductor element into contact with the substrate electrode 1 a of the circuit board 1. As the load is increased, the periphery of the circuit board is deformed by the second recess 7c, and when the circuit board comes into contact with the bottom of the second recess 7c, a larger load is formed on the element electrode of the semiconductor element. Applied to the connecting member 3 and the substrate electrode 1a of the circuit board. At this time, the underfill resin 6 applied in advance flows out from the gap between the semiconductor element and the circuit board onto the circuit board curved upward, and fillets are formed on the circuit board curved so as to surround the semiconductor element 2. Form. In this state, when the heating of the semiconductor element by the tool head 8 is continued, the circuit board is also heated and expanded to bend toward the second recess 7c. Further, the central portion of the circuit board 1 is also curved into the recess 7b. By heating, the underfill resin 6 in the gap between the semiconductor element and the circuit board is cured together with the peripheral fillet, and as shown in FIG. 6B, the peripheral part of the circuit board is fixed in a curved shape upward. When the circuit board is cooled to room temperature, the upward curve in the previous circuit board is opposite to the direction of the warp that occurs when the circuit board is cooled to room temperature, so the periphery of the circuit board approaches horizontal.

以上のように、本発明の半導体装置においては、半導体素子の電極と回路基板の電極を介する導電性の接続部材の高さが、特に低い場合であったり、双方の電極を直接接続する場合においても、半導体素子の回路と回路基板の回路との間隙を拡大させることが可能となる。これにより、回路相互間のクロストークを低減することが可能となる。また、電磁界ノイズの発生源とノイズの受け側を点と考え、こられの間にある空間に、従来の半導体装置と同じ材料が一様に満たされている場合、受け側へ到達するノイズ強度は、発生源からノイズ受け側までの距離の自乗に反比例する。このため、双方ともにノイズ源やノイズの受け側となる可能性がある半導体素子の回路と回路基板との回路は、ある程度の距離を確保した状態で装置に組み込まれることが、クロストーク低減に有効である。
また、本発明の半導体装置の構造は、回路基板の半導体素子が搭載される面の反対側の面の形状は、フリップチップ搭載によって生じる反り対策が実施されていない半導体装置の同じ面の面形状とは、逆向きに湾曲した曲面になっている。
反りを対策されていない半導体装置においては、半導体素子を回路基板へ搭載する際に加熱され、半導体素子と回路基板との間に膨張差が生じた状態で、２枚の平板が積層された形態で固定され、常温にまで冷却される。温度が下がる際、回路基板の収縮量が半導体素子よりも大きいので、半導体装置は先に述べたように半導体素子が搭載されている回路基板面が半導体素子に向かって凸となるように湾曲する。As described above, in the semiconductor device of the present invention, when the height of the conductive connecting member through the electrode of the semiconductor element and the electrode of the circuit board is particularly low, or when both electrodes are directly connected. In addition, the gap between the circuit of the semiconductor element and the circuit of the circuit board can be increased. As a result, crosstalk between circuits can be reduced. If the source of electromagnetic noise and the receiving side of the noise are considered as points, and the space between them is uniformly filled with the same material as a conventional semiconductor device, the noise that reaches the receiving side The intensity is inversely proportional to the square of the distance from the source to the noise receiver. For this reason, it is effective in reducing crosstalk that the circuit between the circuit of the semiconductor element and the circuit board, both of which may be noise sources and noise receivers, is incorporated in the device with a certain distance. It is.
Further, the structure of the semiconductor device of the present invention is such that the shape of the surface on the opposite side of the surface on which the semiconductor element of the circuit board is mounted is the surface shape of the same surface of the semiconductor device in which countermeasures for warping caused by flip chip mounting are not implemented Is a curved surface curved in the opposite direction.
In a semiconductor device in which warpage is not taken, a configuration in which two flat plates are stacked in a state where a heating difference is generated between the semiconductor element and the circuit board when the semiconductor element is mounted on the circuit board. And then cooled to room temperature. Since the shrinkage amount of the circuit board is larger than that of the semiconductor element when the temperature is lowered, the semiconductor device is curved so that the surface of the circuit board on which the semiconductor element is mounted is convex toward the semiconductor element as described above. .

半導体装置のメインボードと接続する面における、半導体装置上にあるメインボードと接続するための電極とメインボードとの電極とが接続されない半導体装置の中央付近の半導体素子と基板とが積層されている部分について、この部分を中央が膨らむ形状に湾曲させる。これにより、曲げに対する剛性が高まる構造となるので、半導体装置の反りを低減させることが可能となる。
半導体装置を構成する回路基板が平坦な場合、回路基板を曲げるように応力が発生すると回路基板の曲げ弾性によって湾曲の程度が決まる。本発明の半導体装置のように、反りが発生する方向とは逆の方向へ湾曲させた形状にするとアーチ型の構造へ上から力が加わるのと同じメカニズムで、反りを発生させようとする応力の一部が回路基板の面内方向に、回路基板を圧縮する向きへ分散され、回路基板を曲げようとする応力は減少する。また、元の構造が反りとは逆向きの湾曲形状であるため、応力により湾曲する方向は平坦に近づく傾向にあり、反りを対策していない半導体装置よりも、反りを低減させることが可能な形状である。この反り低減効果により半導体装置とメインボードとの接触は安定化し、実装歩留まりを高めることが可能となる。A semiconductor element and a substrate in the vicinity of the center of the semiconductor device in which the electrode for connecting to the main board on the semiconductor device and the electrode of the main board are not connected on the surface connected to the main board of the semiconductor device are stacked. About a part, this part is curved in the shape where a center swells. As a result, a structure with increased bending rigidity can be obtained, and thus warpage of the semiconductor device can be reduced.
When a circuit board constituting a semiconductor device is flat, when a stress is generated to bend the circuit board, the degree of bending is determined by the bending elasticity of the circuit board. Stress that tends to cause warping by the same mechanism as when a force is applied to the arched structure when the shape is curved in the direction opposite to the direction in which warpage occurs as in the semiconductor device of the present invention. Is distributed in the in-plane direction of the circuit board in the direction of compressing the circuit board, and the stress to bend the circuit board is reduced. In addition, since the original structure has a curved shape opposite to the warp, the direction of bending due to stress tends to be flat, and the warp can be reduced as compared with a semiconductor device that does not take measures against the warp. Shape. Due to this warp reduction effect, the contact between the semiconductor device and the main board is stabilized, and the mounting yield can be increased.

また、本発明の半導体装置の半導体素子積層部のみの厚みを増した構造は、部材の追加なしで、半導体素子と回路基板との間隙に充填される樹脂の増量と、半導体素子搭載プロセスにおける回路基板の加熱による膨張を利用することによって実現できるので、特殊な組立て装置を必要とせず、低コストな組立てプロセスとすることが可能である。さらに、本発明は上述した実施の形態のみに限定されるものではなく、既に述べた本発明の要旨を逸脱しない範囲において種々の変更が可能であることは勿論である。   Further, the structure in which only the thickness of the semiconductor element stacked portion of the semiconductor device of the present invention is increased without adding members, and the amount of resin filled in the gap between the semiconductor element and the circuit board can be increased. Since this can be realized by utilizing expansion due to heating of the substrate, a special assembling apparatus is not required and a low-cost assembling process can be achieved. Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

この出願は、２００８年３月２６日に出願された日本出願特願２００８−７９６９５を基礎とする優先権を主張し、その開示の全てをここに取り込む。   This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-79695 for which it applied on March 26, 2008, and takes in those the indications of all here.

本発明は、半導体装置およびその製造方法に適用でき、特に半導体素子が回路基板上にフリップチップ接続された半導体装置の実装構造およびその製造方法に適用できる。   The present invention can be applied to a semiconductor device and a manufacturing method thereof, and in particular, can be applied to a semiconductor device mounting structure in which a semiconductor element is flip-chip connected to a circuit board and a manufacturing method thereof.

Claims (8)

（ａ）回路基板をボンディングステージ上に載置し、
（ｂ）前記回路基板の中央部上の半導体素子搭載領域に充填用の樹脂を供給し、
（ｃ）ツールヘッドにて半導体素子を把持し、半導体素子−回路基板間の位置合わせを行ない、前記半導体素子の回路形成面が前記回路基板に対向するようにして、前記回路基板上に前記半導体素子を配置し、
（ｄ）前記ツールヘッドにより、前記半導体素子を加熱すると共に、半導体素子−回路基板間に圧力を加えて、前記半導体素子の第１電極と前記回路基板の第２電極間に電気的接続が行なわれるようにし、
前記（ｄ）においては、半導体素子搭載領域の前記回路基板が、熱膨張により半導体素子−回路基板間の距離が広がるように湾曲する、
半導体装置の製造方法であって、前記（ａ）においては、
前記ボンディングステージには、第１凹部及び第２凹部を有する段付き凹部が形成されており、
前記第１凹部は、前記回路基板の半導体素子搭載領域下に形成されており、
前記第２凹部は、前記第１凹部の外側に、前記第１凹部より浅く形成されており、
前記第２凹部の前記第１凹部側は平坦面となっており、
前記第２凹部の前記第１凹部と反対側は傾斜面となっている、
ことを特徴とする、半導体装置の製造方法。 (A) Place the circuit board on the bonding stage,
(B) supplying a filling resin to the semiconductor element mounting region on the center of the circuit board;
(C) A semiconductor element is gripped by a tool head, alignment between the semiconductor element and the circuit board is performed, and a circuit forming surface of the semiconductor element is opposed to the circuit board so that the semiconductor is placed on the circuit board. Place the elements,
(D) The tool head is used to heat the semiconductor element and apply a pressure between the semiconductor element and the circuit board to make an electrical connection between the first electrode of the semiconductor element and the second electrode of the circuit board. And
In (d), the circuit board in the semiconductor element mounting region is curved so that the distance between the semiconductor element and the circuit board is widened by thermal expansion .
A method of manufacturing a semiconductor device, wherein in (a),
In the bonding stage, a stepped recess having a first recess and a second recess is formed,
The first recess is formed under a semiconductor element mounting region of the circuit board,
The second recess is formed outside the first recess and shallower than the first recess.
The first recess side of the second recess is a flat surface,
The opposite side of the second recess to the first recess is an inclined surface.
A method for manufacturing a semiconductor device. 前記（ｃ）においては、前記第１凹部の側壁のなす平面は、搭載される前記半導体素子の前記第１電極の内側辺を含んでいるかそれより内側に存在するように前記位置合わせを行う、
ことを特徴とする請求項１に記載の半導体装置の製造方法。 In the (c) is formed plane of the side wall of the first recess, the positioning to be present in said Ri Does it'll includes an inner side of the first electrode of the semiconductor element to be mounted Do,
The method of manufacturing a semiconductor device according to claim 1 . 前記（ｄ）においては、湾曲した前記回路基板の凸部が前記第１凹部の底面に接触する、
ことを特徴とする請求項１または２に記載の半導体装置の製造方法。 In (d), the convex part of the curved circuit board contacts the bottom surface of the first concave part ,
The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that. 前記（ｃ）においては、前記ツールヘッドの下面は、下に凸の曲面をなしている、
ことを特徴とする請求項１から３のいずれかに記載の半導体装置の製造方法。 In (c), the lower surface of the tool head forms a downwardly convex curved surface ,
The method of manufacturing a semiconductor device according to any of claims 1 to 3, characterized in that. 前記（ａ）においては、前記半導体素子搭載領域の半導体素子対向面の中央部にスペーサとなる絶縁体層が形成されている、In (a), an insulator layer serving as a spacer is formed at the center of the semiconductor element facing surface of the semiconductor element mounting region.
ことを特徴とする請求項１から４のいずれかに記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein: 前記（ａ）においては、前記絶縁体層がソルダーレジストにより形成されている、In (a), the insulator layer is formed of a solder resist.
ことを特徴とする請求項５に記載の半導体装置の製造方法。6. A method of manufacturing a semiconductor device according to claim 5, wherein: 前記（ａ）においては、前記半導体素子搭載領域の半導体素子対向面の中央部から周辺部にかけて前記半導体素子に向って凸形状の樹脂絶縁層が形成されている、In (a), a convex resin insulating layer is formed from the central part to the peripheral part of the semiconductor element facing surface of the semiconductor element mounting region toward the semiconductor element.
ことを特徴とする請求項１から４のいずれかに記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein: 前記（ａ）においては、前記樹脂絶縁層の高さは、前記半導体素子−回路基板間距離の最小値に等しい、In (a), the height of the resin insulation layer is equal to the minimum value of the distance between the semiconductor element and the circuit board.
ことを特徴とする請求項７に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 7.
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