JP6012531B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP6012531B2
JP6012531B2 JP2013076650A JP2013076650A JP6012531B2 JP 6012531 B2 JP6012531 B2 JP 6012531B2 JP 2013076650 A JP2013076650 A JP 2013076650A JP 2013076650 A JP2013076650 A JP 2013076650A JP 6012531 B2 JP6012531 B2 JP 6012531B2
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor device
resin
electronic component
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013076650A
Other languages
Japanese (ja)
Other versions
JP2014203871A (en
Inventor
裕史 川島
裕史 川島
菊池　正雄
正雄 菊池
川藤　寿
寿 川藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2013076650A priority Critical patent/JP6012531B2/en
Publication of JP2014203871A publication Critical patent/JP2014203871A/en
Application granted granted Critical
Publication of JP6012531B2 publication Critical patent/JP6012531B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、半導体装置に関し、特に基板にチップ部品を搭載する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which chip components are mounted on a substrate.

チップ部品を実装した基板を含む半導体装置、例えば電力用半導体装置は、基板全体も一体に成型して封止することで信頼性を高める構造をとる。ここでチップ部品とは、受動素子である例えば抵抗、コンデンサ、インダクタ等の素子で、その大きさが例えば３．２ｍｍ×１．６ｍｍ、１．０ｍｍ×０．５ｍｍ、０．４ｍｍ×０．２ｍｍ、等の部品である。また、半導体装置の封止方法としては、ポッティング、トランスファーモールド、アンダーフィルなどが存在するが、一般的にはトランスファーモールドを用いることが多い。   A semiconductor device including a substrate on which chip components are mounted, for example, a power semiconductor device, has a structure in which the entire substrate is integrally molded and sealed to increase reliability. Here, the chip component is a passive element such as a resistor, a capacitor, or an inductor, and the size thereof is, for example, 3.2 mm × 1.6 mm, 1.0 mm × 0.5 mm, 0.4 mm × 0.2 mm. , Etc. Moreover, as a method for sealing a semiconductor device, there are potting, transfer mold, underfill and the like, but generally transfer mold is often used.

モールド成型するにあたり、例えば電力用半導体装置のように内部に発熱量が大きい部品を多数用いる場合には、放熱性の向上を図る観点から熱伝導率の高いモールド樹脂が用いられる。一方、高熱伝導性の樹脂は、樹脂中のフィラー成分の配合率が高いことから、モールド樹脂の粘度が高くなる。その結果、チップ部品と基板との間の隙間まで樹脂を流し込むことが困難となる。したがってこの隙間には、熱伝導性が低い気体のボイドが形成され、これは放熱性低下及び信頼性劣化などの問題を誘発する。   When molding, for example, when a large number of components that generate a large amount of heat, such as a power semiconductor device, are used, a mold resin with high thermal conductivity is used from the viewpoint of improving heat dissipation. On the other hand, since the highly heat conductive resin has a high compounding ratio of the filler component in the resin, the viscosity of the mold resin is increased. As a result, it becomes difficult to pour the resin up to the gap between the chip component and the substrate. Therefore, a gas void having a low thermal conductivity is formed in the gap, which induces problems such as a decrease in heat dissipation and a deterioration in reliability.

そこで特許文献１では、絶縁基板におけるチップ部品下に貫通穴を設けることで、モールド樹脂注入時には、この貫通穴を経由してチップ部品下にモールド樹脂を流し込むことが提案されている。   Therefore, Patent Document 1 proposes that a through hole is provided under the chip component in the insulating substrate, and at the time of molding resin injection, the mold resin is poured into the chip component via the through hole.

特開２００６−４１０００号公報（図１）JP 2006-41000 A (FIG. 1)

しかしながら、上記特許文献１の発明では以下の問題が発生する。即ち、熱伝導率を高めた樹脂、つまりフィラー量の多いモールド樹脂を用いた場合、このようなモールド樹脂は、高粘度、高チクソ性の性質を有するため、樹脂注入方向に垂直方向に延在する貫通穴には樹脂が侵入しにくい。よって、貫通穴にモールド樹脂が流れてチップ部品下にまで充填される時期は、樹脂注入後半の静水圧が作用するタイミングとなる。そのためチップ部品下には、やはりボイドがトラップされてしまう。このため、チップ部品下の放熱性低下が発生し、また、静水圧加圧時にボイド周辺に応力が集中することでチップ部品が割れるなどの問題があった。   However, the invention described in Patent Document 1 has the following problems. That is, when a resin with high thermal conductivity, that is, a mold resin with a large amount of filler is used, such a mold resin has high viscosity and high thixotropy, and thus extends in a direction perpendicular to the resin injection direction. It is difficult for the resin to enter the through hole. Therefore, the time when the mold resin flows into the through hole and is filled under the chip part is the timing when the hydrostatic pressure acts in the latter half of the resin injection. Therefore, the void is still trapped under the chip part. For this reason, there is a problem in that the heat dissipation under the chip component is reduced, and the chip component is cracked due to stress concentration around the void when hydrostatic pressure is applied.

本発明は、上述のような課題を解決するためになされたもので、電子部品下で絶縁基板との間にボイドの発生を抑制することができる半導体装置を提供することを目的とする。   SUMMARY An advantage of some aspects of the invention is that it provides a semiconductor device capable of suppressing the generation of voids between an electronic component and an insulating substrate.

上記目的を達成するため、本発明は以下のように構成する。
即ち、本発明の一態様における半導体装置は、封止体及び端子を有する電子部品と、上記電子部品の上記端子を接合して当該電子部品を実装する絶縁基板で、実装された電子部品に対応した位置に当該絶縁基板を貫通する貫通穴を形成した絶縁基板と、フィラーを含有し、上記電子部品を実装した絶縁基板を封止する封止樹脂とを備えた半導体装置であって、上記絶縁基板は、凹形状の変位発生部をさらに有し、この変位発生部は、上記電子部品を実装する上記絶縁基板の実装面で上記貫通穴の周縁部に形成されることを特徴とする。 In order to achieve the above object, the present invention is configured as follows.
That is, a semiconductor device according to one embodiment of the present invention is an electronic component having a sealing body and a terminal, and an insulating substrate that mounts the electronic component by bonding the terminal of the electronic component, and corresponds to the mounted electronic component. A semiconductor device comprising: an insulating substrate in which a through hole penetrating the insulating substrate is formed at a position; and a sealing resin that contains a filler and seals the insulating substrate on which the electronic component is mounted. The substrate further includes a concave displacement generating portion, and the displacement generating portion is formed on a peripheral portion of the through hole on the mounting surface of the insulating substrate on which the electronic component is mounted.

本発明の一態様における半導体装置によれば、絶縁基板に変位発生部を備えたことで、封止工程において封止樹脂のフィラーが絶縁基板の実装面と電子部品の封止体との隙間に挟まるような場合でも、貫通穴周縁部は変位可能となり、例えば電子部品の下方へ撓むことができる。したがって電子部品下にも封止樹脂が進入し易くなり、ボイド形成の防止を図ることができる。その結果、製造された半導体装置の長寿命化、及び歩留まりの向上を図ることも可能となる。   According to the semiconductor device of one embodiment of the present invention, since the insulating substrate includes the displacement generation portion, the sealing resin filler is placed in the gap between the mounting surface of the insulating substrate and the sealing body of the electronic component in the sealing process. Even in the case of being pinched, the peripheral portion of the through hole can be displaced, and can be bent downward, for example, of the electronic component. Therefore, the sealing resin can easily enter under the electronic component, and the formation of voids can be prevented. As a result, it is possible to extend the life of the manufactured semiconductor device and improve the yield.

本発明の実施の形態における半導体装置を示す図であり、図２に示すＡ−Ｂ部における断面図である。It is a figure which shows the semiconductor device in embodiment of this invention, and is sectional drawing in the AB section shown in FIG. 図１に示す半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. 図１に示す半導体装置の樹脂封止工程の概略を示す図であり、（ａ）から（ｆ）は封止動作の一例を工程順に示した図である。It is a figure which shows the outline of the resin sealing process of the semiconductor device shown in FIG. 1, (a) to (f) is the figure which showed an example of sealing operation in process order. 高熱伝導性の樹脂で封止を行う一般的な場合を模式的に示した図である。It is the figure which showed typically the general case which seals with highly heat conductive resin. 図１に示す半導体装置における樹脂封止動作状態を示す図である。It is a figure which shows the resin sealing operation state in the semiconductor device shown in FIG. 図５に示すＣ部の拡大図である。It is an enlarged view of the C section shown in FIG. 図１に示す半導体装置の変形例における樹脂封止動作状態を示す図である。It is a figure which shows the resin sealing operation state in the modification of the semiconductor device shown in FIG. 図７に示すＤ部の拡大図である。It is an enlarged view of the D section shown in FIG. 図１に示す半導体装置に備わる変位発生部の形成方法を説明するための図である。It is a figure for demonstrating the formation method of the displacement generation part with which the semiconductor device shown in FIG. 1 is equipped.

本発明の実施の形態における半導体装置について、図を参照しながら以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。また、以下の説明が不必要に冗長になるのを避け当業者の理解を容易にするため、既によく知られた事項の詳細説明及び実質的に同一の構成に対する重複説明を省略する場合がある。また、以下の説明及び添付図面の内容は、特許請求の範囲に記載の主題を限定することを意図するものではない。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. In addition, in order to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art, a detailed description of already well-known matters and a duplicate description of substantially the same configuration may be omitted. . Further, the contents of the following description and the accompanying drawings are not intended to limit the subject matter described in the claims.

実施の形態１．
実施の形態１における半導体装置について図を用いて説明する。尚、以下の説明では、半導体装置として、発熱量の大きい電力用半導体素子を備えた電力用半導体装置を例に採るが、これに限定するものではない。
まず、このような電力用半導体装置及びその主な部材の基本的構成について、図２を用いて説明する。また図１は、図２に示す絶縁基板のＡ−Ｂ部における断面図である。 Embodiment 1 FIG.
The semiconductor device in Embodiment 1 will be described with reference to the drawings. In the following description, a power semiconductor device including a power semiconductor element having a large calorific value is taken as an example of the semiconductor device, but the present invention is not limited to this.
First, the basic configuration of such a power semiconductor device and its main members will be described with reference to FIG. 1 is a cross-sectional view taken along the line AB of the insulating substrate shown in FIG.

図２に示すように、電力用半導体装置１は、絶縁基板２とフレーム５０との二つの基板で構成されている。フレーム５０には、電力用半導体素子としてのＩＧＢＴ５１、Ｄｉ（ダイオード）５２が搭載されており、Ａｌワイヤ５３で配線接続されている。一方、絶縁基板２には、配線パターン６（図１）上に、はんだ５を用いてチップ部品３を実装している。チップ部品３は既に説明した、受動素子の、例えば抵抗、コンデンサ等の部品であり、ここでは封止体３Ａと端子３Ｂとを有する。また、絶縁基板２とフレーム５０とはＡｌワイヤ５３で電気的に接続している。そしてフレーム５０上、及び絶縁基板２上の部品のすべてを封止樹脂８にて封止して電力用半導体装置１が形成されている。
尚、ここでは絶縁基板２にはチップ部品３を実装したが、実装される部品はチップ部品に限定するものではなく、一般的な電子部品であってもよい。
また、図１に示すように、チップ部品３に対応した位置で絶縁基板２には、絶縁基板２を貫通する貫通穴７を設けている。貫通穴７の面積は、絶縁基板２と対向するチップ部品３の下面表面積よりも小さいことが望ましい。 As shown in FIG. 2, the power semiconductor device 1 includes two substrates, an insulating substrate 2 and a frame 50. An IGBT 51 and a Di (diode) 52 as power semiconductor elements are mounted on the frame 50, and are interconnected by Al wires 53. On the other hand, the chip component 3 is mounted on the insulating substrate 2 using the solder 5 on the wiring pattern 6 (FIG. 1). The chip component 3 is a component of a passive element, for example, a resistor or a capacitor, which has already been described. The insulating substrate 2 and the frame 50 are electrically connected by an Al wire 53. The power semiconductor device 1 is formed by sealing all components on the frame 50 and the insulating substrate 2 with a sealing resin 8.
Although the chip component 3 is mounted on the insulating substrate 2 here, the mounted component is not limited to the chip component, and may be a general electronic component.
As shown in FIG. 1, the insulating substrate 2 is provided with a through hole 7 penetrating the insulating substrate 2 at a position corresponding to the chip component 3. The area of the through hole 7 is desirably smaller than the lower surface area of the chip component 3 facing the insulating substrate 2.

さらに電力用半導体装置１では、特徴的構成部分の一つとして、絶縁基板２は、チップ部品３を実装する実装面２ｃで貫通穴７の周縁部に変位発生部２０（図１）を有する。この変位発生部２０は、チップ部品３の封止体３Ａの厚みよりも大きい深さを有する凹形状で形成される。また本実施の形態では、変位発生部２０は、チップ部品３の封止体３Ａの４つの側面３Ｃつまり封止体３Ａの外周４辺よりも外側に位置する。図６等を参照して、変位発生部２０についてさらに詳しく説明する。   Further, in the power semiconductor device 1, the insulating substrate 2 has a displacement generating portion 20 (FIG. 1) on the peripheral portion of the through hole 7 on the mounting surface 2 c on which the chip component 3 is mounted as one of characteristic components. The displacement generating part 20 is formed in a concave shape having a depth larger than the thickness of the sealing body 3 </ b> A of the chip component 3. Further, in the present embodiment, the displacement generator 20 is located outside the four side surfaces 3C of the sealing body 3A of the chip component 3, that is, the outer peripheral four sides of the sealing body 3A. The displacement generator 20 will be described in more detail with reference to FIG.

絶縁基板２の延在方向２ｂにおいて、凹状断面の変位発生部２０は、外側端２１と内側端２２とを有する。外側端２１は、貫通穴７の外側でチップ部品３の封止体側面３Ｃよりも外側で、配線パターン６よりも内側に位置する。内側端２２は、図６に示すように外側端２１と貫通穴７との間に位置するか、又は図７及び図８に示すように貫通穴７の内周面７ａに一致する。このように、絶縁基板２の延在方向２ｂにおいて変位発生部２０の幅の大きさは任意であるが、変位発生部２０の深さＤは、上述のようにチップ部品３の封止体３Ａの厚みｔよりも大きいことが望ましい。
また、変位発生部２０を真上から見たとき、外側端２１及び内側端２２は、貫通穴７と同心円状に配置されてもよいし、また、チップ部品３と相似形状に配置されてもよい。 In the extending direction 2 b of the insulating substrate 2, the displacement generating section 20 having a concave cross section has an outer end 21 and an inner end 22. The outer end 21 is located outside the through hole 7, outside the sealing body side surface 3 </ b> C of the chip component 3, and inside the wiring pattern 6. The inner end 22 is located between the outer end 21 and the through hole 7 as shown in FIG. 6, or coincides with the inner peripheral surface 7a of the through hole 7 as shown in FIGS. As described above, the width of the displacement generating unit 20 in the extending direction 2b of the insulating substrate 2 is arbitrary, but the depth D of the displacement generating unit 20 is the sealing body 3A of the chip component 3 as described above. It is desirable that the thickness be larger than the thickness t.
Further, when the displacement generator 20 is viewed from directly above, the outer end 21 and the inner end 22 may be arranged concentrically with the through hole 7 or may be arranged in a similar shape to the chip component 3. Good.

以上説明した構成を備えた電力用半導体装置１を例に採り、図３から図６を参照して該半導体装置の製造方法について、特に樹脂封止動作について説明する。   Taking the power semiconductor device 1 having the above-described configuration as an example, a method for manufacturing the semiconductor device, particularly a resin sealing operation, will be described with reference to FIGS.

まず、チップ部品３をはんだ付けした絶縁基板２を用意して、既にＩＧＢＴ５１、Ｄｉ５２を搭載したフレーム５０に絶縁基板２を接着剤などで貼り付け固定する。その後、絶縁基板２とフレーム５０とをＡｌワイヤ５３で電気的に接続する。その後、モールド工程つまり樹脂封止工程に移行する。   First, the insulating substrate 2 to which the chip component 3 is soldered is prepared, and the insulating substrate 2 is attached and fixed to the frame 50 on which the IGBT 51 and Di 52 are already mounted with an adhesive or the like. Thereafter, the insulating substrate 2 and the frame 50 are electrically connected by the Al wire 53. Thereafter, the process proceeds to a molding process, that is, a resin sealing process.

本実施形態では、樹脂封止はトランスファーモールド技術を用いる。ここでトランスファーモールド工程について簡単に説明する。トランスファーモールドは、熱硬化性のモールド樹脂（封止樹脂）を熱によって溶融させた状態のまま、注入圧をかけて押し出してモールド金型に注入する封止方法である。注入後、まだ溶融しているモールド樹脂に静水圧としての圧力をかけ続けることで樹脂密度を高める。そのまま数分間置いて熱硬化させた後、モールド金型から成型体を取り出して完成する。   In this embodiment, the resin sealing uses a transfer mold technique. Here, the transfer molding process will be briefly described. The transfer mold is a sealing method in which a thermosetting mold resin (sealing resin) is melted by heat and extruded and injected into a mold. After injection, the resin density is increased by continuing to apply a hydrostatic pressure to the molten mold resin. After leaving for several minutes as it is and thermosetting, the molded body is taken out from the mold and completed.

さらに樹脂封止工程について説明する。
樹脂封止工程にあたり、部品実装後の絶縁基板２は、図３の（ａ）に示すようにモールド金型（封止用金型）１０内に配置される。また図３の（ａ）から（ｆ）では、封止工程内の各動作を経時的に示している。ここで「１１」は可動ピンを示す。可動ピン１１は、モールド金型１０に備わり、駆動装置１０Ａによって絶縁基板２の板厚方向２ａに昇降可能な棒状の例えば金属製の部材である。尚、図示では、可動ピン１１の先端を円錐台形状で示すが、可動ピン１１の先端部形状はこの形状に限定するものではない。また、図３の（ｂ）から（ｆ）において駆動装置１０Ａの図示は省略する。 Further, the resin sealing process will be described.
In the resin sealing process, the insulating substrate 2 after component mounting is disposed in a molding die (sealing die) 10 as shown in FIG. 3A to 3F show each operation in the sealing process over time. Here, “11” indicates a movable pin. The movable pin 11 is a rod-shaped, for example, metal member that is provided in the mold 10 and can be moved up and down in the plate thickness direction 2a of the insulating substrate 2 by the driving device 10A. In the drawing, the tip of the movable pin 11 is shown in a truncated cone shape, but the tip shape of the movable pin 11 is not limited to this shape. Also, the illustration of the driving device 10A is omitted in FIGS.

また絶縁基板２をモールド金型１０に配置する際には、図３の（ａ）に示すように可動ピン１１は、予めモールド金型１０の下型から上昇させておき、絶縁基板２の貫通穴７に挿入する。これにより、可動ピン１１の先端は、チップ部品３の下面３ａに接する。   When the insulating substrate 2 is placed on the mold 10, the movable pin 11 is raised from the lower mold of the mold 10 in advance as shown in FIG. Insert into hole 7. Thereby, the tip of the movable pin 11 is in contact with the lower surface 3 a of the chip component 3.

モールド樹脂注入では、図３の（ａ）に示すように、モールド樹脂８を絶縁基板２の横（面方向）から絶縁基板２の延在方向２ｂに沿ってモールド金型１０内へ注入する。このようにモールド樹脂８の注入方向は絶縁基板２の延在方向２ｂと一致する。よって以下では「注入方向２ｂ」と記す場合もある。また、本実施の形態ではＩＧＢＴ５１等の発熱性素子を備えるため、放熱性を考慮する観点からモールド樹脂８は、高熱伝導性の樹脂材であり、既に説明したように、樹脂中のフィラー成分の配合率が高く粘性が高い樹脂材である。
よって、この高い粘度に起因して、モールド樹脂注入では、チップ部品３の部品直下にはモールド樹脂８が注入されにくく、図３の（ｂ）のようにチップ部品３と絶縁基板２との間にボイド３０がトラップされることが懸念される。 In the mold resin injection, as shown in FIG. 3A, the mold resin 8 is injected into the mold 10 from the side (surface direction) of the insulating substrate 2 along the extending direction 2b of the insulating substrate 2. Thus, the injection direction of the mold resin 8 coincides with the extending direction 2 b of the insulating substrate 2. Therefore, in the following, it may be referred to as “injection direction 2b”. In the present embodiment, since the heat generating element such as IGBT 51 is provided, the mold resin 8 is a highly thermally conductive resin material from the viewpoint of heat dissipation, and as already described, the filler component in the resin It is a resin material with a high blending ratio and high viscosity.
Therefore, due to this high viscosity, in the molding resin injection, it is difficult for the molding resin 8 to be injected directly under the component of the chip component 3, and between the chip component 3 and the insulating substrate 2 as shown in FIG. There is a concern that the void 30 is trapped.

一方、可動ピン１１とモールド金型１０との間には、可動ピン１１が摺動可能なように微小な隙間１０Ｂが存在し、この隙間１０Ｂがエアベントの役割を果たす。したがって、可動ピン１１付近のボイド３０は、可動ピン１１とモールド金型１０との間の隙間１０Ｂを通り金型１０の外部へ抜けることが可能である（図３の（ｃ））。   On the other hand, a minute gap 10B exists between the movable pin 11 and the mold 10 so that the movable pin 11 can slide, and this gap 10B serves as an air vent. Therefore, the void 30 in the vicinity of the movable pin 11 can pass through the gap 10B between the movable pin 11 and the mold 10 and escape to the outside of the mold 10 ((c) in FIG. 3).

その後、図３の（ｄ）、（ｅ）に示すように、モールド樹脂８に静水圧を作用させた状態にて、可動ピン１１を貫通穴７さらにモールド樹脂８から引き抜くことで、モールド樹脂８内で可動ピン１１が存在した部分にもモールド樹脂８を充填して行き、ボイド３０を消滅させる。このとき可動ピン１１の移動は、連続的に行っても良いし、途中で一旦移動を停止させてもよい。
最後に可動ピン１１をモールド金型１０の規定位置（通常の初期位置）に戻し、モールド樹脂８を硬化させて、可動ピン１１を引き抜く（図３の（ｆ））。 Thereafter, as shown in FIGS. 3D and 3E, the movable pin 11 is pulled out from the through-hole 7 and further from the mold resin 8 in a state where the hydrostatic pressure is applied to the mold resin 8, whereby the mold resin 8 The mold resin 8 is filled in the portion where the movable pin 11 is present, and the void 30 disappears. At this time, the movement of the movable pin 11 may be performed continuously, or the movement may be temporarily stopped on the way.
Finally, the movable pin 11 is returned to the specified position (normal initial position) of the mold 10, the mold resin 8 is cured, and the movable pin 11 is pulled out ((f) in FIG. 3).

本実施形態におけるモールド工程では、フィラーを含むモールド樹脂８の溶融時の粘度は、一例として５〜１００Ｐａ・ｓである。また、モールド樹脂８及びモールド金型１０における温度、つまりモールド温度は、例えば１６０〜２００℃程度に設定することができる。また、モールド樹脂８の樹脂成分は、エポキシ系樹脂を主剤とし、フィラー８１としてＳｉＯ２等が挙げられ、高熱伝導率とするにはその含有量を例えば４０ｖｏｌ％以上とすることができる。 In the molding process in the present embodiment, the viscosity at the time of melting of the mold resin 8 containing the filler is, for example, 5 to 100 Pa · s. Moreover, the temperature in the mold resin 8 and the mold 10, that is, the mold temperature can be set to about 160 to 200 ° C., for example. In addition, the resin component of the mold resin 8 includes an epoxy resin as a main component and SiO 2 or the like as the filler 81, and the content can be set to, for example, 40 vol% or more in order to achieve high thermal conductivity.

次に、上述した樹脂封止工程における変位発生部２０の作用について、図４から図６を参照して説明する。
まず一般的な樹脂封止工程では、モールド樹脂８の流動後、モールド樹脂８に静水圧を作用するタイミングにおいて、図４に示すようにモールド樹脂８に含まれるフィラー８１がチップ部品３下へ流動しようとする。ここでモールド樹脂８が高熱伝導率を有するタイプであって、フィラー８１の粒径がチップ部品３と絶縁基板２の実装面２ｃとの隙間３１の大きさ、つまり板厚方向２ａにおける隙間３１の高さ、と同等又はこれを超える大きさを有するフィラーを含有する場合には、隙間３１の入口部分へのフィラー８１の詰まりが発生する。このような詰まりが発生すると、チップ部品３下にはモールド樹脂８の未充填部分３２が形成され、モールド樹脂８の静水圧によりチップ部品３が変形して損傷する場合も発生する。 Next, the effect | action of the displacement generation | occurrence | production part 20 in the resin sealing process mentioned above is demonstrated with reference to FIGS.
First, in a general resin sealing process, after the mold resin 8 flows, the filler 81 contained in the mold resin 8 flows below the chip part 3 as shown in FIG. 4 at a timing when hydrostatic pressure is applied to the mold resin 8. try to. Here, the mold resin 8 is a type having a high thermal conductivity, and the particle size of the filler 81 is the size of the gap 31 between the chip component 3 and the mounting surface 2c of the insulating substrate 2, that is, the gap 31 in the plate thickness direction 2a. When a filler having a size equal to or exceeding the height is contained, the filler 81 is clogged in the entrance portion of the gap 31. When such clogging occurs, an unfilled portion 32 of the mold resin 8 is formed under the chip component 3, and the chip component 3 may be deformed and damaged by the hydrostatic pressure of the mold resin 8.

これに対し、本実施の形態の電力用半導体装置１では、隙間３１の入口部分に対応して、上述したように絶縁基板２には変位発生部２０を形成している。したがって、図５及び図６に示すように、隙間３１の入口部分でフィラー８１の詰まりが生じた場合でも、変位発生部２０の外側端２１から貫通穴７側に位置しチップ部品３下方に位置する、絶縁基板２における変位可能部分２ｅは、変位発生部２０に起因して、チップ部品３とは反対側へ撓むことが可能である。これによってフィラー８１は、隙間３１が広くなり入口部分を通過することができ、モールド樹脂８は、チップ部品３下に流動可能である。その結果、フィラー８１の流動性が向上し、チップ部品３下におけるモールド樹脂８の充填密度をより高めることができ、未充填部分３２の形成も防止することができる。よって、静水圧印加時においてもチップ部品３は変形せず、割れ等の損傷も発生しないことから、半導体装置の信頼性を確保することができ、また、半導体装置の長寿命化及び歩留まりの向上を図ることも可能となる。   On the other hand, in the power semiconductor device 1 of the present embodiment, the displacement generating portion 20 is formed in the insulating substrate 2 as described above corresponding to the entrance portion of the gap 31. Therefore, as shown in FIGS. 5 and 6, even when the filler 81 is clogged at the entrance portion of the gap 31, it is located on the through hole 7 side from the outer end 21 of the displacement generating portion 20 and is located below the chip part 3. The displaceable portion 2e in the insulating substrate 2 can be bent to the side opposite to the chip component 3 due to the displacement generating portion 20. As a result, the gap 81 is widened and the filler 81 can pass through the inlet portion, and the mold resin 8 can flow under the chip component 3. As a result, the fluidity of the filler 81 is improved, the filling density of the mold resin 8 under the chip component 3 can be further increased, and the formation of the unfilled portion 32 can be prevented. Therefore, the chip component 3 is not deformed even when a hydrostatic pressure is applied, and damage such as cracks does not occur. Therefore, the reliability of the semiconductor device can be ensured, and the life of the semiconductor device is increased and the yield is improved. Can also be achieved.

また、変位発生部２０を設けることで、より大きな粒径のフィラー８１を用いることができるため、より高い熱伝導率を有するモールド樹脂８を用いることができ、半導体装置における放熱性をさらに向上させ、チップ部品の寿命をさらに延ばすことも可能となる。   In addition, since the filler 81 having a larger particle size can be used by providing the displacement generator 20, the mold resin 8 having higher thermal conductivity can be used, and the heat dissipation in the semiconductor device can be further improved. Further, it is possible to further extend the life of the chip component.

また、変位発生部２０は、図７及び図８に示され上述したように、その内側端２２を貫通穴７の内周面７ａに一致させてもよい（説明上、変位発生部２０−２と記す）。このような構成を採った場合でも、少なくとも上述と同様の効果を得ることができる。
このような変位発生部２０−２では、チップ部品３下方の、絶縁基板２における変位可能部分２ｅは、変位発生部２０の場合に比べて板厚の薄い領域が大きいことから、変位がさらに容易となる。したがって、チップ部品３下でのフィラー８１の流動自由度がさらに増し、上下方向つまり絶縁基板２の板厚方向２ａにも増すため、変位発生部２０を有する構成よりもモールド樹脂８の充填密度を高めることができる。 Further, as shown in FIGS. 7 and 8 and described above, the displacement generator 20 may have its inner end 22 aligned with the inner peripheral surface 7a of the through hole 7 (for the sake of explanation, the displacement generator 20-2). ). Even when such a configuration is adopted, at least the same effects as described above can be obtained.
In such a displacement generator 20-2, the displaceable portion 2e of the insulating substrate 2 below the chip component 3 has a smaller thickness than that of the displacement generator 20, so that the displacement is further facilitated. It becomes. Therefore, the degree of freedom of flow of the filler 81 under the chip component 3 is further increased and also increased in the vertical direction, that is, the plate thickness direction 2a of the insulating substrate 2, so Can be increased.

上述したような、絶縁基板２の変位発生部２０、２０−２を形成するために、絶縁基板２は、図９に示すように、例えば２層以上の基板、つまり第１層基板２−１、及び第２層基板２−２を有することが望ましい。このような２層基板で構成することで、例えば図１に示すような変位発生部２０では、第１層基板２−１に変位発生部２０を形成して、第２層基板２−２では変位発生部２０を有しない単なる平坦な基板とし、これらを重ねることで、変位発生部２０を有する絶縁基板２を容易に作製することができる。   In order to form the displacement generating portions 20 and 20-2 of the insulating substrate 2 as described above, the insulating substrate 2 is, for example, a substrate having two or more layers, that is, a first layer substrate 2-1, as shown in FIG. And a second layer substrate 2-2. By configuring with such a two-layer substrate, for example, in the displacement generation unit 20 as shown in FIG. 1, the displacement generation unit 20 is formed on the first layer substrate 2-1, and in the second layer substrate 2-2, The insulating substrate 2 having the displacement generation unit 20 can be easily manufactured by simply forming a flat substrate having no displacement generation unit 20 and stacking them.

尚、本実施の形態では、封止方法をトランスファー方式で説明したが、これに限定するものではなく例えばコンプレッション方式でも良く、さらに射出成型などの熱可塑性樹脂を用いる場合など静水圧などの圧力を印加可能な方式であれば、同様の効果を得ることができる。   In this embodiment, the sealing method has been described by the transfer method. However, the present invention is not limited to this. For example, a compression method may be used, and pressure such as hydrostatic pressure may be applied when a thermoplastic resin such as injection molding is used. The same effect can be obtained if the method can be applied.

１ 半導体装置、２ 絶縁基板、２ａ 板厚方向、２ｂ 注入方向、２ｃ 実装面、
３ チップ部品、３Ａ 封止体、３Ｂ 端子、３Ｃ 側面、７ 貫通穴、
７ａ 内周面、 ８ モールド樹脂、１０ モールド金型、１１ 可動ピン、
２０，２０−２ 変位発生部、２１ 外側端、２２ 内側端、３１ 隙間、
８１ フィラー。 DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Insulating substrate, 2a Thickness direction, 2b Injection | pouring direction, 2c Mounting surface,
3 chip parts, 3A sealing body, 3B terminal, 3C side surface, 7 through hole,
7a inner peripheral surface, 8 mold resin, 10 mold die, 11 movable pin,
20, 20-2 Displacement generating part, 21 outer end, 22 inner end, 31 gap,
81 filler.

Claims (4)

封止体及び端子を有する電子部品と、
上記電子部品の上記端子を接合して当該電子部品を実装する絶縁基板で、実装された電子部品に対応した位置に当該絶縁基板を貫通する貫通穴を形成した絶縁基板と、
フィラーを含有し、上記電子部品を実装した絶縁基板を封止する封止樹脂とを備えた半導体装置であって、
上記絶縁基板は、凹形状の変位発生部をさらに有し、この変位発生部は、上記電子部品を実装する上記絶縁基板の実装面で上記貫通穴の周縁部に形成されることを特徴とする半導体装置。 An electronic component having a sealing body and a terminal;
An insulating substrate that joins the terminals of the electronic component and mounts the electronic component, and an insulating substrate that has a through hole that penetrates the insulating substrate at a position corresponding to the mounted electronic component;
A semiconductor device comprising a filler and a sealing resin for sealing an insulating substrate on which the electronic component is mounted,
The insulating substrate further includes a concave-shaped displacement generating portion, and the displacement generating portion is formed on a peripheral portion of the through hole on a mounting surface of the insulating substrate on which the electronic component is mounted. Semiconductor device. 上記封止樹脂の上記フィラーは、上記実装面と電子部品の上記封止体との隙間と同等の粒径を有する、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the filler of the sealing resin has a particle size equivalent to a gap between the mounting surface and the sealing body of the electronic component. 上記変位発生部の深さは、上記電子部品の封止体の厚みよりも大きい、請求項１又は２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a depth of the displacement generation portion is larger than a thickness of the sealing body of the electronic component. 上記絶縁基板の延在方向において、上記変位発生部は、上記貫通穴の外側で上記電子部品の封止体側面よりも外側に位置する外側端と、内側端とを有し、この内側端は、上記外側端と上記貫通穴との間に位置する、又は上記貫通穴の内周面である、請求項１から３のいずれか１項に記載の半導体装置。   In the extending direction of the insulating substrate, the displacement generating part has an outer end located outside the through hole and outside the sealing member side surface of the electronic component, and an inner end. 4. The semiconductor device according to claim 1, which is located between the outer end and the through hole or is an inner peripheral surface of the through hole. 5.
JP2013076650A 2013-04-02 2013-04-02 Semiconductor device Active JP6012531B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013076650A JP6012531B2 (en) 2013-04-02 2013-04-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013076650A JP6012531B2 (en) 2013-04-02 2013-04-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2014203871A JP2014203871A (en) 2014-10-27
JP6012531B2 true JP6012531B2 (en) 2016-10-25

Family

ID=52354072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013076650A Active JP6012531B2 (en) 2013-04-02 2013-04-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JP6012531B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6634316B2 (en) * 2016-03-04 2020-01-22 日立オートモティブシステムズ株式会社 Resin-sealed in-vehicle controller

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3565724B2 (en) * 1998-10-06 2004-09-15 沖電気工業株式会社 Flip chip type semiconductor package and resin injection method in the device
JP2000294692A (en) * 1999-04-06 2000-10-20 Hitachi Ltd Resin-sealing type electronic device and manufacture of the same, ignition coil for internal combustion engine using the same device
JP4319759B2 (en) * 2000-03-21 2009-08-26 アピックヤマダ株式会社 Resin sealing device and resin sealing method
JP2002270638A (en) * 2001-03-06 2002-09-20 Nec Corp Semiconductor device, resin-sealing method and resin- sealing apparatus
JP2009049218A (en) * 2007-08-21 2009-03-05 Nec Electronics Corp Semiconductor device, and manufacturing method of semiconductor device
JP5589836B2 (en) * 2008-03-26 2014-09-17 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP2010153497A (en) * 2008-12-24 2010-07-08 Shinko Electric Ind Co Ltd Molding method and molding apparatus
JP2011176036A (en) * 2010-02-23 2011-09-08 Fujitsu Semiconductor Ltd Substrate for semiconductor device, and the semiconductor device

Also Published As

Publication number Publication date
JP2014203871A (en) 2014-10-27

Similar Documents

Publication Publication Date Title
US9087924B2 (en) Semiconductor device with resin mold
JP5563917B2 (en) Circuit device and manufacturing method thereof
JP6469660B2 (en) Manufacturing method of semiconductor device
CN107078127B (en) Power semiconductor device and method for manufacturing the same
JP2013055150A (en) Semiconductor device and manufacturing method thereof
JP4254527B2 (en) Semiconductor device
US8481367B2 (en) Method of manufacturing circuit device
KR102004785B1 (en) Power Semi-Conductor package and Method of Manufacturing for the same
TWI486105B (en) A package structure and the method to fabricate thereof
CN102800601B (en) For applying the laminate packaging technique of moulding compound
CN103650135A (en) Expanded semiconductor chip and semiconductor device
JP6667401B2 (en) Method for manufacturing power semiconductor device
JP6012531B2 (en) Semiconductor device
JP6391430B2 (en) Electronic control device and manufacturing method thereof
JP6141072B2 (en) Manufacturing method of semiconductor device
JP6347323B2 (en) Semiconductor device
JP7090716B2 (en) Semiconductor equipment
JP5308107B2 (en) Circuit device manufacturing method
JP2006086337A (en) Resin-sealed electronic device and manufacturing method thereof
JP5607447B2 (en) Circuit equipment
WO2015174198A1 (en) Semiconductor device and manufacturing method therefor
JP2014116366A (en) Semiconductor device and manufacturing method of the same
CN116705721A (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
WO2013061603A1 (en) Circuit device manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151015

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160812

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160823

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160920

R150 Certificate of patent or registration of utility model

Ref document number: 6012531

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250