JP5581798B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device that performs a planarization step by a chemical mechanical polishing (hereinafter simply referred to as CMP) method.

  Conventionally, a base wiring is provided on a substrate and an interlayer insulating film covering the base wiring is provided. A via hole for exposing the base wiring is formed in the interlayer insulating film, and the base wiring and the electrical wiring are formed in the via hole. Semiconductor devices in which conductive members to be connected are embedded are known.

  Such a semiconductor device is manufactured, for example, as follows (see, for example, Patent Document 1). That is, first, a base wiring is formed on a substrate and an interlayer insulating film covering the base wiring is disposed. Subsequently, after a via hole is formed in the interlayer insulating film, a conductive member is disposed in the via hole and on the interlayer insulating film by a CVD (Chemical Vapor Deposition) method or the like. Thereafter, the interlayer insulating film is planarized by removing the conductive member deposited on the interlayer insulating film by CMP.

  In the CMP method, for example, the polishing surface may be irradiated with light and reflected light from the polishing surface may be detected, and the planarization process of the interlayer insulating film may be completed based on the change over time in the intensity of the detected reflected light. Are known. Specifically, the reflectivity differs between the conductive member and the interlayer insulating film, and when the polishing surface changes from the conductive member to the interlayer insulating film, the reflection intensity changes. Has ended.

JP-A-8-8218

  However, such a method for manufacturing a semiconductor device has the following problems. That is, as the planarization process proceeds, the polished surface changes to a conductive member, a state where the conductive member partially remains on the interlayer insulating film, and the interlayer insulating film. At this time, the reflection intensity does not change clearly when the polished surface changes from the state in which the conductive member partially remains on the interlayer insulating film to the state of only the interlayer insulating film, but gradually changes. It will be. That is, in such a semiconductor device manufacturing method, it is difficult to clearly determine the end point of the planarization step, and when the polishing is insufficient, the conductive member remains on the interlayer insulating film. There's a problem.

  In view of the above-described points, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing the conductive member from remaining on an interlayer insulating film when performing a planarization process by a CMP method. .

In order to achieve the above object, according to the first aspect of the present invention, the step of forming the base step (2a to 2f) on the substrate (1) and the step of the base step (2a to 2f) on the substrate (1) are covered. After the step of forming the interlayer insulating film (3) and the step of forming the interlayer insulating film (3), a film (7) having a lower viscosity than the interlayer insulating film (3) is disposed on the interlayer insulating film (3). A step, a step of disposing an end point detection material (5) on the interlayer insulating film (3) formed on the low-viscosity film (7), an interlayer insulating film (3) covering the base step (2a to 2f ) , Forming a via hole (4) that exposes the underlying step (2a to 2f) in the low-viscosity film (7) and the interlayer insulating film (3) formed on the low-viscosity film (7); 4) disposing the conductive member (6) on the interlayer insulating film (3) formed on the inner and low-viscosity film (7); The interlayer insulating film (3) formed on the low-viscosity film (7) while removing the conductive member (6) on the interlayer insulating film (3) formed on the low-viscosity film (7) by CMP. In the step of disposing the end point detection material (5), the end point detection material (5) having a lower reflectance than the interlayer insulating film (3) is used, and the conductive member (6) In the step of disposing, a conductive member (6) having a higher reflectance than the interlayer insulating film (3) is used, and in the step of flattening, the polishing surface is irradiated with light and reflected light from the polishing surface is detected. The CMP method is terminated after the reflection intensity of the detected reflected light decreases and increases.

  In such a method of manufacturing a semiconductor device, an interlayer insulating film (3), an end point detection material (5), and a conductive member (6) are sequentially laminated on a substrate (1). In addition, a material having a lower reflectance than the interlayer insulating film (3) is used as the end point detection material (5), and a material having a higher reflectance than the interlayer insulating film (3) is used as the conductive member (6). That is, the reflectance is made lower in the order of the conductive member (6), the interlayer insulating film (3), and the end point detection material (5). For this reason, as the planarization process proceeds, the reflection intensity decreases and then increases. That is, when the polishing surface is the end point detection material (5), the reflection intensity is the smallest, and after that, the polishing surface is partially left on the interlayer insulating film (3). When the state is reached, the reflection intensity increases. Therefore, the conductive member (6) can be prevented from remaining on the interlayer insulating film (3) by ending the planarization step after the reflection intensity decreases and increases.

For example, as in the invention described in claim 2, using the conductive material as the end point detection material (5), the step of arranging the end point detection material (5) is performed after the step of forming the via hole (4), The end point detection material (5) can be disposed on the interlayer insulating film (3) formed on the via hole (4) and the low viscosity film (7) .

Further, as in the third aspect of the invention, the step of using the insulating material as the end point detection material (5) and disposing the end point detection material (5) is performed before the step of forming the via hole (4). In the step of forming the via hole (4), the interlayer insulating film (3) covering the base step (2a to 2f ) , the low-viscosity film (7), and the low-viscosity film (7) are formed on the interlayer insulating film. In addition, a via hole (4) that exposes the base step (2a to 2f) can be formed in the end point detection material (5).

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure which shows the cross-sectional structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device in 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. It is a figure which shows the relationship between the time of a planarization process, and reflection intensity. It is sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device in 3rd Embodiment of this invention. It is a figure which shows the cross-sectional structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device in 4th Embodiment of this invention. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 6. It is a figure which shows the cross-sectional structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device in other embodiment of this invention.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment.

  As shown in FIG. 1, the semiconductor device of this embodiment includes a base wiring 2a corresponding to a base step of the present invention on one surface of a semiconductor substrate 1 such as silicon, and an interlayer covering the base wiring 2a. An insulating film 3 is provided. The base wiring 2a is made of, for example, Al, and the interlayer insulating film 3 is made of, for example, a silicon oxide film, BPSG (Boron-doped Phosphorus-Silicate Glass), PSG (Phosphorus-Silicate Glass), BSG (Boron-Bond). doped Silicate Glass) or the like.

  A via hole 4 is formed in the interlayer insulating film 3 to expose the underlying wiring 2a. The via hole 4 is provided with an end point detection material 5 made of a conductive material on the wall surface, and a conductive member 6 that is electrically connected to the underlying wiring 2a. That is, in the present embodiment, the conductive member 6 is electrically connected to the base wiring 2 a via the end point detection material 5.

  The end point detection material 5 is used to detect the end point of the flattening process, and will be described later. A material having a lower reflectance than the interlayer insulating film 3 such as Ti, TiN, TaN or the like is used. . The conductive member 6 is made of a material having a higher reflectance than the interlayer insulating film 3 such as tungsten or copper.

  Next, a method for manufacturing such a semiconductor device will be described. FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device in this embodiment.

  As shown in FIG. 2A, first, the base wiring 2 a is formed on one surface of the semiconductor substrate 1. The underlying wiring 2a is not particularly limited, and is formed, for example, by arranging a conductive film on one surface of the semiconductor substrate 1 by a CVD method or sputtering, and then patterning the conductive film by photolithography or the like. . Thereafter, as shown in FIG. 2B, an interlayer insulating film 3 covering the base wiring 2a is formed on one surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method or the like. At this time, a step is formed on the surface of the interlayer insulating film 3 between a portion located on the underlying wiring 2a and a portion not on the underlying wiring 2a, and a portion located on the underlying wiring 2a is not on the underlying wiring 2a. It becomes a convex shape with respect to the part. Subsequently, as shown in FIG. 2C, the interlayer insulating film 3 is etched to form a via hole 4 that exposes the underlying wiring 2a.

  Next, as shown in FIG. 2D, the end point detection material 5 is disposed on the wall surface of the via hole 4 and the interlayer insulating film 3 by CVD or sputtering. Subsequently, as shown in FIG. 2E, a conductive member 6 is disposed in the via hole 4 and on the interlayer insulating film 3 by a CVD method, sputtering, or the like.

  Thereafter, as shown in FIG. 2F, a planarization step of planarizing the interlayer insulating film 3 while removing the end point detection material 5 and the conductive member 6 deposited on the interlayer insulating film 3 by CMP. I do. Specifically, the flattening step is performed until the polished surface is irradiated with light and the reflected light from the polished surface is detected, and the reflected intensity of the detected reflected light is decreased and increased.

  FIG. 3 is a diagram showing the relationship between the planarization process time (polishing time) and the reflection intensity. As shown in FIG. 3, when the planarization process proceeds, the polished surface is in the conductive member 6, the conductive member 6 partially remains on the end point detection material 5, the end point detection material 5, and the interlayer insulating film 3. The state in which the end point detection material 5 partially remains on the interlayer insulating film 3 is changed in this order. Since the reflection intensity decreases in the order of the conductive member 6, the interlayer insulating film 3, and the end point detection material 5, when the planarization process proceeds, the reflection intensity increases after decreasing. That is, when the polished surface is the end point detection material 5, the reflection intensity is the smallest, and then the end surface detection material 5 partially remains on the interlayer insulating film 3. The reflection intensity will increase. In other words, the conductive member 6 can be prevented from remaining on the interlayer insulating film 3 by ending the planarization process after the reflection intensity decreases and increases.

  More preferably, the planarization step is terminated when the reflection intensity decreases and increases and then becomes substantially constant. Thereby, the semiconductor device in a state where the end point detection material 5 is also removed from the interlayer insulating film 3 can be manufactured, and FIG. 2F shows the semiconductor device in this state.

  As described above, in the semiconductor device of this embodiment, the interlayer insulating film 3, the end point detection material 5, and the conductive member 6 are sequentially stacked on the semiconductor substrate 1, and the reflectance is the conductive member 6 and the interlayer insulating film 3. The end point detection material 5 is lower in this order. In the planarization step, the polishing surface is in a state where the conductive member 6 is partially left on the conductive member 6 and the end point detection material 5, and the end point detection material 5 is partially on the end point detection material 5 and the interlayer insulating film 3. In this case, the remaining state and the interlayer insulating film 3 are changed in this order, so that the reflection intensity of the reflected light from the polished surface decreases and increases. For this reason, if the planarization process is terminated after the reflection intensity of the reflected light decreases and increases, it is possible to suppress the conductive member 6 from remaining on the interlayer insulating film 3.

(Second Embodiment)
A second embodiment of the present invention will be described. The manufacturing method of the semiconductor device according to the present embodiment uses an insulating material as the end point detection material 5 with respect to the first embodiment, and is otherwise the same as the first embodiment. Omitted. FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device in this embodiment.

  First, in the present embodiment, as shown in FIGS. 4A and 4B, after performing the same steps as in FIGS. 2A and 2B, as shown in FIG. 4C. In addition, an insulating material such as SiN is disposed on the interlayer insulating film 3 as the end point detecting material 5. Thereafter, as shown in FIG. 4D, via holes 4 are formed in the interlayer insulating film 3 and the end point detection material 5.

  Subsequently, as shown in FIGS. 4E and 4F, the same process as in FIGS. 2E and 2F is performed, and the conductive member 6 is formed in the via hole 4 and on the interlayer insulating film 3. Then, the interlayer insulating film 3 is planarized while removing the conductive member 6 by CMP. Even in such a method of manufacturing a semiconductor device, since the end point detection material 5 is disposed on the interlayer insulating film 3, the same effect as in the first embodiment can be obtained.

(Third embodiment)
A third embodiment of the present invention will be described. The semiconductor device manufacturing method of this embodiment is a method in which a film having a viscosity lower than that of the interlayer insulating film 3 is disposed between the end point detection material 5 and the interlayer insulating film 3 with respect to the second embodiment. Since this is the same as that of the second embodiment, description thereof is omitted here. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device in the present embodiment.

  First, in the present embodiment, as shown in FIGS. 5A and 5B, after performing the same steps as in FIGS. 4A and 4B, as shown in FIG. 5C. Further, an SOG film 7 is disposed on the interlayer insulating film 3 as a film having a lower viscosity than the interlayer insulating film 3 to reduce the step on the surface of the interlayer insulating film 3. Specifically, by disposing the low-viscosity SOG film 7 on the interlayer insulating film 3, the SOG film 7 flows into a portion of the surface of the interlayer insulating film 3 that is not on the underlying wiring 2 a, and the interlayer insulating film 3. Reduce the surface level difference. Subsequently, as illustrated in FIG. 5D, the interlayer insulating film 3 is disposed again on the SOG film 7, and the end point detection material 5 is disposed on the interlayer insulating film 3.

  Thereafter, as shown in FIGS. 5E to 5G, the same process as in FIGS. 4D to 4F is performed to form the via hole 4 in the interlayer insulating film 3 and the end point detection material 5. After disposing the conductive member 6 in the via hole 4 and on the interlayer insulating film 3, the interlayer insulating film 3 is planarized while removing the conductive member 6 by CMP. Even in such a method of manufacturing a semiconductor device, since the end point detection material 5 is disposed on the interlayer insulating film 3, the same effect as in the second embodiment can be obtained.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The manufacturing method of the semiconductor device according to the present embodiment is different from the second embodiment in that the base level difference is changed, and the others are the same as those of the second embodiment, and thus the description thereof is omitted here. FIG. 6 is a diagram showing a cross-sectional configuration of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment.

  As shown in FIG. 6, in this embodiment, a capacitor is configured by providing first and second electrodes 2 b and 2 c as base steps on one surface of a semiconductor substrate 1, and the capacitor is an interlayer insulating film. 3 is covered. The first and second electrodes 2b and 2c are electrically connected to the conductive member 6 disposed in the via hole 4 formed in the interlayer insulating film 3, respectively.

  Next, a method for manufacturing such a semiconductor device will be described. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. First, as shown in FIG. 7A, a first electrode 2 b constituting one electrode of a capacitor is formed on one surface of a semiconductor substrate 1. Then, as shown in FIG. 7B, a first interlayer insulating film 3a covering the first electrode 2b is formed, and as shown in FIG. 7C, the first interlayer insulating film 3a is formed by CMP. Flatten the surface.

  Subsequently, as shown in FIG. 7D, a second electrode 2c constituting the other electrode of the capacitor is formed on the planarized first interlayer insulating film 3a. Thereafter, as shown in FIG. 7E, a second interlayer insulating film 3b covering the second electrode 2c is formed, and the end point detection material 5 is disposed on the second interlayer insulating film 3b. Then, as shown in FIG. 7 (f), via holes 4 are formed in the first and second interlayer insulating films 3 a and 3 b and the end point detection material 5 to expose the first and second electrodes 2 b and 2 c, respectively.

  Next, as shown in FIGS. 7 (g) and (h), the same process as in FIGS. 4 (e) and (f) is performed, and a conductive member is formed in the via hole 4 and on the second interlayer insulating film 3b. 6 and the second interlayer insulating film 3b is flattened while removing the conductive member 6 by CMP. Even in the case where the base step is the first and second electrodes 2b and 2c as in the method of manufacturing the semiconductor device, the polishing surface is irradiated with light in the planarization step, and from the polishing surface. By detecting the reflected light and ending the flattening step after the reflection intensity of the reflected light decreases and increases, the same effect as in the second embodiment can be obtained.

(Other embodiments)
In the first to third embodiments, the case where the base step is the base wiring 2a will be described as an example, and in the fourth embodiment, the base step is the first and second electrodes 2b and 2c. However, the base level difference is not limited to this. FIG. 8 is a diagram illustrating a cross-sectional configuration of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to another embodiment.

  The semiconductor device shown in FIG. 8A includes a base wiring 2a on one surface of the semiconductor substrate 1 and a first interlayer insulating film 3a covering the base wiring 2a. On the first interlayer insulating film 3a, the first and second base electrodes 2d and 2e as the base step and the resistor 2f that electrically connects the first and second base electrodes 2d and 2e are provided. In addition, a second interlayer insulating film 3b is provided to cover the first and second base electrodes 2d and 2e and the resistor 2f. Via holes 4 exposing the underlying wiring 2a are formed in the first and second interlayer insulating films 3a and 3b, and vias exposing the first and second underlying electrodes 2d and 2e are formed in the second interlayer insulating film 3b. A hole 4 is formed. In the via holes 4, conductive members 6 that are electrically connected to the base wiring 2 a and the first and second base electrodes 2 d and 2 e are disposed.

  The semiconductor device shown in FIG. 8B is provided with a base wiring 2a on one surface of the semiconductor substrate 1 and a first interlayer insulating film 3a covering the base wiring 2a. A resistor 2f as a base step is provided on the first interlayer insulating film 3a, and a second interlayer insulating film 3b covering the resistor 2f is provided. Via holes 4 that expose the underlying wiring 2a are formed in the first and second interlayer insulating films 3a and 3b, and via holes 4 that expose the resistor 2f are formed in the second interlayer insulating film 3b. ing. In these via holes 4, a conductive member 6 that is electrically connected to the underlying wiring 2a and the resistor 2f is disposed.

  The manufacturing method of the present invention can also be applied to the case where the first and second base electrodes 2d and 2e and the resistor 2f are provided as the base step as in these semiconductor devices. That is, in the method of manufacturing the semiconductor device as described above, the planarization process is performed after the conductive member 6 is disposed on the second interlayer insulating film 3b, as in the above embodiments. For this reason, the conductive member 6 is disposed after the end point detection material 5 is disposed on the second interlayer insulating film 3b, and the planarization process is terminated after the reflection intensity is decreased and increased, thereby the second interlayer insulating film. It is suppressed that the conductive member 6 remains on 3b. 8 is a view when an insulating material is used as the end point detection material 5 as in the second to fourth embodiments, and the end point detection material 5 is not arranged on the wall surface of the via hole 4. It has become.

  In the third and fourth embodiments, the end point detection material 5 is described as an example using an insulating material. However, the end point detection material 5 may be a conductive material. For example, in the third embodiment, the end point detection material 5 is not disposed in the step of FIG. 5D, and the end point is formed on the wall surface of the via hole 4 and the interlayer insulating film 3 after the step of FIG. The detection material 5 can be arranged. In the fourth embodiment, the end point detection material 5 is not disposed in the step of FIG. 7E, and the end point is formed on the wall surface of the via hole 4 and the interlayer insulating film 3 after the step of FIG. The detection material 5 can be arranged.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2a Base wiring 3 Interlayer insulation film 4 Via hole 5 End point detection material 6 Conductive member

Claims (3)

The substrate (1) includes a base step (2a to 2f) and an interlayer insulating film (3) covering the base step (2a to 2f). The base step (2a to 2f) is provided on the interlayer insulating film (3). ) Is exposed, and the via hole (4) is embedded with a conductive member (6) electrically connected to the base step (2a to 2f). In the method
Forming the base step (2a to 2f) on the substrate (1);
Forming the interlayer insulating film (3) covering the base step (2a to 2f) on the substrate (1);
After the step of forming the interlayer insulating film (3), disposing a film (7) having a viscosity lower than that of the interlayer insulating film (3) on the interlayer insulating film (3);
Forming the interlayer insulating film (3) again on the low viscosity film (7);
Disposing an end point detection material (5) on the interlayer insulating film (3) formed on the low viscosity film (7);
The interlayer insulating film (3) covering the underlying step ( 2a to 2f), the low-viscosity film (7), and the underlying insulating step (3) formed on the low-viscosity film (7) Forming the via hole (4) exposing (2a-2f);
Disposing the conductive member (6) on the interlayer insulating film (3) formed in the via hole (4) and on the low viscosity film (7);
Formed on the low-viscosity film (7 ) by removing the conductive member (6) on the interlayer insulating film (3) formed on the low-viscosity film (7) by chemical mechanical polishing . Flattening the interlayer insulating film (3),
In the step of arranging the end point detection material (5), the end point detection material (5) having a lower reflectance than the interlayer insulating film (3) is used.
In the step of disposing the conductive member (6), the conductive member (6) having a higher reflectance than the interlayer insulating film (3) is used.
In the step of flattening, the polishing surface is irradiated with light and the reflected light from the polishing surface is detected, and the chemical mechanical polishing method is terminated after the reflected intensity of the detected reflected light decreases and increases. A method of manufacturing a semiconductor device. Using a conductive material as the end point detection material (5),
The step of placing the end point detection material (5) is performed after the step of forming the via hole (4), and the interlayer insulation formed on the via hole (4) and the low viscosity film (7) film. The method for manufacturing a semiconductor device according to claim 1, wherein the end point detection material is disposed on the film. Using an insulating material as the end point detection material (5),
The step of arranging the end point detection material (5) is performed before the step of forming the via hole (4),
In the step of forming the via hole (4), the via hole (4) is formed on the interlayer insulating film (3) , the low-viscosity film (7), and the low-viscosity film (7) covering the base step ( 2a to 2f) . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the via hole (4) that exposes the base step (2 a to 2 f) is formed in the interlayer insulating film and the end point detection material (5). 3. .

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