JP5565893B2 - DC power supply - Google Patents

Description

  The present invention relates to a high-current DC power supply device particularly suitable for use for surface treatment such as electroplating.

  In recent years, DC power supplies for surface treatment such as plating and alumite rectify the supplied commercial AC power, convert the output to high-frequency rectangular AC using an inverter, and convert this rectangular AC to a predetermined voltage. In addition, a system called an inverter system, a switching system, a DC-DC converter system, or the like, which is rectified to obtain a direct current, has come to be used. These systems have the advantage of good output waveforms, and the use of high-frequency transformers reduces the size of the transformer, which has the advantage of making the entire DC power supply compact and lightweight. There is a tendency.

  In general, it is necessary to measure or control the DC output current with high accuracy, not only for surface treatment, but in the past, it was common to connect a shunt to the DC output side to detect the current. It was. However, the shunt has a large loss and is expensive if it has a large current such as several thousand amperes or more. This causes a problem that the efficiency of the DC power supply device is reduced and the cost is high. In addition, the detection voltage is as weak as 60 mV, for example, and is susceptible to noise. Further, since a large current shunt is large and needs to be cooled, a high frequency transformer is used. As a result, there is a problem that the advantage that the DC power supply device becomes small and light is lost. In order to solve such a problem, for example, a method that does not use a shunt for current detection as shown in Patent Document 1 has been proposed.

  The DC power supply device disclosed in Patent Document 1 is a rectifier that obtains DC from a commercial frequency AC power supply, an inverter that receives the output of the rectifier and outputs a square wave AC of a predetermined frequency, and controls the output of the inverter Control device, a transformer for converting the output voltage of the inverter, and a rectifier for rectifying the secondary output of the transformer, and an output signal of a current measuring device for measuring the output current of the inverter by the control device is input. In the DC power supply device for controlling the output current of the rectifier by controlling the waveform width of the square wave, the control device performs absolute rectification by full-wave rectifying the output signal of the current measuring device as its input signal. Absolute value circuit that obtains a value signal, pulse generation that outputs a pulse signal at the intermediate point between the rising point and falling point of the ON command signal of the inverter A sample / hold circuit that samples and holds the output signal of the absolute value circuit using the pulse signal output from the pulse generator as a sample signal, and the output signal of the sample / hold circuit is proportional to the load current. It is made to do.

  In this configuration, the output signal of the current measuring instrument is sampled and held at the rise and fall times of the inverter on-command signal, that is, at the midpoint of the on-period of the inverter semiconductor switch. It is shown in FIG. However, this figure does not accurately represent the actual situation in that the commutation period of the diode that rectifies the secondary output of the transformer is not shown, and the waveform of each part is actually shown in FIG. It will be like that. In FIG. 2, A is the primary voltage of the transformer, B is the primary current of the transformer, C is the secondary voltage of the transformer, D is the DC output voltage, and E is the DC output current. During the commutation of the diode, the primary current of the transformer gradually increases and decreases during that period, and during this period, a short circuit period is caused by both diodes, so the DC output voltage is also zero volts.

  When the commutation period ends, a period in which the primary current of the transformer and the DC output current are in proportion is continued until the semiconductor switch of the inverter is turned off, during which the primary current of the transformer gradually increases linearly. Therefore, if the primary current of the transformer is detected and sampled and held in the middle of the period in which the primary current of the transformer and the DC output current are proportional, a measurement signal proportional to the DC output current can be obtained. Become. On the other hand, in Patent Document 1, the primary current of the transformer is sampled and held at an intermediate point of the ON period of the semiconductor switch of the inverter, and the measured current value and the actual value are shifted because the sample and hold point is shifted. There is a problem that a difference occurs between the current values.

In order to solve this problem, a method of correcting by shifting the time point of sample hold by providing a delay time or the like can be considered. However, especially in a low-voltage, high-current DC power supply device for surface treatment, the commutation period is long, and the length of the commutation period changes when the AC input voltage fluctuates. It also changes when the DC output voltage and current change due to changing settings or changing the load. Corresponding to such a change in commutation time, it is practically impossible to correct the sample-holding time by appropriately shifting, and the DC current cannot be accurately measured with the one of Patent Document 1.
Japanese Patent Laid-Open No. 5-38158

  The present invention has been made in order to solve the above problems and to provide a DC power supply device capable of measuring a DC output current with high accuracy without using a shunt by measuring a primary current of a transformer. It is.

  The invention of claim 1 made to solve the above problem includes a first rectifier circuit for rectifying a commercial power supply, a single-phase inverter for converting the output of the first rectifier circuit into an alternating current, In a DC power supply device comprising a transformer for stepping down the output and a second rectifier circuit for rectifying the secondary output of the transformer, a current transformer for detecting the primary current of the transformer, and a current by the current transformer The average value of the absolute value of the output of one set or two sets of sample hold means and one set of two sample hold means for sampling and holding the detection signal is calculated and stored. One of the average value storage means and the sample-and-hold means set in the above set at the end of commutation of the second rectifier circuit is at the turn-off time when the semiconductor switch constituting the inverter is turned off. A command signal generating means for giving a sample command signal to the other of the sample and hold means in combination, and giving a storage command signal to the average value storage means while the semiconductor switch constituting the inverter is off. And the absolute value of the output signal of the average value storage means is a signal proportional to the DC output current of the DC power supply.

  Here, the command signal generating means gives a sample hold command signal to one and the other of the sample hold means at the end of commutation and the turn-off time during a half cycle of one polarity of alternating current output by the inverter. Suppose that a storage command signal is given to the average value storage means at the time of OFF during the same half cycle, or a sample hold that is paired at the time of turn OFF during the half cycle of one polarity of alternating current output by the inverter One of the means is provided with a sample hold command signal and a storage command signal respectively for the other of the sample hold means and the average value storage means at the end of commutation and the off time during the subsequent half cycle. Or at the end of commutation during a half cycle of one polarity of alternating current output by the inverter A sample hold command signal and a storage command signal are given to one of the sample hold means and the other of the sample hold means and the average value storage means at the turn-off time and the off-time time during the subsequent half cycle, respectively. These are the inventions of claims 2 to 4, respectively.

  In addition, the command signal generating means is averaged at the time when the same half cycle is off to one and the other of the sample hold means that are paired at the commutation end time and turn-off time during each half cycle of the alternating current output by the inverter. According to the invention of claim 5, the sample storage command signal and the storage command signal are respectively given to the value storage means, and the command signal generation means is provided during a half cycle of one polarity of the alternating current output by the inverter. One of the sample hold means in one set at the turn-off time, an inverter in the other of the sample hold means and the average value storage means in the commutation end time and the off time during the subsequent half cycle Of the sample-and-hold means of the other set at the time of turn-off during the half cycle of the other polarity of the alternating current output by On the other hand, a sample hold command signal and a storage command signal are given to the other of the sample hold means and the average value storage means in the other set at the end of commutation and the off time during the subsequent half cycle, respectively. This is the invention of claim 6.

  Further, the command signal generating means is connected to one of the sample and hold means in one set at the end of commutation during a half cycle of one polarity of the alternating current output from the inverter, and the turn-off time during the subsequent half cycle The sample-holding means in the other set and the average value storage means at the time of the off-state and the other set of sample-holding means at the end of commutation during the half cycle of the other polarity of the alternating current output by the inverter On the other hand, the sample hold command signal and the storage command signal are given to the other of the sample hold means and the average value storage means in the other set at the turn-off time and the off-time time during the subsequent half cycle, respectively. This is the invention of claim 7.

In the invention of claims 1 on more than 7, it can be provided with detection means for detecting the end of the commutation period of the second rectifier circuit by detecting the rise of the output voltage of the second rectifier circuit.

  According to the first aspect of the present invention, the current detection signal for detecting the primary current of the transformer is sampled at each time point when the commutation end of the second rectifier circuit ends and when the semiconductor switch constituting the inverter is turned off. A set of two sample hold means for holding is provided, and an average value of the sampled and held values is stored as a current measurement signal proportional to the DC output current of the DC power supply device. What is read is the current value at the start point and end point of the period in which the primary current and the DC output current are proportional to each other. Therefore, the average value is proportional to the DC output current, and there is an advantage that an accurate measurement result can be obtained.

Further, in the inventions according to claims 5 to 7, since the sample-and-hold is measured every half cycle of the alternating current output from the inverter, the current measurement signal has good followability, and when used for feedback control, the response is accelerated. There are advantages that can be made. In the third, fourth, sixth and seventh aspects of the present invention, the current value at one time point is read in two consecutive half cycles having different polarities, and the average is calculated. Even if there is an imbalance between the negative side and the negative side, this will be canceled out, and even if the sample hold time varies slightly, it will be averaged, and an accurate current measurement value without fluctuation due to imbalance will be obtained the advantage can be there Ru.

Next, the best mode for carrying out the present invention will be specifically described with reference to the drawings.
FIG. 1 is a connection diagram of a main circuit showing the configuration of the present invention. A DC power source for converting AC power supplied from an AC input terminal 3 by a rectifier 1 and a capacitor 2 as a first rectifier circuit into DC power is shown. It is provided. The positive poles of the semiconductor switches 4a and 4b are connected to the positive pole of the DC power supply, and the negative poles of the semiconductor switches 4a and 4b are connected to the negative poles of the semiconductor switches 5a and 5b, respectively. The positive pole is connected. These semiconductor switches 4a, 4b, 5a and 5b constitute a single-phase inverter.

  The primary coil of the transformer 6 is connected between the connection point of the semiconductor switches 4a and 5a and the connection point of the semiconductor switches 4b and 5b, which are output terminals of the single-phase inverter, and the secondary coil of the transformer 6 A center tap is provided, and anodes of diodes 7a and 7b are respectively connected to both ends to constitute a second rectifier circuit. The cathodes of the diodes 7a and 7b are connected to the positive DC output terminal 8a, and the center tap of the transformer 6 is connected to the negative DC output terminal 8b. 9 is a current transformer which detects the current of the primary coil of the transformer 6.

  The current transformer 9 can be a general one in which a secondary coil is wound around a toroidal core, and the primary coil of the current transformer 9 has a wire passing through the primary coil of the transformer 6. However, it is preferable that the high-frequency characteristics are good. The current on the primary side of the transformer 6 detected by the current transformer 9 and the voltage of the DC output output to the DC output terminals 8a and 8b are connected so as to be input to the control device 10, respectively. The control device 10 includes a drive signal generation circuit that generates drive signals for the semiconductor switches 4a, 5b, 5a, and 5b, a DC output control circuit that controls the DC output, and the primary of the transformer 6 detected by the current transformer 9. And a current calculation circuit for calculating a DC output current from the current on the side.

  The drive signal generation circuit alternately supplies drive signals to the set of semiconductor switches 4a and 5b and the set of semiconductor switches 4b and 5a, and the DC output control circuit uses the semiconductor switches 4a and 5b and the semiconductor switches by PWM control or the like. The fact that the DC output is controlled by changing the duty of the on-time of 4b and 5a is the same as that of the conventional DC power supply device of such a system, and can have the same configuration as the conventional one. On the other hand, the current calculation circuit is characteristic of the present invention, and the principle, configuration, and operation will be described below.

  FIG. 2 shows the waveform of the main part of the DC power supply device of the present invention, where the horizontal axis represents the passage of time, A is the primary voltage of the transformer 6, B is the primary current of the transformer 6, and C is the transformer. The secondary voltage of the device 6, D is the DC output voltage, and E is the DC output current. The period from t1 to t3 is a period in which the semiconductor switches 4a and 5b are on, and the power supply voltage is applied to the primary coil of the transformer 6 during that period. From t1 to t2 is a commutation period in which the current flowing in the diode 7b is transferred to the diode 7a, and the secondary coil of the transformer 6 is short-circuited by the diode 7a and the diode 7b. No voltage appears on the coil. During this time, the primary current of the transformer 6 gradually increases.

  t2 is the commutation end point at the end of the commutation period, and is released from the short circuit by the diode 7a and the diode 7b, a voltage is generated in the secondary coil of the transformer 6, and is output to the DC output terminals 8a and 8b through the diode 7a. The The period from t2 to t3 is a period in which power is supplied from the primary side of the transformer 6 to the DC output. The primary current of the transformer 6 gradually increases linearly, and the primary current and DC output current of the transformer 6 during this period are Proportional relationship. t3 is a turn-off time when the semiconductor switches 4a and 5b are turned off, and from t3 to t4 is a commutation period in which the current flowing in the diode 7a is transferred to the diode 7b. At time t4, a current is flowing through both the diodes 7a and 7b.

Similarly, the period from t5 to t6 is a period in which the semiconductor switches 4b and 5a are on, and the power supply voltage is applied to the primary coil of the transformer 6 with a reverse polarity. From t5 to t6 is a commutation period in which the current flowing in the diode 7a is transferred to the diode 7b, no voltage appears in the secondary coil of the transformer 6, and the magnitude of the primary current of the reverse polarity of the transformer 6 is large. The gradual increase. t6 is the end of commutation, and a voltage having a reverse polarity is generated in the secondary coil of the transformer 6 and is output to the DC output terminals 8a and 8b through the diode 7b. The period from t6 to t7 is a period in which power is supplied from the primary side of the transformer 6 to the DC output. The magnitude of the primary current of the transformer 6 gradually increases linearly, and the magnitude of the primary current of the transformer 6 during this period. And the DC output current have a proportional relationship. t7 is a turn-off time of the semiconductor switch 4b, 5a is turned off, from t7 to t8 is a commutation period in which current flowing in the diode 7 b is gradually shifted to the diode 7 a. At time t8, the current flows through both the diodes 7a and 7b. Thereafter, such an operation is continuously repeated.

  The waveform of each part changes as described above, and after the commutation period between the diodes 7a and 7b ends, until the semiconductor switches 4a and 5b or the semiconductor switches 4b and 5a are turned off, that is, from t2 to t3 or t6. From t to t7, the magnitude of the primary current of the transformer 6 and the DC output current are in a proportional relationship. Therefore, the primary current of the transformer 6 is detected and sampled and held at an intermediate time tn1 or tn2 between t2 and t3 or between t6 and t7 where the magnitude of the primary current of the transformer 6 and the DC output current are in a proportional relationship. Then, a measurement signal whose absolute value is proportional to the DC output current can be obtained.

  Rather than using the method of detecting and holding the primary current of the transformer 6 at the time of tn1 or tn2, two sample-holding means are provided, and the transformer 6 at the time of t2 or t6 is provided in one sample-holding means. The primary current is detected and sampled and held, and the other sample and hold means detects and samples and holds the primary current of the transformer 6 at time t3 or t7, and the two sample and hold circuits individually sample and hold. By taking the average of the measured values, a measurement signal whose absolute value is proportional to the DC output current can be obtained in the same manner as when the primary current of the transformer 6 is detected and sampled and held at the time of tn1 or tn2. The invention of claim 1 is based on such a principle.

  FIG. 3 shows the relationship between the current of the primary coil of the transformer 6 and the sample-holding timing of the invention of claim 1, where t2 and t6 are the commutation end time and t3 is the turn-off time. , T7, the primary current of the transformer 6 is sampled and held. Since the magnitude of the primary current of the transformer 6 gradually increases linearly from the end of commutation between the diodes 7a and 7b to the time when the semiconductor switches 4a and 5b are turned off, the current value reaches the end of commutation. In comparison, the turn-off time is larger, and here, the commutation end time is represented as LS as the low current side sample hold point, and the turn off time is represented as HS as the high current side sample hold point.

  FIG. 4 shows the configuration of the current calculation circuit provided in the DC power supply device of the invention of claim 2, and the inputs of the first sample hold circuit 11a and the second sample hold circuit 11b which are two sample hold means. The terminal is connected to the current signal input terminal 12a. 12b is a current signal input terminal on the return side, and the secondary coil of the current transformer 9 is connected to the current signal input terminals 12a and 12b. Reference numeral 13 denotes a terminal resistance of the current transformer 9. The output terminals of the two sample and hold circuits 11a and 11b are connected to the input terminal of the average value circuit 14, respectively.

  The output terminal of the average value circuit 14 is connected to the input terminal of the third sample and hold circuit 15, and the output terminal of the third sample and hold circuit 15 is connected to the current signal output terminal 16. The average value circuit 14 and the third sample and hold circuit 15 constitute an average value storage means. The first sample hold circuit 11a is provided with a sample hold command signal for sample holding the current signal input to the current signal input terminal 12a at time t2, and the second sample hold circuit 11b at time t3. It is. The third sample and hold circuit 15 is provided with a sample and hold command signal for sampling and holding the output of the average value circuit 14 at an appropriate time th1 between t4 and t5, and this is supplied to the average value storage means. This is a memory command signal.

FIG. 5 shows an example of a detection circuit for detecting the end of the commutation period. The invention of claim 8 is provided with such a detection circuit, and the input terminal of the comparator 17 is connected via the waveform shaping circuit 18. Are connected to the voltage signal input terminal 19a. The waveform shaping circuit 18 is constituted by a constant current diode and a constant voltage diode, for example, and limits an input signal whose amplitude changes to a constant amplitude. Reference numeral 19b denotes a voltage signal input terminal on the return side, and the voltage signal input terminals 19a and 19b are connected to the DC output terminals 8a and 8b, respectively. The output terminal of the comparator 17 is connected to the detection signal output terminal 20, and outputs a detection signal when the input voltage of the voltage signal input terminal 19a exceeds a threshold value.

  As shown in FIG. 2D, the DC output voltage rises when the commutation period ends, and becomes zero when the semiconductor switch is turned off. As a result, the detection signal output from the comparator 17 rises at the time t2 and falls at the time t3. Therefore, it is possible to detect the time when the semiconductor switch is turned off, and the timing signals at t2 and t3. Can be obtained. Similarly, the detection signal output from the comparator 17 rises at time t6 and falls at time t7. However, t2 and t6, t3 are obtained by logical operation with the drive signals of the semiconductor switches 4a, 4b, 5a, and 5b. And t7 timing signals can be separated. The timing signal for th1 can be generated based on the drive signals for the semiconductor switches 4a, 4b, 5a, and 5b.

  In the second aspect of the present invention, as shown in FIG. 3B, the first sample hold circuit 11a at the time LS1 corresponding to t2 and the second sample hold circuit 11b at the time HS1 corresponding to t3, respectively. The current value at the time is read, and the average value is read into the third sample and hold circuit 15 at the time HD1 corresponding to th1. As a result, a current measurement signal proportional to the DC output current is obtained at the current signal output terminal 16. In this example, reading is performed at times t2, t3, and th1 during the positive half cycle, but reading is performed at times t6, t7, and th2 during the negative half cycle. It is also possible. In that case, those time points become LS1, HS1, and HD1, respectively, and the obtained current measurement signal has a reverse polarity.

  FIG. 6 shows an example of the configuration of the current calculation circuit provided in the DC power supply device according to the third and fourth aspects of the invention. The basic part is the same as that shown in FIG. The code | symbol is attached | subjected. The difference is that a polarity inversion circuit 21 is provided between the output terminal of the second sample-and-hold circuit 11 b and the input terminal of the average value circuit 14. In the case of the invention of claim 3, the sample and hold command signal is given to the first sample and hold circuit 11a at the time t3 and the second sample and hold circuit 11b at the time t6. Thus, a sample hold command signal is given to the third sample hold circuit 15. In the case of the invention of claim 4, the sample hold command signal is given to the first sample hold circuit 11a at the time t2 and to the second sample hold circuit 11b at the time t7, respectively. At this time, a sample hold command signal is given to the third sample hold circuit 15.

  FIG. 3B shows the relationship between the primary current of the transformer 6 and the sample and hold timing in the case of the invention of claim 3. The sample and hold circuits 11a and 11b are respectively connected at the time of HS1 and LS1. The current value at the time is read, and the average value is read into the sample hold circuit 15 at the time of HD1. As a result, a current measurement signal is obtained at the current signal output terminal 16. FIG. 3C shows the relationship between the primary current of the transformer 6 and the timing of sample and hold in the case of the invention of claim 4. The sample and hold circuits 11a and 11b are connected at the time of LS1 and HS1. The current value at that time is read, and the average value is read into the sample and hold circuit 15 at the time HD1. As a result, a current measurement signal is obtained at the current signal output terminal 16. At this time, the current value read into the sample hold circuit 11b is opposite in polarity to the current value read into the sample hold circuit 11a, but is input to the average value circuit 14 with the polarity inverted by the polarity inversion circuit 21. The average value circuit 14 outputs an average value of absolute values of the outputs of the sample hold circuits 11a and 11b.

  In the third aspect of the invention, reading is performed at time t3, t6, and th2. However, it is also possible to read data at time t7 and time t2, th1 of the next cycle. In that case, those time points become HS1, LS1, and HD1, respectively, and the obtained current measurement signal has a reverse polarity. In the invention of claim 4, the reading is made at the time t2, t7, th2. However, the reading can be made at the time t6, t3, th1 of the next cycle. In that case, those time points become HS1, LS1, and HD1, respectively, and the obtained current measurement signal has a reverse polarity.

  FIG. 7 shows an example of the configuration of the current calculation circuit provided in the DC power supply device according to the fifth aspect of the invention. Basically, it is the same as that shown in FIG. It is attached. The difference is that a polarity reversing circuit 22 is provided and the input terminal of the polarity reversing circuit 22 is connected to the output terminal of the average value circuit 14, and the third sample and hold circuit 15 is assumed to have two input terminals. That is, the terminal is connected to the output terminal of the average value circuit 14 and the other input terminal is connected to the output terminal of the polarity inversion circuit 22.

  A sample hold command signal is given to the first sample hold circuit 11a at time t2 and t6, and a sample hold command signal is given to the second sample hold circuit 11b at time t3 and t7. The third sample and hold circuit 15 is supplied with a sample and hold command signal for reading the output of the average value circuit 14 at the time point th1 and the output of the polarity inversion circuit 22 at the time point th2. FIG. 3D shows the relationship between the primary current of the transformer 6 and the sample and hold timing in the case of the invention of claim 5, and the sample and hold circuits 11a and 11b are respectively connected at the time of LS1 and HS1. Reading the current value at the time point and reading the output of the average value circuit 14 into the sample hold circuit 15 at the time point HD1 is the same as in the configuration shown in FIG. Thereafter, the current values at that time are read into the sample hold circuits 11a and 11b at the time LS2 and HS2, respectively, and the output of the polarity inversion circuit 22 is read into the sample hold circuit 15 at the time HD2. As a result, a current measurement signal is obtained at the current signal output terminal 16.

  The current value read at the time of LS2 and HS2 is opposite in polarity to the current value read at the time of LS1 and HS1, and the average value is also opposite in polarity, but the polarity is inverted by the polarity inversion circuit 22 at the time of HD2. Since the average value is read, the polarity of the output signal of the current signal output terminal 16 is not reversed. Needless to say, the current calculation circuit according to the fifth aspect of the present invention can be configured by providing an absolute value circuit on the input side or output side of the third sample hold circuit 15 having the configuration shown in FIG.

  FIG. 8 shows an example of the configuration of the current calculation circuit provided in the DC power supply device according to the sixth and seventh aspects of the present invention. Two current detection signals input to the current signal input terminals 12a and 12b are sampled and held. Two sets of sample and hold circuits are provided. Reference numerals 23a and 23b denote first and second sample and hold circuits in one set, and reference numerals 24a and 24b denote third and fourth sample and hold circuits in the other set. The input terminals of the polarity inversion circuits 25 and 26 are connected to the output terminals of the second and third sample and hold circuits 23b and 24a, respectively. The output terminals of the first sample and hold circuit 23a and the polarity inversion circuit 25 are the first ones. The input terminal of one average value circuit 27 and the output terminals of the third sample hold circuit 24b and the polarity inversion circuit 26 are connected to the input terminal of the second average value circuit 28, respectively.

  Reference numeral 29 denotes a fifth sample-and-hold circuit having two input terminals, and the output terminal is connected to the current signal output terminal 16. One input terminal of the fifth sample hold circuit 29 is connected to the output terminal of the first average value circuit 27, and the other input terminal is connected to the output terminal of the second average value circuit 28. In the case of the invention of claim 6, the first sample hold circuit 23a is supplied with a sample hold command signal at time t3, and the second sample hold circuit 23b is supplied with a sample hold command signal at time t6. A sample hold command signal is supplied to the sample hold circuit 24a at time t7, and a sample hold command signal is supplied to the fourth sample hold circuit 24b at time t2 of the next cycle. The fifth sample hold circuit 29 is supplied with a sample hold command signal for sample-holding the output of the first average value circuit 27 at the time point th2 and the output of the second average value circuit 28 at the time point th1. It is.

  FIG. 3E shows the relationship between the primary current of the transformer 6 and the sample and hold timing in the case of the invention of claim 6. The sample and hold circuits 23a and 23b are connected to the sample and hold circuits 23a and 23b at the time of HS1 and LS1, respectively. The current value at the time is read, and the output of the average value circuit 27 is read into the sample hold circuit 29 at the time of HD1. Also, the current value at that time is read into the sample hold circuits 24a and 24b at the time HS2 and the time LS2 of the next cycle, and the output of the average value circuit 28 is read into the sample hold circuit 29 at the time HD2. As a result, a current measurement signal is obtained at the current signal output terminal 16.

  In the invention of claim 7, the first sample hold circuit 23a is supplied with a sample hold command signal at time t2, and the second sample hold circuit 23b is supplied with a sample hold command signal at time t7. The third sample hold circuit 24a is supplied with a sample hold command signal at time t6, and the fourth sample hold circuit 24b is supplied with a sample hold command signal at time t3 of the next cycle. The fifth sample hold circuit 29 is supplied with a sample hold command signal for sample-holding the output of the first average value circuit 27 at the time point th1 and the output of the second average value circuit 28 at the time point th2. It is.

  FIG. 3 shows the relationship between the primary current of the transformer 6 and the timing of sample and hold in the case of the invention of claim 7. The sample and hold circuits 23a and 23b are respectively connected at the time of LS1 and HS1. The current value at the time is read, and the output of the average value circuit 27 is read into the sample hold circuit 29 at the time of HD1. Further, the current value at that time is read into the sample hold circuits 24a and 24b at the time LS2 and the time HS2 of the next cycle, and the output of the average value circuit 28 is read into the sample hold circuit 29 at the time HD2. As a result, a current measurement signal is obtained at the current signal output terminal 16.

  As described above, the current measurement signal is output from the sample hold circuit 15 or 29 to the current signal output terminal 16. In the case of the invention of claims 2 to 4, every half cycle of one polarity of the alternating current output from the inverter to the sample and hold circuit 15, and in the case of the invention of claim 5, the inverter to the sample and hold circuit 15 In the case of the inventions of claims 6 and 7, the sample and hold command signal is given to the sample and hold circuit 29 every half cycle of the alternating current output by the inverter. The current measurement signal changes every cycle in the second to fourth inventions, and every half cycle in the fifth to seventh inventions. Therefore, the invention according to claims 5 to 7 has an advantage that the followability of the current measurement signal is good, and when used for feedback control, the response can be quickened.

  In the inventions of claims 2 and 5, the time point of LS and the time point of HS are set during the same half cycle. In the inventions of claims 3, 4 and 6, and 7, the time point of LS and the time point of HS are set. Is set across two consecutive half cycles of different polarities. For example, in the case of the invention of claim 3, LS1 is a positive half cycle, HS1 is a negative half cycle, and so on. Ideally, the primary current of the transformer 6 is symmetrical between the positive half cycle and the negative half cycle. Even if the current values at two points in time are read in the same half cycle, the primary current is divided into two consecutive half cycles. Even if the current value at each time point is read, the obtained current measurement signal should have the same value. However, the primary current of the transformer 6 may be unbalanced between the positive side and the negative side. In the invention of claim 5, since the current values at two points in time are read during the same half cycle, the measured value on the positive side and the measured value on the negative side are alternately output as a current measurement signal, If there is an imbalance, the current measurement signal will show fluctuations in the same period as the AC output from the inverter.

  When feedback control is performed using the current measurement signal, if there is a fluctuation in the same cycle as the AC output from the inverter in the current measurement signal, the error amplifier amplifies this and further increases the unbalance, The device 6 is demagnetized. This phenomenon is particularly noticeable when the error amplifier has a gain up to a high frequency. In order to avoid this in the invention of claim 5, it is only necessary to take the average value of the measured value on the positive side and the measured value on the negative side. However, in this case, the current measurement signal changes every cycle. Thus, the advantage of reading the current value at two points in each half cycle is halved.

  In the third, fourth, sixth, and seventh inventions, the current value at one time point is read in two consecutive half cycles having different polarities, and the average value circuit, for example, in the case of the third invention, LS1 The average value of the current value during the positive half cycle read in step S1 and the current value during the negative half cycle read in step HS1 is calculated. As a result, if there is an imbalance between the positive side and the negative side of the primary current of the transformer 6, it is canceled out. In addition, although the LS and HS sample and hold times may vary somewhat, the sample and hold can be averaged and a more accurate current measurement value can be obtained.

  In the above-described embodiment, the average value storage means for calculating the average value of the absolute values of the outputs of the two sets of sample hold means and storing the average value is the average value circuit 14 and the third sample hold means. Although the circuit 15 or the average value circuits 27 and 28 and the fifth sample hold circuit 29 are configured, the output of the sample hold means is converted into digital data by an AD converter, and the calculation and storage of the average value are processed digitally. It is also possible. If analog data is required as a current measurement value, analog data can be obtained by appropriately providing a DA converter.

It is a wiring diagram of the main circuit which shows the structure of this invention. It is a wave form diagram of the principal part at the time of operation. It is a figure which shows the current waveform of a transformer, and the timing of sample hold. It is a connection diagram of a current calculation circuit used in the invention of claim 2. It is a connection diagram which shows the structure of the detection circuit which detects the end of a commutation period. It is a connection diagram of a current calculation circuit used in the inventions of claims 3 and 4. FIG. 9 is a connection diagram of a current calculation circuit used in the invention of claim 5. It is a connection diagram of a current calculation circuit used in the inventions of claims 6 and 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Rectifier 2 Capacitor 3 AC input terminal 4a, 4b, 5a, 5b Semiconductor switch 6 Transformer 7a, 7b Diode 8a, 8b DC output terminal 9 Current transformer 10 Controller 11a, 11b Sample hold circuit 12a, 12b Current signal input terminal 13 Terminating resistor 14 Average value circuit 15 Sample hold circuit 16 Current signal output terminal 17 Comparator 18 Waveform shaping circuit 19a, 19b Voltage signal input terminal 20 Detection signal output terminal 21, 22 Polarity inversion circuit 23a, 23b, 24a, 24b Sample hold circuit 25, 26 Polarity inversion circuit 27, 28 Average value circuit 29 Sample hold circuit

Claims (8)

  A first rectifier circuit that rectifies commercial power, a single-phase inverter that converts the output of the first rectifier circuit into alternating current, a transformer that steps down the output of the inverter, and a secondary output of the transformer is rectified In a DC power supply device composed of a second rectifier circuit, one set or two sets of current transformers for detecting a primary current of a transformer and two sets of two for sampling and holding a current detection signal by the current transformer Commutation of the second rectifier circuit is completed, the average value storage means for calculating the average value of the absolute values of the outputs of the sample hold means, the set of two sample hold means, respectively, and storing the average value. At the end of commutation, one of the sample-and-hold means set as described above is connected to the other of the sample-and-hold means set at the turn-off time when the semiconductor switch constituting the inverter is turned off. And a command signal generating means for providing a storage command signal to the average value storage means at a time point when the semiconductor switch constituting the inverter is turned off is provided, and an output signal of the average value storage means is provided. A DC power supply device characterized in that an absolute value is a signal proportional to a DC output current of the DC power supply device.   A sample hold command signal is given to one and the other of the sample hold means which are set at the commutation end time and the turn off time during a half cycle of one polarity of alternating current output by the inverter. 2. The DC power supply apparatus according to claim 1, wherein a storage command signal is given to the average value storage means at the time of OFF during the cycle.   The command signal generating means is connected to one of the sample and hold means paired at the turn-off time during the half cycle of one polarity of the alternating current output by the inverter, and the commutation end time and the off-time time during the subsequent half cycle 2. The DC power supply apparatus according to claim 1, wherein a sample hold command signal and a storage command signal are respectively given to the other of the sample hold means and the average value storage means.   The command signal generating means is connected to one of the sample and hold means at the end of commutation during a half cycle of one polarity of the alternating current output by the inverter, and the turn-off time and the off-time time during the subsequent half cycle 2. The DC power supply apparatus according to claim 1, wherein a sample hold command signal and a storage command signal are respectively given to the other of the sample hold means and the average value storage means.   The command signal generation means is stored in one of the sample hold means at the end of commutation and the turn-off time during each half cycle of the alternating current output from the inverter, and the average value is stored at the time when the same half cycle is off. 2. The DC power supply device according to claim 1, wherein a sample hold command signal and a storage command signal are respectively given to the means.   When the command signal generating means is turned off during the half cycle of one polarity of the alternating current output from the inverter, one of the sample hold means is set to one end of the commutation end time during the subsequent half cycle and off. In the other of the sample hold means and the average value storage means in one set at the time point, in one of the sample hold means in the other set at the turn-off time point during the half cycle of the other polarity of the alternating current output by the inverter, The sample hold command signal and the storage command signal are given to the other of the sample hold means and the average value storage means in the other set at the end of commutation and the off time during the subsequent half cycle, respectively. 2. The DC power supply device according to claim 1, wherein   The command signal generating means is turned off and turned off during the subsequent half cycle at one of the sample and hold means in one set at the end of commutation during one half cycle of one polarity of alternating current output by the inverter. One of the sample and hold means in one set at the time and one of the sample and hold means in the other set at the end of the commutation between half cycles of the other polarity of the alternating current output by the inverter In addition, the sample hold command signal and the storage command signal are respectively given to the other of the sample hold means and the average value storage means in the other set at the turn-off time and the off-time time during the subsequent half cycle. 2. The DC power supply device according to claim 1, wherein Claims 1, characterized in that a detection means for detecting the end of the commutation period of the second rectifier circuit by detecting the rise of the output voltage of the second rectifier circuit according to 7 or of DC power supply.

Images