JP2014075871A - Ac-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AC-DC converter capable of suppressing the loss incident to rectification operation regardless of the load, by switching the control between synchronous rectification system and asynchronous rectification system depending on the load.SOLUTION: An AC-DC converter 1a includes a synchronous rectification control circuit 2a having a bridge control circuit 3a and a synchronous rectification mask circuit 4a, and a rectification bridge 6. The synchronous rectification mask circuit 4a determines the differential voltage VD1 between a rectification voltage VO1 when the AC voltages VAC1 and VAC2 go above the rectification voltage VO1, and a terminal voltage VC1, and outputs a high level mask signal MA1 when the differential voltage VD1 is equal to or larger than a reference voltage VREF1. Since the PMOS transistors TP1-TP4 of the rectification bridge 6 are maintained in off state by the high level mask signal MA1, the bridge control circuit 3a does not perform synchronous rectification, thereby suppressing gate drive loss incident to rectification operation.

Description

  The present invention relates to an AC-DC converter that converts an AC power supply into a DC power supply, and more particularly to an AC-DC converter using a diode bridge.

  As an AC-DC converter for converting an AC power source into a DC power source, a converter using a full-wave rectifier circuit using a diode bridge is known. As a rectification method in the diode bridge, there are an asynchronous rectification method and a synchronous rectification method. In the asynchronous rectification method, an AC voltage is rectified using a diode to be converted into a DC voltage. On the other hand, the synchronous rectification method uses an active element such as a power MOS transistor instead of a diode. By controlling the on / off operation of these power MOS transistors at an appropriate timing, the AC voltage is rectified and converted into a DC voltage.

  In the asynchronous rectification method using a diode, a loss occurs because a forward voltage is generated between the terminals when a forward current flows through the diode. In the synchronous rectification method, by using a power MOS transistor having a sufficiently low on-resistance, a rectification operation can be performed with a current consumption smaller than a loss due to a diode.

  Conventionally, a rectification control device that can be used in combination with an asynchronous rectification method and a synchronous rectification method has been disclosed (for example, Patent Document 1). A sampling circuit that samples any one of the AC voltage input to the rectifier bridge, the rectified voltage output from the rectifier bridge, and the reference voltage of the rectifier bridge, and the sampling voltage sampled by the sampling circuit and the AC voltage are compared. The rectification control device includes a first comparator and controls on / off of at least one of the plurality of synchronous rectification elements included in the rectification bridge based on an output signal of the first comparator.

JP 2010-74949 A

  In the synchronous rectification method, the loss due to the on-resistance can be made smaller than the loss due to the diode. However, it is necessary to discharge the gate capacitor in order to drive the power MOS transistor. When the load becomes larger, the loss due to the on-resistance of the power MOS transistor and the gate drive loss may exceed the loss due to the diode. In such a case, it is lower to adopt the asynchronous rectification method. Rectification can be performed with loss.

  The technique described in Patent Document 1 is a technique for accurately controlling the on / off timing of a MOSFET that is a synchronous rectifier even when an input AC power supply is affected by noise and is not an accurate sine wave. Is merely disclosed. There is no description regarding control when the loss due to the on-resistance of the MOSFET and the gate drive loss exceed the loss due to the diode.

  In other words, the background art described in Patent Document 1 does not provide any solution for the problem that the load applied to the power supply becomes larger and the loss increases in the synchronous rectification method compared to the asynchronous rectification method. .

  The present invention has been made in view of such a situation. By switching the control between the synchronous rectification method and the asynchronous rectification method according to the load, the loss due to the on-resistance of the power MOS transistor and the gate drive. An object of the present invention is to provide an AC-DC converter capable of suppressing a gate drive loss related to a rectifying operation in a load region where the loss exceeds a loss due to a diode.

  In order to solve the above problems, the AC-DC converter disclosed in the present application includes a rectification bridge unit, a first comparator, a second comparator, and a synchronous rectification mask unit. The rectifying bridge unit includes a synchronous rectifying element that connects between the terminals of the diode, a first node that outputs a rectified voltage, a second node that applies a reference voltage, and third and fourth that apply an AC voltage. Node. The first comparator detects a voltage difference between the first node and the third node, and when the third node is at a higher voltage than the first node, the synchronous rectifier element between the first and third nodes, And outputs a first control signal for conducting the synchronous rectifier between the second and fourth nodes. The second comparator detects a voltage difference between the first node and the fourth node, and when the fourth node is at a higher voltage than the first node, the synchronous rectifier element between the first and fourth nodes, And outputs a second control signal for conducting the synchronous rectifier between the second and third nodes. The synchronous rectification mask unit determines a load state connected to the first node in accordance with at least one of the first and second control signals, and when it is determined that the load exceeds a specified level, the next load Until the determination of the state, the first and second control signals are masked.

  In the AC-DC converter having a rectifier bridge including the synchronous rectifier provided by the technology disclosed in the present application, the load applied to the power supply becomes a heavy load, and the loss due to the on-resistance and the gate drive loss applied to the synchronous rectifier are due to the diode. If the loss exceeds the loss, the loss can be reduced by prohibiting the synchronous rectification operation. In addition to the low loss operation from the low load to the medium load by the synchronous rectification operation, the loss reduction at the heavy load reduces the loss to the rectifier bridge. It becomes possible to reduce the gate drive loss.

Block diagram of the AC-DC converter device 1a according to the first embodiment. Timing chart for explaining the operation of the AC-DC converter device 1a according to the first embodiment. Block diagram of an AC-DC converter device 1b according to the second embodiment Timing chart for explaining the operation of the AC-DC converter device 1b according to the second embodiment. Block diagram of an AC-DC converter device 1c according to the third embodiment Timing chart for explaining the operation of the AC-DC converter device 1c according to the third embodiment.

  FIG. 1 is a block diagram of an AC-DC converter device 1a according to the first embodiment. The AC-DC converter device 1a includes a synchronous rectification control circuit 2a, an AC power supply 5, a rectification bridge 6, a smoothing capacitor 7, a DC-DC converter 8, an inductor 9, and an output capacitor 10.

  The synchronous rectification control circuit 2a controls the on / off of PMOS transistors TP1 to TP4 (described later) connected in parallel to the respective diodes of the rectification bridge 6, thereby generating AC voltages VAC1 and VAC2 output from the AC power supply 5. When full-wave rectification is performed, whether to perform synchronous rectification operation is controlled. The AC voltage that is full-wave rectified via the rectifier bridge 6 is smoothed by the smoothing capacitor 7 to obtain a rectified voltage VO1. The rectified voltage VO1 is input to the DC-DC converter 8. The output terminal of the DC-DC converter 8 becomes an output terminal via an inductor 9. An output capacitor 10 is connected between the output terminal and the ground voltage, and an output voltage VO2 is output.

  The rectification bridge 6 is a full-wave rectification type diode bridge. PMOS transistors TP1 to TP4 are connected in parallel to each diode. In addition, the PMOS transistors TP1 to TP4 can be configured by IGBTs or the like.

  A rectified voltage VO1 subjected to full wave rectification is output from the node N1 of the rectifier bridge 6, and the node N2 is connected to the ground voltage. Further, the AC voltage VAC1 is input to the node N3 of the rectifier bridge 6, and the AC voltage VAC2 is input to the node N4. The voltage polarities of the AC voltage VAC1 and the AC voltage VAC2 are opposite to each other.

  The PMOS transistor TP1 is connected between the nodes N1 and N3, and the SW control signal S1a is input to the gate G1. The source is connected to the node N1, and the rectified voltage VO1 is output. The drain is connected to the node N3 and the AC voltage VAC1 is input. A rectifier diode D1 having a forward direction from the node N3 to the node N1 is connected in parallel between the source and the drain.

  The PMOS transistor TP2 is connected between the nodes N1 and N4, and the SW control signal S2a is input to the gate G2. The source is connected to the node N1, and the rectified voltage VO1 is output. The drain is connected to the node N4 and the AC voltage VAC2 is input. A rectifier diode D2 having a forward direction from the node N4 to the node N1 is connected in parallel between the source and the drain.

  The PMOS transistor TP3 is connected between the nodes N2 and N4, and the SW control signal S1a is input to the gate G3. The source is connected to the node N4 and the AC voltage VAC2 is input. The drain is connected to the node N2 and the ground voltage is input. A rectifier diode D3 having a forward direction from the node N2 to the node N4 is connected in parallel between the source and the drain.

  The PMOS transistor TP4 is connected between the nodes N2 and N3, and the SW control signal S2a is input to the gate G4. The source is connected to the node N3 and the AC voltage VAC1 is input. The drain is connected to the node N2 and the ground voltage is input. A rectifier diode D4 having a forward direction from the node N2 to the node N3 is connected in parallel between the source and the drain.

  The synchronous rectification control circuit 2a includes a bridge control circuit 3a and a synchronous rectification mask circuit 4a. The bridge control circuit 3a compares AC voltages VAC1 and VAC2 that are input voltages of the rectifier bridge 6 with a rectified voltage VO1 that is an output voltage by comparators 31a and 32a described later, and is connected between nodes of the rectifier bridge 6. Controls on / off of the PMOS transistors TP1 to TP4.

  The bridge control circuit 3a includes comparators 31a and 32a, switch control circuits 33a and 34a, and a trigger circuit 35a. The node N1 is connected to the inverting input terminal of the comparator 31a and the rectified voltage VO1 is input. The node N3 is connected to the non-inverting input terminal and the AC voltage VAC1 is input. The comparison signal SC1 is output from the output terminal. The comparator 31a detects that the AC voltage VAC1 is higher than the rectified voltage VO1 by comparing the voltage values of the AC voltage VAC1 and the rectified voltage VO1. During the period in which the AC voltage VAC1 exceeds the rectified voltage VO1, the comparison signal SC1 is at a high level (high potential power supply voltage).

  The node N1 is connected to the inverting input terminal of the comparator 32a and the rectified voltage VO1 is input. The node N4 is connected to the non-inverting input terminal, and the AC voltage VAC2 is input. The comparison signal SC2 is output from the output terminal. The comparator 32a detects that the AC voltage VAC2 is higher than the rectified voltage VO1 by comparing the voltage values of the AC voltage VAC2 and the rectified voltage VO1. The comparison signal SC2 becomes high level during the period in which the AC voltage VAC2 exceeds the rectified voltage VO1.

  An output terminal of the comparator 31a is connected to the first input terminal of the switch control circuit 33a and the comparison signal SC1 is input, and a mask signal MA1 described later is input to the second input terminal. The comparison signal SC1 is inputted after being logically inverted. The output terminal of the switch control circuit 33a is connected to the gate G1 of the PMOS transistor TP1 and the gate G3 of the PMOS transistor TP3, and the SW control signal S1a is output. When the mask signal MA1 is at a low level (low potential power supply voltage), the comparator 31a detects that the AC voltage VAC1 exceeds the rectified voltage VO1, and the SW control signal S1a is inverted to a low level when the comparison signal SC1 becomes a high level. To do. As a result, the PMOS transistors TP1 and TP3 are turned on. On the other hand, when the AC voltage VAC1 is detected to be lower than the rectified voltage VO1, and the comparison signal SC1 becomes low level, the level of the SW control signal S1a is inverted to high level. At this time, the PMOS transistors TP1 and TP3 are turned off. When the mask signal MA1 is at a high level, the SW control signal S1a is at a high level regardless of the logic level of the comparison signal SC1, and the PMOS transistors TP1 and TP3 are maintained in an off state.

  The output terminal of the comparator 32a is connected to the first input terminal of the switch control circuit 34a and the comparison signal SC2 is input, and the mask signal MA1 is input to the second input terminal. The comparison signal SC2 is inputted after being logically inverted. The output terminal of the switch control circuit 34a is connected to the gate G2 of the PMOS transistor TP2 and the gate G4 of the PMOS transistor TP4, and outputs the SW control signal S2a. When the mask signal MA1 is at the low level, the comparator 32a detects that the AC voltage VAC2 has exceeded the rectified voltage VO1, and when the comparison signal SC2 goes to the high level, the SW control signal S2a is inverted to the low level. As a result, the PMOS transistors TP2 and TP4 are turned on. On the other hand, when the AC voltage VAC2 is detected to be lower than the rectified voltage VO1, and the comparison signal SC2 becomes low level, the level of the SW control signal S2a is inverted to high level. At this time, the PMOS transistors TP2 and TP4 are turned off. When the mask signal MA1 is at a high level, the SW control signal S2a is at a high level regardless of the logic level of the comparison signal SC2, and the PMOS transistors TP2 and TP4 are maintained in an off state.

  The output terminal of the comparator 31a is connected to the first input terminal of the trigger circuit 35a and the comparison signal SC1 is input. The second input terminal is connected to the output terminal of the comparator 32a and receives the comparison signal SC2. A trigger signal ST is output from the output terminal of the trigger circuit 35a to the synchronous rectification mask circuit 4a. Since the trigger circuit 35a is an OR logic circuit, the trigger signal ST is at a low level when both the comparison signals SC1 and SC2 are at a low level, and when either one of the comparison signals SC1 and SC2 is at a high level, the trigger signal ST is High level. That is, the trigger signal ST is at a high level during a period in which the AC voltage VAC1 or the AC voltage VAC2 exceeds the voltage of the rectified voltage VO1.

  The synchronous rectification mask circuit 4a includes a sample hold circuit 41a, an operational amplifier 42a, a comparator 43a, and a D flip-flop (hereinafter referred to as D-FF) circuit 44a. A voltage difference between the rectified voltage VO1 when the trigger signal ST is inverted at a high level and the rectified voltage VO1 when the trigger signal ST is inverted at a low level is obtained. When the voltage difference is equal to or greater than a predetermined value, a high level mask signal MA1 is output. In this case, even when the AC voltages VAC1 and VAC2 exceed the rectified voltage VO1, the outputs of the SW control signals S1a and S2a are fixed at a high level. The PMOS transistors TP1 to TP4 are maintained in the off state, and synchronous rectification is not performed. On the other hand, when the voltage difference is equal to or smaller than the predetermined value, the mask signal MA1 is at the low level, and when the AC voltages VAC1 and VAC2 exceed the rectified voltage VO1, the low level SW control signal S1a or S2a is output. The PMOS transistors TP1 to TP4 are turned on to perform synchronous rectification.

  The sample hold circuit 41a includes a switch SW1 and a capacitor C1. The switch SW1 is connected between the node N1 and an inverting input terminal of an operational amplifier 42a described later. During the low level of the trigger signal ST, the switch SW1 is on. When the trigger signal ST is at a high level, the switch SW1 is turned off. One end of the capacitor C1 is connected to a node to which the switch SW1 and the inverting input terminal of the operational amplifier 42a are connected, and the other end is connected to the ground voltage. While the switch SW1 is on, the node N1 and one end of the capacitor C1 are connected. As a result, the capacitor C1 is charged with the rectified voltage VO1. On the other hand, the connection between the node N1 and one end of the capacitor C1 is disconnected during the OFF state of the switch SW1. As a result, the capacitor C1 holds the rectified voltage VO1 immediately before the switch SW1 is turned off. The terminal voltage VC1 at one end of the capacitor C1 becomes the rectified voltage VO1. Thereby, the rectified voltage VO1 immediately before either the PMOS transistor TP1 or the PMOS transistor TP2 is turned on is sampled and held. The minimum value of the rectified voltage VO1 subjected to full-wave rectification is held. As a result of the power consumed by the connected load, the power charged in the smoothing capacitor 7 is always consumed in the output voltage VO2 that is converted and output under the control of the DC-DC converter 8. This is because while the MOS transistors TP1 and TP2 are in the OFF state, no power is supplied to the smoothing capacitor 7 and the rectified voltage VO1 gradually decreases.

  The terminal voltage VC1 is input to the inverting input terminal of the operational amplifier 42a. The node N1 is connected to the non-inverting input terminal and the rectified voltage VO1 is input. The operational amplifier 42a outputs a voltage obtained by amplifying the voltage difference as a difference voltage VD1. As a result, the difference voltage between the rectified voltage VO1 and the lowest value of the rectified voltage VO1 held in the sample hold circuit 41a while the switch SW1 is in the off state, that is, during the period when the MOS transistor TP1 or TP2 is turned on is amplified. .

  The reference voltage VREF1 is input to the inverting input terminal of the comparator 43a, and the output terminal of the operational amplifier 42a is connected to the non-inverting input terminal to input the differential voltage VD1. The difference voltage VD1 becomes higher as the rectified voltage VO1 becomes higher than the terminal voltage VC1. When the difference voltage VD1 exceeds the reference voltage VREF1, the comparison signal SD1 that is the output signal of the comparator 43a is inverted from the low level to the high level.

  The output terminal of the comparator 43a is connected to the terminal D of the D-FF 44a, and the comparison signal SD1 is input. The trigger signal ST is logically inverted and input to the terminal CLK. A mask signal MA1 is output from the terminal Q. The D-FF 44a takes in the comparison signal SD1 and outputs it as a mask signal MA1 in response to the inversion of the trigger signal ST to the low level.

  FIG. 2 is a timing chart for explaining the operation of the AC-DC converter device 1a according to the first embodiment. In FIG. 2, the difference voltage (VAC1-VAC2) between the AC voltage VAC1 and the AC voltage VAC2, the rectified voltage VO1, the difference voltage (VAC1-VO1) between the AC voltage VAC1 and the rectified voltage VO1, the AC voltage VAC2 and the rectified voltage VO1 The operation waveforms of the differential voltage (VAC2-VO1), comparison signals SC1, SC2, trigger signal ST, differential voltage VD1, mask signal MA1, and SW control signals S1a, S2a are shown. In the timing chart, region Ia is a medium load region and region IIa is a heavy load region. In addition, in the differential voltage (VAC1-VO1) between the AC voltage VAC1 and the rectified voltage VO1, and in the differential voltage (VAC2-VO1) between the AC voltage VAC2 and the rectified voltage VO1, description of the negative voltage is omitted.

  First, the case where the load applied to the AC-DC converter device 1a is a medium load shown in the region Ia of FIG. 2 will be described. In this case, the comparison signal SC1 is at a high level during the period T1 in which the AC voltage VAC1 exceeds the rectified voltage VO1. Since the mask signal MA1 is at a low level at a medium load, the switch control circuit 33a outputs a SW control signal S1a at a low level. As a result, the PMOS transistors TP1 and TP3 of the rectifier bridge 6 are turned on. By turning on the PMOS transistors TP1 and TP3 during the period T1, the synchronous rectification operation by the rectification bridge 6 is performed on the alternating current flowing from the node N3 to the node N1 and from the node N2 to the node N4. Here, the mask signal MA1 is at the low level because the difference voltage VD1 between the rectified voltage VO1 and the terminal voltage VC1 does not exceed the reference voltage VREF1, and the comparison signal SD1 is maintained at the low level.

  Further, in the middle load, during the period in which the AC voltage VAC2 exceeds the rectified voltage VO1, the comparison signal SC2 becomes high level, and the switch control circuit 34a inverts the SW control signal S2a to low level, thereby The PMOS transistors TP2 and TP4 are turned on. Thus, in the period in which AC voltage VAC2 exceeds rectified voltage VO1, in the same manner as in period T1 in which AC voltage VAC1 exceeds rectified voltage VO1, the AC current flowing from node N4 to node N1 and from node N2 to node N3 A synchronous rectification operation is performed by the rectification bridge 6.

  A case where the load applied to the AC-DC converter device 1a is a heavy load shown in a region IIa in FIG. 2 will be described. When the AC voltage VAC1 exceeds the rectified voltage VO1 and the comparison signal SC1 is inverted to a high level (period T2), the trigger signal ST output from the trigger circuit 35a is inverted to a high level. In the sample hold circuit 41a, the rectified voltage VO1 is sampled in response to the trigger signal ST being inverted to a high level.

  As shown in FIG. 2, during the period of the voltage cycle F1 of the AC power supply 5, immediately before the comparison signals SC1 and SC2 are inverted to the high level is the timing when the rectified voltage VO1 becomes the lowest. This is because the electric power charged in the smoothing capacitor 7 is consumed by the load of the output voltage VO2 without supplementing the electric power to the smoothing capacitor 7. That is, the lowest rectified voltage VO1 is held in the sample hold circuit 41a as the terminal voltage VC1 during the period of the voltage cycle F1. In the heavy load, the power consumption at the output voltage VO2 is larger than that in the middle load, so that the voltage drop of the terminal voltage VC1 is larger while the MOS transistors TP1 and TP2 are in the off state. Accordingly, the difference voltage VD1 between the rectified voltage VO1 output from the operational amplifier 42a and the terminal voltage VC1 becomes larger than that of the medium load.

  Accordingly, when the region Ia, which is a medium load, is shifted to the region IIa, which is a heavy load, the period T2 in which the AC voltages VAC1, VAC2 exceed the rectified voltage VO1 is longer than the period T1 in the medium load, and the difference voltage VD1 is the reference voltage. Above VREF1.

  The period T3 is a period in which the difference voltage VD1 exceeds the reference voltage VREF1. This is a period from when the difference voltage VD1 exceeds the reference voltage VREF1 to when the comparison signals SC1 and SC2 are inverted to a low level and below the reference voltage VREF1. When the difference voltage VD1 exceeds the reference voltage VREF1, the comparison signal SD1 is inverted to a high level by the comparator 43a. The high-level comparison signal SD1 is determined by inversion of the low level of the trigger signal ST, is taken into the D-FF 44a, and is output as a high-level mask signal MA1.

  When the high level mask signal MA1 is input to the second input terminals of the switch control circuits 33a and 34a of the bridge control circuit 3a, the SW control signals S1a and S2a are high regardless of the logic levels of the comparison signals SC1 and SC2. Fixed to level. The mask signal MA1 has a logic level determined when the comparison signals SC1 and SC2 are inverted to a low level and the synchronous rectification operation is completed, and determines whether or not the synchronous rectification operation is possible in the next cycle. For example, synchronous rectification is performed in the period T2 in a cycle in which the AC voltage VAC1 is a positive voltage. The mask signal MA1 is inverted to a high level at the end of the period T2. The high-level mask signal MA1 suppresses synchronous rectification during the period when the AC voltage VAC2 which is the next cycle is a positive voltage (X in FIG. 2). Similarly, whether or not the synchronous rectification operation is possible in the next cycle is determined in each cycle.

  FIG. 3 is a block diagram of an AC-DC converter device 1b according to the second embodiment. The AC-DC converter device 1b includes a synchronous rectification control circuit 2b, an AC power supply 5, a rectification bridge 6, a smoothing capacitor 7, a DC-DC converter 8, an inductor 9, and an output capacitor 10.

  The rectifier bridge 6, the smoothing capacitor 7, the DC-DC converter 8, the inductor 9, and the output capacitor 10 have the same configuration and the same function as the AC-DC converter device 1a according to the first embodiment. Description of is omitted.

  The synchronous rectification control circuit 2b includes a bridge control circuit 3b and a synchronous rectification mask circuit 4b. Similarly to the bridge control circuit 3a, the bridge control circuit 3b compares the AC voltages VAC1 and VAC2 that are input voltages of the rectification bridge 6 with the rectification voltage VO1, and turns on / off the PMOS transistors TP1 to TP4 of the rectification bridge 6. Control.

  The bridge control circuit 3b includes comparators 31b and 32b and switch control circuits 33b and 34b. In the comparator 31b, similarly to the comparator 31a, the node N1 is connected to the inverting input terminal and the rectified voltage VO1 is input. The node N3 is connected to the non-inverting input terminal and the AC voltage VAC1 is input. The comparison signal SC1 is output from the output terminal. Since the operation of the comparator 31b is the same as that of the comparator 31a, a description thereof is omitted here.

  Similarly to the comparator 32a, the comparator 32b has the inverting input terminal connected to the node N1 and inputted with the rectified voltage VO1. The node N4 is connected to the non-inverting input terminal, and the AC voltage VAC2 is input. The comparison signal SC2 is output from the output terminal. Since the operation of the comparator 32b is the same as that of the comparator 32a, a description thereof is omitted here.

  Similarly to the switch control circuit 33a, the output terminal of the comparator 31b is connected to the first input terminal of the switch control circuit 33b to receive the comparison signal SC1, and the mask signal MA1 in the first embodiment is input to the second input terminal. Instead of this, a mask signal MA2 described later is input. The comparison signal SC1 is inputted after being logically inverted. The gate G1 of the PMOS transistor TP1 and the gate G3 of the PMOS transistor TP3 are connected to the output terminal of the switch control circuit 33b, and the SW control signal S1b is output. Since the operation of the switch control circuit 33b is the same as that of the switch control circuit 33a, description thereof is omitted here.

  Similarly to the switch control circuit 34a, the output terminal of the comparator 32b is connected to the first input terminal of the switch control circuit 34b and the comparison signal SC2 is input, and the mask signal MA1 in the first embodiment is input to the second input terminal. Instead, a mask signal MA2 is input. The comparison signal SC2 is inputted after being logically inverted. The gate G2 of the PMOS transistor TP2 and the gate G4 of the PMOS transistor TP4 are connected to the output terminal of the switch control circuit 34b, and the SW control signal S2b is output. Since the operation of the switch control circuit 34b is the same as that of the switch control circuit 34a, description thereof is omitted here.

  The synchronous rectification mask circuit 4b includes a counter circuit 41b, an operational amplifier 42b, a comparator 43b, an AND circuit 45b, a flip-flop (hereinafter referred to as FF) circuit 46b, and a D-FF circuit 44b. Each time the counter circuit 41b counts the number of high level inversions of the comparison signal SC1 four times, the counter circuit 41b detects the voltage difference between the rectified voltage VO1 and the AC voltage VAC1 when the comparison signal SC1 is inverted to a low level. When the value is equal to or greater than the predetermined value, a high level mask signal MA2 is output. The logic level of the mask signal MA2 is maintained until the counter circuit 41b counts the next count operation, that is, the number of high level inversions of the comparison signal SC1 four times. When the mask signal MA2 is set to the high level, the outputs of the SW control signals S1b and S2b are fixed to the high level even when the AC voltages VAC1 and VAC2 exceed the rectified voltage VO1. The PMOS transistors TP1 to TP4 are maintained in the off state, and synchronous rectification is not performed. On the other hand, when the mask signal MA2 is set to the low level, the low-level SW control signal S1b or S2b is output when the AC voltages VAC1 and VAC2 exceed the rectified voltage VO1. The PMOS transistors TP1 to TP4 are turned on to perform synchronous rectification.

  The counter circuit 41b includes D-FFs 47b and 48b, an inverter INV1, an XOR circuit XOR1, and an AND circuit 49b. The comparison signal SC1 is input and the gate signal GT is output. The count value CO is counted up in response to the high level inversion of the comparison signal SC1. The gate signal GT is inverted to the high level in response to the fourth inversion of the comparison signal SC1, and is inverted to the low level in response to the inversion of the low level.

  The comparison signal SC1 is input to the terminal CLK of the D-FF 47b. An output terminal of the inverter INV1 is connected to the terminal D. The terminal Q is connected to the input terminal of the inverter INV1, the input terminal of the XOR circuit XOR1, and the second input terminal of the AND circuit 49b. Each time the comparison signal SC1 is inverted to a high level by the inverter INV1, the output signal of the terminal Q of the D-FF 47b is logically inverted.

  The comparison signal SC1 is input to the terminal CLK of the D-FF 48b. An output terminal of the XOR circuit XOR1 is connected to the terminal D. The terminal Q is connected to the input terminal of the XOR circuit XOR1 and the third input terminal of the AND circuit 49b.

  The comparison signal SC1 is input to the first input terminal of the AND circuit 49b. The signals input to the second input terminal and the third input terminal of the AND circuit 49b are input after being logically inverted. A gate signal GT is output from the output terminal of the AND circuit 49b. When the counter circuit 41b is counted up and a high level is input to the first input terminal of the AND circuit 49b and a low level is input to the second and third input terminals, the gate signal GT is inverted to a high level.

  The counter circuit 41b sets the count value CO = 0 to the initial state, increments by 1 every time the comparison signal SC1 is inverted to the high level, counts up four times until the count value CO = 3, and then returns to the initial state. The count value returns to CO = 0. Thereafter, the count operation is repeated four times.

  The node N1 is connected to the inverting input terminal of the operational amplifier 42b and the rectified voltage VO1 is input. The node N3 is connected to the non-inverting input terminal and the AC voltage VAC1 is input. The operational amplifier 42b outputs a difference voltage VD2 obtained by amplifying the voltage difference between both input terminals.

  The reference voltage VREF2 is input to the inverting input terminal of the comparator 43b, and the output terminal of the operational amplifier 42b is connected to the non-inverting input terminal to input the differential voltage VD2. When the difference voltage VD2 exceeds the reference voltage VREF2, it is determined that the voltage value of the AC voltage VAC1 exceeding the rectified voltage VO1 exceeds the specified value, and the comparison signal SD2 output from the comparator 43b is inverted from the low level to the high level. .

  In the AND circuit 45b, the output terminal of the counter circuit 41b is connected to the first input terminal and the gate signal GT is input. The output terminal of the comparator 43b is connected to the second input terminal and the comparison signal SD2 is input. The output terminal of the AND circuit 45b is connected to the terminal S of the FF circuit 46b.

  The terminal S of the FF circuit 46b is a set terminal. A high level logic value is latched by a high level input. Terminal R is a reset terminal. A low level logic value is latched by a high level input. The comparison signal SC2 is input to the terminal R. A control signal SQ2 is output from the terminal Q. When it is determined that the voltage value in which the AC voltage VAC1 exceeds the rectified voltage VO1 exceeds the specified value and the comparison signal SD2 is inverted to the high level, and the high level gate signal GT is input, the FF circuit 46b is set to the high level. A level control signal SQ2 is output. In response to the comparison signal SC2 being inverted to the low level, the control signal SQ2 is reset to the low level.

  The terminal D of the D-FF circuit 44b is connected to the terminal Q of the FF circuit 46b and receives the control signal SQ2. The terminal CLK is connected to the output terminal of the counter circuit 41b and receives the gate signal GT. Mask signal MA2 is output from terminal Q. The D-FF circuit 44b takes in the control signal SQ2 and outputs it as a mask signal MA2 in response to the gate signal GT being inverted to a low level.

  FIG. 4 is a timing chart for explaining the operation of the AC-DC converter device 1b according to the second embodiment. In FIG. 4, the differential voltage (VAC1-VAC2) between the alternating voltage VAC1 and the alternating voltage VAC2, the rectified voltage VO1, the differential voltage (VAC1-VO1) between the alternating voltage VAC1 and the rectified voltage VO1, the alternating voltage VAC2 and the rectified voltage VO1 Of the differential voltage (VAC2-VO1), comparison signals SC1, SC2, differential voltage VD2, comparison signal SD2, count value CO, gate signal GT, control signal SQ2, mask signal MA2, and SW control signals S1b, S2b. It is shown. In the timing chart, the region Ib is a medium load region and the region IIb is a heavy load region. Similarly to FIG. 2, in the differential voltage (VAC1-VO1) between the AC voltage VAC1 and the rectified voltage VO1, and the differential voltage (VAC2-VO1) between the AC voltage VAC2 and the rectified voltage VO1, the description of the negative voltage is omitted. .

  When the load applied to the AC-DC converter device 1b is a medium load (region Ib), the mask signal MA2 is the same signal as the mask signal MA1 in the first embodiment, and is input to the bridge control circuit 3b. The mask signal MA2 is at a low level because the difference voltage VD2 between the AC voltage VAC1 and the rectified voltage VO1 does not exceed the reference voltage VREF2 at a medium load. For this reason, the comparison signal SD2 is maintained at a low level. The counter circuit 41b counts the number of high-level inversions of the comparison signal SC1 four times, the count value CO returns to 0 and the gate signal GT inverts to the high level, but the comparison signal SD2 is maintained at the low level, so FF This is because the circuit 46b is maintained at a low level. Here, since the operation of the bridge control circuit 3b is the same as that of the bridge control circuit 3a, the description thereof is omitted here. Since the mask signal MA2 is maintained at the low level, the SW control signals S1b and S2b are alternately at the low level, and the synchronous rectification operation is performed.

  When the load applied to the AC-DC converter device 1b is a heavy load (region IIb), the difference voltage VD2 corresponding to the voltage difference between the AC voltage VAC1 and the rectified voltage VO1 exceeds the reference voltage VREF2. As a result, the comparison signal SD2 is inverted to a high level.

  When the counter circuit 41b counts the number of high level inversions of the comparison signal SC1, the count value CO returns to 0, and the gate signal GT is inverted to the high level. At this time, since the differential voltage VD2 is at a high level, the FF circuit 47b is set, and a high-level mask signal MA2 is output via the D-FF circuit 44b.

  The high level state of the mask signal MA2 is maintained until the count value CO returns to 0 again, and the synchronous rectification operation is not performed regardless of the logical levels of the comparison signals SC1 and SC2 during this period.

  FIG. 5 is a block diagram of an AC-DC converter device 1c according to the third embodiment. The AC-DC converter device 1c includes a synchronous rectification control circuit 2c, an AC power supply 5, a rectification bridge 6, a smoothing capacitor 7, a DC-DC converter 8, an inductor 9, and an output capacitor 10.

  The rectifier bridge 6, the smoothing capacitor 7, the DC-DC converter 8, the inductor 9, and the output capacitor 10 have the same configuration and the same function as the AC-DC converter device 1a according to the first embodiment. Description of is omitted.

  The synchronous rectification control circuit 2c includes a bridge control circuit 3c and a synchronous rectification mask circuit 4c. Similarly to the bridge control circuits 3a and 3b, the bridge control circuit 3b compares the rectified voltage VO1 with the AC voltages VAC1 and VAC2 that are input voltages of the rectifier bridge 6, and turns on / off the PMOS transistors TP1 to TP4 of the rectifier bridge 6. Control off.

  The bridge control circuit 3c includes comparators 31c and 32c and switch control circuits 33c and 34c. In the comparator 31c, similarly to the comparators 31a and 31b, the node N1 is connected to the inverting input terminal and the rectified voltage VO1 is input. The node N3 is connected to the non-inverting input terminal and the AC voltage VAC1 is input. The comparison signal SC1 is output from the output terminal. Since the operation of the comparator 31c is the same as that of the comparators 31a and 31b, description thereof is omitted here.

  In the comparator 32c, similarly to the comparators 32a and 32b, the node N1 is connected to the inverting input terminal and the rectified voltage VO1 is input. The node N4 is connected to the non-inverting input terminal, and the AC voltage VAC2 is input. The comparison signal SC2 is output from the output terminal. Since the operation of the comparator 32c is the same as that of the comparators 32a and 32b, description thereof is omitted here.

  Similar to the switch control circuits 33a and 33b, the output terminal of the comparator 31c is connected to the first input terminal of the switch control circuit 33c to receive the comparison signal SC1, and the mask in the first embodiment is applied to the second input terminal. Instead of the signal MA1, a mask signal MA3 described later is input. The comparison signal SC1 is inputted after being logically inverted. The output terminal of the switch control circuit 33c is connected to the gate G1 of the PMOS transistor TP1 and the gate G3 of the PMOS transistor TP3, and outputs the SW control signal S1c. Since the operation of the switch control circuit 33c is the same as that of the switch control circuits 33a and 33b, description thereof is omitted here.

  Similarly to the switch control circuits 34a and 34b, the output terminal of the comparator 32c is connected to the first input terminal of the switch control circuit 34c and the comparison signal SC2 is input, and the mask in the first embodiment is applied to the second input terminal. A mask signal MA3 is input instead of the signal MA1. The comparison signal SC2 is inputted after being logically inverted. The gate G2 of the PMOS transistor TP2 and the gate G4 of the PMOS transistor TP4 are connected to the output terminal of the switch control circuit 34c, and the SW control signal S2c is output. Since the operation of the switch control circuit 34c is the same as that of the switch control circuits 34a and 34b, description thereof is omitted here.

  The synchronous rectification mask circuit 4c includes a timer circuit 41c, a comparator 43c, an FF circuit 46c, and a D-FF circuit 44c. In the timing circuit 41c, the comparison signal SC1, which is a period in which the AC voltage VAC1 exceeds the rectified voltage VO1, is measured at a high level. When the high level time of the comparison signal SC1 is longer than the predetermined time (in the case of the region IIc in FIG. 6), the high level mask signal MA3 is output. In this case, even when the AC voltages VAC1 and VAC2 exceed the voltage value of the rectified voltage VO1, the outputs of the SW control signals S1c and S2c are fixed at a high level. The PMOS transistors TP1 to TP4 are maintained in the off state, and synchronous rectification is not performed. On the other hand, when the high level time of the comparison signal SC1 is equal to or shorter than the predetermined time (in the case of the region Ic in FIG. 6), when the mask signal MA3 is at the low level and the AC voltages VAC1 and VAC2 exceed the rectified voltage VO1. The low level SW control signal S1c or S2c is output. The PMOS transistors TP1 to TP4 are turned on to perform synchronous rectification.

  The timer circuit 41c includes an inverter INV2, an NMOS transistor TN1, a constant current source I1, and a capacitor C2. The comparison signal SC1 is input to the input terminal of the inverter INV2. A current is supplied from the constant current source I1 to the drain of the NMOS transistor TN1, and a ground voltage is connected to the source. The output terminal of the inverter INV2 is connected to the gate of the NMOS transistor TN1, and an inverted signal of the comparison signal SC1 is input. One end of the capacitor C2 is connected to a connection node between the drain of the NMOS transistor TN1 and the constant current source I1, and the other end is connected to the ground voltage.

  During the low level of the comparison signal SC1, the NMOS transistor TN1 is on and the capacitor C2 is in a discharge state. When the comparison signal SC1 transitions to a high level, the NMOS transistor TN1 is turned off and the capacitor C2 is charged by the constant current source I1. The terminal voltage VC3 generated at one end of the capacitor C2 becomes a voltage that rises linearly in accordance with the off-period of the NMOS transistor TN1.

  The reference voltage VREF3 is input to the inverting input terminal of the comparator 43c, and one terminal of the capacitor C2 is connected to the non-inverting input terminal to input the terminal voltage VC3. When the terminal voltage VC3 exceeds the reference voltage VREF3, the comparator 43c outputs a high level comparison signal SD3.

  The output terminal of the comparator 43c is connected to the set terminal S of the FF circuit 46c. The reset signal R2 is input to the reset terminal R. A control signal SQ3 is output from the terminal Q. When it is determined that the time during which AC voltage VAC1 exceeds rectified voltage VO1 has exceeded a predetermined time and comparison signal SD3 is inverted to high level, FF circuit 46c is set and high level control signal SQ3 is output. In response to the comparison signal SC2 that is half a cycle ahead of the AC voltages VAC1 and VAC2 being inverted to a low level, the control signal SQ3 is reset to a low level.

  The terminal D of the D-FF 44c is connected to the terminal Q of the FF circuit 46c and receives the control signal SQ3. The terminal CLK is input with the comparison signal SC1 logically inverted. Mask signal MA3 is output from terminal Q. The D-FF circuit 44c takes in the control signal SQ3 in response to the low level inversion of the comparison signal SC1 and outputs it as the mask signal MA3.

  FIG. 6 is a timing chart for explaining the operation of the AC-DC converter device 1c according to the third embodiment. In FIG. 6, the difference voltage (VAC1-VAC2) between the AC voltage VAC1 and the AC voltage VAC2, the rectified voltage VO1, the difference voltage (VAC1-VO1) between the AC voltage VAC1 and the rectified voltage VO1, the AC voltage VAC2 and the rectified voltage VO1 The operation waveforms of the differential voltage (VAC2-VO1), comparison signals SC1, SC2, terminal voltage VC2, comparison signal SD3, control signal SQ3, mask signal MA3, and SW control signals S1c, S2c are shown. In the timing chart, the region Ic is a medium load region and the region IIc is a heavy load region. 2 and 4, the negative voltage is described in the differential voltage (VAC1-VO1) between the AC voltage VAC1 and the rectified voltage VO1, and the differential voltage (VAC2-VO1) between the AC voltage VAC2 and the rectified voltage VO1. Omitted.

  When the load applied to the AC-DC converter device 1c is a medium load (region Ic), the mask signal MA3 is the same signal as the mask signals MA1 and MA2, and is input to the bridge control circuit 3c. At medium load (region Ic), the mask signal MA3 is at a low level. The terminal voltage VC3 generated at one end of the capacitor C2 is a voltage corresponding to the high level duration of the comparison signal SC1 during which the AC voltage VAC1 exceeds the rectified voltage VO1. At medium load, the terminal voltage VC3 does not exceed the reference voltage VREF3 during the charging time of the capacitor C2, so the comparison signal SD3 is maintained at a low level. In the low level comparison signal SD3, the FF circuit 46c is not set, and the mask signal MA3 output from the D-FF circuit 44c is maintained at the low level. Here, the operation of the bridge control circuit 3c is the same as the operation of the bridge control circuit 3a, and thus the description thereof is omitted here. Since the mask signal MA3 is maintained at the low level, the SW control signals S1c and S2c are alternately at the low level, and the synchronous rectification operation is performed.

  When the load applied to the AC-DC converter device 1c is a heavy load (region IIc), the control by the DC-DC converter 8 has a characteristic that the conduction angle widens as the load current increases. That is, the heavier the load, the longer the AC voltage VAC1 exceeds the rectified voltage VO1. As a result, the time measured by the time measuring circuit 41c becomes longer and the charging time of the capacitor C2 becomes longer. As a result, the terminal voltage VC3 exceeds the reference voltage VREF3. When the terminal voltage VC3 exceeds the reference voltage VREF3, the comparison signal SD3 is inverted to a high level. The high level comparison signal SD3 sets the FF circuit 46c, and the high level mask signal MA2 is output via the D-FF circuit 44c.

  As described above in detail, according to the first embodiment of the present invention, the trigger circuit 35a of the bridge control circuit 3a has a high level during the period in which the AC voltage VAC1 or the AC voltage VAC2 exceeds the voltage of the rectified voltage VO1. The trigger signal ST is output. In the sample and hold circuit 41a of the synchronous rectification mask circuit 4a, the lowest rectified voltage VO1 is taken in as the terminal voltage VC1 during the voltage cycle F1 of the AC power supply 5 in response to the trigger signal ST being inverted to the high level, and the capacitor C1 can be held. The operational amplifier 42a detects the difference voltage VD1 that is a voltage difference between the terminal voltage VC1 and the rectified voltage VO1, and the comparator 43a compares the difference voltage VD1 with the reference voltage VREF1, thereby applying to the AC-DC converter device 1a. The load can be determined. When the load applied to the AC-DC converter device 1a is a heavy load, the differential voltage VD1 exceeds the reference voltage VREF1, and the comparison signal SD1 becomes high level. In response to the inversion of the low level of the trigger signal ST, a high level mask signal MA1 which is a heavy load determination signal is output from the terminal Q of the D-FF 44a. When the high level mask signal MA1 is input to the switch control circuits 33a and 34a, the SW control signals S1a and S2a are maintained at the high level regardless of the logic levels of the comparison signals SC1 and SC2. Therefore, the PMOS transistors TP1 to TP4 are maintained in the off state. Thereby, the synchronous rectification operation by turning on the PMOS transistors TP1 to TP4 is suppressed.

  Further, according to the second embodiment of the present invention, the counter circuit 41b of the synchronous rectification mask circuit 4b counts the number of high-level inversions of the comparison signal SC1. Every time the high-level inversion of the comparison signal SC1 is performed four times, the difference voltage VD2, which is the voltage difference between the rectified voltage VO1 detected by the operational amplifier 42b and the AC voltage VAC1, is compared with the reference voltage VREF2. Thereby, the load concerning AC-DC converter device 1b can be determined. When the load applied to the AC-DC converter device 1b is a heavy load, the differential voltage VD2 exceeds the reference voltage VREF2, and the comparison signal SD2 becomes high level. In response to the low level inversion of the gate signal GT in accordance with the low level inversion of the comparison signal SC1, a high level mask signal MA2 that is a heavy load determination signal is output from the terminal Q of the D-FF 44b. When the high-level mask signal MA2 is input to the switch control circuits 33b and 34b, the SW control signals S1b and S2b are set to the high level regardless of the logical levels of the comparison signals SC1 and SC2 as in the first embodiment. Maintained. Therefore, the PMOS transistors TP1 to TP4 are maintained in the off state. Thereby, the synchronous rectification operation by turning on the PMOS transistors TP1 to TP4 is suppressed.

  Further, according to the third embodiment of the present invention, the time measuring circuit 41c measures the time during which the comparison signal SC1 during which the AC voltage VAC1 exceeds the rectified voltage VO1 is high. The comparator 43c can determine the load applied to the AC-DC converter device 1c by comparing the reference voltage VREF3 with the terminal voltage VC3 that increases linearly according to the high level time of the comparison signal SC1. When the load applied to the AC-DC converter device 1c is a heavy load, the terminal voltage VC3 exceeds the reference voltage VREF3, and the comparison signal SD3 becomes high level. In response to the low level inversion of the comparison signal SC1, a high level mask signal MA3, which is a heavy load determination signal, is output from the terminal Q of the D-FF 44b. When the high level mask signal MA3 is input to the switch control circuits 33c and 34c, the SW control signals S1c and S2c are high regardless of the logical levels of the comparison signals SC1 and SC2, as in the first and second embodiments. Maintained at level. Therefore, the PMOS transistors TP1 to TP4 are maintained in the off state. Thereby, the synchronous rectification operation by turning on the PMOS transistors TP1 to TP4 is suppressed.

  As a result, the AC-DC converter devices 1a, 1b, and 1c are loaded by the synchronous rectification mask circuits 4a, 4b, and 4c when the load becomes larger and the loss increases in the synchronous rectification method than in the asynchronous rectification method. Therefore, it is possible to suppress the synchronous rectification method, and it is possible to reduce the loss related to the rectification operation regardless of the load.

Needless to say, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the first embodiment of the present application, when the AC voltages VAC1 and VAC2 exceed the rectified voltage VO1, the load state is detected by the synchronous rectification mask circuit 4a to determine whether the synchronous rectification operation is possible. However, the present application is not limited to this. For example, the synchronous rectification mask circuit 4a may be operated in accordance with the comparison signal SC1 or the comparison signal SC2 instead of the trigger signal ST to determine whether the synchronous rectification operation is possible. I do not care.
In the second embodiment of the present application, the input to the non-inverting input terminal of the operational amplifier 42b is not limited to the AC voltage VAC1. The AC voltage VAC2 may be used. In this case, the signal input to the counter circuit 41b is the comparison signal SC2.
The number of high level inversions of the comparison signal SC1 counted by the counter circuit 41b is not limited to four.
Instead of counting the number of high level inversions of the comparison signal SC1, the number of high level inversions of the comparison signals SC1 and SC2 may be counted. In this case, the load state may be determined by outputting a differential voltage between the AC voltage VAC2 and the rectified voltage VO1 instead of the operational amplifier 42b.
In the third embodiment of the present application, the signal input to the timing circuit 41c is not limited to the comparison signal SC1. The comparison signal SC2 may be used. In this case, the conduction angle is detected once in one cycle. However, if each of the comparison signal SC1 and the comparison signal SC2 has a timing circuit corresponding to the timing circuit 41c, the conduction angle is detected every half cycle. can do.

  Here, the comparators 31a, 31b, and 31c are examples of a first comparator, the comparators 32a, 32b, and 32c are examples of a second comparator, the switch control circuits 33a, 33b, 33c, 34a, 34b, and 34c, and synchronous rectification. The mask circuits 4a, 4b, and 4c are examples of synchronous rectification mask units, the operational amplifier 42a is an example of a first detector, the D-FF 44a is an example of a first latch unit, the operational amplifier 42b is an example of a second detector, and a D-FF circuit 44b and the FF circuit 46b are examples of the second latch unit, the timing circuit 41c is an example of the timing unit, the comparator 43c is an example of the third detector, and the D-FF circuit 44c and the FF circuit 46c are examples of the third latch unit. .

1a, 1b, 1c AC-DC converter device 2a, 2b, 2c Synchronous rectification control circuit 3a, 3b, 3c Bridge control circuit 4a, 4b, 4c Synchronous rectification mask circuit 5 AC power supply 6 Rectification bridge 7 Smoothing capacitor 8 DC-DC converter 9 Inductor 10 Output capacitor

Claims (7)

Rectification having a synchronous rectifying element connecting between terminals of a diode, a first node to which a rectified voltage is output, a second node to which a reference voltage is applied, and third and fourth nodes to which an AC voltage is applied The bridge part,
Detecting a voltage difference between the first node and the third node, and when the third node is at a higher voltage than the first node, a synchronous rectifier element between the first and third nodes; and A first comparator that outputs a first control signal that conducts a synchronous rectifier between the second and fourth nodes;
Detecting a voltage difference between the first node and the fourth node, and when the fourth node is at a higher voltage than the first node, a synchronous rectifier element between the first and fourth nodes; and A second comparator for outputting a second control signal for conducting a synchronous rectifying element between the second and third nodes;
A load state connected to the first node is determined according to at least one of the first and second control signals, and when it is determined that the load exceeds a specified level, determination of the next load state And an AC-DC converter, comprising: a synchronous rectification mask unit that masks the first and second control signals. The synchronous rectification mask is
A sampling and holding circuit for holding the rectified voltage at the start of output of at least one of the first and second control signals;
A first detector for detecting a difference voltage between the rectified voltage and the voltage held by the sample and hold circuit;
The first and second control signals are masked until the next detection by the first detector according to the detection result that the differential voltage detected by the first detector exceeds a specified voltage level. The AC-DC converter according to claim 1. The synchronous rectification mask is
3. The AC-DC converter according to claim 2, further comprising: a first latch unit that latches a detection result of the first detector at the end of output of at least one of the first and second control signals. . The synchronous rectification mask is
A counter that repeats counting the number of times that at least one of the first or second control signals is output to a specified number of times;
A second detector for detecting a differential voltage between the rectified voltage and the voltage of at least one of the third or fourth nodes;
The first and second counts until the count by the counter reaches the next specified number of times according to the detection result that the differential voltage by the second detector at the time of counting by the counter exceeds a specified voltage level. 2. The AC-DC converter according to claim 1, wherein the control signal is masked. The synchronous rectification mask is
5. The AC− according to claim 4, further comprising: a second latch unit that latches a detection result when the differential voltage detected by the second detector exceeds a predetermined voltage level at the time of counting by the counter. DC converter. The synchronous rectification mask is
A time measuring unit for measuring an output period of at least one of the first and second control signals;
A third detector for detecting a time measured by the time measuring unit,
Masking the first and second control signals until the next detection by the third detector according to the detection result that the time measured by the third detector exceeds a specified time. The AC-DC converter according to claim 1, wherein: The synchronous rectification mask is
The AC-DC converter according to claim 6, further comprising a third latch unit that latches a detection result when the time measured by the third detector exceeds a specified time.

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