JP5556026B2 - Semiconductor device, electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a technical field of a semiconductor device having a transistor used in an electro-optical device such as a liquid crystal device, an electro-optical device including such a semiconductor device, and an electronic apparatus such as a liquid crystal projector.

  In an electro-optical device including this type of semiconductor device, a pixel portion provided in the image display region and a drive circuit provided in a peripheral region located around the image display region are formed on the same substrate. is there. In this case, there is no problem even if the element characteristics of the transistor for pixel switching formed in the pixel portion provided in the image display area mainly for relatively low-speed switching operation are relatively low. It is required to keep it low. On the other hand, the transistors constituting the drive circuit and the like provided in the peripheral region require relatively high-speed switching operation, current amplification operation or current control operation, rectification operation, voltage holding operation, etc. Is required.

  Here, in a liquid crystal device or the like as an example of an electro-optical device, a transistor provided in a pixel portion is formed to have a smaller size than a transistor provided in a peripheral region because of a demand for high definition. On the other hand, the transistor formed in the peripheral region has a somewhat larger size than the transistor provided in the pixel portion. For this reason, in a transistor in a large peripheral region, a parasitic transistor generated between an edge portion of a semiconductor layer constituting the transistor and an element or wiring arranged in the periphery affects the element characteristics of the transistor. It becomes. In particular, the threshold voltage of the transistor depends on the threshold voltage of the parasitic transistor. For example, when the threshold voltage of the parasitic transistor is smaller than the threshold voltage of the original transistor (that is, the threshold voltage when it is assumed that no parasitic transistor is generated in the transistor in the peripheral region), the actual threshold voltage of the transistor in the peripheral region Changes slightly (that is, shifts to the depletion side). Then, for example, to design in accordance with the threshold voltage of the parasitic transistor, it is necessary to increase the threshold voltage of the original transistor in consideration of the difference between the threshold voltage of the original transistor and the threshold voltage of the parasitic transistor. When a voltage in the vicinity of the voltage is applied, the on-current of the transistor in the peripheral region is reduced, causing a problem that the characteristics of the transistor are deteriorated.

  In order to solve this problem, for example, Patent Document 1 discloses a technique for improving the element characteristics of the transistor in the peripheral region by increasing the threshold voltage of the parasitic transistor by forming the resistance of the edge portion high. It is disclosed. Patent Document 2 discloses a technique for improving element characteristics of a transistor in a peripheral region by increasing a threshold voltage of a parasitic transistor by forming a channel length of an edge portion longer.

Japanese Patent Laid-Open No. 7-326763 JP-A-7-326664

  However, in the technique according to Patent Document 1, it is technically difficult to form a high resistance value only in the edge portion of the semiconductor layer, and it is not easy to realize. Even if it is realized, the manufacturing process of the transistor becomes complicated, which increases the manufacturing cost. In the technique according to Patent Document 2, the channel length of the transistor changes depending on the drive voltage. Therefore, if the effect of the parasitic transistor is to be improved, the transistor must be driven at a specific voltage value. The usage is very limited. As described above, it is difficult to improve the characteristics of the transistor in any of the techniques, and further improvements are required.

  The present invention has been made in view of the above problems, for example. A semiconductor device having a transistor capable of improving the deterioration of transistor characteristics due to the generation of a parasitic transistor, and an electric device including such a semiconductor device. An object is to provide an optical device and an electronic apparatus.

A semiconductor device according to one embodiment of the present invention includes a first transistor and a second transistor which are disposed over a substrate, and the first transistor includes a first channel region, a first source region, and a first drain. A first semiconductor layer formed in a longitudinal shape along a predetermined direction including a region, and a first gate electrode disposed opposite to the first channel region via a first insulating film, The one channel region is formed by implanting predetermined ions into a main body portion serving as a first impurity concentration region and a portion extending in a predetermined direction on the edge of the main body portion when viewed from above the substrate. And the predetermined ions are further implanted, thereby having the same conductivity type as the first source region and the first drain region, and having a second impurity concentration higher than the first impurity concentration. Become an area A second semiconductor layer including a second channel region, and a second gate electrode disposed opposite to the second channel region with a second insulating film interposed therebetween. And the second channel region has the same conductivity type as the first channel region and has a third impurity concentration higher than the first impurity concentration when the predetermined ions are implanted. Features.
The semiconductor device according to the present invention includes : (i) a main body portion in which an impurity region is formed at a first concentration by implanting a predetermined type of ions; and (ii) on the substrate. As viewed in a plan view, the impurity is provided along a portion extending in a predetermined direction among the edges of the main body, and the impurities are implanted at a second concentration higher than the first concentration by being implanted with the ions. A first channel region having an edge portion in which the region is formed; a first semiconductor layer formed in a longitudinal shape along the predetermined direction; and the first channel region disposed opposite to the first channel region via an insulating film The first transistor having the first gate electrode has the same conductivity type as the first channel region, and an impurity region is formed at a third concentration higher than the first concentration by implanting the ions. The second channel region No second semiconductor layer, and comprising a second transistor having a second gate electrode which are oppositely arranged with an insulating film on the second channel region.

  According to the semiconductor device of the present invention, the first transistor and the second transistor are provided on the substrate. The first transistor and the second transistor are typically thin film transistors (hereinafter referred to as “TFT” as appropriate) formed on a substrate, and each semiconductor layer (that is, the first semiconductor layer and the second semiconductor layer). In this case, by performing ion implantation using a predetermined type of ions, electrons or holes are formed as carriers. The ion implantation is, for example, dopant implantation into the semiconductor layer. When the semiconductor layer is made of silicon, boron, phosphorus, arsenic, or the like is implanted. Note that heat treatment may be performed in order to diffuse ions implanted by ion implantation to a deep region of the semiconductor layer.

  The first channel region of the first transistor has a main body portion and an edge portion.

  The main body portion is a region that occupies most of the first channel region, and is a region excluding the edge region described below. In the present invention, in particular, the first impurity region is formed in the main body portion at a first concentration that has a lower impurity amount than the edge portion.

  The edge portion is a region provided along a portion extending in a predetermined direction in the edge portion of the main body portion when viewed in plan on the substrate. “Along a portion extending in a predetermined direction (that is, an edge portion)” means that it is formed along the longitudinal direction of the first semiconductor formed in a longitudinal shape. For example, the source region and the drain region are formed so as to sandwich the channel region in the first semiconductor layer, and the source region, the channel region, and the channel region and the drain region are adjacent to each other when viewed in plan on the substrate. The edge portion of the channel region along the edge portion excluding the edge portion adjacent to the source region and the channel region and the edge portion adjacent to the channel region and the drain region. Is provided. In the present invention, in particular, the second impurity region is formed at the edge portion with the second concentration having a higher impurity concentration than the main body portion.

  The edge portion generates a parasitic transistor between the element and the wiring arranged around the first semiconductor layer. That is, the first transistor in the present invention substantially includes a parasitic transistor generated between an element, a wiring, and the like arranged in the periphery, and is an ideal first transistor (that is, arranged in the periphery). The element characteristics are different from those of a transistor which is not affected by elements and wirings and does not include a parasitic transistor. In particular, since the threshold voltage of the first transistor depends on the threshold voltage of the parasitic transistor, the threshold voltage of the first transistor in the present invention shifts more or less than the ideal first transistor. Specifically, when the ideal threshold voltage of the first transistor is larger than the threshold voltage of the parasitic transistor included in the first transistor, the actual threshold voltage of the first transistor including the parasitic transistor is depletion-side. It will shift to. Then, for example, in order to prevent a through current and to prevent an increase in current when the transistor is in an OFF state, in order to design in accordance with the threshold voltage of the parasitic transistor, the difference between the threshold voltage of the original transistor and the threshold voltage of the parasitic transistor is considered. Thus, it is necessary to increase the threshold voltage of the original transistor, and when a voltage near the threshold voltage of the parasitic transistor is applied, the characteristics of the first transistor deteriorate, and the on-current cannot sufficiently flow near the threshold voltage. End up. This indicates that it is difficult to use the first transistor as, for example, a transistor constituting the drive circuit.

  In the present invention, in order to reduce or eliminate such deterioration of the characteristics of the first transistor, the concentration of impurities in the main body portion and the edge portion (that is, the first and second concentrations in the present invention) is adjusted. According to the research of the present inventor, the ideal threshold voltage of the first transistor mainly depends on the impurity concentration in the main body (that is, the first concentration in the present invention), and the threshold voltage of the parasitic transistor is mainly It has been found that it depends on the impurity concentration (that is, the second concentration) in the edge portion. In particular, if the first concentration is set lower than the second concentration, the difference between the ideal threshold voltage of the first transistor and the threshold voltage of the parasitic transistor can be reduced. It has been found that the degradation of characteristics can be suppressed or eliminated. That is, by reducing the ideal threshold voltage of the first transistor mainly depending on the first concentration (that is, by shifting the element characteristics to the depletion side), the characteristics of the first transistor are improved and the vicinity of the threshold voltage is reached. A sufficient on-current can be secured.

  The second transistor in the present invention is a transistor having the same conductivity type as the first transistor region. Therefore, an impurity region having the same conductivity type can be formed by implanting a predetermined type of ion, that is, the same type of ion, in the same opportunity into the same type of semiconductor layer as the first transistor. Therefore, the manufacturing process can be simplified as compared with the case where transistors having different conductivity types are formed on the substrate, and the manufacturing cost can be reduced by reducing the number of processes.

  The second semiconductor layer of the second transistor has a second channel region in which impurities are formed at a third concentration higher than the first concentration. That is, the second channel region is formed so that the impurity concentration in the first channel region is higher than that of the main body. According to the research of the present inventors, it has been found that the threshold voltage of the second transistor can be kept high by implanting ions so that the impurity concentration in the second channel region becomes high. Therefore, an off current hardly occurs when a low voltage is applied. For example, a second transistor suitable as a transistor with a small pixel switching leakage current can be formed with respect to the peripheral circuit at the same off voltage. That is, it can be formed with a transistor having an off-current optimally designed for pixel switching.

  As described above, according to the present invention, by improving the deterioration of element characteristics due to the occurrence of parasitic transistors, for example, a transistor suitable for a transistor suitable for a drive circuit or the like disposed in a peripheral region, It is possible to realize a semiconductor device in which a second transistor with little leakage current for pixel switching and provided with a small leakage current for pixel switching is provided over a common substrate.

  In one aspect of the electro-optical device of the present invention, the third density is equal to the second density.

  According to this aspect, the edge portion in the first channel region and the second channel region are formed to have the same impurity concentration. Therefore, when manufacturing the semiconductor device according to this aspect, for example, by implanting the same kind of ions at the same opportunity for the edge portion in the first channel region and the second channel region, the impurity region is formed at the same concentration. Can be formed. Therefore, according to this aspect, a semiconductor device can be realized more easily.

  In another aspect of the electro-optical device of the present invention, the third density is higher than the second density.

  According to this aspect, the second channel region is formed so that the impurity concentration is higher than the edge portion in the first channel region. Thus, when the impurity concentration in the second channel region is increased, the threshold voltage of the second transistor can be set higher. As a result, an off-current is less likely to occur when a low voltage is applied, and a second transistor that is very suitable as a pixel switching transistor, for example, can be formed.

  In order to solve the above problems, an electro-optical device according to the present invention includes the above-described semiconductor device according to the present invention (including various aspects thereof), and a plurality of scanning lines and a plurality of crossing lines on the substrate. Data lines and pixel electrodes provided for each pixel corresponding to the intersection, and the first transistor is provided in a peripheral region located around a pixel region in which the pixels are arranged, and The second transistor is provided for each pixel corresponding to the intersection in the pixel region.

  According to the electro-optical device of the present invention, the second transistor in which a plurality of pixels are arranged in a matrix area (that is, an image display area) is used as a switching element in each pixel. An image signal is controlled from the line to the pixel electrode, so that an image display by a so-called active matrix method can be performed. In this way, the second transistor is used, and the first transistor arranged in the peripheral region is switched at a relatively high speed, particularly in a driving method with a high driving frequency, and further, a current amplification operation or a current control operation, and a rectifying operation. By using it for a driver circuit that performs a voltage holding operation or the like (that is, an X driver circuit or a Y driver circuit), it is possible to realize an electro-optical device that can perform higher-quality image display.

  According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above is provided, the number of steps in the manufacturing process can be reduced, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, Various electronic devices such as a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  The effect | action and other gain of this invention are clarified from the form for implementing demonstrated below.

It is a top view which shows the whole structure of the liquid crystal device which concerns on this embodiment. It is HH 'sectional drawing of FIG. It is a block diagram which shows the structure of the principal part of the liquid crystal device which concerns on this embodiment. 3 is an equivalent circuit diagram of a plurality of pixel units of the liquid crystal device according to the present embodiment. FIG. It is a top view of a plurality of pixel parts in a liquid crystal device concerning this embodiment. It is AA 'sectional drawing of FIG. FIG. 5 is a cross-sectional view showing a comparison of a driving circuit TFT and a pixel switching TFT of the liquid crystal device according to the present embodiment. It is a schematic diagram which represents typically the planar structure of TFT for pixel switching of the liquid crystal device which concerns on this embodiment, and TFT for drive circuits. It is a graph which shows the characteristic of TFT for pixel switching of the liquid crystal device which concerns on a comparative example, and TFT for drive circuits. It is a graph which shows the characteristic of TFT for pixel switching and TFT for drive circuits of the liquid crystal device concerning this embodiment. It is process sectional drawing (the 1) which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on this embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a TFT active matrix driving type liquid crystal device with a built-in driving circuit, which is an example of an electro-optical device including the semiconductor device of the present invention, is taken as an example.

<Liquid crystal device>
First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a plan view showing the configuration of the liquid crystal device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. Among the peripheral regions, a data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a peripheral region located outside the seal region where the seal material 52 is disposed. . The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display region 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, in the image display area 10a on the TFT array substrate 10, a laminated structure is formed in which wirings such as pixel switching TFTs (Thin Film Transistors), scanning lines, and data lines are formed. Further, in the peripheral region on the TFT array substrate 10, a laminated structure in which TFTs for driving circuits, routing wires 90, etc. constituting the data line driving circuit 101, the scanning line driving circuit 104, and the sampling circuit 7 are formed. Is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. An alignment film is formed on the pixel electrode 9a. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. An alignment film is formed on the counter electrode 21. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is inspected for quality, defects, etc. of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, and the like may be formed.

  Next, a main configuration of the liquid crystal device according to the present embodiment will be described with reference to FIG.

  FIG. 3 is a block diagram illustrating a configuration of a main part of the liquid crystal device according to the present embodiment.

  3, the liquid crystal device according to the present embodiment includes a scanning line driving circuit 104, a data line driving circuit 101, a sampling circuit 7 and the like in a peripheral area located around the image display area 10a on the TFT array substrate 10. The drive circuit is formed.

  The scanning line driving circuit 104 is supplied with various control signals such as a Y clock signal (and an inverted Y clock signal) and a Y start pulse signal from an external circuit via the external circuit connection terminal 102. Based on these signals, the scanning line driving circuit 104 sequentially generates scanning signals G1,... Gm in this order and outputs them to the scanning line 3a. Further, the power supply VDDY and VSSY for driving the scanning line driving circuit 104 and various control signals are supplied to the scanning line driving circuit 104 via the external circuit connection terminal 102.

  The data line driving circuit 101 is supplied with an X clock signal and an X start pulse signal from an external circuit via the external circuit connection terminal 102. When the X start pulse is input, the data line driving circuit 101 sequentially generates and outputs sampling signals S1,..., Sn at a timing based on the X clock signal. The data line driving circuit 101 is supplied with power supplies VDDX and VSSX and various control signals for driving the data line driving circuit 101 via the external circuit connection terminal 102.

  The sampling circuit 7 includes a plurality of sampling switches 7s made of N-channel TFTs.

  In FIG. 3, the liquid crystal device according to the present embodiment is further provided with a plurality of pixel units 700 arranged in a matrix in an image display region 10 a occupying the center of the TFT array substrate 10.

  Here, the configuration of the pixel unit 700 of the liquid crystal device according to the present embodiment will be described with reference to FIG. 4 in addition to FIG. 3. FIG. 4 is an equivalent circuit diagram of various elements, wirings, and the like in the plurality of pixel units 700 of the liquid crystal device according to the present embodiment.

  Each of the plurality of pixel portions 700 is formed with a pixel electrode 9a and a TFT 30 for switching control of the pixel electrode 9a, and a data line 6a to which image signals VS1, VS2,. The TFT 30 is electrically connected to the source. The TFT 30 is an example of a pixel switching TFT, that is, an example of a “second transistor” according to the present invention, and is configured as an N-type TFT as will be described later.

  Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured as follows. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal VS1, VS2,... Supplied from the data line 6a is closed by closing the TFT 30 as a switching element for a certain period. VSn is written at a predetermined timing.

  Image signals VS1, VS2,..., VSn written to the liquid crystal via the pixel electrode 9a are held for a certain period with the counter electrode 21 (see FIG. 2) formed on the counter substrate. . The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. The storage capacitor 70 is provided side by side with the scanning line 3a, and includes a capacitor line 300 including a fixed potential side capacitor electrode and a predetermined potential. The storage capacitor 70 improves the charge retention characteristics of each pixel electrode. Note that the potential of the capacitor line 300 may be constantly fixed to one voltage value, or may be fixed while being swung to a plurality of voltage values at a predetermined period.

  In the liquid crystal device according to the present embodiment, the pixel unit 700 as described above is arranged in a matrix in the image display region 10a, so that active matrix driving is possible.

  As shown in FIG. 3 again, the image signal is supplied for each group to the set of six data lines 6a corresponding to each of the image signals VID1 to VID6 which are serially and parallelly developed in six phases. It is configured as follows. Note that the number of phase development of the image signal (that is, the number of series of image signals that are serial-parallel-developed) is not limited to six phases, and may be, for example, a plurality of phases such as nine phases, twelve phases, and twenty-four phases. The developed image signal may be supplied to a set of data lines 6a in which the number corresponding to the number of development is set as one set. Alternatively, the data lines 6a may be supplied line-sequentially without being serial-parallel developed.

  Next, a specific configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIGS.

  FIG. 5 is a plan view of a plurality of adjacent pixel portions 700 in the liquid crystal device according to the present embodiment, and FIG. 6 is a cross-sectional view taken along line AA ′ of FIG.

  In FIG. 5, a plurality of pixel electrodes 9a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by a dotted line portion 9a ′), and data is provided along the vertical and horizontal boundaries of the pixel electrode 9a. Line 6a and scanning line 3a are provided. The data line 6a is made of, for example, a metal film such as an aluminum film or an alloy film, and the scanning line 3a is made of, for example, a conductive polysilicon film. The scanning line 3a is disposed so as to face the channel region 1a ′, and the scanning line 3a functions as a gate electrode. That is, each of the intersections between the scanning lines 3a and the data lines 6a is provided with a pixel switching TFT 30 in which the main line portion of the scanning line 3a is disposed opposite to the channel region 1a ′ as a gate electrode.

  As shown in FIG. 6, the liquid crystal device according to this embodiment includes a transparent TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10. Each of the TFT array substrate 10 and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

  A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film.

  On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, and the alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example, similarly to the pixel electrode 9a. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.

  As shown in FIG. 6, the TFT 30 includes a scanning line 3 a functioning as a gate electrode as described above, a semiconductor layer 1 a as an example of a “second semiconductor layer” made of a polysilicon film according to the present invention, and a scanning line 3 a. And a gate insulating film 2a as an example of the “second insulating film” according to the present invention, which insulates the semiconductor layer 1a from each other.

  The semiconductor layer 1a includes a channel region 1a ′, a source region 1s, and a drain region 1d as an example of the “second channel region” according to the present invention. In the present embodiment, the channel region 1a ′, the source region 1s, and the drain region 1d are doped with N-type impurity ions such as phosphorus (P) ions, and the TFT 30 is formed as an N-type TFT. Yes.

  In FIG. 6, the storage capacitor 70 includes a relay layer 71 as a pixel potential side capacitor electrode electrically connected to the drain region 1 d of the TFT 30 and the pixel electrode 9 a, and a part of the capacitor line 300 as a fixed potential side capacitor electrode. Are formed so as to face each other with the dielectric film 75 interposed therebetween. The capacitor line 300 includes, for example, at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). It consists of silicide, polysilicide, or a laminate of these. Alternatively, it can be formed from an Al (aluminum) film.

  The relay layer 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the relay layer 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy, like the capacitor line 300. The relay layer 71 functions not only as a pixel potential side capacitor electrode but also as a relay connection between the pixel electrode 9 a and the drain region 1 d of the TFT 30 via the contact holes 83 and 85.

  As shown in FIG. 5, the capacitor line 300 is formed on the TFT array substrate 10 in a plan view so as to overlap with the formation region of the scanning line 3 a. The capacitor line 300 is preferably extended from the image display region 10a where the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. As such a constant potential source, for example, a constant potential source such as the power supply VDDX or the power supply VSSX supplied to the data line driving circuit 101 described above may be used, or the counter electrode potential supplied to the counter electrode 21 of the counter substrate 20. LCCOM may be used.

  The dielectric film 75 is made of, for example, a relatively thin HTO (High Temperature Oxide) film having a film thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature Oxide) film, or a silicon nitride film. From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better as long as the reliability of the film is sufficiently obtained.

  5 and 6, a lower light-shielding film 11 a is provided below the TFT 30. The lower light-shielding film 11a is patterned in a lattice pattern, thereby defining an opening area of each pixel. The lower light-shielding film 11a is composed of a single layer film or a multilayer film containing a metal or an alloy, like the capacitor line 300 described above.

  A base insulating film 12 is provided under the TFT 30. In addition to the function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 is roughened during the surface polishing or remains after cleaning. For example, the pixel switching TFT 30 has a function of preventing characteristic changes.

  In addition, a first interlayer insulating film 41 in which a contact hole 81 leading to the source region 1 s and a contact hole 83 leading to the drain region 1 d are respectively formed on the scanning line 3 a is formed.

A relay layer 71 and a capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 leading to the source region 1s and a contact hole 85 leading to the relay layer 71 are opened on these, respectively. A second interlayer insulating film 42 is formed.

  In addition, data lines 6a are formed on the second interlayer insulating film 42, and a third interlayer insulating film 43 in which a contact hole 85 leading to the relay layer 71 is formed is formed thereon. Yes.

  Next, the TFT 400 for the driving circuit of the liquid crystal device according to the present embodiment will be described with reference to FIG.

  FIG. 7 is a cross-sectional view of a TFT 400 for a driving circuit formed on the TFT array substrate 10 of the liquid crystal device according to the present embodiment, and is compared with the pixel switching TFT 30 also formed on the TFT array substrate 10. FIG.

  As described above, driving circuits such as the data line driving circuit 101, the scanning line driving circuit 104, and the sampling circuit 7 are formed in the peripheral area located around the image display area 10a on the TFT array substrate 10 (see FIG. (See FIG. 3). These drive circuits are configured to include a TFT 400 for the drive circuit. The TFT 400 for the drive circuit is an example of the “first transistor” according to the present invention, and is formed on the base insulating film 12 in the peripheral region.

  The drive circuit TFT 400 includes a gate electrode 430, a semiconductor layer 410 made of a polysilicon film, and a gate insulating film 2 b that insulates the gate electrode 430 from the semiconductor layer 410.

  The semiconductor layer 410 includes a channel region 410c, a source region 410s, and a drain region 410d as an example of the “first channel region” according to the present invention. The source region 410s and the drain region 410d are disposed on both sides of the channel region 410c and are adjacent to the channel region 410c.

  The semiconductor layer 410 of the driving circuit TFT 400 is formed as an N-type TFT by implanting N-type impurity ions such as phosphorus (P) ions, for example, as in the pixel switching TFT 30 described above. ing. That is, the driving circuit TFT 400 has the same conductivity type as the pixel switching TFT 30.

  Further, a first interlayer insulating film 41 and a second interlayer insulating film 42 are formed on the gate electrode 430. A source electrode 450 s and a drain electrode 450 d are disposed on the second interlayer insulating film 42.

  The source electrode 450s is electrically connected to the source region 410s through a contact hole 491 that is opened through the first interlayer insulating film 41, the second interlayer insulating film 42, and the gate insulating film 2b. .

  The drain electrode 450d is electrically connected to the drain region 410d through a contact hole 492 opened through the first interlayer insulating film 41, the second interlayer insulating film 42, and the gate insulating film 2b.

  A third interlayer insulating film 43 is stacked on the source electrode 450s and the drain electrode 450d.

  Here, a difference in structure between the pixel switching TFT 30 and the driving circuit TFT 400 will be described with reference to FIG. FIG. 8 is a schematic diagram schematically showing a planar structure of the pixel switching TFT 30 and the driving circuit TFT 400.

  As shown in FIG. 8A, the channel region 410c in the driving circuit TFT 400 includes a main body portion 410c1 and an edge portion 410c2.

  The main body 410c1 occupies most of the channel region 410c, and corresponds to a region excluding the edge region 410c2 in the channel region 410c. The main body 410c1 is formed so that the concentration of impurities present inside is lower than that of the edge 410c2.

  On the other hand, the edge portion 410c2 is provided along the longitudinal direction of the semiconductor layer 410 in the edge portion of the main body portion 410c when viewed in plan on the TFT array substrate 10, and the impurity concentration is higher than that of the main body portion 410c1. It is formed to have a high concentration.

  Next, as shown in FIG. 8B, in the channel region 1a ′ of the pixel switching TFT 30, unlike the TFT 400 for the drive circuit, the main body portion and the edge portion are not distinguished. This is because the channel region 1a ′ of the pixel switching TFT 30 is smaller in length in the direction perpendicular to the longitudinal direction (that is, the width of the channel region) than the channel region of the driving circuit TFT 400. Therefore, it has a structure similar to the edge portion of the first transistor.

  In the driving circuit TFT 400, the edge portion 410 c 2 generates a parasitic transistor between an element, a wiring, and the like arranged around the driving circuit TFT 400. That is, the TFT 400 for the drive circuit in the present embodiment has a characteristic different from that of an ideal TFT that is not affected by peripheral elements, wirings, and the like. In particular, the threshold voltage of the TFT 400 for the drive circuit depends on the threshold voltage of the parasitic transistor generated by the presence of the edge portion 410c2.

  Here, FIG. 9 shows that ions are formed so that impurities are formed at the same concentration in the main body portion 410c1 and the edge portion 410c2 in the channel region 410c of the TFT 400 for driving circuit and in the channel region 1a ′ of the TFT 30 for pixel switching. It is a graph which shows the element characteristic of TFT in the inject | poured comparative example.

  In the left diagram of FIG. 9A, the line indicated by the alternate long and short dash line indicates the element characteristics of the TFT 400 for the driving circuit when the influence of the parasitic transistor is ignored (that is, there is no edge portion 410c2 in the channel region and only the main body portion 410c1) Element characteristics when it is assumed that the device is configured. Also, the line indicated by the dotted line represents the element characteristics of the parasitic transistor caused by the edge portion 410c2.

  First, in the element characteristics of the TFT 400 for the drive circuit when the influence of the parasitic transistor indicated by the one-dot chain line is ignored, on-current starts to flow when the applied voltage reaches the threshold voltage V1, and then the applied voltage is further increased. As the current is increased, the on-current increases rapidly. When the on-current increases to near I1, the on-current increases slowly when the applied voltage is increased.

  On the other hand, the element characteristic of the parasitic transistor indicated by the dotted line is that the on-current starts to flow when the applied voltage reaches V2, which is smaller than the threshold voltage V1, and then, when the applied voltage is further increased, the characteristic of the main body 410c1. As with, the on-current increases rapidly. When the on-current increases to around I2, the on-current increases slowly when the applied voltage is increased. Note that the area of the edge portion 410c2 is smaller than that of the main body portion 410c1, and it is difficult for current to flow. Therefore, the maximum on-current value I2 is smaller than I1.

  Here, the right diagram in FIG. 9A represents the element characteristics of the entire TFT 400 for the drive circuit in the comparative example (that is, the element characteristics of the TFT 400 in consideration of the influence of the parasitic transistor). The characteristics of the TFT 400 for the drive circuit as a whole can be obtained by adding the characteristics of the TFT 400 for the drive circuit when the influence of the parasitic transistor shown in the left diagram of FIG. 9A is ignored and the characteristics of the parasitic transistor. It almost matches the characteristics obtained.

  As shown in the right diagram of FIG. 9A, when the applied voltage to the driving circuit TFT 400 in the comparative example reaches the threshold voltage V1, an on-current starts to flow through the driving circuit TFT 400. However, when the voltage is between V1 and V2, the on-current substantially does not flow through the main body 410c1 in the channel region of the TFT 400 for the drive circuit, but flows mainly through the edge 410c2. Therefore, the magnitude of the on-current that flows between V1 and V2 is small. That is, the driving circuit TFT 400 in the comparative example has a characteristic that the on-current hardly flows in the vicinity of the threshold voltage V1.

  On the other hand, FIG. 9B shows element characteristics of the pixel switching TFT 30. As described above, the pixel switching TFT 30 has a structure similar to the edge portion of the first transistor. Therefore, such a problem does not occur.

  FIG. 10 is a graph showing the element characteristics of the driving circuit TFT 400 and the pixel switching TFT 30 in this embodiment.

  In the liquid crystal device according to the present embodiment, the impurity concentration is adjusted in the main body portion 410c1 and the edge portion 410c2 in order to reduce or eliminate the deterioration in characteristics of the TFT 400 for the drive circuit as described above. According to the research of the inventor of the present application, it has been found that the threshold voltage V1 of the TFT 400 for the driving circuit when the influence of the parasitic transistor is ignored depends mainly on the impurity concentration in the main body 410c1 in the semiconductor layer. Therefore, by implanting ions so that the impurity concentration in the main body portion 410c1 is lower than the impurity concentration in the edge portion 410c2, the deterioration in characteristics of the TFT 400 for the drive circuit is reduced or eliminated.

  As shown in the left diagram of FIG. 10A, the threshold voltage V1 of the TFT 400 for the drive circuit when the influence of the parasitic transistor is ignored and the threshold voltage V2 of the parasitic transistor generated due to the edge portion 410c2 are aligned. Alternatively, ions are implanted so that the threshold voltage V2 of the parasitic transistor is higher than the threshold voltage V1 of the parasitic transistor, thereby forming the TFT 400 for the drive circuit. Then, as shown in the right diagram of FIG. 10A, the characteristics of the TFT 400 for the drive circuit are as follows. When the applied voltage reaches the threshold voltage V1 (or V2), the on-current starts to flow, and then the applied voltage is further increased. As the current increases, the on-current increases rapidly. As described above, in the TFT 400 for a drive circuit according to the present embodiment, the element characteristics are not deteriorated such that the on-current flowing in the vicinity of the threshold voltage is reduced.

  FIG. 10B shows the characteristics of the pixel switching TFT 30 according to this embodiment. The pixel switching TFT 30 has a structure similar to the edge portion of the first transistor. Therefore, as in the case of the comparative example (see FIG. 9B), the above problem does not occur.

  In this embodiment, the pixel switching TFT 30 formed on the TFT array substrate 10 and the driving circuit TFT 400 are formed to have the same conductivity type. Then, since the impurity region can be formed by implanting the same kind of ions into the same kind of semiconductor layer, the manufacturing process is simplified as compared with the case where transistors of different conductivity types are formed on the TFT array substrate 10. It is possible to contribute to the reduction of the manufacturing cost through the reduction of the number of processes. The manufacturing process will be described in detail later.

  Further, the pixel switching TFT 30 is formed so that the impurity concentration is higher than that of the main body portion 410c1 in the driving circuit TFT 400. According to the research of the present inventor, it has been found that the threshold voltage can be kept higher than the threshold voltage V1 of the TFT 400 for the drive circuit by forming the pixel switching TFT 30 to have a high impurity concentration. ing. Therefore, an off-current hardly occurs when a low voltage is applied, and a TFT suitable as a transistor with a small leakage current for pixel switching can be formed.

  As described above, according to the present invention, by improving characteristic deterioration based on the generation of parasitic transistors, for example, a transistor suitable as a transistor constituting a driving circuit and an off-current hardly occur. For example, pixel switching Therefore, it is possible to realize a liquid crystal device in which a second transistor having a small leakage current is provided on a common substrate.

<Manufacturing method>
Next, a method for manufacturing the liquid crystal device according to this embodiment described above will be described with reference to FIG.

  FIG. 11 is a process cross-sectional view illustrating a series of manufacturing processes for manufacturing the liquid crystal device according to the present embodiment. In FIG. 11, the driving circuit TFT and the pixel switching TFT shown in FIG. 7 are shown corresponding to the cross-sectional views.

  First, in step (1) of FIG. 11, a TFT array substrate 10 made of, for example, a quartz substrate or a glass substrate is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N 2 (nitrogen) and at a high temperature of about 850 to 1300 ° C., and pre-processing is performed so as to reduce distortion generated in the TFT array substrate 10 in a high-temperature process to be performed later. Keep it.

  Next, in the image display region 10a, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo, and Pb or a metal silicide is formed on the TFT array substrate 10 by sputtering to form a film having a thickness of about 100 to 500 nm. After the thick light shielding film is formed, patterning is performed by etching to form the light shielding film 11a.

  Next, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 (that is, the image display region 10a and the peripheral region).

  Next, a polysilicon film is formed on the base insulating layer 12 by solid phase growth of amorphous silicon formed by a low pressure CVD method or the like or a low pressure CVD method. Subsequently, the polysilicon film is subjected to, for example, a photolithography method and an etching process to form semiconductor layers 1a and 410 having a predetermined pattern in the image display region 10a and the peripheral region, respectively.

  Here, for example, N-type impurity ions such as phosphorus (P) ions are implanted into the semiconductor layers 1a and 410 in two stages as indicated by a downward arrow N- in the drawing. First, N-type impurity ions such as phosphorus (P) ions are implanted at a low concentration into the entire semiconductor layers 1a and 410, for example. Next, as shown in FIG. 11B, a resist film 500 is formed on the semiconductor layer 410 over a region excluding at least the edge portion 410c2 (see, for example, FIG. 8A), for example, phosphorus (P) ions or the like. N-type impurity ions are further implanted. Here, for example, when viewed in plan on the TFT array substrate 10, the resist film 500 is formed so as to avoid the edge portion 410c2, as shown in the lower diagram of FIG. Then, in the channel region 410c, the concentration of ions implanted in the main body portion 410c1 that was not ion-implanted the second time by the resist film 500 corresponds to the other regions (the edge portion 410c2, the source region 410s, and the drain of the semiconductor layer 410). It becomes lower than the region 410d and the semiconductor layer 1a). Thereafter, the resist film 500 is removed. As described above, by forming the main body portion 410c1 to have a lower impurity concentration than other regions, it is possible to prevent a deterioration in characteristics such as a decrease in on-current even in the vicinity of the threshold voltage. A semiconductor layer of the TFT 400 can be formed.

  Subsequently, gate insulating films 2a and 2b are formed by thermally oxidizing the surfaces of the semiconductor layers 410 and 1a, respectively. Then, a conductive polysilicon film is stacked on the gate insulating films 2a and 2b, and gate electrodes 3a and 430 having predetermined patterns are formed by, for example, performing a photolithography method and an etching process. At this time, the gate electrode 3a is formed so as to overlap with the region to be the channel region 1a ′ of the semiconductor layer 1a, and the gate electrode 430 is formed so as to overlap with the region of the semiconductor layer 410 to be the channel region 410c.

  In this manner, the pixel switching TFT 30 is formed in the image display region 10a, and the driving circuit TFT 400 is formed in the peripheral region. Various wirings, electrodes, insulating layers, and the like shown in FIG. 7 are formed on the pixel switching TFT 30 and the driving circuit TFT 400 to form a stacked structure on the TFT array substrate 10.

  On the other hand, for the counter substrate 20 shown in FIG. 6, a glass substrate or the like is first prepared as the counter substrate 20. On the counter substrate 20, a counter electrode 21, an alignment film 22 and the like are formed.

  Finally, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded together with a sealing material (see FIGS. 1 and 2) so that the alignment films 16 and 22 face each other, and vacuum suction or the like is performed. Thus, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked into the space between the two substrates to form a liquid crystal layer 50 having a predetermined layer thickness.

  According to the liquid crystal device manufacturing method described above, the liquid crystal device according to the present embodiment configured as described above can be manufactured.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. Hereinafter, a projector using a liquid crystal device as a light valve will be described. FIG. 12 is a plan view showing a configuration example of the projector.

  As shown in FIG. 12, a projector 1100 has a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 12, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the gist or concept of the invention that can be read from the claims and the entire specification. The manufacturing method, the electro-optical device and the manufacturing method thereof, and the electronic apparatus including the electro-optical device are also included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1a '... Channel region, 1s ... Source region, 1d ... Drain region, 2a, 2b ... Gate insulating film, 3a ... Scan line, 6a ... Data line, 7 ... Sampling circuit, 9a ... Pixel electrode, 10 ... TFT array substrate, 10a ... Image display area, 11a ... Light shielding film, 20 ... Counter substrate, 21 ... Counter electrode, 30 ... TFT, 41, 42, 43 ... Interlayer insulating film, 50 ... Liquid crystal layer, 101 ... Data line drive Circuit 102, external circuit connection terminal 104, scanning line driving circuit, 400 ... TFT, 410 ... semiconductor layer, 410c ... channel region, 410s ... source region, 410d ... drain region

Claims (5)

A first transistor disposed on a substrate; a second transistor;
Including
  The first transistor includes:
  A first semiconductor layer formed in a longitudinal shape along a predetermined direction including a first channel region, a first source region, and a first drain region;
  A first gate electrode disposed opposite to the first channel region via a first insulating film;
Including
  The first channel region is
  A main body portion to be a region having a first impurity concentration by implanting predetermined ions;
  The first source region and the first drain region are arranged along a portion extending in a predetermined direction among the edges of the main body as viewed from above the substrate, and the predetermined ions are further implanted. And an edge portion which becomes a region having a second impurity concentration higher than the first impurity concentration,
Including
  The second transistor is
  A second semiconductor layer including a second channel region;
  A second gate electrode disposed opposite to the second channel region via a second insulating film;
Including
  The second channel region is
  A semiconductor device having the same conductivity type as that of the first channel region and a third impurity concentration higher than the first impurity concentration by implantation of the predetermined ions. The semiconductor device according to claim 1, wherein the third impurity concentration is equal to the second impurity concentration. The semiconductor device according to claim 1, wherein the third impurity concentration is higher than the second impurity concentration. An electro-optical device comprising the semiconductor device according to claim 1,
On top of the substrate,
A plurality of scan lines and a plurality of data lines intersecting each other;
A pixel electrode provided for each pixel corresponding to the intersection ;
With
The first transistor is provided in a peripheral region located around a pixel region in which the pixels are arranged,
The electro-optical device, wherein the second transistor is provided for each pixel corresponding to the intersection in the pixel region.   An electronic apparatus comprising the electro-optical device according to claim 4.

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