JP5555600B2 - Current mirror circuit - Google Patents

Description

  The present invention relates to a current mirror circuit that generates a desired output current by using a reference current flowing from a current source to a mirror source transistor as a reference value and mirroring the output current to a mirror destination transistor.

  As technology (semiconductor manufacturing technology) continues to shrink, the gate leakage current of MOS (Metal-Oxide-Semiconductor) transistors has increased exponentially, which is the mirror source and mirror destination of the current mirror circuit. In many cases, the gate voltage of the MOS transistor is changed from a desired bias point (bias voltage). For this reason, in order to mirror the reference current with high accuracy, a configuration in which a circuit for compensating the gate leakage current is added to the current mirror circuit may be used (see Patent Document 1).

  On the other hand, in order to reduce high-frequency noise included in a reference current supplied from a reference current source, a configuration in which an RC low-pass filter circuit is added to the current mirror circuit itself may be used (Patent Documents 2 and 2). 4). In this way, by adding a low-pass filter circuit to the current mirror circuit, noise having a higher frequency component than the cutoff frequency of the added low-pass filter circuit is removed from the output current, and a stable output current can be supplied. Become.

JP 2006-140299 A Japanese Patent Publication No. 7-3646 JP 2003-124751 A JP 2006-59057 A

FIG. 8 is a circuit diagram illustrating an example of a configuration of a conventional current mirror circuit including an RC type low-pass filter circuit. The current mirror circuit 40 shown in the figure, a current source 12 of the reference current, the mirror source to become N-type MOS transistor and _{M 0} (hereinafter, referred to as NMOS), and NMOSM ₁ as a mirror destination, resistor _{R 0} and capacitor C _An RC type low-pass filter circuit consisting of ₀ is used. Here, it is assumed that the mirror ratio of the current mirror circuit 40 is 1.

The current mirror circuit 40, the reference current _{I REF} supplied from the current source 12 flows to NMOSM ₀ of mirror source. Since the gate of the NMOS M ₀ is connected to the drain thereof, the NMOS M ₀ is biased to a predetermined voltage that allows the reference current I _REF to flow through the NMOS M ₀ .

The voltage of the gate of the NMOSM ₀ is supplied to the gate of NMOSM ₁ of the mirror destination through an RC low-pass filter circuit. Therefore, ideally, an output current I _OUT equal to the reference current I _REF flowing through the mirror source NMOS M ₀ flows through the NMOS M ₁ .

Here, the low-pass filter circuit 40 has a frequency lower than the cutoff frequency included in the reference current I _REF supplied from the current source 12 according to the cutoff frequency determined by the time constant of the resistor R ₀ and the capacitance C _0. Remove high frequency noise.

  When the gate oxide film thickness of the MOS transistor is sufficiently thick, the gate leakage current can be ignored, but as the gate oxide film thickness of the MOS transistor becomes thinner as the miniaturization progresses, as shown by the arrows in the figure, A non-negligible path of gate leakage current is generated. In terms of process, it is very difficult to reduce the gate leakage current itself in the thin film MOS transistor.

If gate leakage current occurs, resulting IR drop by the gate leakage current flows through the resistor _{R 0,} the node X 'voltage V _{X of'} between the gate and the resistance _{R 0} of NMOSM _0, the gate of NMOSM ₁ And the voltage V _{B ′ at} the node B ′ between the resistor R ₀ and the resistor R ₀ . As a result, a difference is generated between the reference current I _REF flowing through the mirror source NMOS M ₀ and the output current I _OUT flowing through the mirror destination NMOS M ₁ .

Further, when an RC type low-pass filter circuit using a MOS capacitor is added to the current mirror circuit in order to reduce high-frequency noise, NMOS M ₀ for mirroring the reference current as shown by an arrow in the figure and A gate leakage current is generated not only in M ₁ but also in a MOS capacitor that functions as a capacitor (C) of the low-pass filter circuit. For this reason, further fluctuation of the bias point due to IR drop in the resistor (R) constituting the low-pass filter circuit is inevitable.

  In other words, since the voltage difference between the gate and the source of the MOS transistor at the mirror source and the mirror destination is further widened, the accuracy of the current mirror in the current mirror circuit is significantly reduced.

  An object of the present invention is to provide a current mirror circuit that can reduce the influence of gate leakage current and can improve resistance to high-frequency noise.

In order to achieve the above object, the present invention provides a current mirror circuit that mirrors the current flowing from the first current source to the gate and drain of the first MOS transistor serving as the mirror source to the current flowing through the second MOS transistor. In
A fourth resistor, a second resistor, a first resistor and a third resistor connected in series in this order between the gate of the first MOS transistor and the gate of the second MOS transistor;
The node between the first resistor and the third resistor and the node between the second resistor and the fourth resistor are input, and the node between the first resistor and the second resistor is input. A differential amplifier circuit for output,
The third resistor is set to a resistance value greater than the first resistance, the fourth resistor is set to a resistance value greater than the second resistance, and the third resistance is the fourth resistance. The present invention provides a current mirror circuit characterized in that the resistance value is set to be larger than the resistance.

  Here, it is preferable that the ratio of the resistance values of the first resistor and the third resistor and the ratio of the resistance values of the second resistor and the fourth resistor are set to be equal.

  And a capacitor having one terminal connected to a node between the third resistor and the gate of the second MOS transistor, the first resistor, the third resistor, and the capacitor It is preferable that a low-pass filter is configured.

  Furthermore, a second current source connected to a node between the first resistor and the second resistor, and a gate and a drain are connected to a node between the first resistor and the second resistor. And a third MOS transistor.

  According to the present invention, by performing feedback control using a differential amplifier circuit, even when a gate leakage current occurs, fluctuations in the bias voltage due to the gate leakage current are reduced, and fluctuations in the mirrored current are reduced. be able to.

It is a circuit diagram of one embodiment showing the composition of the current mirror circuit of the present invention. It is a circuit diagram showing the structure of Amp shown in FIG. FIG. 2 is a circuit conceptual diagram of a specific design example of the current mirror circuit of the present embodiment illustrated in FIG. 1. It is a circuit conceptual diagram showing the simulation result of the current mirror circuit of this embodiment shown in FIG. It is a graph showing the simulation result of the transfer function (Z-> B) in the current mirror circuit of this embodiment shown in FIG. 10 is a graph showing simulation results of the transfer function (X ′ → B ′) in the conventional current mirror circuit shown in FIG. 9 and the transfer function (X → B) in the current mirror circuit of the present embodiment shown in FIG. 3. It is a circuit diagram of another embodiment showing the structure of the current mirror circuit of this invention. It is an example circuit diagram showing the structure of the conventional current mirror circuit. FIG. 9 is a circuit conceptual diagram of a specific design example of the conventional current mirror circuit shown in FIG. 8. FIG. 10 is a circuit conceptual diagram showing a simulation result of the conventional current mirror circuit shown in FIG. 9.

  Hereinafter, a current mirror circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a circuit diagram of an embodiment showing a configuration of a current mirror circuit of the present invention. The current mirror circuit 10 shown in the figure includes current sources 12 and 14, NMOS M ₀ , M ₁ and M ₂ , resistors R ₁ , αR ₁ , R ₂ and αR ₂ , a capacitor C _0, and a differential amplifier circuit. And Amp16. The current mirror circuit 10 of this embodiment is obtained by applying the present invention to the conventional current mirror circuit 40 shown in FIG. 8, and the same components are denoted by the same reference numerals.

A mirror source NMOSM ₀ is connected between the current source 12 and ground, and the gate is connected to the drain (diode connection). Further, the source of the MOSM ₁ serving as a mirror destination is connected to the ground.

The resistors R ₁ , αR ₁ , R ₂ , αR ₂ and the capacitor C ₀ constitute an RC type low pass filter. The resistors R ₁ , αR ₁ , R ₂ , and αR ₂ are arranged between the gate of the NMOS M _{0 and} the gate of the NMOS M ₁ from the gate side of the NMOS M ₀ (from the left side in FIG. 1), the resistors αR ₂ , R ₂ , R ₁ and αR ₁ are connected in series in the order. The capacitor C ₀ is connected between the node B between the resistor αR ₁ and the gate of the NMOS M ₁ and the ground. Current source 14 is connected to a node Z between the resistors R ₁ and R _2. NMOSM ₂ is connected between node Z and ground, and the gate is connected to the drain (diode connection).

Here, the resistance αR ₁ is set to a resistance value larger than the resistance R ₁ . For example, the resistance αR ₁ is desirably set to a resistance value that is about 10 to 50 times the resistance R ₁ . Similarly, the resistance αR ₂ is set to a resistance value larger than the resistance R ₂ . For example, the resistance αR ₂ is desirably set to a resistance value of about 10 to 50 times the resistance R ₂ . The ratio of the resistance values of the resistors R ₁ and αR ₁ and the ratio of the resistance values of the resistors R ₂ and αR ₂ are set to be equal.

A larger resistance value of the resistor αR ₁ is preferable in order to lower the cut-off frequency of the RC low-pass filter composed of αR ₁ and the capacitor C ₀ . As a result, not only high frequency noise included in the current I _REF but also high frequency noise generated by the Amp 16 can be removed.

On the other hand, the resistance value of the resistor R ₁ is preferably small. The reason is as follows.
-To reduce the resistance between the input and output of Amp16.
-Considering that if noise is input to Amp 16, it will be amplified, and increasing the resistance value that causes noise at the mirror source input node is negative in the circuit operation.

Further, it is preferable to set the resistance R ₁ larger than the resistance R ₂ . The reason is as follows.
-Considering eliminating noise with a low-pass filter, it is ideal to place a high resistance value on the side closer to the mirror tip.
When - if a large resistance R ₂ close to the mirror source, nodes connected to AMP 16 is input to the positive input terminal of the AMP 16, (high gain of the positive feedback loop) the input voltage is large in the positive input terminal of the AMP 16 And the loop becomes unstable.
In addition, when a high resistance is arranged as the mirror source resistance αR ₂ , α needs to be equal between the resistance R ₁ and the resistance R ₂ , so that the resistance value of the resistance R ₂ inevitably becomes larger than the current value (for example, When the resistance αR _{2 is set} to 500 kΩ, the resistance R ₂ is 10 kΩ, which is 20 times that of the embodiment), but a noise several times or more is input to the Amp 16, and rather the amplifier 16 amplifies the noise. As described above, the circuit operation is negative. Therefore, it is preferable to arrange a large resistor at the mirror tip for the secondary reason.

The reason why the ratio of the values of the resistors R ₁ and αR ₁ and the ratio of the values of the resistors R ₂ and αR ₂ are set equal will be described later.

Amp16 input terminal -, the resistor _{R 1} and the voltage _{V A} of the node A between the resistor [alpha] R ₁ is input to the input terminal + is the voltage at node Y between the resistor _{R 2} and the resistor [alpha] R ₂ V _Y is input. The Amp 16 detects the difference between the voltage V _A at the node _A and the voltage V _{Y at the} node Y, and outputs a feedback current I _Amp for canceling the difference to the node Z according to the difference.

  Hereinafter, an example of Amp 16 will be described.

  FIG. 2 is a circuit diagram showing the configuration of Amp shown in FIG. Amp 16 shown in FIG. 1 includes an input unit 18, an output unit 20, and a bias voltage generation unit 22.

Bias voltage generating unit 22 includes a current source 30, and a NMOSM _3. NMOSM ₃ is connected between the current source 30 and ground GND. In the bias voltage generation unit 22, the gate of NMOSM ₃ is connected to a node between the drain of the current source 30 and NMOSM ₃ (diode connection), DC bias voltage Vb is generated on the gate of NMOSM _3.

The input unit 18 includes NMOS M ₄ , M ₅ , M ₆ and P-type MOS transistors (hereinafter referred to as PMOS) M ₇ , M ₈ . The gate of NMOSM _{5, M 6,} respectively the input voltage _{V ⁱⁿ -, V} ^{in +} is input, a source connected to the ground GND via the NMOSM _4. The sources of the PMOSs M ₇ and M ₈ are connected to the power supply VDD, the drains are connected to the drains of the NMOSs M ₅ and M ₆ , respectively, and the gates are connected to the drain of the PMOS M ₇ to form a current mirror circuit. .

The output unit 20 includes a PMOS M ₁₀ and an NMOS M ₉ connected in series between the power supply VDD and the ground GND, and a capacitor C ₁ . The capacitor C ₁ is connected between a node D between the PMOS M ₈ and the NMOS M ₆ in the input unit 18 and a node E between the PMOS M ₁₀ and the NMOS M _{9 in} the output unit 20. The gate of the PMOS M ₁₀ is connected to the node D. Further, an output current I _OUT is output from the node E.

Further, the gate of the NMOS M ₃ of the bias voltage generator 22, the gate of the NMOS M ₄ of the input unit 18, and the gate of the NMOS M ₉ of the output unit 20 are connected to constitute a current mirror circuit.

In Amp 16, the output current I corresponding to the differential input voltages V _in ⁻ and V _in ⁺ (that is, voltages V _A and V _Y ) input to the two NMOSs M ₅ and M ₆ of the input unit 18 is determined. _out (that is, feedback current I _Amp ) is output from the node E of the output unit 20. That is, when V _in ⁺ > V _in ⁻ , the output current I _out increases according to the voltage difference. When V _in ⁺ <V _in ⁻ , the output current I _out depends on the voltage difference. Decrease.

  Note that the specific configuration of the Amp 16 is not limited to the above example, and differential amplifier circuits having various configurations can be used.

  Next, the operation of the current mirror circuit 10 will be described.

The current mirror circuit 10 generates a desired output current I _OUT by mirroring the reference current I _REF flowing from the current source 12 to the mirror source NMOS M ₀ as a reference value to the current flowing to the mirror destination NMOS M _1. It is.

In the current mirror circuit 10, the reference current I _REF supplied from the current source 12 flows to the mirror source NMOS M ₀ . Since the gate of the NMOS M ₀ is connected to the drain thereof, the NMOS M ₀ is biased to a predetermined voltage that allows the reference current I _REF to flow through the NMOS M ₀ .

Further, the reference current I _REF supplied from the current source 14 flows through the NMOS M ₂ . Similarly, since the gate of the NMOS M ₂ is connected to its drain, when it is assumed that no gate leakage current flows, the NMOS M ₂ is biased to a predetermined voltage that allows the reference current I _REF to flow through the NMOS M _2. .

The voltage of the gate of the NMOS M ₀ is supplied to the gate of the NMOS M _{1 as} a mirror destination via the resistors αR ₂ , R ₂ , R ₁ , αR ₁ and the capacitor C ₀ . Here, assuming that the gate leakage current does not flow through the resistors αR ₂ , R ₂ , R ₁ , and αR ₁ , the voltage V _X of the node X between the gate of the NMOS M ₀ and the resistor αR ₂ and the node A voltage difference due to IR drop does not occur between the voltage V _{B of B} and an output current I _OUT having a value equal to the reference current I _REF flowing in the mirror source NMOS M ₀ flows through the mirror destination NMOS M ₁ .

In the above description, it is assumed that the gate leakage current does not flow. However, as the technology is miniaturized and the gate oxide film of the MOS transistor is thinned, the gate leakage current increases and is ignored. become unable. In the current mirror circuit 10, the paths (paths) through which the gate leakage current flows are a total of four places, NMOS M ₀ , M ₁ , M ₂ and capacitance C ₀ , as indicated by arrows in FIG.

In the low-pass filter circuit, when the reference current I _REF supplied from the current source 12 includes high frequency noise, the bias voltage generated at the gate of the NMOS M ₀ also includes high frequency noise. However, noise having a frequency component higher than the cutoff frequency is removed according to the cutoff frequency determined by the time constants of the resistors αR ₂ , R ₂ , R ₁ , αR ₁ and the capacitance C ₀ . As a result, it is possible to prevent the voltage V _{B at the} node _B from fluctuating due to the influence of the high frequency noise included in the reference current I _REF and the mirrored current from fluctuating.

Amp 16 is fed back so that the voltage between node _A voltage V _A and node Y voltage V _Y is equal to each other according to the difference when a difference occurs between node A voltage V _A and node Y voltage V _Y due to IR drop caused by gate leakage current. The current I _Amp is output. As a result, even when a gate leakage current occurs, a decrease in bias voltage due to the gate leakage current can be reduced, and a decrease in mirror accuracy can be reduced. Note that a current mirror circuit is also used in Amp 16, and it is considered that the mirror accuracy decreases due to the same phenomenon as the IR drop caused by the gate leakage current in the current mirror circuit of the present application. Since the operating frequency is low, it is unlikely to affect the operating performance. Further, it is not necessary to add a low-pass filter circuit.

Here, the low-pass filter circuit also uses a cutoff frequency determined by the time constants of the resistors R ₁ and αR ₁ and the capacitor C ₀ even when high-frequency noise is included in the feedback current I _Amp output from the _Amp 16. High frequency component noise can be removed. As a result, it is possible to prevent the voltage V _{B at the} node _B from fluctuating due to the influence of the high frequency noise included in the feedback current I _Amp and the mirrored current from fluctuating.

Hereinafter, the voltage difference between the voltage V _A at the node _A and the voltage V _{Y at the} node Y is detected by the _{Amp 16} and a feedback current I _Amp that eliminates the voltage difference is output, whereby the voltage V _{X at the} node X is output. And the fact that the potential difference between node B and voltage V _B can be eliminated.

Here, it is assumed that the mirror ratio of the current in the current mirror circuit 10 is 1. Also, the transconductance of NMOS M ₀ , M ₁ , M ₂ is g _m , and the trans conductance of Amp 16 is G _m . The resistance R1 toward the node Z to the Node-B, a current _{I R1} flowing in [alpha] R _1, resistor _{R 2} toward the node Z to the node X, the current flowing through the [alpha] R ₂ and _{I R2.}

As described above, the Amp 16 detects a difference between the voltage V _A at the node _A and the voltage V _{Y at the} node Y, and cancels the voltage difference according to the difference as shown in the following formula (1). The feedback current I _Amp is output.
_{G m (V Y -V A)} = I Amp ... (1)

Here, if the AMP 16 is ideal, because the current is negligible flow into the input terminal of the AMP 16, with the current _{I R2} flowing through the current _{I R1} and the resistor _{R 2} flows through the resistor _{R 1,} the voltage at node X V The voltage V _{B at X} and the node B can be expressed by the following equation (2).
V _X = V _Z − (1 + α) R ₂ I _R2
V _B = V _Z − (1 + α) R ₁ I _R1 (2)

Similarly, if Amp 16 is ideal, the voltage V _Y at the node _Y and the voltage V _{A at the} node _A are equal, and the following expression (3) is established.
R ₁ I _R1 = R ₂ I _R2 (3)

Therefore, the following formula (4) can be derived by summarizing the formulas (1) to (3).
V _X = V _B (4)
That is, as described above, the voltage difference between the voltage V _A at the node _A and the voltage V _{Y at the} node Y is detected by the _{Amp 16} and the feedback current I _Amp that eliminates the voltage difference is output, thereby outputting the node The potential difference between the voltage V _{X at X} and the voltage V _{B at} node B can be eliminated.

In order to satisfy the above formula (4), it is necessary to set the ratio of the values of the resistors R ₁ and αR ₁ equal to the ratio of the values of the resistors R ₂ and αR ₂ .

If the above way AMP 16 is ideal, the AMP 16, the voltage _{V Y} of the voltage _{V A} and the node Y of the node A equals the voltage _{V B} of the voltage _{V X} and the node B of the node X will be equal, mirror An output current I _OUT equal to the reference current I _REF flowing through the mirror source NMOS M ₀ flows through the previous NMOS M ₁ . However, in the actual Amp 16, an offset corresponding to the magnitude of G _m / gm is approximately generated between the voltage V _X at the node _X and the voltage V _{B at the} node B.

As described above, the IR drop due to the gate leakage current causes a difference between the voltage V _X at the node _X and the voltage V _{B at the} node B. In the current mirror circuit 10, this difference can be canceled out as the value of G _m / g _m increases. Accordingly, it is desired to increase the gain of the Amp 16, but attention must be paid to the relationship between the pole (Pole) of the Amp 16 and the pole outside the Amp 16.

Here, the pole is a point (frequency) at which the gain of the Amp 16 starts to decrease. For example, a graph of the operational characteristics of Amp 16 is assumed with the horizontal axis representing frequency characteristics and the vertical axis representing gain (see, for example, FIG. 5). In this graph, although up to a certain frequency that the gain does not change, when went frequency becomes high to reach the pole frequency, the gain is reduced at higher frequencies (in the case of FIG. 5, 10 ⁴ back and forth in a schematic ).

  When there is only one pole, the phase of the feedback signal to Amp 16 is shifted up to 90 ° at the maximum, so there is no risk of positive feedback. However, there is no possibility that Amp 16 and output node Z and nodes A and Y are poled. When the distance between the main Amp16 pole and other poles is short, the phase of the feedback signal to Amp16 easily shifts to a maximum of 180 °, so depending on the design There is a risk that the positive feedback is applied to Amp16 and oscillation occurs.

Therefore, when there are a plurality of poles, the frequency at which the poles are generated in the Amp 16 is designed to be sufficiently separated from other poles, thereby reducing the possibility that the Amp 16 will oscillate due to positive feedback. can do. Accordingly, as shown in FIG. 7, logically, it is not essential to provide the current source 14 and transistor M _2, in the design, it provided a current source 14 and transistor M ₂ is as described above because there is a merit that can be easily designed, as shown in FIG. 1, toward the structure in which a current source 14 and NMOSM ₂ is preferred.

Here, the reason why the internal pole and the Amp16 output pole can be separated by providing the current source 14 and the NMOS M2 will be described.
• The poles can be moved away by reducing the RC time constant directly visible at the output of Amp16.
A diode MOS is provided in order to reduce the RC time constant “R” (the diode MOS is provided, so that a current source is also required as a result).
-Lowering the Gm (lowering the gain) keeps the pole away and suppresses positive feedback.
This also improves the RC time constant of the output, so that the circuit characteristics of the embodiment are also improved.

  Next, a specific design example of the current mirror circuit 10 will be described.

For the current mirror circuit 10 of the present embodiment shown in FIG. 1 and the conventional current mirror circuit 40 shown in FIG. 8, specific values of each component (current value of reference current I _REF , NMOS transistor size and transconductance value) , Resistance value, capacitance value, etc.) were set and a simulation was carried out.

FIG. 9 is a circuit conceptual diagram of a specific design example of the conventional current mirror circuit shown in FIG. This figure shows the values set for each component of the conventional current mirror circuit 40 shown in FIG. That is, in the current mirror circuit 40 of FIG. 9, the reference current I _REF supplied from the current source 12 is 50 μA, the transistor sizes of NMOS M ₀ and M ₁ are W / L = 10 μm / 1.5 μm, and the transformers of NMOS M ₀ and M ₁ Conductance g _m = 0.5 mS, resistance R ₀ = 500 kΩ, and capacitance C ₀ = 100 pF.

FIG. 3 is a circuit conceptual diagram of a specific design example of the current mirror circuit of the present embodiment shown in FIG. This figure shows values set for each component of the current mirror circuit 10 of the present embodiment shown in FIG. That is, in the current mirror circuit 10 of FIG. 3, the reference current I _REF supplied from the current sources 12 and 14 is 50 μA, the transistor sizes of the NMOS M ₀ , M ₁ , and M ₂ are W / L = 10 μm / 1.5 μm, and the NMOS M ₀ , M ₁ , M ₂ transconductance g _m = 0.5 mS, resistance R ₁ , αR ₁ , R ₂ , αR ₂ = 10 kΩ, 500 kΩ, 0.5 kΩ, 25 kΩ, capacitance C ₀ = 100 pF, Amp16 pole frequency = 100 kHz, Amp16 transconductance G _m = 200 mS.

As described above, the current mirror circuit 10 of the present embodiment shown in FIG. 1 is obtained by applying the present invention to the conventional current mirror circuit 40 shown in FIG. Therefore, in the current mirror circuit 10 shown in FIG. 3, the reference current I _REF supplied from the current source 12, the transistor size W / L of the NMOS M ₀ , M ₁ , the transconductance g _m , and the value of the capacitance C ₀ are as shown in FIG. The current mirror circuit 40 shown in FIG. Also, the value of the combined resistance of the resistors R ₁ , αR ₁ , R ₂ , and αR ₂ is set to a value that is substantially the same as that of the resistor R ₀ .

Next, FIG. 10 is a circuit conceptual diagram showing a simulation result of the conventional current mirror circuit shown in FIG. As shown in the figure, in the conventional current mirror circuit 40, a result of simulation, the current flowing through the NMOSM ₀ of the mirror source is 50 .mu.A, the voltage at node X 'was 506MV. On the other hand, the current flowing through the NMOS M1 at the mirror destination was 30 μA, and the bias voltage at the node B ′ was 457 mV.

In the conventional current mirror circuit 40, the bias voltage at the node X ′ is 506 mV, whereas the bias voltage at the node B ′ is 457 mV, and the bias voltage varies greatly due to the influence of the gate leakage current. I understand. Therefore, while the current flowing through the NMOSM ₀ of the mirror source is 50 .mu.A, the current flowing through the NMOSM ₁ of the mirror destination next 30 .mu.A, are significantly reduced.

On the other hand, FIG. 4 is a circuit conceptual diagram showing a simulation result of the current mirror circuit of the present embodiment shown in FIG. As shown in the figure, in the current mirror circuit 10 of the present embodiment, the current flowing through the NMOSM ₀ of the mirror source is 52Myuei, the bias voltage at node X was 511MV. On the other hand, the current flowing through the NMOS M1 at the mirror destination was 49 μA, and the bias voltage at the node B was 502 mV.

In the current mirror circuit 10 of the present embodiment, the bias voltage at the node X is 511 mV, whereas the bias voltage at the node B is 502 mV, and it can be seen that the bias voltage hardly fluctuates. Current flowing through the NMOSM ₀ of the mirror source, although slightly increased the 52μA by the addition of such AMP 16, the current flowing through the NMOSM ₁ mirror destination 49μA, and the hardly decreased.

  As described above, the current mirror circuit 10 according to the present embodiment significantly reduces the variation in the bias voltage due to the influence of the gate leakage current, compared with the conventional current mirror circuit 40, and the current from the mirror source to the mirror destination with high accuracy. It was found that can be mirrored.

  Next, FIGS. 5 and 6 are graphs of simulation results representing the characteristics of the RC low-pass filter in the current mirror circuit. In these graphs, the vertical axis represents gain G (dB), and the horizontal axis represents frequency freq (Hz).

FIG. 5 shows a simulation result of the transfer function (Z → B) in the current mirror circuit of the present embodiment shown in FIG. The characteristics of the RC type low-pass filter are determined according to the time constants of the resistors R ₁ and αR ₁ and the capacitor C ₀ . As shown in this graph, the cut-off frequency of the RC low-pass filter of the current mirror circuit 10 of this embodiment shown in FIG. 3 is a frequency of 10 ⁴ schematically. Then, as the frequency of the input signal increases by 10 ¹ (10 times) therefrom, the gain of the output signal decreases by 20 dB (−20 dB / dec).

FIG. 6 shows a simulation result of the transfer function (X ′ → B ′) in the conventional current mirror circuit shown in FIG. 9 and the transfer function (X → B) in the current mirror circuit of the present embodiment shown in FIG. As shown in this graph, the cutoff frequency of the conventional current mirror circuit 40 shown in FIG. 9 is roughly between 10 ^{3 and} 10 ⁴ , and the cutoff frequency of the current mirror circuit of this embodiment shown in FIG. Generally, it is between 10 ^{4 and} 10 ⁵ , and the cutoff frequency is slightly lower in the conventional current mirror circuit 40. On the other hand, the amount of gain decrease at a frequency equal to or higher than the cut-off frequency has a graph crossing between 10 ⁵ to 10 ⁶ , and at a frequency higher than that, the current mirror circuit 10 of the present embodiment is a conventional current mirror circuit. Greater than 40. That is, good filter characteristics are shown.

Here, the graphs of the transfer functions of Z → B and X → B (FIGS. 5 and 6) are different because the circuits that affect the transfer function of the target system are completely different.
In FIG. 5 (Z → B), Amp 16 and current source 14 are added, but the circuit configuration is the same as in the prior art in the portion from Z to the mirror tip (the resistance value has increased by 10 kΩ, but can be ignored) Level), which shows that the characteristics have not changed from the conventional technology.
X → B has multiple poles in the system, especially in the first part, the first pole (−20 dB / dec) and the second pole (−40 dB / dec) are considered to be quite close It is done. After that, the characteristic is such that the graph has a third pole after passing through the zero point (the graph does not change. Becomes horizontal), so that the graph is wavy. That is, this is because the circuit such as Amp16 exists in the system.

Further, in FIG. 6 (X → B), the fact that the first pole of the prior art is shifted to the high frequency side is due to the effect of the gain of Amp 16 (expanded about 10 times). When it is reproduced by the resistance value of the filter, it is 80 kΩ, which indicates that “80 kΩ is sufficient if the band is wide”. However, the subsequent filter characteristics are better for the proposed circuit, and as a result, the proposed characteristics are better.
It should be noted that positive feedback is in the loop of A or Y → Z having the Amp16 system, and X → B is not a problem.

  As described above, the current mirror circuit 10 of the present embodiment has greatly improved noise reduction characteristics in the high-frequency region as compared with the conventional current mirror circuit 40 having the same bandwidth (cutoff frequency). I understand.

Note that the current mirror circuit 10 can also be configured using a PMOS instead of the NMOS M _{0 to} M ₂ . Further, the value of the reference current I _REF supplied from the current source 12 may be changed as appropriate, or the mirror ratio of the current mirror circuit 10 may be changed as appropriate. Further, the value of the reference current I _REF supplied from the current source 14 to the NMOS M ₂ may be appropriately changed separately from the reference current I _REF supplied from the current source 12. Further, the current sources 14 and NMOSM ₂ is desirably provided as needed. The capacitor C ₀ can be omitted, for example, by substituting it with the gate capacitance of a mirror-destination MOS transistor. Although it is not essential to provide a diode-connected MOS at the output of Amp, it is preferable to use a circuit configuration provided in consideration of the possibility of positive feedback due to poles.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention. For example, in this embodiment, the mirror ratio of the current mirror is described as 1. However, the present invention is not limited to the mirror ratio, and can be applied to other mirror ratios.

10, 40 Current mirror circuit 12, 14, 30 Current source 16 Amp
18 Input unit 20 Output unit 22 Bias voltage generation unit M _{0 to} M ₆ , M ₉ NMOS
_{M 7, M 8, M 10} PMOS
R ₀ , R ₁ , αR ₁ , R ₂ , αR ₂ resistance C ₀ , C ₁ capacitance

Claims (4)

In a current mirror circuit that mirrors the current flowing from the first current source to the gate and drain of the first MOS transistor serving as the mirror source to the current flowing through the second MOS transistor,
A fourth resistor, a second resistor, a first resistor and a third resistor connected in series in this order between the gate of the first MOS transistor and the gate of the second MOS transistor;
The node between the first resistor and the third resistor and the node between the second resistor and the fourth resistor are input, and the node between the first resistor and the second resistor is input. A differential amplifier circuit for output,
The third resistor is set to a resistance value greater than the first resistance, the fourth resistor is set to a resistance value greater than the second resistance, and the third resistance is the fourth resistance. A current mirror circuit characterized by being set to a resistance value larger than the resistance.   The ratio of the resistance values of the first resistor and the third resistor and the ratio of the resistance values of the second resistor and the fourth resistor are set to be equal to each other. The current mirror circuit described.   And a capacitor having one terminal connected to a node between the third resistor and the gate of the second MOS transistor, the first resistor, the third resistor, and the capacitor A current mirror circuit according to claim 1, wherein a low-pass filter is configured.   Furthermore, a second current source connected to a node between the first resistor and the second resistor, and a gate and a drain are connected to a node between the first resistor and the second resistor. The current mirror circuit according to claim 1, further comprising a third MOS transistor.

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