JP5527929B2 - 過電圧検出回路のための方法と装置 - Google Patents
過電圧検出回路のための方法と装置 Download PDFInfo
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- JP5527929B2 JP5527929B2 JP2007247329A JP2007247329A JP5527929B2 JP 5527929 B2 JP5527929 B2 JP 5527929B2 JP 2007247329 A JP2007247329 A JP 2007247329A JP 2007247329 A JP2007247329 A JP 2007247329A JP 5527929 B2 JP5527929 B2 JP 5527929B2
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- Prior art keywords
- circuit
- integrated circuit
- recording
- voltage
- overvoltage
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M19/00—Current supply arrangements for telephone systems
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
=====
(デバイスピン(Vpin)の値)を読み取る。
もし(Vpin>Vref)であれば、
(Pinx上で超える最大電圧値)を書き込む。
=====
Claims (9)
- 集積回路を過電圧イベントから保護するための装置であって、
電源が接続されるコネクタピンを有する集積回路チップ、
該電源を整流する電力管理デバイス、
上記コネクタピンと上記集積回路チップ上に含まれる少なくとも1つの回路デバイスとの間に接続されて上記集積回路チップ内に埋め込まれる過電圧イベント記録機構、を備え、前記過電圧イベント記録機構は、
過電圧イベントを記録する記録回路、
該集積回路チップに内蔵され、回路ブレーカ及びヒューズの少なくとも1つを備えた電気又は半導体のいずれか一方のタイプの1つ若しくは複数の検出回路であって、過電圧状態において短絡状態を発生させる1つ若しくは複数の検出回路を備え、
前記1つ若しくは複数の検出回路は、上記集積回路チップ上に短絡状態を発生させることによって上記少なくとも1つの回路デバイスを保護するものであり、該短絡状態によって該回路ブレーカ及び該ヒューズのどちらか一方が開放され、該短絡状態の特定が該回路ブレーカ及び該ヒューズの該少なくとも1つが飛ぶ状態によって可能となるものであり、
該過電圧イベント記録機構は並列接続された1以上の検出器回路及び少なくとも1つの記録回路からなる装置。 - 前記少なくとも1つの記録回路は、前記過電圧イベントを、後に前記イベントに関する情報を検索できる媒体に記録するように設計され、
前記1つ若しくは複数の検出回路は、前記集積回路チップ上の前記少なくとも1つの回路デバイスの指定された最大動作電圧をわずかに超える電圧で動作するように設計された請求項1記載の装置。 - 前記過電圧イベント記録機構がさらに、
メモリセル、及び
読み取り可能レジスタ
のうちの少なくとも1つを備える請求項1記載の装置。 - 前記過電圧イベント記録機構は直列接続された1以上の検出回路及び少なくとも1つの記録回路を備える請求項1記載の装置。
- 過電圧イベントが発生したときに、このようなイベントが発生したことの特定が、前記回路ブレーカの状態、前記ヒューズの状態及び前記読み取り可能レジスタの少なくとも1つの値の読出しのうちの少なくとも1つによる物理的観察によって行われる請求項3記載の装置。
- 電話デバイスのコネクタピンへ印加される電圧を検出するための装置であって、
外部電源から前記電話デバイスの集積回路への前記コネクタピンにおける電圧を許容するように設計された少なくとも1つの検出器回路からなり、該少なくとも1つの検出器回路が、
前記外部電源を制限する電源管理デバイス、
過電圧状態によって短絡状態をもたらすための、前記集積回路に内蔵された検出手段であって、電気及び半導体のいずれか一方のタイプの回路ブレーカ及びヒューズからなり、前記短絡状態によって前記回路ブレーカ及び前記ヒューズの少なくとも1つが開放され、該短絡状態の特定が該回路ブレーカ及び該ヒューズの該少なくとも1つが飛ぶ状態によって可能となっている、1つ若しくは複数の検出手段、及び
前記集積回路に埋め込まれ、前記過電圧イベントを記録するための、メモリセル及び読み取り可能レジスタの少なくとも1つからなる記録手段
を備え、
前記1つ若しくは複数の検出器回路及び少なくとも1つの記録回路が並列接続された装置。 - 前記少なくとも1つの検出器回路は、上記電話デバイスの前記集積回路上の少なくとも1つの回路デバイスの指定された最大動作電圧をわずかに超える電圧で動作するように設計された請求項6記載の装置。
- 過電圧イベントが発生したときに、このようなイベントが発生したことの特定を読み取り可能レジスタまたはメモリセルの少なくとも1つの値を読み取ることによって行う請求項6記載の装置。
- 前記電話デバイスの集積回路は、デジタル集積回路、アナログデジタル回路、混合信号集積回路及びメモリデバイス集積回路のうちの1つである請求項6記載の装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/526,522 US7630184B2 (en) | 2006-09-25 | 2006-09-25 | Method and apparatus for an over-voltage detection circuit |
US11/526,522 | 2006-09-25 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008124442A JP2008124442A (ja) | 2008-05-29 |
JP2008124442A5 JP2008124442A5 (ja) | 2010-01-07 |
JP5527929B2 true JP5527929B2 (ja) | 2014-06-25 |
Family
ID=38871940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007247329A Expired - Fee Related JP5527929B2 (ja) | 2006-09-25 | 2007-09-25 | 過電圧検出回路のための方法と装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7630184B2 (ja) |
EP (1) | EP1903765A3 (ja) |
JP (1) | JP5527929B2 (ja) |
KR (1) | KR101422279B1 (ja) |
CN (1) | CN101256207B (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010182921A (ja) * | 2009-02-06 | 2010-08-19 | Toshiba Corp | 放電検知回路 |
US8536893B2 (en) * | 2009-03-09 | 2013-09-17 | Qualcomm Incorporated | Circuit for measuring magnitude of electrostatic discharge (ESD) events for semiconductor chip bonding |
US8238068B2 (en) * | 2009-04-24 | 2012-08-07 | Silicon Laboratories Inc. | Electrical over-stress detection circuit |
US9118179B2 (en) | 2010-11-22 | 2015-08-25 | Freescale Semiconductor, Inc. | Integrated circuit device and method for detecting an excessive voltage state |
US8605401B2 (en) * | 2011-04-29 | 2013-12-10 | Altera Corporation | Systems and methods for securing a programmable device against an over-voltage attack |
CN102707123A (zh) * | 2012-06-21 | 2012-10-03 | 上海华岭集成电路技术股份有限公司 | 提高芯片电压测试精度方法 |
EP2849328A1 (en) | 2013-09-13 | 2015-03-18 | Dialog Semiconductor GmbH | An apparatus and method for a boost converter with improved electrical overstress (EOS) tolerance |
WO2016122473A1 (en) * | 2015-01-28 | 2016-08-04 | Hewlett Packard Enterprise Development Lp | Electrostatic discharge memristive element switching |
US10557881B2 (en) | 2015-03-27 | 2020-02-11 | Analog Devices Global | Electrical overstress reporting |
US9871373B2 (en) | 2015-03-27 | 2018-01-16 | Analog Devices Global | Electrical overstress recording and/or harvesting |
US20170093152A1 (en) * | 2015-09-25 | 2017-03-30 | Mediatek Inc. | Esd detection circuit |
US10338132B2 (en) | 2016-04-19 | 2019-07-02 | Analog Devices Global | Wear-out monitor device |
US10365322B2 (en) | 2016-04-19 | 2019-07-30 | Analog Devices Global | Wear-out monitor device |
GB2550977B (en) * | 2016-05-31 | 2020-07-22 | Cirrus Logic Int Semiconductor Ltd | Monitoring of devices |
JP6681357B2 (ja) * | 2017-03-10 | 2020-04-15 | 日立オートモティブシステムズ株式会社 | 半導体装置 |
US11024525B2 (en) | 2017-06-12 | 2021-06-01 | Analog Devices International Unlimited Company | Diffusion temperature shock monitor |
CN109406922B (zh) * | 2017-08-15 | 2020-09-22 | 昆山维信诺科技有限公司 | 电子产品及其测试方法和装置 |
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US5254953A (en) | 1990-12-20 | 1993-10-19 | Hewlett-Packard Company | Identification of pin-open faults by capacitive coupling through the integrated circuit package |
US5557209A (en) | 1990-12-20 | 1996-09-17 | Hewlett-Packard Company | Identification of pin-open faults by capacitive coupling through the integrated circuit package |
JP3477781B2 (ja) * | 1993-03-23 | 2003-12-10 | セイコーエプソン株式会社 | Icカード |
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JP3493096B2 (ja) * | 1996-06-07 | 2004-02-03 | 株式会社東芝 | 半導体集積回路、icカード、及びicカードシステム |
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FR2794867B1 (fr) * | 1999-06-08 | 2001-08-10 | St Microelectronics Sa | Circuit de detection et de memorisation d'une surtension |
JP4659175B2 (ja) | 2000-04-25 | 2011-03-30 | 富士通東芝モバイルコミュニケーションズ株式会社 | 携帯通信端末 |
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JP3966747B2 (ja) * | 2002-03-13 | 2007-08-29 | ローム株式会社 | 半導体集積回路装置 |
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-
2006
- 2006-09-25 US US11/526,522 patent/US7630184B2/en not_active Expired - Fee Related
-
2007
- 2007-09-21 EP EP07116995A patent/EP1903765A3/en not_active Withdrawn
- 2007-09-24 CN CN200710161850XA patent/CN101256207B/zh not_active Expired - Fee Related
- 2007-09-25 JP JP2007247329A patent/JP5527929B2/ja not_active Expired - Fee Related
- 2007-09-27 KR KR1020070097292A patent/KR101422279B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN101256207B (zh) | 2011-06-08 |
US20080074817A1 (en) | 2008-03-27 |
KR20080027755A (ko) | 2008-03-28 |
US7630184B2 (en) | 2009-12-08 |
JP2008124442A (ja) | 2008-05-29 |
EP1903765A3 (en) | 2010-12-22 |
EP1903765A2 (en) | 2008-03-26 |
CN101256207A (zh) | 2008-09-03 |
KR101422279B1 (ko) | 2014-07-22 |
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