JP5498836B2 - Manufacturing method of electronic equipment - Google Patents
Manufacturing method of electronic equipment Download PDFInfo
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- JP5498836B2 JP5498836B2 JP2010076709A JP2010076709A JP5498836B2 JP 5498836 B2 JP5498836 B2 JP 5498836B2 JP 2010076709 A JP2010076709 A JP 2010076709A JP 2010076709 A JP2010076709 A JP 2010076709A JP 5498836 B2 JP5498836 B2 JP 5498836B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本発明は、電子機器の製造方法に関するものである。 The present invention relates to a method for manufacturing an electronic device.
一般に、ICチップやCCDチップ等の電子機器は、素子を実装基板に固定し、素子と実装基板とをワイヤー等により電気的に接続した後、封止樹脂をワイヤー接続部に塗布して前記ワイヤーの保護を行うようにして製造されている。 In general, in an electronic device such as an IC chip or a CCD chip, an element is fixed to a mounting substrate, the element and the mounting substrate are electrically connected by a wire or the like, and then a sealing resin is applied to a wire connection portion to Manufactured to protect.
図5は従来技術による電子機器の一例で、液晶表示デバイスを示す図である。図5中の(A)は正面断面図、(B)は上面図、(C)は斜視図である。図5を参照し、従来技術による液晶表示デバイスを説明する。 FIG. 5 is a diagram showing a liquid crystal display device as an example of an electronic apparatus according to the prior art. 5A is a front sectional view, FIG. 5B is a top view, and FIG. 5C is a perspective view. A conventional liquid crystal display device will be described with reference to FIG.
図5に示すように、素子である液晶表示素子1は実装基板2に図示しない接着材を介して固定されている。前記液晶表示素子1は、ワイヤー3によって電気的接続が取られている。前記ワイヤー3は、液晶表示素子1に設けられた素子電極6と、実装基板2に設けられた実装基板電極7とを電気的に接続するものである。また、前記ワイヤー3は封止樹脂4及び5にて保護されている。
As shown in FIG. 5, the liquid
図5に示す液晶表示デバイスにおいては、前記封止樹脂4の流れ出しを防止するために前記封止樹脂4の外周に塗布され、封止樹脂4の流れ防止樹脂として機能する封止樹脂5が設けられた構成となっている。(例えば、特許文献1参照) In the liquid crystal display device shown in FIG. 5, a sealing resin 5 is provided which is applied to the outer periphery of the sealing resin 4 to prevent the sealing resin 4 from flowing out and functions as a flow preventing resin for the sealing resin 4. It is the composition which was made. (For example, see Patent Document 1)
図5に示す液晶デバイスの構造であると、前記封止樹脂4の流れ出しを防止することは可能であるが、前記封止樹脂4形成工程において、封止樹脂4内に気泡が混入することを防止できない。封止樹脂4の形成は、ワイヤー3の上方からワイヤー3と実装基板2に向かって適量の封止樹脂4を滴下して形成するのが一般的である。前記気泡は前記封止樹脂4形成時に、前記ワイヤー3の隙間、特に前記ワイヤー3の下部に封止樹脂4を浸透させる際に生じてしまう。
Although it is possible to prevent the sealing resin 4 from flowing out with the structure of the liquid crystal device shown in FIG. 5, in the sealing resin 4 formation step, bubbles are mixed in the sealing resin 4. It cannot be prevented. The sealing resin 4 is generally formed by dropping an appropriate amount of the sealing resin 4 from above the
前記現象は前記封止樹脂4を塗布する工程において、一般的に生じてしまう現象であり、前記ワイヤー3下部の空気を前記封止樹脂4にて追いやる際に気泡として前記封止樹脂内に混入してしまう。特に前記ワイヤー3下部に発生した気泡は電子機器(本先行技術では液晶表示デバイス)の信頼性試験時にワイヤー3の断線の原因となり、高信頼性電子機器の妨げとなってしまう。
The phenomenon is a phenomenon that generally occurs in the step of applying the sealing resin 4, and is mixed into the sealing resin as bubbles when the air below the
前記信頼性試験時の前記ワイヤー3の断線は、特に温度サイクル試験時に顕著であり、温度サイクル試験実施時に前記気泡は膨張と収縮を繰り返す。また、前記封止樹脂4も同様に膨張と収縮を行うが、前記ワイヤー3は金属であるため前記気泡及び封止樹脂の膨張と収縮に追従することは困難であり、結果前記ワイヤー3部分にストレスを与えることとなり断線の原因となってしまう。
The disconnection of the
本発明は、残留した気泡に起因するワイヤーの断線を防止することができる高信頼性の電子機器の製造方法を提供することを目的とするものである。 An object of this invention is to provide the manufacturing method of the highly reliable electronic device which can prevent the disconnection of the wire resulting from the residual bubble.
上記問題点に鑑み本発明の電子機器の製造方法は、基板上に素子を実装した後、前記基板上に設けられた基板電極と前記素子上に設けられた素子電極をワイヤーにて接続し、前記ワイヤーに封止樹脂を塗布して前記ワイヤーを保護する電子機器の製造方法において、前記基板の前記ワイヤー下方に設けられた注入口から前記ワイヤーに向かって前記封止樹脂を注入することにより、前記ワイヤーに前記封止樹脂を塗布すると共に、前記封止樹脂に混入した気泡を前記ワイヤー上方に押し出し、前記ワイヤー上方に押し出した前記気泡を外部からの物理的接触により除去することを特徴とする。 Method of manufacturing an electronic apparatus of the present invention in view of the above problem, after mounting the element on a substrate, an element electrode provided to the substrate electrode provided on the substrate on the device manually connected to the wire over the in wire over by applying a sealing resin to the manufacturing method of an electronic device to protect the wires, Kifutome resin before toward the wire over from injection port provided in the wire over lower sides of the substrate The sealing resin is applied to the wire, the bubbles mixed in the sealing resin are pushed out above the wire, and the bubbles pushed out above the wire are removed by physical contact from the outside. characterized in that it.
本発明により、素子と実装基板の電気的接続を行うワイヤー部分保護の封止樹脂形成時に前記封止樹脂内に気泡を生じさせにくく、また生じた際には、その除去を容易にすることを可能としたので、高信頼性の電子機器製造方法が得られる。 According to the present invention, it is difficult to cause bubbles in the sealing resin when forming the sealing resin for wire part protection for electrical connection between the element and the mounting substrate, and when it occurs, the removal can be facilitated. Therefore, a highly reliable electronic device manufacturing method can be obtained.
図1は本発明の一実施例に係る電子機器を示す図であり、(A)は上面図、(B)はX−X断面図を示している。1は素子であり、例えば半導体チップや固体撮像素子である。素子1は、実装基板2に、例えば熱伝導性の高い両面接着剤(不図示)で固定されており、素子1上の素子電極6と実装基板2上の実装基板電極7とは金属性のワイヤー3にて接続され電気的接続が取られている。
1A and 1B are diagrams showing an electronic apparatus according to an embodiment of the present invention, in which FIG. 1A is a top view and FIG. 1B is an XX cross-sectional view.
前記ワイヤー3の保護をするため、封止樹脂4が塗布されている。ここで、前記封止樹脂4の形成は、前記実装基板2に設けられた封止樹脂注入口9から前記ワイヤー3方向に注入を行う。また、前記封止樹脂注入口9は前記ワイヤー3の下部に設けられており、ワイヤー3のループと重なる位置関係にある。また、この封止樹脂注入口9は、素子電極6と実装基板電極7の間に位置している。
In order to protect the
前記封止樹脂注入口9は前記ワイヤー3の下部に設けられる事が重要であり、形状等は特に問わない、例えばガラスエポキシ基板であれば電極配線のための貫通孔を利用してもよい。またフレキシブル基板形状の際は素子1を固定するための補強基板(不図示)に貫通孔を設け、これを利用して封止樹脂を注入しても良い。
It is important that the sealing
図2は本発明の一実施例で、図1の電子機器の製造工程を示す図で、工程毎断面図である。本図は、封止樹脂4の形成状態を示すと共に、封止樹脂注入時に生じる気泡8の動きを示している。
FIG. 2 is a diagram showing a manufacturing process of the electronic device of FIG. This figure shows the formation state of the sealing resin 4 and the movement of the
まず、図2(A)に示すように、前記封止樹脂注入口9からワイヤー3方向(図中矢印方向)へ向けて封止樹脂4を注入する。徐々に封止樹脂4の注入作業を続けると、図2(B)に示すように封止樹脂4内に気泡8が発生する。
First, as shown in FIG. 2A, the sealing resin 4 is injected from the sealing
しかしながら、封止樹脂4の注入作業を継続すると、図2(C)に示すように、前記気泡8は封止樹脂4の上方への注入流動により、前記ワイヤー3上部に押し出され、封止樹脂4がワイヤー3を覆う状態になった時にはワイヤーの上方に完全に移動する。このような状態になれば、熱膨張による部材の伸縮があっても気泡8がワイヤー3にダメージを与えることがなくなる。また、上記の状態であれば、ワイヤー3上部に押し出された気泡8をワイヤー3に触れることなく除去することもできる。例えば先端の細い金属等を用いれば容易に除去することができる。
However, if the operation of injecting the sealing resin 4 is continued, as shown in FIG. 2C, the
上述の如く、前記封止樹脂注入口9から前記封止樹脂4の注入を行うことにより、封止樹脂4内に気泡8が生じた際も、前記封止樹脂注入口9から封止樹脂4を注入することにより気泡8はワイヤー3上部に追いやられる。気泡8は前記ワイヤー3上部に追いやられることにより前記封止樹脂4の上部から容易に除去が可能である。除去方法としては、例えば先端の細い金属等で潰す方法や、前記封止樹脂4の外部に追いやる方法が挙げられる。
As described above, by injecting the sealing resin 4 from the sealing
本実施例によると、前記ワイヤー3下部に前記気泡8が混入することを防止できるため、熱膨張によるワイヤーへのダメージをなくすことができるので信頼性の高い電子機器の製造が可能となる。
According to the present embodiment, since the
図3は本発明の他の実施例を示す図で、電子機器を示す図である。図3中の(A)は上面図、(B)はX−X断面図を示している。本実施例おいては素子1に設けられた素子電極6と、実装基板2に設けられた実装基板電極7が素子1の互いに対向する両辺部方向に存在しているが、構造及び効果は先の実施例と同じである。本実施例に示されるように、本発明によれば電極位置及び電極数、電極配置にとらわれることなく効果を得ることが可能である。
FIG. 3 is a view showing another embodiment of the present invention and is a view showing an electronic apparatus. 3A is a top view, and FIG. 3B is an XX cross-sectional view. In the present embodiment, the
図4は本発明の他の実施例を示す図であり、(A)は上面図、(B)はX−X断面図である。素子1として液晶表示素子を例としたものである。素子1は、実装基板2に例えば熱伝導性の高い両面接着剤で固定されており、前記素子1を構成する第一基板10上の素子電極6と実装基板2上の実装基板電極7とはワイヤー3にて電気的に接続を取っている。また、素子1を構成する第二基板11は例えば導電性樹脂12にて実装基板2との電気的接続を行っている。
4A and 4B are views showing another embodiment of the present invention, in which FIG. 4A is a top view and FIG. 4B is a cross-sectional view taken along line XX. The
前記ワイヤー3の保護を封止樹脂4で行っているが、前記封止樹脂4形成時には、前記実装基板2に設けられた封止樹脂注入口9から前記ワイヤー3方向に向けて封止樹脂4を注入する。また、前記封止樹脂注入口9は前記ワイヤー3の下部に設けられており、ワイヤーループに重なる位置で、且つ、前記素子電極6と前記実装基板電極7の間に位置している。
The
前記封止樹脂注入口9は前記ワイヤー3の下部に設けられる事が重要であり、形状等は特に問わない。例えばガラスエポキシ基板であれば電極配線のための貫通孔を利用してもよい。またフレキシブル基板形状の際は素子1を固定するための補強基板(不図示)に貫通孔を設け、これを利用して封止樹脂を注入しても良い。
It is important that the sealing
1 素子
2 実装基板
3 ワイヤー
4 封止樹脂
5 流れ出し防止用封止樹脂
6 素子電極
7 実装基板電極
8 気泡
9 封止樹脂注入口
10 第一基板
11 第二基板
DESCRIPTION OF
Claims (1)
前記基板の前記ワイヤー下方に設けられた注入口から前記ワイヤーに向かって前記封止樹脂を注入することにより、前記ワイヤーに前記封止樹脂を塗布すると共に、前記封止樹脂に混入した気泡を前記ワイヤー上方に押し出し、前記ワイヤー上方に押し出した前記気泡を外部からの物理的接触により除去することを特徴とした電子機器の製造方法。
After mounting the element on a substrate, an element electrode provided to the substrate electrode provided on the substrate on the device manually connected to the wire over, the wire is coated with a sealing resin to said wire over In the manufacturing method of electronic equipment to be protected,
By injecting Kifutome resin before toward the wire over from injection port provided in the wire over lower sides of the substrate, together with applying the sealing resin to the wire, mixed in the sealing resin A method of manufacturing an electronic device, wherein the air bubbles are pushed out above the wire and the air bubbles pushed out above the wire are removed by physical contact from the outside .
Priority Applications (1)
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JP2010076709A JP5498836B2 (en) | 2010-03-30 | 2010-03-30 | Manufacturing method of electronic equipment |
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JP2010076709A JP5498836B2 (en) | 2010-03-30 | 2010-03-30 | Manufacturing method of electronic equipment |
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JP2011210923A JP2011210923A (en) | 2011-10-20 |
JP5498836B2 true JP5498836B2 (en) | 2014-05-21 |
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