JP5496856B2 - Photovoltaic element manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a photovoltaic device.

  A structure and manufacturing method of a conventional photovoltaic element is disclosed in JP-A-9-129904. In a photovoltaic device having a stack of an intrinsic semiconductor layer made of amorphous material and a conductive semiconductor layer on substantially the entire surface of each surface of a crystalline semiconductor substrate, an amorphous material formed on one surface In order to prevent the semiconductor layer from undesirably wrapping around the side surface or the other surface of the semiconductor substrate, the characteristics of the semiconductor layer are reduced on both sides as compared with the semiconductor substrate, as shown in FIG. A crystalline semiconductor layer was formed.

JP-A-9-129904

In such a conventional element housing structure, the back surface side having a weak internal electric field is formed after the front surface side, so that the back surface interface of the substrate 7 can be scratched and soiled as the semiconductor layer is formed on the front surface side. Electrons are trapped and recombined, which does not contribute to power generation and may deteriorate output characteristics.

The present invention has been made to solve the above-described problems, and provides a method for manufacturing a photovoltaic device capable of preventing the interface having a weak internal electric field from being scratched or soiled. With the goal.

The method for manufacturing a photovoltaic device according to the present invention includes an n-type semiconductor substrate, an amorphous or microcrystalline n-type semiconductor layer provided on the semiconductor substrate, and an amorphous or microcrystalline material provided on the semiconductor substrate. And a step of forming the p-type semiconductor layer after the step of forming the n-type semiconductor layer.

  According to the present invention, the characteristics of the photovoltaic device are good.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows 1st Example of this invention, (a) is 1st process drawing, (b) is 2nd process drawing, (c) is 3rd process drawing. It is a figure which shows a comparative example, (a) is sectional drawing, (b) is an expanded sectional view of an edge part. 3 is a graph showing output characteristics of the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A first embodiment of the present invention will be described in detail with reference to the drawings. First, in the step shown in FIG. 1A, a crystalline semiconductor substrate 1 made of n-type single crystal silicon (resistivity = about 0.5 to 4 Ωcm) having a square of 100 mm square and a thickness of about 100 to 500 μm is formed. On the back surface, an amorphous silicon intrinsic semiconductor layer 2 (about 50 to 200 Å) and an n-type amorphous silicon conductive semiconductor layer 3 (about 100 to 500 Å) are sequentially formed by plasma CVD. Here, the intrinsic semiconductor layer 2 and the conductive semiconductor layer 3 are formed in a smaller area than the semiconductor substrate 1 using a metal mask. In addition, although amorphous silicon is used for the intrinsic semiconductor layer 2 and the conductive semiconductor layer 3, microcrystalline silicon may be used.

  Subsequently, in the process shown in FIG. 1B, an amorphous silicon intrinsic semiconductor layer 4 (about 50 to 200 mm) and a p-type non-layer are formed on substantially the entire surface of the semiconductor substrate 1 by plasma CVD. A conductive semiconductor layer 5 (about 50 to 150 mm) of crystalline silicon is sequentially formed. In addition, although the intrinsic semiconductor layer 4 and the conductive semiconductor layer 5 are made of amorphous silicon, microcrystalline silicon may be used.

  As described above, in this embodiment, the intrinsic semiconductor layer 2 and the conductive semiconductor layer 3 are formed from the back surface side of the semiconductor substrate 1. If a layer and a p-type conductive semiconductor layer are formed, good characteristics cannot be obtained. The reason why the characteristics are not good is that the internal electric field is weak on the back surface side of the photovoltaic element. Therefore, when a semiconductor layer is formed later on the back surface side, the back surface of the substrate 1 is formed as the semiconductor layer is formed on the front surface side in the previous step. It is considered that scratches, dirt, etc. are formed on the interface, electrons are trapped and recombined, and do not contribute to power generation and output characteristics deteriorate. Therefore, when the intrinsic semiconductor layer and the n-type conductive semiconductor layer are first formed from the back side of the substrate 1 as in the manufacturing process of this embodiment, there are few scratches, dirt, etc. on the back surface of the substrate 1, Good characteristics.

  Next, on both surfaces of the semiconductor substrate 1, transparent conductive films 6 and 7 made of ITO having substantially the same area are formed on the conductive semiconductor layers 3 and 5, respectively, and a silver paste or the like is formed thereon. The collector electrodes 8 and 9 are formed. The photovoltaic element of this example is completed through the above steps. In the present embodiment, since the transparent conductive film 6 is also used on the back side, power is generated even if light enters the back side.

  Next, in order to compare the output characteristics of this example, a photovoltaic element of a comparative example was prepared. The structure is shown in FIG. In the figure, the same structure as that of the present embodiment is denoted by the same reference numeral, and the description thereof is omitted. The difference from the above embodiment is that an amorphous silicon intrinsic semiconductor layer 12 (about 100 mm) and an n-type amorphous silicon conductive semiconductor are formed on substantially the entire back surface of the semiconductor substrate 1 by plasma CVD. The point is that the layer 13 (about 200 mm) was formed in sequence.

  And as explained in the prior art, when an amorphous semiconductor layer is formed on substantially the entire surface of the substrate 1, the amorphous semiconductor layer is also formed on the side surface or the other surface of the substrate 1, As shown in FIG. 2B, which is an enlarged cross-sectional view of the end portion (side surface side) of the substrate 1, an amorphous semiconductor layer is formed. In particular, in the manufacturing process of the present example and the comparative example, since the intrinsic semiconductor layer and the n-type conductive semiconductor layer are formed first from the back surface side of the substrate 1, the side surface of the substrate 1, particularly the end of the surface. In FIG. 3, an amorphous silicon pin layer is formed when viewed from the outside. Power generation as a photovoltaic element usually occurs mainly at the junction of the amorphous silicon pi / n-type crystal semiconductor substrate, and the output can be taken out from the front side and the back side. However, in the comparative example, an unusual amorphous pin layer is formed on the side surface and the end of the surface of the substrate 1. As a result, the generated electrons and holes disappear at this portion, and do not contribute to power generation, and the output characteristics are considered to deteriorate.

  FIG. 3 is a graph showing changes in output characteristics (Pmax) when the areas of the intrinsic semiconductor layer 2 and the n-type conductive semiconductor layer 3 on the back surface side are changed in the photovoltaic element of this example. The horizontal axis of the graph indicates the distance from the end of the semiconductor substrate 1, and this distance means that the semiconductor layer is formed in a small area by this distance all around the end of the substrate 1 ( This is the distance X shown in FIG. The vertical axis is a relative value when the output characteristic of the comparative example of FIG. At each distance X, the average output characteristics (Pmax) of 10 photovoltaic elements are plotted. In the photovoltaic element whose characteristics were measured, the substrate 1 was a 100 mm square, n-type single crystal silicon substrate 1 having a thickness of about 250 μm (resistivity = about 1 Ωcm, 100 surface texture shape), intrinsic semiconductor layer 2 is about 100 mm, the conductive semiconductor layer 3 is 200 mm, the intrinsic semiconductor layer 4 is about 100 mm, and the conductive semiconductor layer 5 is about 100 mm.

  As can be understood from the graph, when the distance from the edge of the substrate is within 1.4 to 3.2 mm, output characteristics equal to or higher than those of the comparative example can be obtained. Since the intrinsic semiconductor layer 2 and the n-type conductivity type semiconductor layer 3 have a small area, these layers do not adhere to the side surface and the end of the surface side of the substrate 1, so that the characteristics are not deteriorated and the area is reduced. Nevertheless, if the distance is X (about 1.4 to 3.2 mm), the generated electrons or holes can contribute to power generation to some extent without annihilation, and overall, as shown in FIG. It is considered that an output equal to or higher than that of the comparative example can be obtained. Further, if the resistivity value of the single crystal silicon substrate 1 is in the range of about 0.5 to 4 Ωcm, the same result as in FIG. 3 is obtained.

  Next, a second embodiment of the present invention will be described with reference to FIG. First, an amorphous silicon intrinsic semiconductor layer 22 (about 100 Å) is formed on substantially the entire back surface of a crystalline semiconductor substrate 21 made of n-type single crystal silicon having a thickness of about 500 μm by plasma CVD. .

  Next, an amorphous silicon intrinsic semiconductor layer 23 (about 100 Å) and a p-type amorphous silicon conductive semiconductor layer 24 (about 100 Å) are formed on substantially the entire surface of the substrate 21 (= light receiving surface). Sequentially formed.

  After that, an n-type amorphous silicon conductive semiconductor layer 25 (about 200 mm) is formed on the back surface of the intrinsic semiconductor layer 22 on substantially the entire back surface of the substrate 21.

  As described above, when an amorphous semiconductor layer is formed on substantially the entire surface of the substrate 21, the amorphous semiconductor layer is also formed on the side surface or the other surface of the substrate 21, but in this embodiment, As shown in FIG. 4, an np layer of amorphous silicon is formed on the side surface of the substrate 21, particularly on the edge of the surface, as viewed from the outside. Since this np layer does not generate electricity as a photovoltaic element, it is considered that the output characteristics of this embodiment are hardly affected.

  In this embodiment, by forming the intrinsic semiconductor layers on both sides prior to the formation of the conductive semiconductor layer, the semiconductor layer that deteriorates the characteristics is not formed on the side surface or the end of the surface side of the substrate. Since the layer is formed on substantially the entire surface of the substrate, there are few ineffective portions and the characteristics are good.

  1,21 Crystal-type semiconductor substrate, 2, 4, 22, 23 Intrinsic semiconductor layer 3, 5, 24, 25 Conductive semiconductor layer.

Claims (3)

And the n-type silicon semiconductor substrate having one surface and the other surface, and the n-type silicon semiconductor layer of amorphous or microcrystalline provided on the one surface of the silicon semiconductor substrate, the other of said silicon semiconductor substrate A method for producing a photovoltaic device comprising an amorphous or microcrystalline p-type silicon semiconductor layer provided on a surface,
A method for manufacturing a photovoltaic device, comprising a step of forming the p-type silicon semiconductor layer by a CVD method after the step of forming the n-type silicon semiconductor layer by a CVD method. In the manufacturing method of the photovoltaic device according to claim 1,
The photovoltaic element includes an intrinsic amorphous or microcrystalline first intrinsic silicon semiconductor layer between the one surface of the silicon semiconductor substrate and the n-type silicon semiconductor layer, and the silicon semiconductor substrate. A second intrinsic silicon semiconductor layer made of intrinsic amorphous or microcrystalline material between the other surface of the p-type silicon semiconductor layer, and
Forming the first intrinsic silicon semiconductor layer on the one surface of the silicon semiconductor substrate by a CVD method ;
Further seen including a step of forming by the CVD method the second intrinsic silicon semiconductor layer on the other surface of the silicon semiconductor substrate,
The first intrinsic silicon semiconductor layer, the n-type the silicon semiconductor layer after passing through the step of forming by the CVD method a second intrinsic silicon semiconductor layer, step a including formed by CVD said p-type silicon semiconductor layer Photovoltaic element manufacturing method. In the manufacturing method of the photovoltaic device according to claim 1 or 2 ,
Said one surface and the back surface of the silicon semiconductor substrate, the other surface as a light receiving surface of the silicon semiconductor substrate, photovoltaic forming the n-type silicon semiconductor layer and the p-type silicon semiconductor layer on said silicon semiconductor substrate A method for manufacturing a power element.

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