JP4854387B2 - Photovoltaic element - Google Patents

Photovoltaic element Download PDF

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JP4854387B2
JP4854387B2 JP2006147595A JP2006147595A JP4854387B2 JP 4854387 B2 JP4854387 B2 JP 4854387B2 JP 2006147595 A JP2006147595 A JP 2006147595A JP 2006147595 A JP2006147595 A JP 2006147595A JP 4854387 B2 JP4854387 B2 JP 4854387B2
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semiconductor layer
substrate
amorphous
back surface
photovoltaic element
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JP2006222469A (en
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孝裕 羽賀
浩一 廣瀬
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Sanyo Electric Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02E10/547—Monocrystalline silicon PV cells

Description

本発明は、光起電力素子に関する。   The present invention relates to a photovoltaic device.

従来の光起電力素子の構造、製造方法が、特開平９-１２９９０４号に開示されている。結晶系半導体基板の各面上の略全面に、非晶質からなる真性半導体層及び導電型半導体層の積層体を備えた光起電力素子においては、一方の面に形成される非晶質の半導体層が、半導体基板の側面又は他面に不所望に回り込むことにより特性が低下するのを防止するために、上記特許公報の図８に示されるように、両面において半導体基板より小面積に非晶質半導体層を形成していた。
特開平９-１２９９０４号公報 A structure and manufacturing method of a conventional photovoltaic element is disclosed in JP-A-9-129904. In a photovoltaic device having a stack of an intrinsic semiconductor layer made of amorphous material and a conductive semiconductor layer on substantially the entire surface of each surface of a crystalline semiconductor substrate, an amorphous material formed on one surface In order to prevent the semiconductor layer from undesirably wrapping around the side surface or the other surface of the semiconductor substrate, the characteristics of the semiconductor layer are reduced on both sides as compared with the semiconductor substrate, as shown in FIG. A crystalline semiconductor layer was formed.
JP-A-9-129904

このような従来の収納構造においては、上記のように回り込みによる特性低下は低減できるものの、半導体基板の外周部が無効部となるため、この分、特性が低くかった。   In such a conventional storage structure, although the characteristic deterioration due to the wraparound can be reduced as described above, the outer peripheral part of the semiconductor substrate becomes an ineffective part, and thus the characteristic is low.

本発明は、上述のような問題点を解決するために成されたものであり、回り込みによる特性低下を低減すると共に、無効部を低減する光起電力素子を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a photovoltaic device that reduces the degradation of characteristics due to wraparound and reduces the ineffective portion.

本発明は、結晶系半導体基板の両面上に、互いに逆導電型を有する非晶質又は微結晶からなる半導体層を設けてなる光起電力素子であって、表面側の前記半導体層は、前記基板の表面上の略全面に形成され、裏面側の前記半導体層は、マスクを用いて、前記基板の全周において端部から所定の距離を隔てて前記基板の裏面より小面積となるように形成されていることを特徴とする。 The present invention is a photovoltaic element comprising a semiconductor layer made of amorphous or microcrystalline having opposite conductivity types on both surfaces of a crystalline semiconductor substrate, wherein the semiconductor layer on the surface side is is formed on the substantially whole of the surface of the substrate, the semiconductor layer on the back side, using a mask, such that the small area from the back surface of the substrate from the end portion at a predetermined distance in the entire circumference of the substrate It is formed .

また他の本発明は、結晶系半導体基板の表面上に、非晶質又は微結晶からなる真性半導体層及び一導電型を有する非晶質又は微結晶からなる半導体層をこの順序で有し、前記基板の裏面上に、非晶質又は微結晶からなる真性半導体層及び前記一導電型と逆導電型の非晶質又は微結晶からなる半導体層をこの順序で有する光起電力素子であって、前記表面側の前記各半導体層は、前記基板の表面上の略全面に形成され、前記裏面側の前記各半導体層は、マスクを用いて、前記基板の全周において端部から所定の距離を隔てて前記基板の裏面より小面積となるように形成されていることを特徴とする。 Another aspect of the present invention includes an intrinsic semiconductor layer made of amorphous or microcrystalline material and a semiconductor layer made of amorphous or microcrystalline material having one conductivity type in this order on the surface of the crystalline semiconductor substrate. A photovoltaic element comprising an intrinsic semiconductor layer made of amorphous or microcrystalline material and a semiconductor layer made of amorphous or microcrystalline material having a conductivity type opposite to that of the one conductive type on the back surface of the substrate in this order. Each of the semiconductor layers on the front surface side is formed on substantially the entire surface of the surface of the substrate, and each of the semiconductor layers on the back surface side is formed at a predetermined distance from an end portion on the entire circumference of the substrate using a mask. It is characterized by being formed so as to have a smaller area than the back surface of the substrate with a gap therebetween .

本発明において、裏面側の半導体層が、マスクを用いて、基板の全周において端部から所定の距離を隔てて基板の裏面より小面積となるように形成されているので、基板の側面又は表面側の端部に、裏面側の半導体層が形成されることなく、出力特性の低下が少ない。加えて、表面側の半導体は略全面に形成されているので、無効部が少なく、特性が良好である。 In the present invention, the semiconductor layer on the back surface side is formed so as to have a smaller area than the back surface of the substrate at a predetermined distance from the end portion of the entire circumference of the substrate using a mask. The semiconductor layer on the back surface side is not formed at the end portion on the front surface side, so that the output characteristics are hardly deteriorated. In addition, since the semiconductor on the surface side is formed on substantially the entire surface, there are few ineffective portions and the characteristics are good.

以下、図面に基づいて本発明の実施形態を詳述する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

本発明の第1実施例を、図面を用いて、詳細に説明する。まず、図１（ａ）に示す工程において、１００ｍｍ角の正方形で、厚さ約１００〜５００μmのｎ型の単結晶シリコン（抵抗率＝約０．５〜4Ωｃｍ）からなる結晶系半導体基板１の裏面上に、プラズマＣＶＤ法を用いて非晶質シリコンの真性半導体層２（約５０〜２００Å）、及びｎ型非晶質シリコンの導電型半導体層３（約１００〜５００Å）を順次形成する。ここで、真性半導体層２及び導電型半導体層３は、金属マスクを用いて、半導体基板１より小面積に形成される。また、真性半導体層２、導電型半導体層３には、非晶質シリコンを用いているが、微結晶シリコンを用いても良い。   A first embodiment of the present invention will be described in detail with reference to the drawings. First, in the step shown in FIG. 1A, a crystalline semiconductor substrate 1 made of n-type single crystal silicon (resistivity = about 0.5 to 4 Ωcm) having a square of 100 mm square and a thickness of about 100 to 500 μm is formed. On the back surface, an amorphous silicon intrinsic semiconductor layer 2 (about 50 to 200 Å) and an n-type amorphous silicon conductive semiconductor layer 3 (about 100 to 500 Å) are sequentially formed by plasma CVD. Here, the intrinsic semiconductor layer 2 and the conductive semiconductor layer 3 are formed in a smaller area than the semiconductor substrate 1 using a metal mask. In addition, although amorphous silicon is used for the intrinsic semiconductor layer 2 and the conductive semiconductor layer 3, microcrystalline silicon may be used.

続いて、図１（ｂ）に示す工程において、半導体基板１の表面上の略全面に、プラズマＣＶＤ法を用いて非晶質シリコンの真性半導体層４（約５０〜２００Å）、及びｐ型非晶質シリコンの導電型半導体層５（約５０〜１５０Å）を順次形成する。また、真性半導体層４、導電型半導体層５には、非晶質シリコンを用いているが、微結晶シリコンを用いても良い。   Subsequently, in the process shown in FIG. 1B, an amorphous silicon intrinsic semiconductor layer 4 (about 50 to 200 mm) and a p-type non-layer are formed on substantially the entire surface of the semiconductor substrate 1 by plasma CVD. A conductive semiconductor layer 5 (about 50 to 150 mm) of crystalline silicon is sequentially formed. In addition, although the intrinsic semiconductor layer 4 and the conductive semiconductor layer 5 are made of amorphous silicon, microcrystalline silicon may be used.

以上のように、本実施例においては、半導体基板１の裏面側より、真性半導体層２及び導電型半導体層３を形成しているが、仮に、半導体基板１の表面側から最初に、真性半導体層及びｐ型導電型半導体層を形成するなら、良好な特性を得ることができない。特性が良くない理由としては、光起電力素子の裏面側においては内部電界が弱いので、裏面側に後から半導体層を形成すると、前工程で表面側に半導体層を形成するに伴い基板１裏面界面に傷、汚れ等ができ、電子がトラップされ、再結合して発電に寄与せず出力特性が低下するものと考えられる。よって、本実施例の製造工程のように、基板１の裏面側から最初に、真性半導体層及びｎ型導電型半導体層を形成する場合には、基板１裏面界面の傷、汚れ等が少なく、特性が良好である。   As described above, in this embodiment, the intrinsic semiconductor layer 2 and the conductive semiconductor layer 3 are formed from the back surface side of the semiconductor substrate 1. If a layer and a p-type conductive semiconductor layer are formed, good characteristics cannot be obtained. The reason why the characteristics are not good is that the internal electric field is weak on the back surface side of the photovoltaic element. Therefore, when a semiconductor layer is formed later on the back surface side, the back surface of the substrate 1 is formed as the semiconductor layer is formed on the front surface side in the previous step. It is considered that scratches, dirt, etc. are formed on the interface, electrons are trapped and recombined, and do not contribute to power generation and output characteristics deteriorate. Therefore, when the intrinsic semiconductor layer and the n-type conductive semiconductor layer are first formed from the back side of the substrate 1 as in the manufacturing process of this embodiment, there are few scratches, dirt, etc. on the back surface of the substrate 1, Good characteristics.

次に、半導体基板１の両面において、導電型半導体層３、５上に、各々、これらと略同面積のＩＴＯからなる透明導電膜６、７を形成し、これらの上に、銀ペースト等からなる集電極８，９を形成する。以上の工程にて、本実施例の光起電力素子が完成する。なお、本実施例では、裏面側においても透明導電膜６を採用しているので、裏面側に光が入射しても発電される。   Next, on both surfaces of the semiconductor substrate 1, transparent conductive films 6 and 7 made of ITO having substantially the same area are formed on the conductive semiconductor layers 3 and 5, respectively, and a silver paste or the like is formed thereon. The collector electrodes 8 and 9 are formed. The photovoltaic element of this example is completed through the above steps. In the present embodiment, since the transparent conductive film 6 is also used on the back side, power is generated even if light enters the back side.

次に、本実施例の出力特性を比較するために、比較例の光起電力素子を作成した。その構造を、図２に示す。図においては、本実施例と同一の構造については、同一の符号を付し、説明を省略する。上記実施例との違いは、半導体基板１の裏面上の略全面に、プラズマＣＶＤ法を用いて非晶質シリコンの真性半導体層１２（約１００Å）、及びｎ型非晶質シリコンの導電型半導体層１３（約２００Å）を順次形成した点である。   Next, in order to compare the output characteristics of this example, a photovoltaic element of a comparative example was prepared. The structure is shown in FIG. In the figure, the same structure as that of the present embodiment is denoted by the same reference numeral, and the description thereof is omitted. The difference from the above embodiment is that an amorphous silicon intrinsic semiconductor layer 12 (about 100 mm) and an n-type amorphous silicon conductive semiconductor are formed on substantially the entire back surface of the semiconductor substrate 1 by plasma CVD. The point is that the layer 13 (about 200 mm) was formed in sequence.

そして、従来の技術で説明したように、基板１の略全面に非晶質半導体層を形成するとき、基板１の側面又は他面にも、非晶質半導体層が形成されることになり、基板１の端部（側面側）の拡大断面図である図２（ｂ）に示されるように、非晶質半導体層が形成されることになる。特に、本実施例及び比較例の製造工程においては、基板１の裏面側から最初に、真性半導体層及びｎ型導電型半導体層が形成されるので、基板１の側面、特に、表面の端部において、外側から見て、非晶質シリコンのｐｉｎ層が形成されることになる。光起電力素子としての発電は、通常は、主に、非晶質シリコンｐｉ／ｎ型結晶系半導体基板の接合で発生し、表面側、裏面側より出力を取り出すことができる。しかしながら、比較例においては、基板１の側面、表面の端部に通常でない非晶質層のｐｉｎ層が形成される。これにより、発生した電子・正孔がこの部分で消滅し、発電に寄与せず、出力特性が低下すると考えられる。   And as explained in the prior art, when an amorphous semiconductor layer is formed on substantially the entire surface of the substrate 1, the amorphous semiconductor layer is also formed on the side surface or the other surface of the substrate 1, As shown in FIG. 2B, which is an enlarged cross-sectional view of the end portion (side surface side) of the substrate 1, an amorphous semiconductor layer is formed. In particular, in the manufacturing process of the present example and the comparative example, since the intrinsic semiconductor layer and the n-type conductive semiconductor layer are formed first from the back surface side of the substrate 1, the side surface of the substrate 1, particularly the end of the surface. In FIG. 3, an amorphous silicon pin layer is formed when viewed from the outside. Power generation as a photovoltaic element usually occurs mainly at the junction of the amorphous silicon pi / n-type crystal semiconductor substrate, and the output can be taken out from the front side and the back side. However, in the comparative example, an unusual amorphous pin layer is formed on the side surface and the end of the surface of the substrate 1. As a result, the generated electrons and holes disappear at this portion, and do not contribute to power generation, and the output characteristics are considered to deteriorate.

図３は、本実施例の光起電力素子において、裏面側の真性半導体層２及びｎ型導電型半導体層３の面積を変更したときの、出力特性（Ｐｍａｘ）変化を示すグラフである。グラフの横軸は、半導体基板１の端部からの距離を示し、この距離は、基板１の端部より全周でこの距離だけ小面積に、半導体層を形成したことを意味している（図１（ｂ）に示す距離Ｘである）。また、縦軸は、図２の比較例の出力特性を１としたときの相対値である。各距離Ｘにおいて、１０個の光起電力素子の平均出力特性（Ｐｍａｘ）が、プロットされている。なお、特性測定をした光起電力素子においては、基板１が１００ｍｍ角、厚さ約２５０μmのｎ型の単結晶シリコン基板１（抵抗率＝約１Ωｃｍ、１００面の表面テクスチャー形状）、真性半導体層２が約１００Å、導電型半導体層３が２００Å、真性半導体層４が約１００Å、導電型半導体層５が約１００Åである。   FIG. 3 is a graph showing changes in output characteristics (Pmax) when the areas of the intrinsic semiconductor layer 2 and the n-type conductive semiconductor layer 3 on the back surface side are changed in the photovoltaic element of this example. The horizontal axis of the graph indicates the distance from the end of the semiconductor substrate 1, and this distance means that the semiconductor layer is formed in a small area by this distance all around the end of the substrate 1 ( This is the distance X shown in FIG. The vertical axis is a relative value when the output characteristic of the comparative example of FIG. At each distance X, the average output characteristics (Pmax) of 10 photovoltaic elements are plotted. In the photovoltaic element whose characteristics were measured, the substrate 1 was a 100 mm square, n-type single crystal silicon substrate 1 having a thickness of about 250 μm (resistivity = about 1 Ωcm, 100 surface texture shape), intrinsic semiconductor layer 2 is about 100 mm, the conductive semiconductor layer 3 is 200 mm, the intrinsic semiconductor layer 4 is about 100 mm, and the conductive semiconductor layer 5 is about 100 mm.

グラフより理解できるように、基板の端部からの距離が１．４〜３．２ｍｍ以内であれば、比較例と同等以上の出力特性が得ることができる。真性半導体層２及びｎ型導電型半導体層３が小面積であるので、基板１の側面、表面側の端部にこれら層が付着することないので特性が低下することがないと共に、小面積にもかかわらず、距離X（約１．４〜３．２ｍｍ）であれば、発電された電子或は正孔が消滅することなくある程度発電に寄与でき、総合的には、図３に示すように、比較例と同等以上出力が得ることができると考えられる。また、単結晶シリコン基板１の抵抗率の値は、約０．５〜４Ωcmの範囲であれば、図３と同様の結果となる。   As can be understood from the graph, when the distance from the edge of the substrate is within 1.4 to 3.2 mm, output characteristics equal to or higher than those of the comparative example can be obtained. Since the intrinsic semiconductor layer 2 and the n-type conductivity type semiconductor layer 3 have a small area, these layers do not adhere to the side surface and the end of the surface side of the substrate 1, so that the characteristics are not deteriorated and the area is reduced. Nevertheless, if the distance is X (about 1.4 to 3.2 mm), the generated electrons or holes can contribute to power generation to some extent without annihilation, and overall, as shown in FIG. It is considered that an output equal to or higher than that of the comparative example can be obtained. Further, if the resistivity value of the single crystal silicon substrate 1 is in the range of about 0.5 to 4 Ωcm, the same result as in FIG. 3 is obtained.

次に、本発明の第2実施例を、図４を用いて説明する。まず、厚さ約５００μmのｎ型の単結晶シリコンからなる結晶系半導体基板２１の裏面上の略全面に、プラズマＣＶＤ法を用いて非晶質シリコンの真性半導体層２２（約１００Å）を形成する。   Next, a second embodiment of the present invention will be described with reference to FIG. First, an amorphous silicon intrinsic semiconductor layer 22 (about 100 Å) is formed on substantially the entire back surface of a crystalline semiconductor substrate 21 made of n-type single crystal silicon having a thickness of about 500 μm by plasma CVD. .

次に、基板２１の表面（＝受光面）上の略全面に、非晶質シリコンの真性半導体層２３（約１００Å）、及びｐ型非晶質シリコンの導電型半導体層２４（約１００Å）を順次形成する。   Next, an amorphous silicon intrinsic semiconductor layer 23 (about 100 Å) and a p-type amorphous silicon conductive semiconductor layer 24 (about 100 Å) are formed on substantially the entire surface of the substrate 21 (= light receiving surface). Sequentially formed.

その後、裏面側の真性半導体層２２上に、基板２１の裏面上の略全面に、ｎ型非晶質シリコンの導電型半導体層２５（約２００Å）を形成する。   After that, an n-type amorphous silicon conductive semiconductor layer 25 (about 200 mm) is formed on the back surface of the intrinsic semiconductor layer 22 on substantially the entire back surface of the substrate 21.

上述したように、基板２１の略全面に非晶質半導体層を形成するとき、基板２１の側面又は他面にも、非晶質半導体層が形成されることになるが、本実施例においては、図４に示すように、基板２１の側面、特に、表面の端部において、外側から見て、非晶質シリコンのｎｐ層が形成される。このｎｐ層では、光起電力素子として発電することがないので、本実施例の出力特性に影響を及ぼすことは少ないと考えられる。   As described above, when an amorphous semiconductor layer is formed on substantially the entire surface of the substrate 21, the amorphous semiconductor layer is also formed on the side surface or the other surface of the substrate 21, but in this embodiment, As shown in FIG. 4, an np layer of amorphous silicon is formed on the side surface of the substrate 21, particularly on the edge of the surface, as viewed from the outside. Since this np layer does not generate electricity as a photovoltaic element, it is considered that the output characteristics of this embodiment are hardly affected.

本実施例においては、両面の真性半導体層を、導電型半導体層の形成に先立って形成することにより、基板の側面又は表面側の端部において、特性を低下させる半導体層が形成されず、半導体層は基板の略全面に形成されるので無効部が少なく、特性が良好である。   In this embodiment, by forming the intrinsic semiconductor layers on both sides prior to the formation of the conductive semiconductor layer, the semiconductor layer that deteriorates the characteristics is not formed on the side surface or the end of the surface side of the substrate. Since the layer is formed on substantially the entire surface of the substrate, there are few ineffective portions and the characteristics are good.

本発明の第1実施例を示す断面図であり、（a）は第1工程図、（ｂ）は第2工程図、（ｃ）は第3工程図である。BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows 1st Example of this invention, (a) is 1st process drawing, (b) is 2nd process drawing, (c) is 3rd process drawing. 比較例を示す図であり、（ａ）は断面図、（ｂ）は端部の拡大断面図である。It is a figure which shows a comparative example, (a) is sectional drawing, (b) is an expanded sectional view of an edge part. 本発明の第1実施例の出力特性を示すグラフである。3 is a graph showing output characteristics of the first embodiment of the present invention. 本発明の第2実施例を示す断面図である。FIG. 6 is a cross-sectional view showing a second embodiment of the present invention.

符号の説明Explanation of symbols

１、２１ 結晶系半導体基板
２、４、２２、２３ 真性半導体層
３、５、２４、２５ 導電型半導体層 1,21 Crystalline semiconductor substrate 2, 4, 22, 23 Intrinsic semiconductor layer 3, 5, 24, 25 Conductive semiconductor layer

Claims (5)

結晶系半導体基板の両面上に、互いに逆導電型を有する非晶質又は微結晶からなる半導体層を設けてなる光起電力素子であって、
表面側の前記半導体層は、前記基板の表面上の略全面に形成され、
裏面側の前記半導体層は、マスクを用いて、前記基板の全周において端部から所定の距離を隔てて内側の領域に形成され、前記基板の裏面より小面積となるように形成されていることを特徴とする光起電力素子。 A photovoltaic device comprising semiconductor layers made of amorphous or microcrystalline materials having opposite conductivity types on both surfaces of a crystalline semiconductor substrate,
The semiconductor layer on the front side is formed on substantially the entire surface of the surface of the substrate,
The semiconductor layer on the back surface side is formed in an inner region at a predetermined distance from an end portion of the entire circumference of the substrate using a mask so as to have a smaller area than the back surface of the substrate. A photovoltaic device characterized by the above. 前記所定の距離は、１．４〜３．２ｍｍの範囲であることを特徴とする請求項１記載の光起電力素子。   The photovoltaic element according to claim 1, wherein the predetermined distance is in a range of 1.4 to 3.2 mm. 前記半導体基板と、前記半導体層との間に、非晶質又は微結晶からなる真性半導体層を介在したことを特徴とする請求項１又は２記載の光起電力素子。   3. The photovoltaic element according to claim 1, wherein an intrinsic semiconductor layer made of amorphous or microcrystal is interposed between the semiconductor substrate and the semiconductor layer. 結晶系半導体基板の表面上に、非晶質又は微結晶からなる真性半導体層及び一導電型を有する非晶質又は微結晶からなる半導体層をこの順序で有し、前記基板の裏面上に、非晶質又は微結晶からなる真性半導体層及び前記一導電型と逆導電型の非晶質又は微結晶からなる半導体層をこの順序で有する光起電力素子であって、
前記表面側の前記各半導体層は、前記基板の表面上の略全面に形成され、
前記裏面側の前記各半導体層は、マスクを用いて、前記基板の全周において端部から所定の距離を隔てて内側の領域に形成され、前記基板の裏面より小面積となるように形成されていることを特徴とする光起電力素子。 On the surface of the crystalline semiconductor substrate, there is an intrinsic semiconductor layer made of amorphous or microcrystalline and a semiconductor layer made of amorphous or microcrystalline having one conductivity type in this order, and on the back surface of the substrate, A photovoltaic element having an intrinsic semiconductor layer made of amorphous or microcrystal and a semiconductor layer made of amorphous or microcrystalline of the opposite conductivity type to the one conductivity type in this order,
Each of the semiconductor layers on the surface side is formed on substantially the entire surface of the surface of the substrate,
Each of the semiconductor layers on the back surface side is formed in an inner region at a predetermined distance from an end portion of the entire circumference of the substrate using a mask so as to have a smaller area than the back surface of the substrate. A photovoltaic device characterized by comprising: 前記所定の距離は、１．４〜３．２ｍｍの範囲であることを特徴とする請求項４記載の光起電力素子。   The photovoltaic device according to claim 4, wherein the predetermined distance is in a range of 1.4 to 3.2 mm.
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