JP5496838B2 - Aggregate substrate for semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a collective substrate for a semiconductor device such as a light emitting diode (LED) and a method for manufacturing the same.

  There is a concave light emitting device as a light emitting device for LED (see Patent Document 1). The concave light-emitting device includes a lower substrate on which a metal pattern is formed, and an upper substrate (peripheral wall body) that is bonded onto the lower substrate with an adhesive. A hole is provided in the upper substrate, and an LED element is mounted in the hole. Thereby, since the light from the LED element is blocked from being emitted in the lateral direction of the concave light emitting device, the light is emitted only forward, and the use efficiency of the emitted light is increased.

JP 2001-144333 A

  However, when the above-described conventional concave light emitting device is manufactured alone, the manufacturing efficiency is low, and as a result, the manufacturing cost increases.

  Accordingly, the present invention provides a collective substrate for a semiconductor device, for example, a collective substrate for a light-emitting device for LED, and aims to reduce the manufacturing cost of the above-described semiconductor device, for example, a light-emitting device for LED.

  In order to solve the above-described problems, an aggregate substrate for a semiconductor device according to the present invention has a semiconductor element mounting region composed of a plurality of unit regions arranged in a row and a semiconductor element non-mounting region surrounding the semiconductor element mounting region. And a lower collective substrate made of a metal pattern formed on the insulating substrate and a part of the insulating substrate, and attached to the lower collective substrate via an adhesive layer, corresponding to each unit region of the semiconductor element mounting region And an upper assembly board having an auxiliary through hole corresponding to a semiconductor element housing through hole and a semiconductor element non-mounting region, and the metal pattern of the lower assembly board is not formed in the auxiliary through hole and the outermost semiconductor element housing through hole. The metal pattern non-formation region that is at least partially overlapped with the region and is exposed in the auxiliary through hole and the innermost semiconductor element housing through hole is continuous on the insulating substrate. Thereby, an electrical short circuit of the metal pattern in the endmost unit region of the semiconductor element mounting region can be prevented.

  Moreover, a metal plating layer is provided on the metal pattern exposed inside the through hole for accommodating semiconductor elements and the auxiliary through hole.

  The method for manufacturing a collective substrate for a semiconductor device according to the present invention includes a semiconductor element mounting region composed of a plurality of unit regions arranged in a row and a semiconductor element non-mounting region surrounding the semiconductor element mounting region, and an insulating substrate. And a step of preparing a lower assembly substrate composed of a metal pattern formed on a part of the insulating substrate, and corresponding to a semiconductor element housing through hole corresponding to each unit area of the semiconductor element mounting area and a semiconductor element non-mounting area A step of preparing the upper assembly substrate having the auxiliary through-hole, and the auxiliary through-hole and the through hole for accommodating the semiconductor element at least partially overlap the metal pattern non-formation region of the lower assembly substrate, And a metal pattern non-formation region exposed in the outermost semiconductor element housing through hole includes a step of overlapping and pasting so as to be continuous on the insulating substrate. Further, after the step of bonding the upper collective substrate to the lower collective substrate, a step of forming a metal plating layer on the metal pattern exposed inside the auxiliary through hole and the through hole for housing a semiconductor element by an electrolytic plating method is provided.

  According to the present invention, the manufacturing cost of the light emitting device for the semiconductor device can be reduced by the collective substrate for the semiconductor device, and the electrical short circuit of the metal pattern in the outermost unit region of the collective substrate for the semiconductor device can be prevented. Can improve the manufacturing cost.

It is a figure for demonstrating the manufacturing method of the lower assembly substrate as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the lower assembly substrate as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the lower assembly substrate as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the upper assembly board | substrate as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the upper assembly board | substrate as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the aggregate substrate for semiconductor devices as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the aggregate substrate for semiconductor devices as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the aggregate substrate for semiconductor devices as a comparative example, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a photograph which shows the dent of the adhesive sheet in FIG. 7, and the plating solution residue of a metal pattern. It is a figure for demonstrating the manufacturing method of the lower assembly board | substrate as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the lower assembly board | substrate as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the lower assembly board | substrate as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the upper assembly board | substrate as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). It is a figure for demonstrating the manufacturing method of the upper assembly board | substrate as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the manufacturing method of the aggregate substrate for semiconductor devices as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). . BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the manufacturing method of the aggregate substrate for semiconductor devices as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). . BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the manufacturing method of the aggregate substrate for semiconductor devices as embodiment which concerns on this invention, Comprising: (A) is a top view, (B) is the BB sectional drawing of (A). . It is a photograph which shows the adhesive sheet and metal pattern in FIG.

  Prior to the description of the embodiments of the present invention, a manufacturing method of a collective substrate for a semiconductor device as a comparative example will be described with reference to FIGS.

  1 to 3 are diagrams for explaining a method of manufacturing a lower assembly substrate of a comparative example. 1 to 3 is a region for mounting a semiconductor element, for example, a region for mounting a light emitting element for LED, and is a region where a semiconductor device is obtained. A plurality of unit regions to be semiconductor devices after dicing are arranged in a row, and in FIG. 1 to FIG. 3, four unit regions in the X direction are arranged in four rows in the Y direction. Has been. On the other hand, the outside of the alternate long and short dash line is a region where no semiconductor element is mounted, for example, a region where LED light emitting elements are not mounted. The LED light emitting element non-mounting area is an area that does not become a light emitting device after dicing, but the metal pattern is formed in both the LED light emitting element mounting area and the LED light emitting element non-mounting area.

  First, referring to FIG. 1, copper (Cu) foil layers 12 a and 12 b having a thickness of about 10 to 20 μm are attached to the front and back of an insulating base material 11 made of epoxy resin or the like. The copper foil layer 12b is patterned so that the copper foil at the location where the filled via is to be formed is removed by photolithography / etching. The insulating base material 11 is dug until the copper foil layer 12a is exposed by irradiating a laser to the portion where the copper foil of the copper foil layer 12b is removed. The diameter of the hole at this time is about 0.05 to 0.2 mm.

  Next, referring to FIG. 2, copper (Cu) plating layers 14a and 14b having a thickness of about 30 μm are formed on the copper foil layers 12a and 12b by an electroless plating method. As a result, the copper plating layer 14 b is also embedded in the through hole 13, and the filled via 15 is formed in the through hole 13. Therefore, the copper foil layer 12a and the copper layer 13a on the front surface side of the insulating base 11 and the copper foil layer 12b and the copper layer 13b on the back surface side are electrically connected by the filled via 15.

  Next, referring to FIG. 3, the copper foil layer 12a and the copper plating layer 14a are integrated, and the copper foil layer 12b and the copper plating layer 14b are integrated, and photolithography is performed on the copper foil layer 12a and the copper plating layer 14a side. The row-shaped metal pattern non-formation region Z formed as a single piece as shown in FIG. 3 is formed by an etching method. As a result, the copper foil layer 12a and the copper plating layer 14a patterned on the front side of the insulating base material 11 become metal patterns used as a circuit sandwiching the metal pattern non-formation region Z after dicing each light emitting device. Although not shown, patterning for electrode formation is simultaneously performed on the back surface. At this time, two circuit patterns respectively connected to the two filled vias 15 are formed in each unit region R that becomes one light emitting device after dicing in the semiconductor element mounting region inside the one-dot chain line. In addition, the position correction marks 16X and 16Y are formed at equal intervals on the X direction side and the Y direction side of the semiconductor element non-mounting area outside the one-dot chain line. In this case, the position correction marks 16X and 16Y are marks indicating the boundaries of the unit regions R of the semiconductor element mounting region, and indicate the positions of dicing lines described later. In addition, the metal pattern non-formation region Z extends to the semiconductor element non-mounting region immediately outside the endmost unit region R aligned in the X direction because the circuit pattern in each unit region R is separated by dicing processing described later. It is a margin for performing completely. This ensures that no electrical short circuit occurs. However, the metal pattern non-formation region Z is made as small as possible. On the other hand, although not shown in FIG. 3, the patterned copper foil layer 12 b and the copper plating layer 14 b are also formed on the back side of the insulating substrate 11 as a circuit pattern connected to the filled via 15.

  4 and 5 are diagrams for explaining a method of manufacturing the upper aggregate substrate of the comparative example. 4 and FIG. 5, the inside of the dot-dash line is also a region for mounting a semiconductor device, for example, a light emitting element for LED, and the outside of the dot-dash line is also a region not mounting a semiconductor element.

  Referring to FIG. 4, an adhesive sheet 22 is affixed to the back surface of the insulating base material 21 made of epoxy resin or the like.

  Next, referring to FIG. 5, the cavity bases 23, 24 </ b> X, and 24 </ b> Y are opened by integrating the insulating base material 21 and the adhesive sheet 22. In this case, each cavity hole 23 is a semiconductor element accommodation cavity hole (through hole) provided for one unit region R of the semiconductor element mounting region, while each cavity hole 24X, 24Y is a non-semiconductor element. This is a position correction mark cavity hole (auxiliary through hole) provided for the mounting area, and corresponds to the position correction marks 16X and 16Y of FIG.

  6 to 8 are diagrams for explaining a method of manufacturing a collective substrate for a semiconductor device after the upper collective substrate of FIG. 5 is attached to the lower collective substrate of FIG. 3 of the comparative example. 6 to 8, the inside of the one-dot chain line is a region where a semiconductor element is mounted, for example, a region for mounting a light-emitting element for LED, and the outside of the one-dot chain line is also a region where no semiconductor element is mounted, such as a non-LED light-emitting element It is a mounting area.

  Referring to FIG. 6, when the upper assembly substrate of FIG. 5 is bonded to the lower assembly substrate of FIG. 3 by the adhesive sheet 22 and heated and pressed, the gas escapes from the adhesive sheet 22 as indicated by an arrow. At this time, if the thickness of the metal pattern (12a, 14a) is large, the metal pattern non-formation region Z has a deep groove structure with respect to the metal pattern, so that the adhesive sheet 22 becomes the groove-shaped metal pattern non-formation region Z. It becomes difficult to become familiar with. Furthermore, since the gas outlet is limited to one direction in the non-metal-formed part below the one-dot chain line, a cavity due to the remaining gas tends to occur. As a result, the bonding strength between the lower aggregate substrate and the upper aggregate substrate is lowered.

  Next, referring to FIG. 7, a nickel (Ni) plating layer 32 and a silver (Ag) plating layer 33 are formed on each metal pattern (12a, 14a) by an electrolytic plating method. Here, the nickel plating layer 32 is for improving the adhesion between the copper plating layer 14 a and the silver plating layer 33, and the silver plating layer 33 has a high reflectivity, and will be described later from the LED element 34. This is for efficiently reflecting the light.

  Finally, referring to FIG. 8, an LED element (chip) 34 is mounted on each silver plating layer 33. Next, the p-side electrode and the n-side electrode of the LED element 34 are connected to two metal patterns (in this case, the silver plating layer 33) as circuit patterns by bonding wires (not shown). Next, the sealing resin layer 35 is injected into the cavity hole 23 and sealed. The sealing resin layer 35 contains a phosphor as necessary. Next, dicing is performed along the dicing lines DLX and DLY defined by the position correction marks 16X and 16Y viewed from the position correction mark cavity holes 24X and 24Y, and LED light emitting devices can be obtained individually.

  In the comparative example described above, as shown in FIG. 6B, when the thickness of the metal pattern (12a, 14a) is larger than 30 μm, for example, a cavity 31 is generated in the non-metal-formed portion below the one-dot chain line. As a result, when the nickel plating layer 32 and the silver plating layer 33 are grown by the electroless plating method, when the plating solution component is deposited in the cavity 31 and the cleaning solution does not reach the cavity 31, the cavity 31 is formed. The plating grows abnormally in the plating solution residue. Therefore, as shown in FIG. 9, when the adhesive sheet 22 is peeled off, a depression due to the cavity 31 is observed in the adhesive sheet 22 in the semiconductor element non-mounting region (FIG. 9A), while the semiconductor element non-mounting region A plating solution residue is observed on the metal pattern (FIG. 9B). As a result, in the worst case, the metal pattern in the semiconductor element non-mounting region may be electrically short-circuited, and the metal pattern in the outermost unit region R may be electrically short-circuited. On the other hand, as shown in FIG. 8, when the sealing resin layer 35 is injected into the cavity hole 23, the sealing resin layer 35 enters the cavity 31, and as a result, the liquid level of the sealing resin layer 35 is not high. The air bubbles may become stable or air bubbles may be generated during the thermosetting and the air bubbles may remain in the sealing resin layer 35.

  A method for manufacturing a collective substrate for a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

  10-12 is a figure explaining the manufacturing method of the lower assembly board | substrate which concerns on embodiment of this invention. 10 to 12, the inside of the one-dot chain line is a region for mounting a semiconductor element, for example, a region for mounting a light-emitting element for LED, while the outside of the one-dot chain line is a region for mounting a semiconductor element, for example, LED This is a light emitting element non-mounting area. The metal pattern is formed in any region.

  First, referring to FIG. 10, copper (Cu) foil layers 12 a and 12 b having a thickness of about 10 to 20 μm are pasted on the front and back of the insulating base material 11 as in the case of FIG. 1. Next, a through hole 13 having a diameter of about 0.1 to 0.2 μm is opened from the back surface of the insulating substrate 11 by laser irradiation. The copper foil layer 12b is patterned so that the copper foil at the location where the filled via is to be formed is removed by photolithography / etching. The insulating base material 11 is dug until the copper foil layer 12a is exposed by irradiating a laser to the portion where the copper foil of the copper foil layer 12b is removed. The diameter of the hole at this time is about 0.05 to 0.2 mm.

  Next, referring to FIG. 11, similarly to the case of FIG. 2, copper (Cu) plating layers 14a and 14b having a thickness of about 30 μm are formed on the copper foil layers 12a and 12b by electroless plating. As a result, the copper plating layer 14 b is also embedded in the through hole 13, and the filled via 15 is formed in the through hole 13.

  Next, referring to FIG. 12, the copper foil layer 12a and the copper plating layer 14a are integrated, and the copper foil layer 12b and the copper plating layer 14b are integrated, and photolithography is performed on the copper foil layer 12a and the copper plating layer 14a side. The row-shaped metal pattern non-formation region Z ′ formed as a single piece as shown in FIG. 12, for example, is formed by an etching method. As a result, the copper foil layer 12a and the copper plating layer 14a patterned on the front side of the insulating base material 11 become a metal pattern used as a circuit sandwiching the metal pattern non-formation region Z 'after dicing each light emitting device. Although not shown, patterning for electrode formation is simultaneously performed on the back surface. At this time, two circuit patterns respectively connected to the two filled vias 15 are formed in each unit region R of the semiconductor element mounting region inside the one-dot chain line. Further, the position correction marks 16X and 16Y 'are formed at equal intervals on the X direction side and the Y direction side of the semiconductor element non-mounting area outside the one-dot chain line. In this case, the position correction mark 16X is a mark indicating the X direction boundary of each unit region R of the semiconductor element mounting region. However, the position correction mark 16Y 'is formed by a metal pattern non-formation region Z' obtained by deforming or enlarging the metal pattern non-formation region Z of FIG. Therefore, the intermediate position between the position correction mark 16X and the outermost position correction mark 16Y 'and the intermediate position between the position correction marks 16Y' are marks indicating the Y direction boundary of each unit region R of the semiconductor element mounting region. Accordingly, these positions indicate the positions of dicing lines described later. However, the metal pattern non-formation region Z ′ is made as small as possible. On the other hand, although not shown in FIG. 12, as in the case of FIG. 3, the patterned copper foil layer 12 b and the copper plating layer 14 b are also formed on the back side of the insulating base 11 as a circuit pattern connected to the filled via 15. A metal pattern is formed.

  FIG. 13 and FIG. 14 are diagrams for explaining a method of manufacturing the upper collective substrate according to the embodiment of the present invention. 13 and 14, the inside of the one-dot chain line is a region for mounting a semiconductor element, for example, a region for mounting a light-emitting element for LED. It is a mounting area.

  Referring to FIG. 13, as in the case of FIG. 4, the adhesive sheet 22 is attached to the back surface of the insulating base material 21 made of an epoxy resin or the like.

  Next, referring to FIG. 14, the cavity bases 23, 24 </ b> X, and 24 </ b> Y are opened by integrating the insulating base material 21 and the adhesive sheet 22. In this case, as in the case of FIG. 5, each cavity hole 23 is a semiconductor element accommodating cavity hole (through hole) provided for one unit region R of the semiconductor element mounting region, and each cavity The hole 24X is a position correction mark cavity hole (auxiliary through hole) provided in the semiconductor element non-mounting region, and corresponds to the position correction mark 16X in FIG. On the other hand, the cavity holes 24Y ′ correspond to the position correction marks 16Y ′ (Z ′) in FIG. 12, and are arranged in the same row so as to be adjacent to the outermost ends of the semiconductor element receiving cavity holes 23 arranged in a row in the X direction. Located side by side.

  FIGS. 15 to 17 are views for explaining a method of manufacturing a collective substrate for a semiconductor device after the upper collective substrate of FIG. 14 is attached to the lower collective substrate of FIG. 12 of the comparative example. 15-17, for example, the LED light emitting element mounting region is also inside, and the one-dot chain line outside is also a semiconductor element non-mounting region.

  Referring to FIG. 15, when the upper aggregate substrate of FIG. 14 is bonded to the lower aggregate substrate of FIG. 12 by the adhesive sheet 22 and heated and pressed, the gas escapes from the adhesive sheet 22 as indicated by an arrow. At this time, since the cavity hole adjacent to the auxiliary through hole is connected by the metal pattern non-formation region, gas also escapes from the auxiliary through hole, so that the generation of the cavity 31 in FIG. I can do it. In addition, the auxiliary through hole exposes the end of the metal pattern non-formation region so that the boundary line between the metal pattern and the metal pattern non-formation region is visible. Because it does not cover, no cavities are generated. As a result, the bonding strength between the lower aggregate substrate and the upper aggregate substrate is lowered. In FIG. 15, the auxiliary through holes are arranged in the same row as the cavity holes 23, but the present invention is not limited to this, and the continuous through holes are not interrupted on the insulating substrate in the cavity holes 23 and auxiliary through holes at the end of the row. The metal pattern non-formation region may be provided so as to expose at least a part thereof. However, it is preferable to arrange them in the same row because the gas escape path is straight and gas escape is easy.

  Next, referring to FIG. 16, similarly to the case of FIG. 7, a nickel (Ni) plating layer 32 and a silver (Ag) plating layer 33 are formed on each metal pattern (12a, 14a) by an electrolytic plating method.

Finally, referring to FIG. 17, an LED element (chip) 34 is mounted on each silver plating layer 33 as in the case of FIG. 8. Next, the p-side electrode and the n-side electrode of the LED element 34 are connected to two metal patterns (in this case, the silver plating layer 33) as circuit patterns by bonding wires (not shown). Next, the sealing resin layer 35 is injected into the cavity hole 23 and sealed. The sealing resin layer 35 contains a phosphor as necessary. Next, dicing is performed along the dicing lines DLX and DLY defined by the position correction marks 16X and 16Y ′ viewed from the position correction mark cavity holes 24X and 24Y. The cavity holes 24X, the cavity holes 23, and the cavity holes 24Y are cut to obtain LED light emitting devices individually.
Although the dicing line DLX is directly defined by the position correction mark 16X, the dicing line DLY is defined by an intermediate position between the position correction mark 16X and the outermost position correction mark 16Y ′ and an intermediate position between the position correction marks 16Y ′. Is done.

  In the embodiment of the present invention described above, as shown in FIG. 15B, even if the film thickness of the metal pattern (12a, 14a) is larger than, for example, 30 μm, the semiconductor element mounting region / semiconductor element non-mounting region The cavity 31 shown in FIG. 6 does not occur near the boundary. As a result, when the nickel plating layer 32 and the silver plating layer 33 are grown by the electroless plating method, there is no abnormal growth of plating due to the plating solution residue. Therefore, as shown in FIG. 18, when the adhesive sheet 22 is peeled off, no depression is observed in the adhesive sheet 22 near the boundary between the semiconductor element mounting area and the semiconductor element non-mounting area ((A) in FIG. 18). On the other hand, no plating solution residue is observed in the metal pattern near the boundary between the semiconductor element mounting region and the semiconductor element non-mounting region ((B) of FIG. 18). As a result, the metal pattern near the boundary between the semiconductor element mounting region and the semiconductor element non-mounting region is electrically short-circuited, and there is no possibility that the metal pattern in the outermost unit region R is electrically short-circuited. On the other hand, as shown in FIG. 17, when the sealing resin layer 35 is injected into the cavity hole 23, there is no cavity into which the sealing resin layer 35 enters, so that the liquid level of the sealing resin layer 35 is unstable. In other words, bubbles are not generated in the sealing resin layer 35 due to generation of bubbles during thermosetting.

  In the embodiment of the present invention described above, there is no increase in the number of manufacturing steps as compared with the comparative example, and the yield is increased by the amount that the electrical short circuit of the metal pattern in the outermost unit region can be prevented. Cost can be reduced.

11: Insulating substrate
12a, 12b: Copper foil layer
13: Through hole
14a, 14b: Copper plating layer
15: Filled beer
16X, 16Y, 16Y ′: Position correction mark
Z, Z ′: Metal pattern non-formation region
21: Insulating substrate
22: Adhesive sheet
23: Cavity hole (through hole)
24X, 24Y, 24Y ′: Cavity hole for position correction mark (auxiliary through hole)
31: Cavity 32: Nickel plating layer
33: Silver plating layer
34: LED element 35: Sealing resin layer

Claims (7)

A semiconductor element mounting region composed of a plurality of unit regions arranged in a line and a semiconductor element non-mounting region surrounding the semiconductor element mounting region, and an insulating substrate and a metal pattern formed on a part of the insulating substrate. A lower assembly substrate,
A semiconductor element housing through hole corresponding to each unit region of the semiconductor element mounting region and an auxiliary through hole corresponding to the semiconductor element non-mounting region are pasted on the lower assembly substrate via an adhesive layer. An upper assembly board, and
The auxiliary through hole and the endmost through hole for housing a semiconductor element overlap at least partly on the metal pattern non-formation region of the lower assembly substrate, and the through hole for housing the semiconductor element in the auxiliary through hole and at the end. The collective substrate for a semiconductor device, wherein the metal pattern non-formation region exposed inside is continuous on the insulating substrate.   2. The collective substrate for a semiconductor device according to claim 1, further comprising a metal plating layer on the metal pattern exposed inside the through hole for housing a semiconductor element and the auxiliary through hole.   3. The collective substrate for a semiconductor device according to claim 1, wherein the auxiliary through holes are arranged side by side at end portions on the same row of the plurality of through holes for accommodating semiconductor elements arranged in a row.   4. The collective substrate for a semiconductor device according to claim 1, wherein the auxiliary through hole overlaps an end portion of the metal pattern non-formation region. 5. A semiconductor element mounting region composed of a plurality of unit regions arranged in a line and a semiconductor element non-mounting region surrounding the semiconductor element mounting region, and an insulating substrate and a metal pattern formed on a part of the insulating substrate. Preparing a lower assembly substrate,
Preparing an upper assembly substrate having a through hole for accommodating a semiconductor element corresponding to each unit region of the region for mounting a semiconductor element and an auxiliary through hole corresponding to the non-mounting region of the semiconductor element;
The auxiliary through hole and the endmost through hole for housing a semiconductor element overlap at least partly on the metal pattern non-formation region of the lower assembly substrate, and the through hole for housing the semiconductor element in the auxiliary through hole and at the end. A method of manufacturing a collective substrate for a semiconductor device, comprising: a step of overlapping and laminating the metal pattern non-exposed region exposed in the substrate so as to be continuous on the insulating substrate. After the step of bonding the upper collective substrate to the lower collective substrate, further comprising a step of forming a metal plating layer on the metal pattern exposed inside the auxiliary through hole and the through hole for accommodating a semiconductor element by electrolytic plating. The manufacturing method of the collective substrate for semiconductor devices of Claim 5 which comprises. A semiconductor element mounting region composed of a plurality of unit regions arranged in a line and a semiconductor element non-mounting region surrounding the semiconductor element mounting region, and an insulating substrate and a metal pattern formed on a part of the insulating substrate. Preparing a lower assembly substrate,
Preparing an upper assembly substrate having a through hole for accommodating a semiconductor element corresponding to each unit region of the region for mounting a semiconductor element and an auxiliary through hole corresponding to the non-mounting region of the semiconductor element;
The auxiliary through hole and the endmost through hole for housing a semiconductor element overlap at least partly on the metal pattern non-formation region of the lower assembly substrate, and the through hole for housing the semiconductor element in the auxiliary through hole and at the end. A step of laminating and pasting the metal pattern non-formation region exposed inside to be continuous on the insulating substrate;
Mounting a semiconductor element on the metal pattern exposed in the through hole for housing the semiconductor element;
A step of cutting between the adjacent through holes for accommodating semiconductor elements and between the adjacent through holes for accommodating semiconductor elements and the auxiliary through holes.