JP5488783B2 - Electronic component built-in substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a substrate in which an electronic component is embedded in an insulating layer, a manufacturing method thereof, and a method for inspecting an interlayer connection between an electronic component and a wiring layer on the substrate.

  In recent years, there has been a demand for further downsizing, thinning, and high-density mounting of electronic devices. Active components such as semiconductor devices such as IC chips (bare chips: die) used in electronic devices, capacitors (capacitors) ), Circuit board modules mounted with electronic components such as inductors (coils), thermistors, and passive components such as resistors are similarly eagerly desired to be reduced in size and thickness. In order to meet such demands for miniaturization and thinning, recently, an electronic component-embedded substrate having a high-density mounting structure in which electronic components are embedded inside a substrate in which a plurality of insulating layers made of resin or the like are laminated. Proposed.

  In addition, with the advancement of electronics technology, it is required to increase the density of printed wiring boards including such electronic component built-in boards, and multilayer printed wiring boards in which a plurality of wiring patterns or electronic parts and insulating layers are laminated are widely used. It is like that.

  Conventionally, a multilayer printed wiring board used for this kind of application is a collective board of about 300 to 500 mm square, for example, provided with a plurality of wiring pattern groups (wiring layers) for printed wiring boards in order to improve productivity. It is manufactured by so-called multi-cavity, in which a plurality of printed wiring boards (individual substrates, individual pieces, and individual items) are obtained by dividing individual pieces (also called work boards, worksheets, etc.) by dicing or the like.

  As a method of manufacturing such a multilayer printed wiring board, for example, in Patent Document 1, a wiring layer is formed on a board provided with copper foil on both sides, an electronic component having an electrode is embedded in an insulating layer, In addition, a method has been proposed in which after a metal layer having an opening is formed on the surface of the insulating layer, the insulating layer is selectively removed by blasting using the metal layer as a mask. For example, Patent Document 2 proposes a method of forming a via hole in an insulating layer by laser processing in order to make a conductor on an insulating layer of a multilayer printed wiring board and a conductor below the insulating layer conductive. .

JP 2007-173276 A JP 2001-102720 A

  By the way, in a multilayer printed wiring board, an electronic component provided therein and a wiring layer (wiring pattern) are connected to the electronic component via an insulating layer, so that a connection hole (for example, a via hole) for connecting the two is connected. If the processing conditions of the plug hole) vary (that is, the depth of the connection hole varies) or the thickness of the insulating layer varies, poor connection between the electronic component and the wiring layer may occur. Therefore, it is inevitable that the connection state between the electronic component and the wiring layer needs to be confirmed.

  On the other hand, according to the technique described in the above-mentioned conventional Patent Document 1, a plurality of multilayer printed wiring boards can be obtained. However, for example, several thousand electrodes are formed on one collective board. During the manufacturing process of the multilayer printed wiring board, it is extremely difficult to perform an inspection (total inspection) as to whether or not all those electrodes are connected to a metal layer (a wiring layer connected via an insulating layer). For this reason, after processing and forming connection holes in the insulating layer, a partial inspection is performed, and after completion of the multilayer printed wiring board, a sampling inspection is performed to perform a cross-sectional analysis of a part of the sampled individual board or collective board. Therefore, there was no practical method other than performing an estimation inspection of the interlayer connection between the electrode of the electronic component and the metal layer. In such an appearance inspection, it is difficult to quantify it, and there is a disadvantage that the quantitative property is poor, and the method of performing a cross-sectional analysis after completion requires a destructive inspection, and thus the product yield is reduced. There was an inconvenience.

  Further, in the multilayer printed wiring board described in Patent Document 2, a processing layer is provided between the insulating layer and the underlying conductor, and a connection hole is formed in the insulating layer by laser processing. Inspecting whether or not the connection hole formed in the insulating layer penetrates to the conductor by measuring the electromagnetic wave radiated from the processing layer, that is, whether or not the insulating layer at that portion has been removed reliably The method is taken.

  However, according to such a method, during the manufacturing process of the multilayer printed wiring board, an inspection of the interlayer connection is performed to check whether or not the connection hole is reliably formed in the insulating layer. It is not preferable to perform the inspection by the laser irradiation for the formation because it takes a lot of time and cost. In addition, such inspection by laser irradiation cannot be applied to a manufacturing process (for example, blasting) that does not use laser processing to form connection holes.

  Furthermore, even if a continuity test for electrical connection between the electrode and the metal layer is performed for the total number of built-in electronic components, the contact resistance and the wiring resistance during the test are included. In addition, if the built-in electronic component is a semiconductor device, the continuity test is limited to measuring the protection diode built in the semiconductor device, and the test is performed only on the order of several (Ω) using the two-terminal method. I can't. Considering the wear failure after being distributed to the market, the continuity inspection needs to be evaluated on the order of several (mΩ), and the above-described appearance inspection, destructive inspection, and continuity inspection are not sufficient.

  Therefore, the present invention has been made in view of such circumstances, and when manufacturing a multilayer printed wiring board, an external observation during processing and a cross-sectional analysis of a finished product are not performed, and an insulation provided with an electronic component is provided. Electronic component-embedded board that can easily and accurately inspect the state of interlayer connection between electronic components and wiring layers in a multilayer printed wiring board, regardless of the type of layer removal method (connection hole processing method) An object of the present invention is to provide a manufacturing method and an inspection method thereof.

  In order to solve the above problems, a semiconductor-embedded substrate according to the present invention includes a base, an electronic component placed on the base, a conductor placed on a non-placed portion of the electronic component on the base, an electronic component, An insulating layer formed so as to cover the conductor, a first wiring formed in the insulating layer and connected to the electronic component, and a second wiring formed in the insulating layer and connected to the conductor It is to be prepared.

  In the present specification, the “electronic component built-in substrate” means not only an individual substrate (individual piece, individual product) that is a unit substrate in which an electronic component is built, but also the above-described collective substrate having a plurality of the individual substrates ( Work board, worksheet). The type of “electronic component” is not particularly limited, and examples thereof include active elements such as semiconductor ICs and passive elements such as varistors, resistors, and capacitors. Furthermore, the “conductor” may be formed integrally as a whole, or a plurality of members formed separately may be connected to each other. For example, there is no gap in the form of an integral frame around the electronic component. Or the form arrange | positioned in multiple by the predetermined space | interval is mentioned.

  In the above configuration, in addition to the first wiring connected to the electronic component provided in the insulating layer on the base, the conductor provided in the same insulating layer is a non-mounting portion of the electronic component in the base. Since the second wiring connected to the first wiring is formed, the electrical resistance between the conductor and the second wiring is directly measured without directly measuring the electrical resistance (conduction resistance, connection resistance) between the electronic component and the first wiring. By measuring the above, it is possible to determine the electrical connection state (conductivity) between the electronic component and the first wiring formed thereon at the thickness of the resin layer. With regard to this point, as a result of detailed studies by the present inventors, there is a close correlation between the connection state between the electronic component and the conductor mounted in the same insulating layer and the first wiring and the second wiring, respectively. The relationship was confirmed to exist.

  As described above, in order to measure the electrical resistance between the conductor and the second wiring and inspect the connection state between the electronic component and the first wiring based on the result, the “first wiring” and the “first wiring” are used. It is only necessary that both of the “2 wirings” are exposed (exposed) on the same surface of at least one of the substrate front surface, the substrate back surface, and the substrate side surface. For example, when there is one second wiring connected to a conductor (in the case of a plurality of conductors, the same applies hereinafter), the conductor is also connected to an electronic component among the substrate surface, the substrate back surface, and the substrate side surface. If it is exposed on the same surface as the first conductor, the electrical resistance between the conductor provided in the insulating layer and the second wiring is measured by connecting an inspection terminal to both of them, and If a plurality of the two wirings are connected, the electrical resistance between the conductor and the second wiring can be measured by connecting the inspection terminal to at least two of the second wirings.

  Further, the arrangement relationship between the electronic component and the conductor inside the insulating layer, for example, the thickness of the insulating layer above the portion to which the first wiring is connected in the electronic component (the first thickness of the insulating layer, the first And the thickness of the insulating layer above the portion where the second wiring is connected in the conductor (the second thickness of the insulating layer, the second interlayer distance) are the same or different. May be. In other words, the depth level (height level) of the electronic component and the conductor inside the insulating layer is not particularly limited.

  When the first and second thicknesses of these insulating layers are different, the first thickness of the insulating layer is thinner (smaller) than the second thickness, that is, the first thickness of the insulating layer. If the thickness is less than the second thickness of the insulating layer, the connection hole (for example, via hole or connection plug) for forming the second wiring on the conductor forms the first wiring on the electronic component. Must be cut deeper than the connecting hole. Then, under the condition that the processing rate (processing depth per hour) of both the connection holes is the same, the interlayer connection between the second wiring on the conductor deeper than the first wiring on the electronic component and the conductor is performed. If the state is confirmed, it is useful because it is possible to more reliably determine the state of the interlayer connection between the first wiring formed on the electronic component and the electronic component based on the result.

  In this case, specifically, by using a conductor whose thickness (height) is thinner (lower) than the thickness (height) of the electronic component, the first thickness of the insulating layer is It becomes easy to make it thinner than the second thickness.

  More specifically, the conductor is preferably arranged so as to surround the outer periphery of each aggregate with respect to a plurality of aggregates including at least one or more individual substrates arranged in the plane direction. Note that “an assembly including at least one or more individual substrates” means at least one of a plurality of individual substrates included in an aggregate substrate in which a plurality of individual substrates (pieces, individual items) are formed in a plane direction. Means a collection of one or more individual substrates.

  In such a configuration, the conductor functions as a structure that improves the mechanical strength of the collective substrate in a substantially isotropic manner, and suppresses changes in shape such as “warping” of the collective substrate against stress application. The correlation between the connection state between the electronic component and the first wiring and the connection state between the conductor and the second wiring is suppressed from being deteriorated, thereby increasing the above-described connection state determination accuracy. In addition, the individual mounting reliability of the individual substrates obtained from the collective substrate can be further improved.

  Further, the method for manufacturing an electronic component built-in substrate according to the present invention is a method for effectively manufacturing the electronic component built-in substrate of the present invention, the step of preparing a base, the step of placing the electronic component on the base, A step of placing a conductor on a non-mounting portion of an electronic component on a base, a step of forming an insulating layer covering the electronic component and the conductor, and a step of forming a first wiring connected to the electronic component on the insulating layer And forming a second wiring connected to the conductor in the insulating layer.

  Further, the thickness of the insulating layer above the portion where the first wiring is connected in the electronic component (the first thickness of the insulating layer) is the insulating layer above the portion where the second wiring is connected in the conductor. It is useful to form it so as to be thinner than the first thickness (first thickness of the insulating layer).

  Furthermore, the processing amount (for example, processing depth) of the first connection hole for forming the first wiring in the insulating layer and the processing of the second connection hole for forming the second wiring in the insulating layer The amount (for example, processing depth) may be varied. In this way, the connection state between the first wiring formed in the first connection hole and the electronic component, and the connection state between the second wiring formed in the second connection hole and the conductor, Since various correlations can be examined, it is possible to realize a more precise (fine) management of the manufacturing process, and to detect a process abnormality in the manufacturing process sensitively.

  Furthermore, the method for inspecting an electronic component built-in substrate according to the present invention is a method for inspecting the interlayer connection, and is an effective method in the method for producing an electronic component built-in substrate according to the present invention, comprising a step of preparing a substrate. A step of placing an electronic component on the substrate, a step of placing a conductor on a non-mounting portion of the electronic component on the substrate, a step of forming an insulating layer covering the electronic component and the conductor, and connection to the electronic component Forming a first wiring on the insulating layer, forming a second wiring connected to the conductor on the insulating layer, measuring an electrical resistance between the conductor and the second wiring, Determining a connection state between the conductor and the second wiring based on the electrical resistance, and determining a connection state between the electronic component and the first wiring based on the connection state between the conductor and the second wiring; Have

  In this case, in the step of determining the connection state between the electronic component and the first wiring, the connection for forming the first wiring when it is determined that the electronic component and the first wiring are not connected. So-called feedback control having a step of adjusting the processing conditions of the connection hole so as to further increase the processing amount (for example, processing depth) of the hole can be applied to the manufacturing process.

  According to the electronic component built-in substrate, the manufacturing method thereof, and the inspection method for inspecting the interlayer connection according to the present invention, it takes time and effort to observe the appearance during processing or to individually analyze the cross section of the finished product at the time of manufacturing the product. There is no need to perform inspection, and the insulating layer is not incorporated in the insulating layer, and is not limited by the type of removal method (for example, blasting, carbon dioxide laser irradiation, polishing using a grinder, etc.). The state of interlayer connection between the electronic component and the wiring layer can be inspected easily and accurately. As a result, the collective substrate and thus the individual substrate can be manufactured at low cost in a short time, and the product yield can be improved. Therefore, the productivity and economy of the electronic component built-in substrate can be improved, and the manufacturing process conditions (recipe) can be optimized by performing such inspection prior to manufacturing the actual product. It is also possible to improve the mounting reliability.

It is a top view which shows the principal part of 1st Embodiment of the aggregate substrate by this invention. It is sectional drawing which follows the II line | wire in FIG. 2 is a perspective view showing a schematic configuration of an electronic component 41. FIG. 3 is a plan view showing a schematic configuration of a plate-like integrated frame 51. FIG. 4 is a plan view showing a main part of a plate-like integrated frame 51. FIG. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. It is a graph which shows the relationship between the opening diameter of a mask and cutting depth in wet blasting. It is the graph which showed the relationship of the connection yield with respect to the opening diameter of a mask for every lot. FIG. 6 is a process diagram illustrating an example of a procedure for manufacturing the work board 100. FIG. 3 is a plan view showing measurement points on the work board 100. It is the graph which showed the correlation with the thickness of the insulating layer 21 of product area S1-S4 of each lot, and the thickness of the insulating layer 21 of T outside a product area. 4 is a graph showing the correlation between the thickness of the insulating layer 21 in the product areas S1 to S4 of the work board 100 and the thickness of the insulating layer 21 outside the product area T. It is the top view which showed the dispersion | variation in the thickness of the insulating layer 21 of the work board 100 in a normal manufacturing process. It is the top view which showed the dispersion | variation in the thickness of the insulating layer 21 of the work board 100 in the manufacturing process on the process conditions different from usual. It is the graph which showed the correlation with the thickness of the insulating layer 21 of product area S1-S4 of each lot, and the thickness of the insulating layer 21 of T outside a product area. It is the graph which showed the correlation with the dispersion | variation in the thickness of the insulating layer 21 of the product areas S1-S4 of each lot, and the dispersion | variation in the thickness of the insulating layer 21 outside T of product areas. It is a top view which shows the thickness of the insulating layer 21 in the product area T in the 1st work board 100. FIG. It is a top view which shows the thickness of the insulating layer 21 in the product area T in the 2nd work board 100. FIG. It is a top view which shows the thickness of the insulating layer 21 in product area T in the 3rd work board 100. FIG. It is a top view which shows the thickness of the insulating layer 21 in the product area T in the 4th work board 100. FIG. FIG. 28 is an enlarged view of adjacent areas inside and outside the product area S1 of FIG. It is a graph which shows the dispersion | variation in the thickness of the insulating layer 21 inside and outside the product area with respect to arbitrary rows (C row to R row) inside and outside the product area S1. It is a graph which shows the result of having performed the continuity test for every lot. It is sectional drawing which shows the principal part of 2nd Embodiment of the aggregate substrate by this invention. It is sectional drawing which shows the principal part of 2nd Embodiment of the plate-shaped integrated frame 61 by this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios. Further, the following embodiments are exemplifications for explaining the present invention, and are not intended to limit the present invention only to the embodiments. Furthermore, the present invention can be variously modified without departing from the gist thereof.

(First embodiment)
FIGS. 1 and 2 are an enlarged plan view and a cross-sectional view, respectively, of a main part schematically showing the structure of the first embodiment of the electronic component built-in substrate according to the present invention. The work board 100 is an electronic component built-in substrate (collection substrate) that includes a plurality of worksheets (collections) capable of producing a plurality of individual substrates in the surface direction within the sheet surface. The work board 100 includes an insulating layer 21 on one surface (illustrated upper surface) of a substantially rectangular substrate 11 (base), and an electronic component 41 and a plate-like integrated frame 51 (conductor) at predetermined positions inside the insulating layer 21. Embedded in the wiring layer 31 (first wiring) and the wiring layer 34 (second wiring) formed through the insulating layer 21 and connected to the electronic component 41 and the plate-like integrated frame 51 (conductor). It is what you have.

  The substrate 11 is formed by using, for example, a double-sided CCL (Copper Clad Laminate), etc., and wiring layers (patterns) 12a and 12b are formed on both sides of the insulating layer 12, and on the wiring layer 12a. It has the insulating layer 13 laminated | stacked by carrying out the vacuum pressure bonding of the insulating resin film. Thus, the substrate 11 has an RCC (Resin Coated Copper) structure.

  The wiring layers 12a and 12b are respectively formed corresponding to the intended individual substrates. The material of these metal layers 12a and 12b is not particularly limited. For example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), tin (Sn), chromium (Cr), aluminum Metal conductive materials such as (Al), tungsten (W), iron (Fe), titanium (Ti), and SUS material can be mentioned, and among these, copper (Cu) is preferable from the viewpoint of conductivity and cost ( The same applies to other conductors and wirings (layers). The wiring layer 12a and the wiring layer 12b are electrically connected via a via 14 penetrating the insulating layer 12 for each target individual substrate.

  The material used for the insulating layers 12 and 13 is not particularly limited as long as it can be molded into a sheet or film. Specifically, for example, a vinyl benzyl resin, a polyvinyl benzyl ether compound resin, a bis Maleimide triazine resin (BT resin), polyphenyl ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate ester resin, epoxy + active ester cured resin, polyphenylene ether resin (polyphenylene oxide resin), curable polyolefin resin, benzo Cyclobutene resin, polyimide resin, aromatic polyester resin, aromatic liquid crystal polyester resin, polyphenylene sulfide resin, polyetherimide resin, polyacrylate resin, polyetheretherketone resin, fluorine resin, Poxy resin, phenol resin or benzoxazine resin alone, or these resins can be added to silica, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whisker, potassium titanate fiber, alumina, glass Materials added with flakes, glass fibers, tantalum nitride, aluminum nitride, etc. In addition to these resins, magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodymium, samarium, aluminum, bismuth, lead, lanthanum A material in which a metal oxide powder containing at least one metal of lithium and tantalum is added, or a material in which a resin fiber such as glass fiber or aramid fiber is blended with these resins, or these Glass resin Scan, aramid fibers, the material is impregnated into a nonwoven fabric or the like, can be exemplified, and electrical properties, mechanical properties, water absorption, from the viewpoint of reflow resistance, can be appropriately selected.

  The insulating layer 21 is made of, for example, a thermosetting resin. Examples of the resin material include an epoxy resin, a phenol resin, a vinyl benzyl ether compound resin, a bismaleimide triazine resin, a cyanate ester resin, a polyimide, a polyolefin resin, a polyester, Examples thereof include polyphenylene oxide, liquid crystal polymer, silicone resin, and fluorine resin, and these can be used alone or in combination. Further, it may be a rubber material such as acrylic rubber or ethylene acrylic rubber, or a resin material partially including a rubber component. In addition, silica, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whisker, potassium titanate fiber, alumina, glass flake, glass fiber, tantalum nitride, aluminum nitride, etc. are added to these resins. In addition to the added materials, and these resins, at least one metal selected from magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodymium, samarium, aluminum, bismuth, lead, lanthanum, lithium and tantalum. Materials containing added metal oxide powders, or materials containing resin fibers such as glass fibers or aramid fibers, or glass resins, aramid fibers, nonwoven fabrics, etc., impregnated with these resins. List the materials, etc. Can be, electrical properties, mechanical properties, water absorption, from the viewpoint of reflow resistance, can be appropriately selected.

  FIG. 3 is a perspective view schematically showing the structure of the electronic component 41. This electronic component 41 is a semiconductor IC (die) in a bare chip state, and has a large number of land electrodes 42 on a main surface 41a having a substantially rectangular plate shape. In the drawing, the land electrodes 42 are shown only at the four corners, and the display of the other land electrodes 42 is omitted. The type of the electronic component 41 is not particularly limited. For example, a digital IC having a very high operating frequency such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor), a high-frequency amplifier, Examples include analog ICs such as antenna switches and high-frequency oscillation circuits.

  The back surface 41b of the electronic component 41 is polished, whereby the thickness t1 (distance from the main surface 41a to the back surface 41b) of the electronic component 41 is made thinner than that of a normal semiconductor IC. Specifically, the thickness t1 of the electronic component 41 is, for example, 200 μm or less, more preferably 100 μm or less, and particularly preferably about 20 to 50 μm. In addition, the back surface 41b of the electronic component 41 is preferably subjected to a surface roughening process such as etching, plasma processing, laser processing, blast polishing, buff polishing, chemical processing, or the like in order to reduce the thickness or improve adhesion.

  The back surface 41b of the electronic component 41 is preferably polished in a lump for a large number of electronic components 41 and then separated into individual electronic components 41 by dicing. When the individual electronic components 41 are cut and separated by dicing before being thinned by polishing, the back surface 41b can be polished with the main surface 41a of the electronic components 41 covered with a thermosetting resin or the like.

  Each land electrode 42 may be formed with a bump (terminal) (not shown) which is a kind of conductive protrusion. The type of the bump is not particularly limited, and various bumps such as a stud bump, a plate bump, a plating bump, and a ball bump can be exemplified. When a stud bump is used as the bump, silver (Ag) or copper (Cu) can be formed by wire bonding, and when a plate bump is used, it can be formed by plating, sputtering, or vapor deposition. In addition, when using a plating bump, it can be formed by plating. When using a ball bump, the solder ball is placed on the land electrode 42 and then melted or cream solder is applied to the land electrode. After printing on top, it can be formed by melting it. Further, it is also possible to use conical or columnar bumps obtained by screen printing a conductive material and curing it, or bumps obtained by printing nano paste and sintering it by heating.

  The metal species that can be used for the bump is not particularly limited. For example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), tin (Sn), chromium (Cr), nickel / chromium An alloy, solder, etc. are mentioned. Among these, it is preferable to use gold or copper, and more preferable to use copper in consideration of connectivity and migration. When copper is used as the material of the bumps, for example, higher bonding strength to the land electrode 42 can be obtained than when gold is used, and the reliability of the electronic component 41 itself is improved.

  The size and shape of the bumps can be appropriately set according to the interval (pitch) between the land electrodes 42. For example, when the pitch of the land electrodes 42 is about 100 μm, the maximum diameter of the bumps is about 10 to 90 μm. The height may be about 2 to 100 μm. The bumps can be cut and separated into individual electronic components 41 by dicing the wafer, and then bonded to each land electrode 42 using a wire bonder.

  4 and 5 are a plan view and a main part enlarged plan view schematically showing the structure of the plate-like integrated frame 51, respectively. The plate-like integrated frame 51 used in the present embodiment includes a frame portion 52 made of a plate-like body in which four rectangular windows W are partitioned in a lattice shape. The outer shape of the frame portion 52 is a substantially rectangular shape that is substantially similar to the outer shape of the substrate 11. In this embodiment, the outer dimension is designed to be slightly smaller than the substrate 11. As shown in FIG. 2, in the present embodiment, the thickness t2 (the thickest portion) of the frame portion 52 is designed to be approximately the same as the thickness t1 of the electronic component 41 (t1≈t2). .

  On the inner peripheral wall 52a (inner periphery) of the lattice window W of the frame portion 52, a plurality of concave portions 53 having an opening width of Δs are arranged in parallel at equal intervals. In other words, a plurality of concave portions 53 are formed by cutting out a part of the inner peripheral wall 52a of each window W of the frame portion 52 in a substantially rectangular parallelepiped shape at equal intervals. The recess 53 is formed so as to correspond to a boundary (cutting surface) of the individual substrate 300 described later. A hole 54 is formed between the adjacent recesses 53. A plurality of holes 54 are formed at a regular pitch on a straight line connecting adjacent recesses 53. In addition, a plurality of holes 55 are formed on the outer periphery of the hole 54 at the same pitch as the arrangement interval of the holes 54.

As a material that can be used for the plate-like integrated frame 51, the following formula (1);
α1 <α3 and α2 <α3 (1),
(Where α1 represents the linear thermal expansion coefficient (ppm / K) of the electronic component 41, α2 represents the linear thermal expansion coefficient (ppm / K) of the plate-like integrated frame 51, and α3 represents the above substrate. 11, which shows the coefficient of linear thermal expansion (ppm / K) of each wiring layer or each insulating layer) can be used without particular limitation. In electronic parts, substrates, wiring layers and insulating layers used for this type of application, α1 is generally about 1 to 8 ppm / K and α3 is about 14 to 20, so α2 is 3 to 16 (Ppm / K) is preferable. More specifically, a metal, an alloy, a resin, and the like having a linear thermal expansion coefficient of 3 to 16 (ppm / K) are used. For example, SUS430 (10.5 ppm / K) is more preferably used.

  Hereinafter, with reference to FIGS. 6 to 16, a manufacturing method of the work board 100 including four worksheets incorporating a plurality of electronic components 41 will be described.

  First, a double-sided copper-clad glass epoxy which is a double-sided CCL is drilled, and after electroless plating and electrolytic plating, unnecessary portions are removed by etching, etc., using a known technique such as wiring layer (pattern) 12a. , 12b and vias 14 are prepared (FIG. 6). Here, a circuit configuration group composed of the wiring layers 12a and 12b and the vias 14 is formed separately at four positions corresponding to the lattice windows W of the plate-like integrated frame 51 (not shown). Each circuit configuration is individually formed corresponding to a target individual substrate. Further, an insulating layer 13 is formed on the wiring layer 12a of the substrate 11 (FIG. 7). Thereafter, the substrate 11 obtained by the above operation is placed and fixed at a predetermined position on a stainless steel work stage (not shown), and the subsequent steps are performed.

  Next, the electronic component 41 is placed at predetermined positions in the product areas S1 to S4 on the insulating layer 13 of the substrate 11 (FIGS. 8 and 9). Here, the product areas S1 to S4 are regions for manufacturing a target individual substrate that is defined based on a circuit configuration group such as the wiring layers 12a and 12b and the vias 14. In FIG. 9, the electronic component 41 is not shown for easy understanding. Here, as described above, four identical circuit configuration groups are formed in the substrate 11 at the four locations corresponding to the lattice windows W of the plate-like integrated frame 51, and accordingly, 2 × 2 Product areas S1 to S4 and grid-like non-product areas T (areas excluding the product areas S1 to S4) arranged in a grid pattern are defined (FIG. 9).

  Further, a plate-like integrated frame 51 is placed on the insulating layer 13 of the substrate 11 (FIGS. 8 and 9). The electronic component 41 and the plate-like integrated frame 51 are placed on the same plane on the insulating layer 13 of the substrate 11 (FIG. 8). Here, the plate-like integrated frame 51 is placed at a predetermined position in the non-product area T where the electronic component 41 is not placed so that each lattice window W of the plate-like integrated frame 51 coincides with the product areas S1 to S4. Is placed. The plate-like integrated frame 51 is placed so as to surround the product areas S1 to S4 (FIG. 9). The plate-like integrated frame 51 may be placed prior to placing the electronic component 41 or simultaneously with the placing of the electronic component 41.

  Thereafter, the insulating layer 21 is formed so as to cover the electronic component 41 and the plate-like integrated frame 51 placed on the insulating layer 13 of the substrate 11 as described above (FIG. 10). More specifically, after an uncured or semi-cured thermosetting resin is applied on the insulating layer 13 of the substrate 11, it is cured by applying heat and then cured while being pressed by a pressing means or the like. It is preferable to mold. In this way, the adhesion between the wiring layers 12a, 12b, the insulating layers 12, 13, 21, the electronic component 41, and the plate-like integrated frame 51 is improved.

  Further, a conductor layer 32 for forming the wiring layer 31 is formed on the insulating layer 21 provided on the substrate 11 (FIG. 11). As described above, the conductor layer 32 is mainly made of copper foil, for example. Thereafter, in order to form the wiring layer 31 in the same layer as the conductor layer 32, a part of the conductor layer 32 is removed by etching, and a pattern of the conductor layer 32 is formed (FIG. 12).

  Next, the conductor layer 32 that has not been removed by etching is used as a mask layer 33, and the insulating layer 21 exposed in the opening pattern is cut by a blasting process, which is a known technique, on the electronic component 41 and the plate-like integrated frame 51. In addition, a via hole 22 (first connection hole) and a via hole 23 (second connection hole) are respectively formed (FIG. 13). As a type of blasting treatment, wet blasting treatment is preferable in order to protect the electronic component 41 by preventing charging due to static electricity generated during cutting.

  Here, FIG. 14 shows the processing amount of the insulating layer 21 with respect to the opening diameters of the via holes 22 and 23 formed by cutting the insulating layer 21 (pattern opening diameter of the mask layer 33) when performing the blasting process. It is a graph which shows a change (relationship). In the figure, the “processing amount” is indicated by the cutting depth of the insulating layer 21. As described above, it is understood that the processing amount of the insulating layer 21 increases depending on the size of the opening diameter of the via holes 22 and 23 due to a certain amount of processing.

  In the present embodiment, the thickness t1 of the electronic component 41 and the thickness t2 of the plate-like integrated frame 51 are approximately the same, that is, the thickness of the insulating layer 21 on the electronic component 41 (the first thickness of the insulating layer). ) And the thickness of the insulating layer 21 on the plate-like integrated frame 51 (second thickness of the insulating layer) are approximately the same, so that the opening diameters of the electronic component 41 and the mask layer 33 on the plate-like integrated frame 51 are If blasting is performed in the same manner, via holes 22 and 23 having the same opening diameter and the same cutting depth can be obtained.

  On the other hand, when the thickness t1 of the electronic component 41 is different from the thickness t2 of the plate-like integrated frame 51, that is, the thickness of the insulating layer 21 on the electronic component 41 (first thickness of the insulating layer) and When the thickness of the insulating layer 21 on the plate-like integrated frame 51 (second thickness of the insulating layer) is different, the via holes 22 and 23 having different cutting depths are formed from the relationship shown in FIG. It is necessary to perform a blasting process in which the opening diameters of the electronic component 41 and the mask layer 33 on the plate-like integrated frame 51 are made different. For example, when the thickness t2 of the plate-like integrated frame 51 is smaller than the thickness t1 of the electronic component 41, the plate shape is larger than the thickness of the insulating layer 21 on the electronic component 41 (first thickness of the insulating layer). Since the thickness of the insulating layer 21 on the integrated frame 51 (second thickness of the insulating layer) is increased, the opening diameter of the mask layer 33 for forming the via hole 23 formed on the plate-shaped integrated frame 51 is increased. By making it larger than the opening diameter of the via hole 22 formed on the electronic component 41, the cutting depth of the via hole 23 can be made deeper than the cutting depth of the via hole 22.

  FIG. 15 shows that the insulating layer 21 is cut when blasting (the blast media flux is constant) to the insulating layer 21 in which the electronic component 41 and the plate-like integrated frame 51 having the same thickness are incorporated. It is a graph used as the parameter | index for determining the opening diameter of the via holes 22 and 23 formed. In the figure, the horizontal axis indicates the lot number, and the vertical axis indicates the yield (%) of the interlayer connection between the wiring layer 31 formed from the via hole 22 and the electronic component 41. Here, the “lot” refers to a panel group that processes a series of manufacturing steps for manufacturing the work board 100 on the same line. That is, work boards 100 having different lot numbers are processed at different times and times on the same production line in the series of manufacturing processes, or are processed at different times and times on different production lines, Furthermore, it is processed at different times and times on different production lines.

  In the figure, the black circle (●) and the solid line L1 are blasted with an opening diameter larger than the opening diameter of the mask layer 33 pattern used in the actual product (design value: hereinafter referred to as “actual diameter”). The black painted triangle mark (▲) and the alternate long and short dash line L2 indicate the result of blasting with the same opening diameter as the actual diameter, and the black painted square mark (■) and the alternate long and two short dashes line L3 are larger than the actual diameter. The result of blasting with a small opening diameter is shown. From these results, in the case of blasting using an opening diameter larger than the actual diameter, the yield of interlayer connection between the electronic component 41 and the wiring layer 31 is maintained at 97 (%) or more. It turns out that it is an opening diameter. In other words, in the work board 100 in which the electronic component 41 and the plate-like integrated frame 51 having the same thickness are built, if the via holes 22 and 23 are formed by performing a blasting process using an opening diameter larger than a predetermined actual diameter. It is understood that both the connection between the electronic component 41 and the wiring layer 31 and the connection between the plate-like integrated frame 51 and the wiring layer 34 can be sufficiently secured.

  According to the knowledge of the present inventor, instead of blasting, for example, even when the via holes 22 and 23 are formed in the insulating layer 21 using a high-power pulse laser such as a carbon dioxide laser, the graph shown in FIG. Similar results are obtained. Specifically, the number of shots for irradiating a laser pulse of a carbon dioxide gas laser to the same location is changed before and after the number of shots (design value) used in an actual product. Then, a tendency similar to that shown in FIG. 15 is recognized, and as a result, when a predetermined number of shots used in an actual product is used, the yield of interlayer connection between the wiring layer 31 and the electronic component 41 is increased. Similarly to the case of the blasting process, it is possible to hold at 97 (%) or more.

  After forming the via holes 22 and 23 so as to penetrate the insulating layer 21 on the substrate 11 by blasting or laser processing as described above, the inner and bottom walls of the via holes 22 and 23, the insulating layer 21, and the mask layer The seed layer is formed by electroless plating so as to cover 21. Then, after a metal plating layer is grown (not shown) by electrolytic (electric) plating, the mask layer 33 is removed to obtain wiring layers 31 and 34 (FIG. 16).

  Here, in the manufacturing process shown in FIGS. 6 to 16, the thickness of the insulating layer 21 of the substrate 11 (the first thickness of the insulating layer) in the product areas S1 to S4 (see FIG. 9) containing the electronic component 41. And the thickness of the insulating layer 21 of the substrate 11 (second thickness of the insulating layer) in the area T outside the product in which the plate-like integrated frame 51 is incorporated, the insulation inside and outside the product areas S1 to S4 is measured. It has been found that the thickness of the layer 21 varies, and that a significant correlation is established between the thicknesses of the insulating layers 21 inside and outside the product areas S1 to S4 and the variations thereof. The “variation” of the thickness of the insulating layer referred to in the present embodiment means that the thickness of the insulating layer 21 is not uniform and constant anywhere inside and outside the product area, and the value varies locally and / or locally. In other words, due to such a variation in the thickness of the insulating layer 21, the state of interlayer connection may also vary (fluctuate). Hereinafter, it will be described that a correlation is established between the thickness of the insulating layer 21 and the variation thereof inside and outside the product area.

  FIG. 17 is a plan view showing a location where the thickness of the insulating layer 21 on the work board 100 is measured. In the figure, the work boat 100 has locations where the thickness of the insulating layer 21 in the product areas S1 to S4 and the thickness of the insulating layer 21 outside the product area T are actually measured by magnifying the cross section. Show. More specifically, black circles (●) shown in the figure indicate locations (36 locations) where the thickness of the insulating layer 21 was measured in the product areas S1 to S4, and black triangles (▲) indicate product The measurement location (45 places) which measured the thickness of the insulating layer 21 in the area outside T is shown. In addition, although this inventor is performing many such measurements, the measurement location is not restricted to the location shown in FIG. 17, and the number of measurements is not restricted to the number shown in FIG.

  FIG. 18 is a graph showing the correlation between the thickness of the insulating layer 21 in the product areas S1 to S4 of each lot and the thickness of the insulating layer 21 outside the product area T based on the measurement values at the measurement points shown in FIG. is there. In the figure, the horizontal axis indicates the lot number, and the vertical axis indicates the ratio (%) of each measured value to the average value of the thickness of the insulating layer 21 inside and outside the product area. Also, the black circle (●) and the solid line L4 indicate the average values of the measurement values (36 points) measured for each lot in the product areas S1 to S4, and the black triangle (▲) and the alternate long and short dash line L5 shows the average value of the measurement values measured for each lot at the measurement locations (45 locations) outside the product area T for each lot. From the results shown in FIG. 18, it is confirmed that in each lot, when the thickness of the insulating layer 21 in the product areas S1 to S4 changes, it changes at a rate substantially the same as the thickness of the insulating layer 21 outside the product area T. From this, it is understood that a significant correlation is established with the thickness of the insulating layer 21 inside and outside the product area.

FIG. 19 shows the correlation between the thickness of the insulating layer 21 in the product areas S1 to S4 of the work board 100 and the thickness of the insulating layer 21 outside the product area T based on the measurement values at the measurement points shown in FIG. It is a graph to show. In the figure, the horizontal axis indicates the ratio (%) of each measured value of the thickness of the insulating layer 21 in the product areas S1 to S4 to the average value of the thickness of the insulating layer 21 inside and outside the product area. The ratio (%) of each measured value of the thickness of the insulating layer 21 outside the product area T to the average value of the thickness of the insulating layer 21 inside and outside the product area is shown. From the plot value (black diamond (♦)) shown in FIG. 19 and the solid line L6 (calculated by regression analysis) as a guideline, a very strong correlation is established between the thickness of the insulating layer 21 inside and outside the product area. Turned out to be. Note that the “R ² ” value shown in the figure indicates a correlation coefficient.

  Here, in addition to the method of measuring the actual thickness of the insulating layer 21, the electronic component 41 can also be obtained by measuring the dielectric constant of the insulating layer 21 and converting the thickness of the insulating layer 21 from the measured value. The thickness from the top to the top of the insulating layer 21 (first thickness of the insulating layer) and the thickness from the top of the plate-like integrated frame 51 to the top of the insulating layer 21 (second thickness of the insulating layer) ) Can be measured over almost all areas of the work board 100.

  20 and 21 are graphs showing the thickness of the insulating layer 21 calculated based on the measured dielectric constant of the insulating layer 21 over almost the entire area of the work board 100. FIG. 20 and 21 correspond to the elements of the work board 100 shown in FIG.

  In this measurement, as a substitute for the electronic component 41, simulated substrates (mock-ups, mirrors) are built in chips in the product areas S1 to S4 of the work board 100, and for each area S10 in which these simulated substrates are built. The thickness of the insulating layer 21 was calculated. In addition, a plate-like integrated frame 51 is incorporated in the work board 100 outside the product area T in the same manner as the actual product, and the thickness of the insulating layer 21 is calculated by dividing each area T10 having the same area as the area S10. did. In the same figure, the numerical values described in each area S10, T10 are (calculated value of thickness of insulating layer 21 in each area−average value of thickness of insulating layer 21) / (thickness of insulating layer 21). (Average value) is shown as a percentage (%).

  Specifically, the numerical values described in each of the areas S10 and T10 are, for example, an average value of the thickness of the insulating layer 21 of the work board 100 is 18 μm, and the thickness of the insulating layer 21 in any area S10 is calculated. When the value is 20 μm, the percentage of the thickness in the area S10 is calculated as + 11% according to the above formula. Further, when the average value of the thickness of the insulating layer 21 of the work board 100 is 18 μm and the calculated value of the thickness of the insulating layer 21 in an arbitrary area S10 is 25 μm, the percentage of the thickness in the area S10 is Calculated as + 38%. Based on the percentage (%) thus determined, the degree of variation in the thickness of the insulating layer 21 formed on the work board 100 can be determined. 20 and 21, the larger the percentage (%) of the thickness described in each area S10, T10, and the darker the areas S10, T10 are displayed, the more the area is displayed. It is shown that the thickness of the formed insulating layer 21 is greatly deviated from the overall average value of the thickness of the insulating layer 21.

  FIG. 20 is a plan view showing variations in the thickness of the insulating layer 21 inside and outside the product area of the work board 100 when the normal manufacturing process (FIGS. 6 to 16) described above is performed. It is understood that the variation in the thickness of the insulating layer 21 in the product areas S1 to S4 is small, and the variation in the thickness of the insulating layer 21 outside the product area T is also small.

  On the other hand, FIG. 21 shows that an insulating layer is formed so that a thickness variation is intentionally significant under processing conditions different from those of the insulating layer 21 formed in a normal manufacturing process. It is a top view which shows the result of having measured and evaluated the dispersion | variation in the thickness of the insulating layer. From this result, it is understood that when the variation in the thickness of the insulating layer 21 in the product areas S1 to S4 is large, the variation in the thickness of the insulating layer 21 outside the product area T is also large.

  Thus, the results shown in FIG. 20 and FIG. 21 also confirmed that there is a significant correlation in the variation in the thickness of the insulating layer 21 inside and outside the product area.

FIG. 22 shows areas S10 adjacent to each other inside and outside the product area with the thickness of the insulating layer formed so as to intentionally vary the thickness under processing conditions different from those of the insulating layer 21 formed in the normal manufacturing process. , T10 is a graph showing the results of measurement. By the filled rhombus shown in FIG. 22 (◆) and solid L7 (R ² correlation coefficient), the thickness of the insulating layer of the area S10, T10 which are adjacent the product areas inside and outside the very strong correlation is established confirmed.

FIG. 23 shows the thickness of the insulating layer 21 in the product areas S1 to S4 of each lot and the insulating layer 21 outside the product area T based on the measured dielectric constant of the insulating layer 21 as described above. It is a graph which shows the correlation of both obtained by calculating thickness. By each plot and solid L8 (R ² correlation coefficient) shown in FIG. 23, in each lot, the thickness variation degree of the insulating layer 21 in the product area S1~S4 changes, insulation in the product area outside T layer It can be seen that the degree of variation in thickness 21 also changes at a substantially similar ratio, and this also indicates that there is a significant strong correlation between the thickness of the insulating layer 21 inside and outside the product area. confirmed.

  Furthermore, the thickness of the insulating layer 21 outside the product area T of the work board 100 when the same process as the actual manufacturing process is carried out with one work lot of four work boards 100 incorporating a general substrate as a chip. This is shown in FIGS. These results were obtained by using a method for calculating the thickness of the insulating layer 21 based on the dielectric constant of the insulating layer 21, and the numerical values described in the areas S10 and T10 in each figure are ( The calculated value of the thickness of the insulating layer 21 in each area−the average value of the thickness of the insulating layer 21 / (average value of the thickness of the insulating layer 21) is expressed as a percentage (%). .

  The first work board 100 shown in FIG. 24, the second work board 100 shown in FIG. 25, and the third work board 100 shown in FIG. 26 have variations in the thickness of the insulating layer outside the product area. Since the range (R) is within 30%, it can be said that the variation in the thickness of the insulating layer 21 is relatively small outside the product area T. On the other hand, in the fourth work board 100 shown in FIG. 27, the variation range (R) is relatively large at 45%, and in particular, the thickness of the insulating layer 21 formed between the product areas S1 and S2. It can be said that there are large variations.

  When the adjacent areas inside and outside the product area S1 are enlarged between the product areas S1 and S2 where the variation is particularly large (FIG. 28), the product area with respect to any column (column C to column R) inside and outside the product area S1. It has been found that a significant correlation also holds in the variation in the thickness of the insulating layer 21 inside and outside (FIG. 29). According to these results, even when the same process as the actual manufacturing process is performed with four work boards 100 as one lot, if the thickness of the insulating layer 21 varies outside the product area T, it will respond accordingly. In addition, it is understood that the thickness of the insulating layer 21 in the product areas S1 to S4 also varies. From this result, there is a significant correlation with the variation in the thickness of the insulating layer 21 inside and outside the product area. It was confirmed that it was established.

  By utilizing the above correlation, whether or not the electronic component 41 and the wiring layer 31 in the product area are conductive in the collective substrate manufactured in the manufacturing process of FIGS. It is possible to determine effectively by inspecting whether or not the plate-like integrated frame 51 and the wiring layer 34 built in are electrically connected. That is, as shown in FIGS. 17 to 29, since the correlation is established between the thickness of the insulating layer 21 and the variation in the thickness of the insulating layer 21 inside and outside the product area, the plate built in the outside T of the product area. If the integrated frame 51 and the wiring layer 34 are electrically connected, it can be determined with high probability that the electronic component 41 and the wiring layer 31 incorporated in the product areas S1 to S4 are electrically connected. On the contrary, if the plate-like integrated frame 51 built in the outside T of the product area and the wiring layer 34 are not conductive, the electronic component 41 and the wiring layer 31 built in the product areas S1 to S4 are connected. If it is not conductive, it can be determined with high probability.

  Therefore, in the inspection of the electronic component built-in substrate according to the present embodiment, the electrical resistance between the wiring layer 34 formed on the plate-like integrated frame 51 and the plate-like integrated frame 51 is measured in the manufacturing process of FIGS. It is preferable to conduct a continuity test. Specifically, among the plurality of formed wiring layers 34, a plurality of wiring layers 34 formed on one area T10 are used as inspection electrodes (TEG terminals), and inspection probes are applied to these wiring layers 34. It is preferable to conduct a continuity test by measuring the electrical resistance using a four-terminal method which is a known technique.

  The electrical resistance can also be measured by using a known two-terminal method. In this case, however, the electrical resistance is affected by the wiring resistance inside the electronic component 41 and the contact resistance of the inspection probe during the measurement. Because it is easy, it is necessary to measure an electrical resistance value of several tens (Ω) level. Since the electric resistance value that can be measured in this way is a large resistance value of several tens (Ω) level, is the resistance value varied due to variations in the electrical connection state between the electronic component 41 and the wiring layer 31? It is determined whether the measured electrical resistance value has a variation in resistance value due to the wiring of the electronic component 41 or the wiring layers 31 and 34, or whether the measured electrical resistance value is a resistance value based on the measurement cause. Difficult to do. If it is determined that the electrical connection state between the electronic component 41 and the wiring layer 31 is a conductive state by point contact, the contact part due to point contact is worn out after being shipped to the market as a product, and the product is There is a high possibility of failure.

  Therefore, in order to perform an electrical connection state between the electronic component 41 and the wiring layer 31 by continuity inspection, it is preferable to use the four-terminal method, but the electronic component 41 and the wiring using the four-terminal method which is a known method. If an attempt is made to directly determine the state of electrical connection with the layer 31, the electronic component that enables measurement by the four-terminal method must use a dedicated electronic component, making it difficult to use the electronic component as a general-purpose product. . For this reason, the electrical connection state between the electronic component 41 and the wiring layer 31 is measured by measuring the electrical connection state between the plate-like integrated frame 51 and the wiring layer 34 formed on the plate-like integrated frame 51 by the four-terminal method. Can be determined indirectly and equivalently. Furthermore, since the electrical resistance value at the level of several (mΩ) can be measured, even when the product is shipped to the market, it is possible to prevent the product from being damaged due to wear.

  From the above, three or more areas are measured on one area T10 for measuring the electrical connection state between the plate-like integrated frame 51 and the wiring layer 34 formed on the plate-like integrated frame 51 using the four-terminal method. A wiring layer 34 as an inspection electrode is formed. In the drawing, an example is shown in which three wiring layers 34 as inspection electrodes are formed on one area T10 (FIG. 13).

  If the resistance value of one wiring layer 34, the plate-like integrated frame 51, and the other wiring layer 34 is a positive real value based on this inspection result, the electrical connection between the plate-like integrated frame 51 and the wiring layer 34 is achieved. It can be determined that the state is conducting. Since the correlation is established between the thickness of the insulating layer 21 and the variation in the thickness of the insulating layer 21 inside and outside the product area as described above, the plate-like integrated frame 51 and the wiring layer 34 are electrically connected to each other. It can be determined that the electronic component 41 and the wiring layer 31 are electrically connected based on the determination result that they are connected.

  On the other hand, if the resistance value of one wiring layer 34, the plate-like integrated frame 51, and the other wiring layer 34 is an infinite value, the plate-like integrated frame 51 and the wiring layer 34 are non-conductive. It can be determined that the electronic component 41 and the wiring layer 31 are not electrically connected based on the result.

  FIG. 30 shows the result of conducting the continuity test based on the measurement of the electrical resistance for each lot. The horizontal axis of the graph shown in the figure is the lot number, and the vertical axis indicates the resistance value (Ω). Each plot is a minimum value, a maximum value, and an average value of resistance values measured for each lot. In the measurement of the present embodiment, when the resistance value within 1 (Ω) is a normal conducting value, for example, lot 7 and lot 9 have a maximum resistance value exceeding 1 (Ω). These lots are abnormal lots because the insulating layer 21 is thick at any part of the worksheet 100 and the wiring layer 34 and the plate-like integrated frame 51 may not be electrically connected. It is judged.

  The following methods can be used to manage products. First, for the detected abnormal lot, the continuity inspection is performed again on the plate-like integrated frame 51 for each work sheet (1/4 of the work board 100) for the work board 100 manufactured in the abnormal lot, and the thickness of the insulating layer 21 is determined. Detect worksheets that show abnormalities. Thereafter, by managing so that the detected abnormal worksheet is removed and shipped, proper quality control at the time of shipment can be realized.

  Further, the continuity test is performed on all the electronic components 41 incorporated in the product area of the detected abnormal worksheet, or the burn-in (heating) test is performed on all the electronic components 41, and the thickness of the insulating layer 21 is abnormal. Is detected. Thereafter, by managing to remove the detected abnormal electronic component 41 and ship the individual substrates, the number of defective individual substrates can be reduced, so that the product yield can be improved.

  Thus, during the manufacturing process of forming the via hole 22 on the electronic component 41, the via hole 23 is also formed on the plate-like integrated frame 51, and then the electrical connection between the plate-like integrated frame 51 and the wiring layer 34 is measured. The electrical connection state between the electronic component 41 and the wiring layer 31 can be measured easily and reliably with high accuracy without directly measuring the electrical connection state between the electronic component 41 and the wiring layer 31 by performing a simple inspection. Judgment can be made.

  In addition, it is possible to easily and accurately inspect the interlayer connection between the electronic component 41 built in the insulating layer 21 and the wiring layer 31 without performing cross-sectional analysis of the finished product of all the collective substrates. Board pieces (worksheets or individual substrates) can be manufactured at low cost, thereby improving yield, improving productivity and economy, and improving product mounting reliability. Become.

(Second Embodiment)
FIG. 31 is an essential part enlarged cross-sectional view schematically showing the structure of the second embodiment of the collective substrate according to the present invention. As shown in the figure, the work board 100 has resin sheets 25a and 25b having different thicknesses placed on the insulating layer 13 of the substrate 11, and is replaced with a plate-like integrated frame 51 (conductor) at a predetermined position inside the insulating layer 21. Except that the plate-like integrated frame 61 is embedded, it is configured in the same manner as the worksheet 100 of the first embodiment.

  FIG. 32 is an enlarged sectional view schematically showing the structure of the second embodiment of the plate-like integrated frame 61 of the present invention. The plate-like integrated frames 61 are placed on the resin sheets 25 having different thicknesses and are arranged at different levels inside the insulating layer 21. At least one of the levels is located at the same level as the electronic component 41, and the distance d1 from the electronic component 41 to the wiring layer 31 and the distance d1 from the plate-like integrated frame 61 to the wiring layer 34a are substantially the same distance. It has become. The other levels are arranged such that the distances d2 and d3 from the plate-like integrated frame 61 to the wiring layers 34b and 34c are sequentially longer than the distance d1 from the electronic component 41 to the wiring layer 31.

  Even if such a plate-like integrated frame 51 is used, the same effects as those of the first embodiment can be obtained. In addition, when conducting a continuity test between the plate-like integrated frame 61 and the wiring layer 34c first, if the resistance values of the plate-like integrated frame 61 and the wiring layer 34c can be measured, they are conducted even though the distance d3 is the farthest. Therefore, it can be determined that there is no need to conduct a continuity test on the other wiring layers 34a and 34b and that the electronic component 41 and the wiring layer 31 are conductive.

  Similarly, if the resistance values of the plate-like integrated frame 61 and the wiring layer 34c can be measured, conduction at a distance d2 far from the distance d1 from the electronic component 41 to the wiring layer 31 can be confirmed. Even if the resistance values of 61 and the wiring layer 34c cannot be measured, if the other wiring layer 34b and the plate-like integrated frame 61 are electrically connected, there is no need to conduct a continuity test on the other wiring layer 34a and the electronic component 41 It can be determined that the wiring layer 31 is conductive. Furthermore, when the resistance values of the plate-like integrated frame 61 and the wiring layer 34 b cannot be measured finally, the resistance values of the plate-like integrated frame 61 and the wiring layer 34 a may be measured, and the electronic component 41 built in the insulating layer 21. It is possible to easily and accurately inspect the interlayer connection between the wiring layer 31 and the wiring layer 31 quickly.

  Furthermore, since the blasting process, which is a known technique, causes the projecting material to collide with the insulating layer 21, if the shape of the projecting material is deformed due to wear, the amount of processing for cutting the insulating layer 21 is reduced, and the product yield is increased. Inconvenience of lowering occurs. Therefore, as in the present embodiment, by arranging the plate-like integrated frame 61 at a level different from the electronic component 41 and farther from the distance d1 from the electronic component 41 to the wiring layer 31, the shape of the projection material can be reduced. Deformation can be detected. More specifically, since the resistance values cannot be measured in order of increasing distances d1, d2, and d3 from the plate-like integrated frame 61 to the wiring layer 34, the distance d3 from the plate-like integrated frame 61 to the wiring layer 34c or / In addition, when the resistance value at the distance d2 from the plate-like integrated frame 61 to the wiring layer 34b cannot be measured, the processing amount for cutting the insulating layer 21 can be determined. Thus, since the amount of processing can be determined before the resistance value at the distance d1 from the plate-like integrated frame 61 to the wiring layer 34a can no longer be measured, it is possible to prevent the product yield from decreasing.

  In this embodiment, the processing amount is determined by arranging the plate-like integrated frame 61 at a level different from that of the electronic component 41. For example, the pattern opening diameter of the mask layer 33 (opening diameter of the via holes 22 and 23) is large. The amount of machining can be similarly determined when blasting is performed while changing the number of times, or when laser machining is performed by changing the number of shots.

  As described above, according to the electronic component built-in substrate, the manufacturing method thereof, and the inspection method thereof according to the present invention, the electrical connection state between the electronic component and the wiring layer is not directly measured and is separated from the electronic component. Equipment with built-in electronic components that can be easily and accurately determined by continuity inspection between conductors and wiring layers provided on the body, improving productivity, economy, and product reliability. It can be widely and effectively used for devices, systems, various devices, etc. that require particularly small size and high performance.

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate (base | substrate) 12, 13, 21 ... Insulating layer, 12a, 12b, 21a, 34, 34a, 34b, 34c ... Wiring layer, 25a, 25b ... Resin sheet, 41 ... Electronic component, 42 ... Land electrode, 51, 61 ... plate-like integrated frame (conductor), 100 ... work board (collected substrate), S1 to S4 ... product area, S10 ... one area in the product area, T ... non-product area, T10 ... in the non-product area 1 area, W ... windows.

Claims (3)

A substrate;
An electronic component placed on the substrate;
A conductor mounted on a non-mounting portion of the electronic component in the base;
An insulating layer formed to cover the electronic component and the conductor;
A first wiring formed in the insulating layer and connected to the electronic component;
A second wiring formed on the insulating layer and connected to the conductor;
Have
The thickness of the insulating layer above the site where the first wires are connected in an electronic component, rather thin than the thickness of the insulating layer above the site where the second wiring is connected in said conductor,
The conductor is arranged so as to surround the outer periphery of each aggregate with respect to a plurality of aggregates including at least one or more individual substrates arranged in the plane direction.
Electronic component built-in substrate. Preparing a substrate;
Placing an electronic component on the substrate;
Placing a conductor on a non-mounting portion of the electronic component on the base;
Forming an insulating layer covering the electronic component and the conductor;
Forming a first wiring connected to the electronic component in the insulating layer;
Forming a second wiring connected to the conductor in the insulating layer;
Have
The thickness of the insulating layer above the site where the first wires are connected in the electronic component, and thinner than the thickness of the insulating layer above the site where the second wiring is connected in said conductor,
The conductor is arranged so as to surround the outer periphery of each aggregate with respect to a plurality of aggregates including at least one or more individual substrates arranged in a plane direction.
Manufacturing method of electronic component built-in substrate. The amount of processing of the first connection hole for forming the first wiring in the insulating layer is different from the amount of processing of the second connection hole for forming the second wiring in the insulating layer. ,
The manufacturing method of the electronic component built-in substrate according to claim 2 .