JP5483493B2 - Bullet ball machine - Google Patents

Description

  The present invention relates to a ball game machine in which a driving means outputs a driving signal based on driving data output at a predetermined cycle, and a driven device is driven by this driving signal to perform a gaming operation.

  Conventionally, as this type of ball game machine, for example, there is a pachinko game machine disclosed in Patent Document 1 below.

  In the game area of this pachinko gaming machine, there are provided driven devices such as a normal symbol display composed of 7-segment LEDs (light emitting diodes) and a variable winning ball apparatus controlled to open and close by a solenoid. Drive data from the CPU (central processing unit) is output to the output circuit via the output port and amplified in the output circuit. The amplified drive data is output as a drive signal from the output circuit, and the 7-segment LED of the driven device is controlled to emit light according to the drive signal, and the solenoid of the driven device is driven.

Japanese Unexamined Patent Publication No. 2000-300812 (see paragraphs [0050] and [0052] and FIGS. 5 and 6)

  However, in the conventional pachinko gaming machine described above, since the output cycle of the drive data output from the CPU coincides with the drive cycle in which the driven device is actually driven, the drive cycle of the driven device that can be recognized by the player The CPU processing cycle is recognized. For this reason, the conventional pachinko gaming machine has a problem that an illegal act is performed from the processing cycle of the CPU recognized by the player.

The present invention has been made to solve such a problem, and an oscillation means for generating an oscillation signal at a constant period, and a game operation is controlled and processed at a predetermined period based on the oscillation signal generated by the oscillation means. Game control means, data output means for outputting drive data at a predetermined cycle by control processing of the game control means, drive means for outputting a drive signal based on drive data output from the data output means, and In a ball game machine comprising a driven device that is driven by a driving signal output from a driving means and performs a gaming operation,
A data holding means for holding drive data output from the data output means, and an oscillation signal generated by the oscillating means is divided into a specific period different from a predetermined period, and the divided clock signal is driven at this specific period. A frequency dividing means for outputting to the means,
The driving means outputs a driving signal based on the driving data held by the data holding means in synchronization with a specific period by the input of the frequency-divided clock signal from the frequency dividing means.

  According to this configuration, in the driven device, the drive unit is driven by the drive signal based on the drive data held in the data holding unit in synchronization with a specific period by the input of the frequency-divided clock signal from the frequency-dividing unit. Is driven. Therefore, the output cycle of drive data output from the data output means at a predetermined cycle under the control of the game control means and the output cycle of drive signals output at a specific cycle different from the predetermined cycle from the drive means are: To be different. For this reason, the player cannot recognize the control processing cycle of the game operation by the game control means from the recognizable operation cycle of the driven device. Therefore, it is possible to prevent the player from performing an illegal act by recognizing the control processing cycle of the game control means. Further, since the driven device is driven in synchronization with a specific cycle based on the divided clock signal input from the frequency dividing means, the driving cycle of the driven device changes the control processing of the game control means. Without changing, the frequency dividing means can be changed only by changing the frequency dividing period of the oscillation signal.

Further, the present invention is a variable winning device that operates from a closed state in which a game ball is difficult to win to an open state in which a game ball is easy to win when a predetermined condition is satisfied,
When a game ball wins the variable winning device, a special determination means for performing a special determination process on whether or not to activate a special game advantageous to the player at a predetermined cycle is provided.

  According to this configuration, the special determination process by the special determination unit is performed in a predetermined cycle. When a predetermined condition is satisfied, the drive signal for operating the variable winning device is the data holding unit and the drive unit. Is output in synchronization with a specific period. Therefore, the cycle in which the variable winning device operates is different from the cycle in which the special determination means performs a special determination process as to whether or not to activate a special game advantageous to the player. For this reason, the period in which the special determination unit performs the special determination process and the period in which the variable winning device operates does not continue to be synchronized. As a result, in a special determination process for determining whether or not to activate a special game advantageous to the player, which is performed when a game ball wins the variable winning device, the determination that the operation of the special game is determined Will not continue or will not continue to be determined. Therefore, it is possible to ensure the fairness of the special determination process. Further, the player cannot recognize the control processing cycle of the game control means from the cycle of the operation of opening and closing the variable winning device. Therefore, it is possible to prevent an illegal act in which a player aims for a special game based on the operation of the variable prize device.

Further, the present invention provides a normal determination means for performing a normal determination process whether or not to establish a predetermined condition at a predetermined cycle;
A normal symbol display device for displaying whether or not a predetermined condition is satisfied as a result of the normal determination process by the normal determination means in a stop display mode after the normal symbol variation display;
Interval time that sets the interval time between the operation time when the variable winning device is in the open state and the operation time when the normal symbol display device is displaying longer than the time of the difference between the specific cycle and the predetermined cycle Setting means,
After the interval time set by the interval time setting means has elapsed, the data output means outputs drive data for displaying the normal symbol display device or drive data for operating the variable winning device in the open state at a predetermined cycle. It is characterized by doing.

  According to this configuration, the interval time between the operation time in which the variable winning device is in the open state and the operation time in which the normal symbol display device performs display is determined by the interval time setting means using a specific period and a predetermined period. It is set longer than the difference time. Further, the drive data for causing the normal symbol display device to perform display or the drive data for operating the variable winning device in the open state is output by the data output means after the interval time set by the interval time setting means has elapsed. Therefore, even though the variable winning device is operating in the open state, the normal symbol display device variably displays or the normal symbol display device does not display the stop display mode in which the predetermined condition is satisfied. It is possible to eliminate a peculiar situation in which the variable winning device operates in an open state. For this reason, it is possible to prevent the player's recognition regarding the game situation from being confused. In addition, since the operation time in which the variable winning device is in the open state and the operation time in which the normal symbol display device is displaying are reliably distinguished, the variable winning device can be detected by an illegal act during the variable display of the normal symbol display device. Can be prevented from operating in an open state.

In addition, the present invention provides a special display that displays whether or not the driven device activates a special game advantageous to the player as a result of the special determination process by the special determination means in the stop display mode after the special symbol variation display. When it is determined that a special game advantageous to the player is activated by a special determination process by the symbol display device and the special determination means, the game ball is won by the variable display device from the closed state where the game ball is difficult to win. Including a special variable prize-winning device that operates to an open state
Interval for setting the interval time between the operation time for which the special symbol display device is displaying and the operation time for which the special variable winning device is in the open state to be longer than the time of the difference between the specific cycle and the predetermined cycle Time setting means,
After the interval time set by the interval time setting means has elapsed, the data output means outputs drive data for operating the special variable winning device in an open state or drive data for displaying on the special symbol display device at a predetermined cycle. It is characterized by outputting.

  According to this configuration, the interval time between the operation time for which the special symbol display device is displaying and the operation time for which the special variable prize-winning device is in the open state is determined by the interval time setting means with a specific period. It is set longer than the time of the difference from the cycle. Further, the drive data for operating the special variable prize-winning device in the open state or the drive data for displaying on the special symbol display device is output by the data output means after the interval time set by the interval time setting means has elapsed. . Therefore, even though the special symbol display device performs the variable display, the special variable winning device operates in the open state or the special variable winning device operates in the open state. It is possible to eliminate the peculiar situation that the device displays the fluctuation. For this reason, it is possible to prevent the player's recognition regarding the game situation from being confused. In addition, since the operation time during which the special symbol display device is displaying and the operation time during which the special variable prize-winning device is in the open state are reliably distinguished, the special variable prize is displayed due to fraud during the variable display of the special symbol display device. It is possible to prevent the device from operating in the open state.

  According to the present invention, as described above, since the player cannot recognize the control processing cycle of the game operation by the game control means from the recognizable operation cycle of the driven device, the player can control the game. By recognizing the control processing cycle of the means, it is possible to prevent cheating. Further, the driving cycle of the driven device can be changed by changing only the frequency dividing cycle of the oscillation signal in the frequency dividing means without changing the control processing of the game control means.

It is a front view of the pachinko machine by the 1st and 2nd embodiment of the present invention. It is a block diagram which shows the main structures of the electronic circuit which carries out process control of the game operation | movement of the pachinko machine shown in FIG. It is a flowchart which shows the outline of the main process in the main control board of the pachinko machine shown in FIG. It is a flowchart which shows the outline of the system timer interruption process in the main control board of the pachinko machine shown in FIG. It is a flowchart which shows the detail of the special symbol control process shown in FIG. It is a figure which shows the flow of the special symbol control process shown in FIG. It is a flowchart which shows the detail of the special symbol memory | storage check process shown in FIG. It is the figure which showed the timing chart of the drive data in the pachinko machine shown in FIG. 1, a frequency-divided clock signal, and a drive signal. It is a flowchart which shows the outline of the modification of the main process in the main control board of the pachinko machine shown in FIG. It is a flowchart which shows the outline of the modification of the system timer interruption process in the main control board of the pachinko machine shown in FIG. It is a block diagram which shows the main structures of the modification of the electronic circuit which carries out process control of the game operation | movement of the pachinko machine shown in FIG. It is a block diagram which shows the main structures of the electronic circuit which processes and controls the game operation | movement of the pachinko machine by the 2nd Embodiment of this invention. In the pachinko machine shown in FIG. 12, the interval between the operation time of the ordinary electric accessory and the operation time during which the ordinary symbol display device performs display when the operation time in which the ordinary electric accessory is in the open state is the longest. It is the timing chart figure which showed time. In the pachinko machine shown in FIG. 12, the interval between the operation time of the ordinary electric accessory and the operation time during which the ordinary symbol display device performs display when the operation time in which the ordinary electric accessory is in the open state is the shortest. It is the timing chart figure which showed time.

  Next, the best mode for carrying out the present invention will be described.

  FIG. 1 is a front view of a pachinko machine 1 according to a first embodiment of the present invention.

  A game board 2 is provided in front of the pachinko machine 1 to allow the pachinko balls, which are game balls, to flow down. In the game area on the surface of the game board 2, a large number of nails for changing the flow direction of the flowing pachinko balls are planted. In the figure, only some nails are shown. An upper plate 3 is provided below the game board 2, and on the lower right side of the upper plate 3, a launch handle 5 that is operated when a pachinko ball is driven into the game area of the game board 2 via the rail 4. Is provided. Further, an upper frame decoration lamp 6 is provided above the game board 2.

  A decorative symbol display device 10 for displaying decorative symbols is provided at the center of the game board 2. The decorative symbol display device 10 includes a liquid crystal display (LCD), and displays a plurality of symbol elements such as numbers and characters as decorative symbols. A normal symbol display device 11 and a special symbol display device 12 are provided at the lower left of the game board 2. The normal symbol display device 11 includes two LEDs (light emitting diodes) that alternately display “green” and “red” that constitute the normal symbol, and the special symbol display device 12 includes “0” to “0” that constitute the special symbol. It consists of two 7-segment LEDs that display the number “9” in 7 digits in 2 digits. The decorative symbol display device 10 displays the special symbol displayed by the special symbol display device 12 as the decorative symbol.

  Further, on the right side of the special symbol display device 12, a normal symbol start memory number display unit 13 and a special symbol start memory number display unit 14 composed of four LEDs are provided. In addition, a state display unit 15 composed of two LEDs is provided on the right side of the normal symbol start storage number display unit 13 and the special symbol start storage number display unit 14. The state display unit 15 notifies the player of the gaming state of the pachinko machine 1, for example, the probability variation state, the probability normal state, the short time state, and the like by lighting the two LEDs. In addition, passing gates 16 are provided on the left and right sides of the decorative symbol display device 10. The passing gate 16 constitutes a normal symbol starting port for starting a normal symbol variation display that is lit and displayed on the normal symbol display device 11.

  Also, below the decorative symbol display device 10, there is provided an ordinary electric accessory 17 constituting a special symbol start winning opening. The ordinary electric accessory 17 constitutes a special symbol start winning opening for starting a special symbol variation display displayed on the special symbol display device 12, and the pachinko ball shown in FIG. The ball receiving opening has a vane member that is displaceable between an open state where it is easy to win a prize and a closed state where a pachinko ball, which is in a disadvantageous state, is difficult to win. Also, below the ordinary electric accessory 17 is provided a big prize opening 18 that is opened in the case of a jackpot game, which will be described later, and a general prize opening 19 is provided on the left and right of the ordinary electric accessory 17 respectively. ing. Further, below the grand prize winning opening 18, an out opening 20 is provided through which a pachinko ball that has not won a prize in any of the above-mentioned ordinary electric accessory 17, big prize winning opening 18 and general prize winning opening 19 enters. .

  Up to four pachinko balls that have passed through the passage gate 16 are reserved, and the number of retained pachinko balls is stored in a normal symbol retained number counter stored in the main RAM 34 to be described later. In accordance with the number of reserved items, the above-described normal symbol start memorized number display unit 13 is lit and displayed up to four. Similarly, up to four pachinko balls won in the ordinary electric accessory 17 are retained, and the number of retained pachinko balls is stored in an ordinary electrification winning counter stored in the main RAM 34 described later. Depending on the number of reserves, the above-mentioned special symbol start memorized number display section 14 is lit up to a maximum of four.

  Above the upper plate 3, a ball lending button 7a, a return button 7b, a selection button 7c, and a decision button 7d are provided. The ball lending button 7a is operated when lending a pachinko ball within the range of the balance of the prepaid card inserted in the card unit provided in the pachinko machine 1 is received. The return button 7b is operated when returning the card inserted in the card unit. The selection button 7c is operated when an information item displayed on the decorative symbol display device 10 is selected. The determination button 7d is operated when determining an information item to be displayed on the decorative symbol display device 10.

  FIG. 2 is a block diagram showing a main configuration of an electronic circuit that controls the gaming operation of the pachinko machine 1 according to the first embodiment of the present invention.

  This electronic circuit is provided on the main control circuit provided on the main control board 30, the sub control circuit provided on the sub control board 50, the payout control circuit provided on the payout control board 60, and the launch control board 70. It consists of a launch control circuit. The main control board 30 is a game control board that performs electrical control related to the progress of the pachinko game on the game board 2, and the sub control board 50 is based on various control devices and game information from the main control board 30. It is an effect control board which performs electrical control of the game effect by. The payout control circuit of the payout control board 60 and the fire control circuit of the fire control board 70 control payout of winning balls and rental balls and launching of pachinko balls based on control signals and game information from the main control board 30.

  A microcomputer 31 and an oscillator 40 are mounted on the main control board 30. The oscillator 40 constitutes an oscillating unit that generates an oscillation signal at a constant period. The microcomputer 31 includes a main CPU 32, a main ROM (read only memory) 33, and a main RAM (random access memory) 34. The main CPU 32 constitutes game control means for controlling the game operation at a predetermined cycle based on the oscillation signal generated by the oscillator 40, in this embodiment, a cycle of 2 [msec]. The main ROM 33 stores a program for the main CPU 32 to control the gaming operation of the pachinko machine 1, various tables, and the like. Data is temporarily stored in the main RAM 34 when processing of the main CPU 32 is controlled. The main RAM 34 also has a big winning opening opening counter for counting the number of opening of the big winning opening 18 in the big winning game that constitutes a special game advantageous to the player, and the big winning opening 18 is opened in each round of the big winning game. A special winning opening opening time timer that counts the current time, the above-described normal symbol holding number counter for counting the number of normal symbol starting memories, and the special symbol holding number counter for counting the number of special symbol starting memories are stored.

  A watchdog timer circuit 35 and an oscillator 36 are mounted on the main control board 30. The watchdog timer circuit 35 is driven based on an oscillation signal generated by the oscillator 36 at a constant cycle, and outputs a reset signal to the main CPU 32 when the main CPU 32 enters a state where control processing is impossible and becomes a runaway state. When this reset signal is input to the main CPU 32, the main CPU 32 is reset, and the main CPU 32 resumes control processing from a predetermined address of the program stored in the main ROM 33.

  A switch input circuit 37 is mounted on the main control board 30. The microcomputer 31 is connected to the passing gate switch 16s, the start winning port switch 17s, the count switch 18s, and the general winning port switch 19s through the switch input circuit 37. The passing gate switch 16 s is provided inside the above-described passing gate 16 and detects that the pachinko ball passes the passing gate 16, and the start winning port switch 17 s detects the pachinko ball that has won the ordinary electric accessory 17. The count switch 18 s detects a pachinko ball that has won the grand prize opening 18, and the general prize opening switch 19 s detects a pachinko ball that has won the general prize opening 19. When these various switches 16 s, 17 s, 18 s, 19 s detect a pachinko sphere, the detection signal is input to the microcomputer 31 via the switch input circuit 37.

  Further, an output driving circuit 38, a data latch circuit 39, and a frequency dividing circuit 41 are mounted on the main control board 30. The output drive circuit 38 is connected to the normal symbol display device 11, the special symbol display device 12, the state display device 15, the start winning port solenoid 17v, and the big winning port solenoid 18v. The start winning port solenoid 17v expands the ball receiving port of the ordinary electric accessory 17, and the large winning port solenoid 18v opens and closes the door of the large winning port 18. The normal symbol display device 11, the special symbol display device 12, the status display device 15, the ordinary electric accessory 17 including the start winning port solenoid 17v, and the large winning port 18 including the large winning port solenoid 18v constitute a driven device. ing. The main CPU 32 constitutes data output means for outputting drive data for driving these driven devices at a predetermined cycle by the control processing of the game control means described above. The output drive circuit 38 constitutes drive means for driving the driven device based on the drive data output from the data output means. The driven device is driven by a drive signal output from the output drive circuit 38 and performs a game operation.

  Further, the output drive circuit 38 is connected to the microcomputer 31 via the data latch circuit 39, and the drive data output from the microcomputer 31 is not directly output to the output drive circuit 38, but to the data latch circuit 39. Output and hold. The data latch circuit 39 constitutes data holding means for holding drive data output from the main CPU 32. The frequency dividing circuit 41 receives an oscillation signal generated by the oscillator 40, divides the oscillation signal into a specific cycle of 8 [msec], and generates a divided clock signal at a specific cycle of 8 [msec]. Frequency dividing means for outputting to the output drive circuit 38 is configured. This specific cycle is different from a predetermined cycle of 2 [msec] in which the main CPU 32 controls the game operation. The output drive circuit 38 outputs a drive signal based on the drive data held in the data latch circuit 39 in synchronization with a specific cycle of 8 [msec] by the input of the divided clock signal from the frequency divider circuit 41. To do.

  Further, the ordinary electric accessory 17 constitutes a variable winning device that operates from a closed state where a pachinko ball is difficult to win to an open state where a game ball is easily won when a predetermined condition is satisfied. When the pachinko ball passes through the passage gate 16, the main CPU 32 performs a normal determination process for determining whether or not the predetermined condition is satisfied, that is, whether or not the blade member of the ordinary electric accessory 17 is opened or closed. An ordinary determination means for determining at a predetermined period of msec] is configured. Further, when the main CPU 32 wins a pachinko ball in the ordinary electric accessory 17, a special determination is made to perform a special determination process for determining whether or not to activate a jackpot game advantageous to the player at a predetermined cycle of 6 [msec]. Means.

  When the predetermined condition is satisfied as a result of the normal determination process by the normal determination unit, the main CPU 32 sets drive data for causing the data output unit to operate the ordinary electric accessory 17 at a predetermined cycle of 2 [msec]. To output. Further, the normal symbol display device 11 displays whether or not the predetermined condition is satisfied as a result of the normal determination process by the normal determination means in a stop display mode after the normal symbol variation display. In the present embodiment, two LEDs that alternately display “green” and “red” are stopped and displayed in “green” to indicate that a predetermined condition has been established. In addition, the special symbol display device 12 displays whether or not the big hit game advantageous to the player is activated as a result of the special determination process by the special determination means in the stop display mode after the special symbol variation display. In this embodiment, two 7-segment LEDs that display the numbers from “0” to “9” are displayed in a stopped state at “7” to indicate that it has been decided to activate a big hit game advantageous to the player. To do. Further, when it is determined that the big hit game advantageous to the player is activated by the special determination process by the above-mentioned special determination means, the special winning opening 18 is the ordinary electric accessory from the closed state where the game ball is difficult to win. The special variable prize-winning device that operates to an open state in which the game ball is easier to win than 17 is configured.

  Further, a backup clear switch board (not shown) is connected to the main control board 30 via a switch circuit 37. A backup clear switch is mounted on the backup clear switch board. The backup clear switch is a backup command for clearing the backup contents of the main RAM 34 constituting the microcomputer 31 mounted on the main control board 30 and the work RAM 64 constituting the microcomputer 65 mounted on the payout control circuit of the payout control board 60. Output a clear signal.

  The main CPU 32 is connected to a sub control circuit of the sub control board 50, a payout control circuit of the payout control board 60, and a command output port (not shown) for outputting various commands to the launch control circuit of the launch control board 70. Yes. From this command output port, a control signal (command) sent from the main CPU 32 is serially transmitted to each of the boards 50, 60 and 70.

  The sub control board 50 is connected to the LCD 10 and performs image display control for displaying an image on the LCD 10. Further, the sub-control board 50 is connected to the speaker 58 and the lamp / LED 59, sound control for emitting a sound effect from the speaker 58 according to the gaming state, and electrical control for controlling the light emission of the lamp / LED 59. I do. The lamp / LED 59 represents a frame upper decoration lamp 6, a normal symbol start memory number display unit 13, a special symbol start memory number display unit 14, and the like. A sub CPU 51, a program ROM 52, and a work RAM 53 are mounted on the sub control board 50. The sub CPU 51 interprets commands received from the main control board 30 via a relay board and a command input port (not shown), and issues control commands to the image control circuit 54, the sound control circuit 55, and the lamp control circuit 56. The program ROM 52 stores a control program for the sub CPU 51 to control the operations of the LCD 10, the speaker 58, and the lamp / LED 59. The work RAM 53 serves as a temporary storage unit when the sub CPU 51 performs processing control according to the control program.

  The image control circuit 54 generates image data to be displayed on the LCD 10 in accordance with a control command from the sub CPU 51. The main CPU 32 performs the above-described special determination process as a big hit determination when a pachinko ball wins the normal electric accessory 17 and a start win occurs, displays the result of the big hit determination on the special symbol display device 12, and displays an image. The control circuit 54 sequentially stops and displays decorative symbols on the LCD 10 in a manner corresponding to the result of the jackpot determination. When the left symbol and the right symbol are in the reach state where the same symbol is stopped and displayed together, the reach effect is performed on the LCD 10 using the decorative symbol and the effect image. The sound control circuit 55 controls the speaker 58 by a drive signal from the sub CPU 51. The lamp control circuit 56 controls the light emission of the lamp / LED 59 according to the gaming state of the pachinko machine 1 according to the drive signal from the sub CPU 51.

  The program ROM 52 constitutes an effect storage means in which a plurality of effect modes are stored in a pattern. The main CPU 32, the main ROM 33, and the main RAM 34 in the main control board 30, and the sub CPU 51, the program ROM 52 in the sub control board 50, and The work RAM 53 constitutes an effect determining unit that determines an effect mode corresponding to the effect to be executed from the effect modes stored in the effect storage unit. The LCD 10 and the image control circuit 54, the speaker 58 and the sound control circuit 55, and the lamp / LED 59 and the lamp control circuit 56 constitute an effect means for executing an effect corresponding to the effect mode determined by the effect determination means. Yes.

  The payout control board 60 is connected to the main control board 30 via a frame relay board (not shown). On the payout control board 60, a payout control circuit is configured, and an oscillator 61 and a microcomputer 65 are mounted. The microcomputer 65 includes a CPU 62, a program ROM 63, and a work RAM 64. The oscillator 61 generates an oscillation signal at a constant period and drives the microcomputer 65. The program ROM 63 stores and stores a control program for the CPU 62 to process and control the launching of pachinko balls, a control program for controlling the processing of pachinko ball lending and prize ball payout, and the like. The work RAM 64 temporarily stores data when processing control is performed by the CPU 62. Further, a payout solenoid 66 is connected to the payout control board 60 as an actuator. The payout solenoid 66 is driven and controlled when paying out a prize ball or lending a pachinko ball. A count switch 67 is connected to the payout control board 60. The counting switch 67 counts the pachinko balls to be paid out, and outputs a detection signal to the CPU 62 when detecting that a predetermined number of pachinko balls have been paid out.

  The launch control board 70 is connected to the payout control board 60, and the launch control circuit configured on the launch control board 70 is controlled by the microcomputer 65 mounted on the payout control board 60. An oscillator 71 is mounted on the launch control board 70, and a ball feed solenoid 72, a launch solenoid 73, a touch switch 74, and a launch volume 75 are connected to the launch control board 70. The oscillator 71 generates an oscillation signal with a period of 6 [msec]. This period is different from a specific period of 8 [msec] in which the output drive circuit 38 drives the driven device such as the ordinary electric accessory 17 under the control of the main CPU 32. The touch switch 74 outputs a detection signal to the CPU 62 when it is detected that the player's hand or the like has touched the operation part of the launch handle 5. When receiving this detection signal, the CPU 62 detects that the player has touched the firing handle 5. The firing volume 75 detects the amount of operation of the firing handle 5 for a predetermined time. The ball feed solenoid 72 is driven when the launch handle 5 is rotated while the touch sensor is touched by the player, and sends the pachinko balls stored in the upper plate 3 to the launch position. The firing solenoid 73 is driven in synchronism with a period of 6 [msec] of an oscillation signal generated by the oscillator 71 when the firing handle 5 is rotated while the touch sensor is touched by the player. The pachinko ball sent to the launch position by the ball feed solenoid 72 is fired on the game board 2 100 per minute via the rail 4.

  A power supply monitoring circuit 81 is mounted on the power supply board 80. The power monitoring circuit 81 supplies power to the circuits and the like configured on the respective boards 30, 50, 60, and 70 and monitors the power supply state.

  Next, the processing of the gaming operation of the pachinko machine 1 according to the first embodiment of the present invention will be described.

  FIG. 3 is a flowchart showing an outline of the main game process performed in the main control circuit of the main control board 30 of the pachinko machine 1 according to the first embodiment of the present invention.

  When the power of the pachinko machine 1 is turned on, first, initialization setting processing of the operation of the main CPU 32 is performed (see FIG. 3, step (hereinafter referred to as S) 1). In this initialization setting processing, processing such as access permission of the main RAM 34, backup restoration processing, and work area initialization is executed. Subsequently, a CTC operation setting process for setting 2 [msec] in a CTC register built in the main CPU 32 is performed so that a system timer interrupt described later occurs every 2 [msec] (S2).

  Next, an interrupt prohibition process is performed so as to mask execution of the interrupt process (S3), the initial value random number is updated (S4), and an interrupt is permitted (S5). Next, it is determined whether or not the value of the system timer monitoring timer is 3 (S6). If the value of the system timer monitoring timer is not 3, the processes of S3 to S6 are repeated. When the value of the system timer monitoring timer becomes 3, that is, when 6 [msec] (= 3 × 2 [msec]) has elapsed, 3 is subtracted from the value of the system timer monitoring timer (S7), The system timer monitoring timer value is reset. Subsequently, the main CPU 32 updates various timers, such as a waiting time timer for synchronizing the main control circuit of the main control board 30 and the sub control circuit of the sub control board 50, and a prize winning opening time timer. Is executed (S8).

  Next, a special symbol control process, which will be described later, is performed by the main CPU 32 to control the variation of the special symbol (S9). In this special symbol control process, as will be described later, a special determination process is performed to determine whether or not to activate a big hit game advantageous to the player. Subsequently, a normal symbol control process for controlling the fluctuation of the normal symbol is performed (S10). In this normal symbol control process, a normal determination process is performed by the above-described normal determination means, and it is determined whether or not to open and close the blade member of the normal electric accessory 17. Next, a symbol display device control process is performed in which the special symbol display device 10 and the normal symbol display device 11 are variably displayed in the variation display mode determined in the symbol control processes of S9 and S10 (S11).

  Next, a game state command control process is performed (S12), followed by an effect control command output control process (S13) and a payout process (S14). When this process ends, the process returns to S3, and the processes of S3 to S14 are repeatedly executed.

  FIG. 4 is a flowchart showing the flow of the system timer interrupt process performed by the main CPU 32 by interrupting every 2 [msec] while the main process described above is executed.

  In this system timer interrupt process, first, the main CPU 32 saves the value of each register at the time of occurrence of the interrupt in the stack area of the main RAM 34 (see FIG. 4, S21). Next, 1 is added to the system timer monitoring timer value (S22), and then clear data is set in the watchdog output data (S23).

  Next, based on the detection signals output from the switches 16 s to 19 s described above, whether or not the pachinko ball has passed through the passage gate 16, the ordinary electric accessory 17, the big prize opening 18, the general prize opening 19, etc. A switch input detection process for detecting whether or not a pachinko ball has won is executed (S24). In the process of S24, a process of extracting a jackpot determination random number used for the jackpot determination or the like is also performed, and it is determined whether or not the jackpot game is performed in the special symbol control process (see FIG. 3, S9). .

  Next, after the processing of S24 is completed, the main CPU 32 executes port output processing (S25). In this process, the main CPU 32 outputs various commands stored in the transmission data storage area of the main RAM 34 to the data latch circuit 39. Specifically, these commands include the normal symbol display device 11, the special symbol display device 12, the status display device 15, the driving signal for the start winning port solenoid 17v, and the special winning port solenoid 18v.

  Thereafter, in order to return to the state at the time of occurrence of the interrupt, a register return process for returning the register value saved in the stack area of the main RAM 34 to the register is performed (S26), and the interrupt process is permitted ( S27), the system timer interrupt process ends. When this system timer interrupt process ends, this subroutine ends, and the main process by the main CPU 32 is executed again from the state at the time of the interrupt occurrence.

  Next, the special symbol control process performed by the main CPU 32 in FIGS. 3 and S9 will be described with reference to FIG. In the figure, the numerical values drawn on the sides of S32 to S40 indicate the contents of the control state flags corresponding to those processes, the processing corresponding to the numerical values of the control state flags is executed, and the special symbol game is executed. Will progress.

  In the special symbol control process, first, the main CPU 32 loads and reads the control state flag (see S31 in FIG. 5). In S32 to S40, which will be described later, the main CPU 32 determines whether to execute various processes based on the value of the control state flag, as will be described later. This control state flag indicates the game state of the special symbol game, and enables one of the processes in S32 to S40 to be executed. In addition, the main CPU 32 executes each process at a predetermined timing determined according to a waiting time timer (t) set for each process. Before reaching the predetermined timing, the process ends without executing each process, and another subroutine is executed. Of course, the system timer interrupt process is also executed at a predetermined cycle.

  In S32, a special symbol memory check process is executed. Although details will be described later with reference to FIG. 7, in this process, the main CPU 32 holds the pachinko ball winning the normal electric accessory 17 when the control state flag is a value (00) indicating the special symbol memory check. The number is checked, and when there is a reserve number, the big hit determination, the special symbol to be stopped and displayed, and the variation pattern of the special symbol are determined. Then, the main CPU 32 sets a value (01) indicating special symbol variation time management in the control state flag, and sets a variation time corresponding to the variation pattern determined in the current process in the waiting time timer (t). Then, when the variation time set in the waiting time timer (t) has elapsed, the process proceeds to S33.

  In S33, a special symbol variation time management process is executed. In this process, the main CPU 32 sets the control state flag to a value (01) indicating special symbol variation time management, and when the variation time has elapsed, sets the value (02) indicating special symbol display time management to the control state flag. The waiting time after the change is confirmed (for example, 1 second) is set in the waiting time timer (t). Then, when the waiting time after the fluctuation is set set in the waiting time timer (t), the process is shifted to S34.

  In S34, a special symbol display time management process is executed. The main CPU 32 determines whether or not it is a big hit when the control state flag is a value (02) indicating special symbol display time management and the waiting time after the change is determined. In the case of a big hit, the main CPU 32 sets a value (03) indicating the big hit start interval management in the control state flag, and sets a time (for example, 10 seconds) corresponding to the big hit start interval in the waiting time timer (t). . Then, when the time corresponding to the big hit start interval set in the waiting time timer (t) has elapsed, the process proceeds to S35. On the other hand, if it is not a big hit, the main CPU 32 sets a value (08) indicating the end of the special symbol game and moves the process to S40.

  In S35, a big hit start interval management process is executed. In this process, the main CPU 32 has a value (03) indicating that the control status flag indicates the jackpot start interval management, and when the time corresponding to the jackpot start interval has elapsed, the main CPU 32 Based on the data read from the ROM 33, the variables positioned in the main RAM 34 are updated. Then, the main CPU 32 sets a value (04) indicating that the big prize opening is open to the control state flag and sets the execution of the process of S37, and sets the upper opening time (for example, 30 seconds) to the big prize opening. Set to the time timer, and set the initial value “1” to the winning prize opening number counter. Then, the main CPU 32 sets data indicating the number of rounds and a command for opening a special prize opening indicating that the special prize opening 18 is being opened in a predetermined area of the main RAM 34. As a result, the special winning opening open command is transmitted from the main CPU 32 of the main control board 30 to the sub CPU 51 of the sub control board 50. As a result, the number of rounds and the state of the big prize opening 18 are also recognized in the sub control circuit of the sub control board 50. If this process ends, the process moves to S37.

  In S36, a waiting time management process before reopening the big winning opening is executed. In this process, the main CPU 32 sets the special prize opening number counter to “0” when the control state flag is a value (06) indicating the big prize opening reopening waiting time management and the time corresponding to the interval between rounds has elapsed. Update the memory so that it increases by 1 ″. Then, the main CPU 32 sets a value (04) indicating that the big prize opening is open to the control state flag and sets the execution of the process of S37, and sets the upper opening time (for example, 30 seconds) to the big prize opening. Set to time timer. If this process ends, the process moves to S37.

  In S37, a special winning opening opening process is executed. In this process, when the control status flag is a value (04) indicating that the big prize opening is open, the main prize winning counter winning counter for counting the number of pachinko balls won in the big prize opening 18 is “10”. It is determined whether or not either of the conditions “over” or the condition that the upper limit opening time of the special winning opening 18 has passed (the special winning opening release time timer is “0”) is satisfied. The main CPU 32 updates a variable positioned in the main RAM 34 in order to close the special winning opening 18 when any one of the conditions is satisfied. Then, the main CPU 32 sets a value (05) indicating monitoring of the winning ball in the winning mouth in the control state flag, and sets a monitoring time (for example, 1 second) in the winning ball in the waiting time timer (t). That is, it is set so that the process of S38 is executed after the winning ball residual ball monitoring time has elapsed. Note that the main CPU 32 does not execute the above-described processing when none of the above conditions is satisfied. When the process of S37 is completed, the process proceeds to S38.

  In S38, a special winning opening residual ball monitoring process is executed. In this process, the main CPU 32 indicates that the control state flag is a value (05) indicating monitoring of the winning ball in the winning prize mouth, and when the remaining winning ball monitoring time in the winning game mouth has elapsed, It is determined whether or not the condition that the number of times of release is equal to or greater than the maximum value (the final round) is satisfied. When this condition is satisfied, the main CPU 32 sets a value (07) indicating the jackpot end interval in the control state flag, and sets a time corresponding to the jackpot end interval in the waiting time timer. In other words, after the time corresponding to the big hit end interval has elapsed, the process of S39 is set to be executed. On the other hand, when this condition is not satisfied, the main CPU 32 sets the value (06) indicating the big winning opening reopening waiting time management in the control state flag and sets the time corresponding to the interval between rounds in the waiting time timer. To do. In this case, after the time corresponding to the interval between rounds has elapsed, the setting of S36 is performed.

  In S39, a big hit end interval process is executed. In this process, the main CPU 32 controls the value (08) indicating the end of the special symbol game when the control state flag is a value (07) indicating the jackpot end interval and the time corresponding to the jackpot end interval has elapsed. The flag is set to execute the process of S40. Then, when the big hit symbol is a probable variation symbol, the main CPU 32 performs control to shift the gaming state to the probability variation state. If this process ends, the process moves to S40.

  In S40, a special symbol game end process is executed. In this process, when the control state flag is a value (08) indicating the end of the special symbol game, the main CPU 32 sets the value (holding number) of the ordinary electric winning prize counter shown in the special symbol start memory number display unit 12. The memory is updated so that “1” is decreased. Further, the main CPU 32 sets data indicating a start memory number designation command to the effect that the reserved number decreases by “1” in a predetermined storage area of the main RAM 34. The set start memory number designation command is transmitted from the main CPU 32 of the main control board 30 to the sub CPU 51 of the sub control board 50. As a result, the sub-control circuit of the sub-control board 50 also recognizes that the reserved number has decreased by “1”. Then, the main CPU 32 updates the special symbol storage area in order to perform the next fluctuation display, sets a value (00) indicating a special symbol storage check to the control state flag, and executes the process of S32. Set to. When this process is finished, this subroutine is finished.

  As described above, the special symbol game is executed on the special symbol display device 12 by setting the control state flag. Specifically, as shown in FIG. 6, the main CPU 32 sets the control status flags to “00”, “01”, “02”, “08” when the result of the big hit determination is lost and the big hit gaming state is not achieved. By setting in order, the processing of S32, S33, S34, and S40 shown in FIG. 5 is executed at a predetermined timing. Further, the main CPU 32 sets the control state flags in order of “00”, “01”, “02”, “03” when the result of the big hit determination is a big hit game state as shown in FIG. The processing of S32, S33, S34, and S35 is executed at a predetermined timing, and control to the big hit gaming state is executed. Furthermore, when the control to the big hit gaming state is executed, the main CPU 32 sets the control state flags in order of “04”, “05”, “06”, thereby performing S37 and S38 shown in FIG. The process of S36 is executed at a predetermined timing, and a big hit game is executed. When the big hit game is being executed and the end condition for the big hit game state is satisfied, the control state flag is set in the order of “04”, “05”, “07”, “08”. Then, the processing from S37 to S40 shown in FIG. 5 is executed at a predetermined timing, and the big hit gaming state is ended. The end condition of the jackpot gaming state is that the maximum number of continuations of the jackpot round (the upper limit number of rounds, for example, 15 rounds in the present embodiment) has ended.

  FIG. 7 is a flowchart showing details of the special symbol storage check process performed in S32 of the special symbol control process shown in FIG.

  In the special symbol memory check process, first, the main CPU 32 determines whether or not the control state flag is a value (00) indicating the special symbol memory check (see S41 in FIG. 7). If this determination is “No”, the special symbol memory check process ends. On the other hand, if the determination in S41 is “Yes”, then the main CPU 32 reads the value of the ordinary electric winning prize counter in the main RAM 34 and the number of pachinko balls held in the ordinary electric accessory 17 is “0”. It is determined whether or not (S42). If this determination is “Yes”, the special symbol memory check process ends. On the other hand, if the determination in S42 is “No”, the main CPU 32 sets a value (01) indicating special symbol variation time management in the control state flag (S43), and then performs a big hit determination process (S44). . In the big hit determination process, the special determination process described above is performed. That is, a big hit lottery for determining whether or not to execute the big hit game by reading the value of the big hit determination random number counter is performed, and whether or not the big hit is won is determined.

  Subsequently, the main CPU 32 performs a special symbol determination process (S45). In the special symbol determination process, the main CPU 32 reads the value of the jackpot symbol determination random number counter and determines the special symbol to be stopped and displayed in the symbol determination stop display process based on the result of the jackpot lottery. Subsequently, the main CPU 32 performs a variation pattern determination process (S46). In the variation pattern determination process, referring to the variation pattern table, one random number value is extracted from the random number range based on the result of “big loss” or “big hit” in S44, and the command number and the variation time are extracted. Randomly determine the production content. The command number variation pattern command lottered in this process is transmitted from the main control board 30 to the sub-control board 50 in the port output process (see S25 in FIG. 4) in the system timer interrupt process described above. Subsequently, the variation time determined by the variation pattern determination process is set in the waiting time timer (t) (S47). When the processing of S47 ends, the main CPU 32 clears the storage area of the main RAM 34 used for the current variation (S48), and ends the special symbol storage check processing.

  According to the pachinko machine 1 according to this embodiment, the normal symbol display device 11, the special symbol display device 12, the state display device 15, the normal electric accessory 17, and the big prize opening 18 which are driven devices are output. The drive circuit 38 outputs a drive signal based on the drive data held in the data latch circuit 39 in synchronization with a specific cycle of 8 [msec] by the input of the divided clock signal from the frequency divider circuit 41. It is driven by this.

  FIG. 8 is a timing chart of signals in each part of the circuit at this time. The horizontal axis represents time [msec], the vertical axis represents high voltage level “ON”, and low voltage level “OFF”. Yes. FIG. 4A shows drive data output by the data output means constituted by the main CPU 32 at a predetermined cycle of 2 [msec] by the port output processing of FIG. 4 and S25. FIG. 6B shows a divided clock signal that is generated by the frequency dividing circuit 41 at a specific period of 8 [msec] and output to the output drive circuit 38. FIG. 3C shows a drive signal that the output drive circuit 38 outputs in synchronization with the divided clock signal from the frequency divider circuit 41.

  As shown in FIG. 6A, the drive data is in an “ON” state during 18 [msec] from time A to time C, and this “ON” signal is held in the data latch circuit 39. The frequency-divided clock signal is turned ON once at a time interval of 8 [msec] and input to the output drive circuit 38 as shown in FIG. As shown in FIG. 5C, the output drive circuit 38 is the time B when the divided clock signal is first input after the drive data input from the data latch circuit 39 is in the “ON” state at time A. The drive signal is turned on and output. Further, the output drive circuit 38 turns the drive signal into the “OFF” state at time D when the drive data input from the data latch circuit 39 is turned “OFF” at time C and then the divided clock signal is input for the first time. To stop the output. As a result, as shown in FIG. 5C, the drive signal is in the “ON” state from time B to time D for 16 [msec], and is based on the divided clock signal input from the frequency dividing circuit 41. , And 8 [msec] are output in synchronization with a specific period.

  Therefore, according to the pachinko machine 1 according to the present embodiment, the output cycle of the drive data output at a predetermined cycle of 2 [msec] from the data output means under the control of the main CPU 32 constituting the game control means, and the output drive circuit From 38, the output cycle of the drive signal output at a specific cycle of 8 [msec], which is different from the predetermined cycle, becomes different. For this reason, the player cannot recognize the control processing period of the game operation by the main CPU 32 from the recognizable operation period of the driven device. Therefore, it is possible to prevent the player from performing an illegal act by recognizing the control processing cycle of the main CPU 32. Further, since the driven device is driven in synchronization with a specific cycle of 8 [msec] based on the frequency-divided clock signal input from the frequency dividing circuit 41, the driving cycle of the driven device is the main CPU 32. The change can be made only by changing the frequency dividing period of the oscillation signal in the frequency dividing circuit 41 without changing the control processing.

  Further, in the pachinko machine 1 according to the present embodiment, the special determination process by the main CPU 32 for determining whether or not to activate the jackpot game advantageous to the player is performed at a predetermined cycle of 6 [msec]. When the above condition is satisfied, the drive signal for operating the ordinary electric accessory 17 is output by the data latch circuit 39 and the output drive circuit 38 in synchronization with a specific cycle of 8 [msec] as described above. Therefore, the cycle in which the ordinary electric accessory 17 operates is different from the predetermined cycle of 6 [msec] in which the main CPU 32 performs a special determination process as to whether or not to activate the big hit game advantageous to the player. Become. For this reason, the period in which the main CPU 32 performs special determination processing, that is, jackpot determination, and the period in which the ordinary electric accessory 17 operates do not continue to be synchronized. As a result, the operation of the jackpot game is determined in the jackpot determination process for determining whether or not to activate the jackpot game advantageous to the player, which is performed when the pachinko ball wins the normal electric accessory 17. The determination does not continue or the determination that is not determined continues. Therefore, it is possible to ensure the fairness of the jackpot determination process. Further, the player cannot recognize the control processing cycle of the main CPU 32 from the cycle of the operation of opening and closing the ordinary electric accessory 17. Therefore, it is possible to prevent an illegal act in which the player aims for a big hit game based on the operation of the ordinary electric accessory 17.

  Further, in the pachinko machine 1 according to the present embodiment, the period of 8 [msec] in which the driven device is driven is different from the period of 6 [msec] in which the pachinko ball is fired onto the game board 2 by the launch solenoid 73. Therefore, for example, the period in which the ordinary electric accessory 17 operates and the period in which the pachinko ball is fired on the game board 2 are not kept synchronized. Therefore, the pachinko ball does not continue to win or come off from the ordinary electric accessory 17 and a wave of winning can be created.

  In the pachinko machine 1 according to the above-described embodiment, the main CPU 32 performs a port output process in which various commands stored in the transmission data storage area of the main RAM 34 are output to the data latch circuit 39. The system timer shown in FIG. A case has been described in which the interrupt processing is performed in synchronization with an interrupt cycle of 2 [msec] in S25. However, as shown in FIG. 9, the port output process of S25 may be performed in synchronization with a predetermined cycle of 6 [msec] after the symbol display device control process of S11 in the main process. . In this case, the system timer interrupt process shown in FIG. 4 is a form obtained by removing the same process of S25 as shown in FIG. 9 and 10, the same or corresponding processes as those in FIGS. 3 and 4 are denoted by the same step numbers and description thereof is omitted.

  In such a configuration, the main CPU 32 outputs various commands stored in the transmission data storage area of the main RAM 34 at a predetermined cycle of 6 [msec]. The output drive data is output from the data latch circuit 39. The output drive circuit 38 outputs a drive signal at a specific cycle of 8 [msec]. For this reason, the driven device is driven at a specific cycle of 8 [msec]. Therefore, even in this configuration, the drive data output cycle output from the main CPU 32 at a predetermined cycle of 6 [msec] and the output drive circuit 38 output at a specific cycle of 8 [msec] different from the predetermined cycle. The output cycle of the drive signal is different, and the same effect as the above-described embodiment is achieved.

  Further, in the pachinko machine 1 according to the above-described embodiment, an oscillator 40 that generates an oscillation signal input to the frequency dividing circuit 41 and an oscillator 36 that generates an oscillation signal input to the watchdog timer circuit 35 are shown in FIG. The case where it was provided separately as shown was described. However, as shown in FIG. 11, you may comprise so that each transmitter 36,40 may be combined.

  FIG. 11 is a block diagram showing the main configuration of an electronic circuit that controls the gaming operation of the pachinko machine 1 according to this modification. In the figure, the same or corresponding parts as in FIG.

  In the main control board 30 shown in the figure, only the oscillator 40 is mounted without including the oscillator 36 shown in FIG. The oscillator 40 outputs an oscillation signal generated at a constant period to the microcomputer 31, the watchdog timer circuit 35, and the frequency dividing circuit 41, and also serves as the oscillator 36. Therefore, according to this configuration, only one oscillator is required to be mounted on the main control board 30, so that a space for mounting a new element on the main control board 30 is created and the cost of components can be reduced.

  Next, a pachinko machine according to a second embodiment of the present invention will be described.

  FIG. 12 is a block diagram showing a main configuration of an electronic circuit that controls the gaming operation of the pachinko machine according to the second embodiment. In the figure, the same or corresponding parts as in FIG.

  The pachinko machine according to the second embodiment is different from the pachinko machine 1 according to the first embodiment described above only in the circuit configuration between the microcomputer 31 and the driven device in the main control board 30, and the other configurations are described above. This is the same as the pachinko machine 1 according to the first embodiment.

  In the pachinko machine 1 according to the present embodiment, as shown in FIG. 12, the normal symbol display device 11 and the big prize opening solenoid 18v among the driven devices are not connected via the data latch circuit 39 but via the output drive circuit 38a. It is connected to the microcomputer 31. The special symbol display device 12, the status display device 15, and the start port solenoid 17v are connected to the microcomputer 31 via the data latch circuit 39 and the output drive circuit 38b. Therefore, the special symbol display device 12, the status display device 15, and the start port solenoid 17v specify 8 [msec] of the divided clock signal output from the frequency dividing circuit 41 by the output drive circuit 38b and the data latch circuit 39. However, the normal symbol display device 11 and the big prize opening solenoid 18v are driven by the main CPU 32 to output drive data in synchronization with a predetermined cycle of 2 [msec]. Accordingly, the output drive circuit 38a is driven by a drive signal output in synchronization with a predetermined cycle of 2 [msec].

  In addition, the main CPU 32 displays the interval time between the operation time in which the normal electric accessory 17 is in the open state and the operation time in which the normal symbol display device 11 performs display, and the special symbol display device 12 performs display. The interval time between the operating time during which the prize winning opening 18 is in the open state is set to a specific period of 8 [msec] by the output driving circuit 38b from the time when the output of the driving data output by the main CPU 32 is stopped. The maximum delay time until the output stop of the drive signal output in synchronism with the time interval, that is, the interval time setting that is set longer than the time of the difference between the specific period of 8 [msec] and the predetermined period of 2 [msec] Means.

  Further, the main CPU 32 constituting the data output means opens the drive data to be displayed on the normal symbol display device 11 or the normal electric accessory 17 after the interval time set by the interval time setting means has elapsed. The drive data to be operated is output at a predetermined cycle of 2 [msec]. Further, the main CPU 32 outputs 2 [msec] of drive data for operating the special winning opening 18 to be opened after the interval time set by the interval time setting means has elapsed or for displaying the special symbol display device 12 on display. ] Is output at a predetermined cycle.

  FIG. 13 shows an operation in which the delay time from the stop of output of the drive data output by the main CPU 32 to the stop of output of the drive signal output by the output drive circuit 38b is maximized, and the ordinary electric accessory 17 is in an open state. FIG. 6 is a timing chart showing an interval time between an operation time when the ordinary electric accessory 17 is in an open state and an operation time when the ordinary symbol display device 11 performs display when the time is the longest. In the figure, the horizontal axis represents time [msec], and the vertical axis represents high voltage level “ON” and low voltage level “OFF”.

  4A shows solenoid drive data output from the main CPU 32 to the data latch circuit 39 for controlling the start port solenoid 17v, and FIG. 4B shows output from the frequency divider circuit 41 to the output drive circuit 38b. The frequency-divided clock signal (c) in FIG. 5 shows the solenoid drive signal output from the output drive circuit 38b to the start port solenoid 17v. The solenoid drive data is in an “ON” state for 18 [msec] from time A to time B as shown in FIG. As shown in FIG. 6B, the divided clock signal is turned on in a single cycle with a specific period of 8 [msec]. Since the rise time of the solenoid drive data coincides with the generation time of the divided clock signal at time A, the solenoid drive signal becomes “ON” at time A as shown in FIG. In addition, the solenoid drive signal becomes “OFF” at time D when the frequency-divided clock signal is generated for the first time after the solenoid drive data becomes “OFF”. In this case, the delay time from when the output of the solenoid drive data is stopped at time A to when the output of the solenoid drive signal is stopped at time D is 6 [msec]. The solenoid drive signal is output in synchronization with a specific cycle of 8 [msec] because the solenoid drive data synchronized with the cycle of 2 [msec], so that the delay time of 6 [msec] is maximized.

  In this case, as drive data for controlling the display of the normal symbol display device 11, the output at time C after the elapse of the normal interval time of 2 [msec] from when the output of the solenoid drive data shown in FIG. When the normal symbol display data 1 is output from the main CPU 32 to the output drive circuit 38a at the timing, this data is not held by the data latch circuit 39. Therefore, the normal symbol display signal 1 which is a drive signal for displaying the normal symbol display device 11 is: The output drive circuit 38a outputs the signal to the normal symbol display device 11 at the same time C.

  Therefore, the solenoid drive signal shown in FIG. 6C and the normal symbol display signal 1 shown in FIG. 8E overlap in the period of 4 [msec] indicated by a thick solid line in the diagrams from time C to time D. For this reason, even if the normal electric accessory 17 is operating in the open state, a unique situation occurs in which the normal symbol display device 11 displays a variation.

  Therefore, in the present embodiment, the interval time between the operation time in which the ordinary electric accessory 17 is in the open state and the operation time in which the ordinary symbol display device 11 is displaying is set by the main CPU 32 by the interval time setting means. It is set longer than the maximum delay time 6 [msec] from when the output of the solenoid drive data to be output is stopped to when the output of the solenoid drive signal output by the output drive circuit 38b is stopped.

  In other words, in the present embodiment, as the drive data for controlling the display of the normal symbol display device 11, the maximum delay of 6 [msec] in the normal interval time of 2 [msec] from when the output of the solenoid drive data at time B is stopped. The normal symbol display data 2 is output from the main CPU 32 to the output drive circuit 38 at the timing of time E shown in FIG. The normal symbol display data 2 is converted into the normal symbol display signal 2 shown in FIG. 5G which is turned on at the same timing by the output drive circuit 38a. Driven by.

  FIG. 14 shows that the interval time between the operation time in which the ordinary electric accessory 17 is in the open state and the operation time in which the ordinary symbol display device 11 performs display is minimized, and the ordinary electric accessory 17 is in the open state. FIG. 6 is a timing chart showing an interval time between an operation time when the ordinary electric accessory 17 is in an open state and an operation time when the ordinary symbol display device 11 performs display when the operation time is the shortest. In the figure, the horizontal axis represents time [msec], and the vertical axis represents high voltage level “ON” and low voltage level “OFF”.

  The solenoid drive data is “ON” for 22 [msec] from time A to time C as shown in FIG. The frequency-divided clock signal is “ON” in a single cycle with a specific period of 8 [msec] as shown in FIG. The solenoid drive signal becomes “ON” as shown in FIG. 5C at time B when the frequency-divided clock signal is first generated after the solenoid drive data is turned “ON”. Further, the solenoid drive signal is in the “OFF” state at time C as shown in FIG. 5C because the falling time of the solenoid drive data and the generation time of the divided clock signal coincide at time C. .

  In this case, as the drive data for controlling the display of the normal symbol display device 11, as shown in FIG. 4D, a normal interval time of 2 [msec] has elapsed since the output stop at time B of the solenoid drive data. The normal symbol display data 1 is output from the main CPU 32 to the output drive circuit 38 at the timing of the later time D, and the normal symbol display signal 1 is output from the output drive circuit 38a at the same timing as shown in FIG. However, the solenoid drive signal shown in FIG. 5C does not overlap with the normal symbol display signal 1 shown in FIG.

  However, even in this case, in the present embodiment, after the interval time set by the interval time setting means has elapsed, the normal symbol display data 2 shown in FIG. 5F and the normal symbol display signal shown in FIG. 2 is output in the same manner as the normal symbol display data 2 and the normal symbol display signal 2 shown in FIGS.

  In FIG. 13 and FIG. 14, a case has been described in which an interval time of 8 [msec] by the interval time setting means is provided between the operation time of the ordinary electric accessory 17 and the operation time of the ordinary symbol display device 11. However, an interval time of 8 [msec] is similarly provided by the interval time setting means between the variable display time of the special symbol display device 12 and the operation time for opening the special winning opening 18.

  According to the pachinko machine 1 according to the second embodiment, the interval time between the operation time in which the ordinary electric accessory 17 is in the open state and the operation time in which the ordinary symbol display device 11 performs display, and The interval time between the operation time when the special symbol display device 12 is displaying and the operation time when the special winning opening 18 is in the open state is the output of the drive data output by the main CPU 32 by the interval time setting means. The maximum delay time of 6 [msec] from the stop to the output stop of the drive signal output in synchronization with the specific cycle of 8 [msec] by the output drive circuit 38b, that is, the specific cycle of 8 [msec] It is set longer than the time of the difference from the predetermined period of 2 [msec].

  In addition, the drive data for causing the normal symbol display device 11 to display or the drive data for operating the normal electric accessory 17 to the open state is output by the main CPU 32 after the interval time set by the interval time setting means has elapsed. The Accordingly, the normal symbol display device 11 displays a variable display, or the normal symbol display device 11 displays a stop display mode in which a predetermined condition is satisfied, even though the normal electric accessory 17 operates in the open state. In spite of this, it is possible to eliminate a peculiar situation in which the ordinary electric accessory 17 operates in an open state. In addition, since the operation time in which the normal electric accessory 17 is in the open state and the operation time in which the normal symbol display device 11 is displaying are reliably distinguished, the normal symbol display device 11 may be subjected to an illegal act during the variable display. Thus, it is possible to prevent the ordinary electric accessory 17 from operating in the open state.

  In addition, the drive data for operating the special winning opening 18 to be opened or the drive data for displaying on the special symbol display device 12 is output by the main CPU 32 after the interval time set by the interval time setting means has elapsed. . Therefore, even though the special symbol display device 12 performs the variable display, the special symbol 18 operates in the open state or the special symbol 18 operates in the open state. It is possible to eliminate a unique situation in which the display device 12 performs variable display. For this reason, it is possible to prevent the player's recognition regarding the game situation from being confused. In addition, since the operation time during which the special symbol display device 12 is displaying and the operation time during which the special prize opening 18 is in the open state are surely distinguished, the special symbol display device 12 may cause a large amount of fraud during the variable display. It is possible to prevent the winning opening 18 from operating in the open state.

  In the pachinko machine according to each of the above embodiments, the case where the oscillator 40 and the frequency dividing circuit 41 are mounted on the main control board 30 has been described as shown in FIGS. 2, 11, and 12. However, the oscillator 40 and the frequency dividing circuit 41 may not be mounted on the main control board 30, but may be mounted on another separate board so that the divided clock signal is output to the main control board 30. Even in this configuration, the above-described functions and effects can be obtained.

  In the above embodiment, the case where the ball game machine according to the present invention is applied to the pachinko machine 1 has been described. However, the drive means outputs a drive signal based on the drive data output at a predetermined cycle, and the drive signal Thus, the present invention can be applied to other ball game machines in which the driven device is driven to perform a game operation. Even when the present invention is applied to such a ball game machine, the same effects as the above-described embodiment can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 11 ... Normal symbol display device 12 ... Special symbol display device 15 ... Status display device 17 ... Normal electric accessory 17v ... Starting-port solenoid 18 ... Grand prize port 18v ... Grand prize port solenoid 32 ... Main CPU32
33 ... Main ROM
34 ... Main RAM
38, 38a, 38b ... output drive circuit 39 ... data latch circuit 40 ... oscillator 41 ... frequency divider circuit

Claims (2)

Oscillating means for generating an oscillation signal at a constant period, game control means for controlling a game operation at a predetermined period based on the oscillation signal generated by the oscillation means, and the predetermined period by the control processing of the game control means A data output means for outputting drive data in the above, a drive means for outputting a drive signal based on the drive data output from the data output means, and a game operation driven by the drive signal output from the drive means In a ball game machine equipped with a driven device,
A data holding means connected to the data output means and holding drive data output from the data output means; and an oscillation signal generated by the oscillation means is divided into a specific cycle different from the predetermined cycle. And a frequency dividing means for outputting a frequency-divided clock signal to the driving means at this specific cycle,
The driving means is connected to the data holding means and is also connected to the frequency dividing means, and in synchronization with the specific period by the input of the frequency-divided clock signal from the frequency dividing means, Output a drive signal based on the drive data held in the data holding means ,
The driven device is a variable winning device that operates from a closed state in which a game ball is difficult to win to an open state in which a game ball is easy to win when a predetermined condition is satisfied,
When a game ball wins in this variable winning device, it is provided with a special determination means for performing a special determination process on whether or not to activate a special game advantageous to the player at the predetermined cycle,
Ordinary determination means for performing an ordinary determination process on whether or not to satisfy the predetermined condition at the predetermined period;
A normal symbol display device that displays whether or not the predetermined condition is satisfied as a result of a normal determination process by the normal determination means in a stop display mode after a normal symbol variation display;
The interval time between the operation time in which the variable winning device is in the open state and the operation time in which the normal symbol display device is displaying is longer than the time of the difference between the specific cycle and the predetermined cycle. An interval time setting means for setting,
The data output means outputs drive data for causing the normal symbol display device to display after the elapse of the interval time set by the interval time setting means, or drive data for operating the variable winning device to be in the open state. A ball game machine characterized by being output in a cycle of . The driven device is a special symbol display device that displays whether or not to activate a special game advantageous to the player as a result of the special determination process by the special determination means in a stop display mode after the special symbol variation display, When it is determined that the special game advantageous to the player is activated by the special determination process by the special determination means, the game ball is easier to win than the variable display device from the closed state where the game ball is difficult to win. Including a special variable prize-winning device that operates to the open state,
The interval time between the operation time during which the special symbol display device is displaying and the operation time during which the special variable prize-winning device is in an open state is set to be greater than the difference time between the specific period and the predetermined period. Interval time setting means to set longer,
The data output means outputs drive data for operating the special variable prize-winning device in an open state after the elapse of the interval time set by the interval time setting means, or drive data for causing the special symbol display device to perform display. 2. The ball game machine according to claim 1 , wherein the ball game machine is output at a predetermined cycle.

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