JP5480103B2 - Output buffer circuit - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to an output buffer circuit that supplies a constant voltage.

  In order to reduce costs and increase competitiveness with competitors, there is an increasing demand for reducing the core size of semiconductor devices. On the other hand, diversification of functions is also required as a core, and even when a new function is added, a device that does not increase the core size is necessary. One example is the addition of a Battery Charging function to a USB (Universal Serial Bus) 2.0 transceiver core. The transceiver core is a core that controls an electrical interface of USB 2.0. The Battery Charging function defines a mechanism for charging a USB device from a Host device such as a PC (Personal Computer). In recent years, the number of cases where the host device is used not for communication but for charging is increasing. Therefore, specifications have been added to the host device so that a current value necessary for charging can be supplied.

  The Battery Charging circuit includes a comparator that detects whether the connected USB device is a compatible device and an output buffer circuit that notifies the connected USB device whether the Host device is a compatible device. . The output voltage of the output buffer circuit is determined by the specification with a minimum value of 0.5V and a maximum value of 0.7V. Within that range, the output voltage is constant without being affected by variations in elements such as temperature changes and resistance. It is necessary to output a voltage value. The present invention relates to the output buffer circuit.

  Although various circuit formats are conceivable as the output buffer, a voltage follower circuit that outputs a constant voltage regardless of a temperature change will be described. FIG. 1 is a circuit of a voltage follower described in Non-Patent Document 1. The voltage follower circuit has an operational amplifier configuration, and applies a negative feedback from the output to the input to make the output voltage constant. The voltage follower circuit is characterized in that the voltage gain is 1 time, the output impedance is small, and the input impedance is high, and is often used as an output buffer circuit.

  The voltage follower circuit includes a bias unit, a differential unit, and an output unit. Referring to FIG. 1, the bias unit includes an NMOS transistor 101 and a constant current source 102. When the current flowing through the constant current source 102 is I, the NMOS transistor 101 passes I. The differential section is composed of NMOS transistors 103, 104, 107 and PMOS transistors 105, 106. NMOS transistors 103 and 104 are an input differential pair in the differential circuit, NMOS transistor 107 is a constant current source, and PMOS transistors 105 and 106 are loads. The NMOS transistor 104 is connected to the positive input terminal Vinp, and the NMOS transistor 103 is connected to the negative input terminal Vinm. The NMOS transistor 107 is a current mirror circuit in which the NMOS transistor 101 of the bias unit is paired, and causes a mirror current equivalent to the reference current flowing through the NMOS transistor 101 to flow through the NMOS transistor 107. The output unit is a source follower circuit including a PMOS transistor 108 and an NMOS transistor 109. The gate of the PMOS transistor 108 is connected to the drains of the NMOS transistor 104 and the PMOS transistor 106 in the differential section. The positive input terminal Vinp is connected to an internal voltage supply circuit having a small temperature dependency such as BGR (Band Gap Regulator), and the negative input terminal Vinm is connected to the output terminal Vout of the output unit. As a result, feedback is applied in the direction of making the output voltage constant with respect to the voltage fluctuation of the positive input terminal Vinp.

  FIG. 2 is a voltage follower circuit including the phase compensation capacitor Cc described in Non-Patent Document 1. In FIG. 2, the same components as those in FIG. Referring to FIG. 2, the voltage follower circuit has a feature that it easily oscillates, and therefore includes a phase compensation capacitor Cc as a countermeasure for preventing it.

Tadashi Masuki, “Basics of CMOS Analog / Digital IC Design”, 1st Edition, CQ Publishing Co., Ltd., March 15, 2010, p. 38, 121

FIG. 3 is an example of a graph relating to frequency characteristics of a voltage follower circuit designed by a 40 nm process. The horizontal axis represents frequency, the first axis (left side) of the vertical axis represents voltage gain, and the second axis (right side) represents phase. A dotted line A and a dotted line C indicate the voltage follower circuit of FIG. 1 (before adding the phase compensation capacitor). A dotted line A is a voltage gain before the phase compensation capacitor is added, and a dotted line C is a phase at that time. On the other hand, a solid line B and a solid line D indicate the voltage follower circuit of FIG. 2 (after adding the phase compensation capacitor). The solid line B is the voltage gain after adding the phase compensation capacitance, and the solid line D is the phase at that time. The voltage follower circuit is aimed at ensuring a phase margin of usually 45 degrees or more in order to prevent oscillation. The phase margin is a difference between the phase when the voltage gain is 1 time (0 dB) and −180 degrees, and is used for determining the oscillation stability. In FIG. 3, P1 represents a phase margin before the addition of the phase compensation capacitance, and P2 represents a phase margin after the addition of the phase compensation capacitance. In the voltage follower circuit of FIG. 1, it is difficult to satisfy a phase margin of 45 degrees or more as in P1 in consideration of variations in V _T (threshold voltage) and output load conditions. Since the voltage follower circuit of FIG. 2 has a phase compensation capacitor added, a phase margin of 45 degrees or more can be secured as in P2. However, when a gate capacitance having a small temperature dependency is used as the phase compensation capacitance, the capacitance value per unit area of the gate capacitance is small, and the area of the capacitance itself becomes very large. Taking the 40 nm process as an example, simply adding a phase compensation capacitance to the voltage follower circuit of FIG. As described above, the voltage follower circuit to which a phase compensation capacitor must be added in order to prevent oscillation has a problem that the circuit scale becomes large.

  Hereinafter, means for solving the problems will be described using the reference numerals used in the mode for carrying out the invention (example) in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the modes and embodiments for carrying out the invention. Do not use to interpret the technical scope.

The output buffer circuit (1) of the present invention includes an input unit (20), a constant current unit (30) connected to the input unit (20), and a current-voltage conversion unit ( 40) and an output unit (50) connected to the current-voltage conversion unit (40). The input unit (20) includes a first source, a first drain connected to the first node (34) on the reference current side of the constant current unit (30), and a first gate connected to the input terminal (10). And a first resistance element (22), one of which is connected to a first power source (80) and the other is connected to a first source. The current-voltage conversion unit (40) includes a second source connected to the first power source (80), and a third node (36) on the current supply side of the constant current unit (30) via the second node (45). A second MOS transistor (41) of a first conductivity type channel having a second drain connected to the second drain and a second gate connected to the second drain, one connected to the first power supply (80) and the other to A second resistance element (43) connected to the fifth node (35) on the current supply side of the constant current section (30) via the fourth node (47), and one of them is connected to the second node (45). , And a third resistor element (44) connected to the fourth node (47). A potential difference _{V gs1} between the first source and the first gate, equal to the second source potential difference _{V gs2} of the second gate, and the resistance value _{R 1} of the first resistor element (22), the third resistance element (44 ) equal to the resistance _{R 3} of the.

  Since the output buffer circuit of the present invention does not require a phase compensation capacitor, the circuit scale is small, and the output can be made constant regardless of temperature changes and resistance variations.

FIG. 1 is a circuit of a voltage follower described in Non-Patent Document 1. FIG. 2 is a voltage follower circuit including the phase compensation capacitor Cc described in Non-Patent Document 1. FIG. 3 is an example of a graph relating to frequency characteristics of a voltage follower circuit designed by a 40 nm process. FIG. 4 is a configuration diagram of the output buffer circuit 1 according to the embodiment of the present invention. FIG. 5 is a diagram showing the temperature characteristics of the output voltage in the output buffer circuit 1 of the present invention constructed by a 40 nm process and the voltage follower circuit of FIG.

  Hereinafter, an output buffer circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 4 is a configuration diagram of the output buffer circuit 1 according to the embodiment of the present invention. Referring to FIG. 4, the output buffer circuit 1 includes an input terminal 10, an input unit 20, a current mirror unit 30, a current / voltage conversion unit 40, an output unit 50, and an output terminal 60.

  The input terminal 10 is a terminal connected to the previous stage circuit of the output buffer circuit 1.

The input unit 20 includes an NMOS transistor 21 and a resistance element 22. The NMOS transistor 21 has a source connected to one of the resistance elements 22, a drain connected to a current mirror unit 30 (specifically, a drain of a PMOS transistor 31 described later (node 34 on the reference current side)), and a gate connected to an input terminal. 10 is connected. One of the resistance elements 22 is connected to the GND 80 (first power supply), and the other is connected to the source of the NMOS transistor 21. Input unit 20, a voltage _{V in} applied to the input terminal 10 is converted into a predetermined current _{I 0.}

The current mirror unit 30 is connected to the input unit 20 and the current-voltage conversion unit 40. The current mirror unit 30 includes a PMOS transistor 31, a PMOS transistor 32, and a PMOS transistor 33. The PMOS transistor 31 is the reference current side, and the PMOS transistor 32 and the PMOS transistor 33 are the sides that supply the mirror current. The PMOS transistor 31 has a source connected to the VDD 70 (second power supply), a drain connected to the drain of the NMOS transistor 21 via the node 34, and a gate connected to the drain (node 34). The PMOS transistor 32 has a source connected to the VDD 70, a drain connected to a current-voltage converter 40 (a node 46 described later in detail) via a node 35 on the current supply side, and a gate connected to the drain (node) of the PMOS transistor 31. 34). The PMOS transistor 33 has a source connected to the VDD 70, a drain connected to a current-voltage converter 40 (a node 45 described later in detail) via a node 36 on the current supply side, and a gate connected to the drain (node) of the PMOS transistor 31. 34). The current mirror section 30 as a reference current to current I ₀ that is generated by the input unit 20, generates the mirror current I ₀ of the same value, and supplies the current-voltage converter 40.

The current-voltage conversion unit 40 is connected to the current mirror unit 30 and the output unit 50. The current-voltage conversion unit 40 includes an NMOS transistor 41, an NMOS transistor 42, a resistance element 43, and a resistance element 44. The NMOS transistor 41 has a source connected to the GND 80, a drain connected to the drain (node 36) of the PMOS transistor 33 of the current mirror unit 30 via the node 45, and a gate connected to the drain. The NMOS transistor 42 has a source connected to the node 47, a drain connected to the drain (node 35) of the PMOS transistor 32 of the current mirror unit 30 via the node 46, and a gate connected to the drain (node 46). One of resistance elements 43 is connected to GND 80 and the other is connected to node 47. One of resistance elements 44 is connected to node 45 and the other is connected to node 47. Here, the potential difference V _gs1 between the source and gate of the NMOS transistor 21 is equal to the potential difference V _gs2 between the source and gate of the NMOS transistor 41, and the resistance value R ₁ of the resistance element 22 and the resistance of the resistance element 44 equal to the value _{R 3.} The current-voltage conversion circuit 40 converts the current I ₀ supplied from the current mirror unit 30 into a predetermined voltage.

The output buffer circuit 1 needs to reduce the output impedance in order to suppress the influence of the input impedance of the circuit connected to the next stage. Accordingly, the output unit 50 has a source follower configuration. The output unit 50 includes an NMOS transistor 51 and a load current unit 52. The NMOS transistor 51 has a source connected to the load current unit 52 and the output terminal 60 via the node 53, a drain connected to the VDD 70, and a gate connected to the node 46 of the current-voltage converter 40. One of the load current units 52 is connected to the GND 80, and the other is connected to the source of the NMOS transistor 51 and the output terminal 60 via the node 53. The output unit 50 receives the output voltage of the current-voltage conversion unit 40 and outputs the voltage V _out through the output terminal 60.

  The output terminal 60 is a terminal connected to a subsequent circuit of the output buffer circuit 1. The output buffer circuit 1 of the present invention can be configured by replacing each PMOS transistor and each NMOS transistor. In this case, VDD 70 corresponds to the first power supply, and GND 80 corresponds to the second power supply. To do. The resistance elements 22, 43, and 44 are not limited to being realized by a single resistor, and may be realized by using a plurality of resistance components.

Since the output buffer circuit 1 of the present invention does not have a configuration for applying data feedback, it is not necessary to add a phase compensation capacitor. Furthermore, the output buffer circuit 1 of the present invention can supply a constant output voltage _Vout to the subsequent stage without depending on temperature and variations in the resistance elements 22, 43, and 44. Details of the mechanism will be described below.

The input voltage at the input terminal 10 is V _in , the output voltage at the output terminal 60 is V _out , the current value flowing through the NMOS transistor 21 of the input unit 20 is I ₀ , the current value flowing through the resistance element 44 is I ₁ , and the resistance element 22 The resistance value is R ₁ , the resistance value of the resistance element 43 is R ₂ , the resistance value of the resistance element 44 is R ₃ , the voltage between the gate and the source of the NMOS transistor 21 is V _gs1 , and the voltage between the gate and the source of the NMOS transistor 41 is _Is V _gs2 , and the voltage at the node 47 is V _x ,
I ₀ = (V _in −V _gs1 ) / R ₁ (1)
I ₁ = (V _gs2 −V _x ) / R ₃ (2)
It becomes.

In addition, since I ₀ flows to the PMOS transistors 32 and 33 via the PMOS transistor 31,
V _x = (I ₀ + I ₁ ) × R ₂ (3)
It can be expressed as.

Substituting Equation (1) and Equation (2) into Equation (3), V _x = R ₂ / R ₁ × (V _in −V _gs1 ) + R ₂ / R ₃ × (V _{gs 2} −V _x )
It becomes. Therefore,
V _x = R ₂ × R ₃ / (R ₁ (R ₂ + R ₃ )) × V _in
−R ₂ × R ₃ / (R ₁ (R ₂ + R ₃ )) × V _gs1
+ R ₂ / (R ₂ + R ₃ ) × V _gs2 (4)
It becomes.

Differentiating equation (4) with temperature T,
dV _x / dT = R ₂ × R ₃ / (R ₁ (R ₂ + R ₃ )) × (dV _in / dT)
−R ₂ × R ₃ / (R ₁ (R ₂ + R ₃ )) × (dV _gs1 / dT)
+ R ₂ / (R ₂ + R ₃ ) × (dV _gs2 / dT) (5)
It becomes.

Here, when dV _gs1 / dT = dV _gs2 / dT = dV _gs / dT, the equation (5) is
dV _x / dT = R ₂ / (R ₂ + R ₃ ) × (1−R ₃ / R ₁ ) × dV _gs / dT
It becomes. If R ₁ = R ₃ , dV _x / dT = 0, so V _x is determined regardless of the temperature change. In order to set dV _gs1 / dT = dV _gs2 / dT = dV _gs / dT, it is realized by making the NMOS transistor 21 and the NMOS transistor 41 the same element.

  FIG. 5 is a diagram showing the temperature characteristics of the output voltage in the output buffer circuit 1 of the present invention constructed by a 40 nm process and the voltage follower circuit of FIG. Referring to FIG. 5, it can be seen that a constant output voltage is obtained regardless of the temperature change, as in the voltage follower circuit of FIG.

Further, as another feature, when R ₁ = R ₃ and V _gs1 = V _gs2 , the expression (4) is
V _x = R ₂ / (R ₁ + R ₂ ) × V _in
Therefore, when deformed,
V _x / V _in = R ₂ / (R ₁ + R ₂ )
_Next, the relationship between _{V in} and _{V x} is determined by only relative ratio of _{R 1} and _{R 2.} Therefore, the output voltage does not depend on the variation of the resistance elements 22, 43, and 44. V _gs1 = V _gs2 can be realized by making the NMOS transistor 21 and the NMOS transistor 41 the same element.

In addition, the NMOS transistor 42 of the current-voltage conversion unit 40 has an effect of offsetting the V _T (threshold voltage) variation of the NMOS transistor 51 of the output unit 50. The reason is as follows. _Assuming that the voltage between the gate and the source of the NMOS transistor 42 is V _gs3 , the voltage between the gate and the source of the NMOS transistor 51 is V _gs4 , and the voltage at the node 46 is V _Y.
V _Y = V _X + V _gs3 (6)
V _Y = V _out + V _gs4 (7)
It becomes. Therefore, from (6) and (7), V _out = V _gs3 −V _gs4 + V _X (8)
It becomes. Here, the mutual conductance of the NMOS transistor 42 is gm ₃ , the current flowing through the transistor is I ₃ , V _T (threshold voltage) is V _T3 , the mutual conductance of the NMOS transistor 51 is gm ₄ , and the current flowing through the transistor is I ₄ , If V _T (threshold voltage) is V _T4 ,
V _gs3 = 2 × I ₃ / gm ₃ + V _T3 (9)
V _gs4 = 2 × I ₄ / gm ₄ + V _T4 (10)
It becomes. When Expression (9) and Expression (10) are substituted into Expression (8), V _out = 2 × (I ₃ / gm ₃ −I ₄ / gm ₄ ) + V _T3 −V _T4 + V _X (11)
It becomes. Here, since the V _T of the NMOS transistor 42 and the NMOS transistor 51 are the same, the variations in V _T3 and V _{T4 in} the equation (11) are also the same, and the variations in V _T with respect to V _out are offset.

  As described above, since the output buffer circuit 1 of the present invention is not a feedback circuit, it is not necessary to add a phase compensation capacitor for preventing oscillation, so that the circuit scale can be reduced. In the output buffer circuit 1 of the present invention, the gate-source voltage of the NMOS transistor 21 of the input unit 20 and the NMOS transistor 41 of the current-voltage conversion unit 40 are the same, and the resistance element 22 of the input unit 20 By making the size of the 40 resistance elements 44 the same, a constant voltage can be output regardless of temperature changes and resistance variations. Taking the 40 nm process as an example, the output buffer circuit 1 of the present invention can be expected to have an area reduction effect of about 30% compared to the voltage follower circuit of FIG.

DESCRIPTION OF SYMBOLS 1 Output buffer circuit 10 Input terminal 20 Input part 21 NMOS transistor 22 Resistance element 30 Current mirror part 31,32,33 PMOS transistor 34,35,36 Node 40 Current voltage conversion part 41,42 NMOS transistor 43,44 Resistance element 45, 46, 47 Node 50 Output section 51 NMOS transistor 52 Load current section 53 Node 60 Output terminal

Claims (2)

An input section;
A constant current unit connected to the input unit;
A current-voltage conversion unit connected to the constant current unit;
An output unit connected to the current-voltage conversion unit,
The input unit is
A first MOS transistor of a first conductivity type channel having a first source, a first drain connected to a first node on a reference current side of the constant current section, and a first gate connected to an input terminal;
A first resistance element having one connected to a first power supply and the other connected to the first source;
The current-voltage converter is
A second source connected to the first power source; a second drain connected to a third node on the current supply side of the constant current portion via a second node; and a second connected to the second drain. A second MOS transistor of the first conductivity type channel having a gate;
A second resistance element, one connected to the first power supply and the other connected to a fifth node on the current supply side of the constant current section via a fourth node;
A third resistance element having one connected to the second node and the other connected to the fourth node;
The potential difference between the first source and the first gate is equal to the potential difference between the second source and the second gate;
An output buffer circuit in which a resistance value of the first resistance element is equal to a resistance value of the third resistance element. The output buffer circuit according to claim 1,
The current-voltage converter is
A third source connected to the fourth node; a third drain connected to the fifth node on the current supply side of the constant current section through a sixth node; and a third source connected to the third drain. A third MOS transistor of the first conductivity type channel having three gates;
The output unit is
A load current unit, one connected to the first power supply and the other connected to the output terminal via a seventh node;
The first conductivity type having a fourth source connected to the output terminal via the seventh node, a fourth drain connected to a second power source, and a fourth gate connected to the sixth node. An output buffer circuit comprising a fourth MOS transistor of the channel.

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