CN109992034B - Low dropout regulator - Google Patents
Low dropout regulator Download PDFInfo
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- CN109992034B CN109992034B CN201910313977.1A CN201910313977A CN109992034B CN 109992034 B CN109992034 B CN 109992034B CN 201910313977 A CN201910313977 A CN 201910313977A CN 109992034 B CN109992034 B CN 109992034B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
The invention relates to a low dropout linear regulator, which comprises an error amplifying circuit, a voltage sampling circuit, a power-on control circuit, a power adjusting device and a current adjusting device, wherein the error amplifying circuit obtains a feedback voltage related to the output voltage of the low dropout linear regulator through the voltage sampling circuit and outputs an error amplifying signal to a control node of the power adjusting device, the current adjusting device is connected with the power adjusting device in series, the output node of the current adjusting device is connected with a load node of the low dropout linear regulator, and the power-on control circuit obtains the feedback voltage through the voltage sampling circuit and outputs a power-on control signal to the control node of the current adjusting device so as to adjust the output current of the current adjusting device, thereby realizing the real-time rapid power-on capability. In addition, the Schmitt trigger can be used for power-on control, so that the power consumption is low and the occupied chip area is small.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a low dropout regulator.
Background
With the rapid development of electronic technology, especially the increasing popularity of portable and consumer electronics, power management chips are increasingly playing a vital role in various portable electronic devices, such as smart phones, tablet computers, or other electronic products. Low dropout regulator (LDO) is commonly used in power management chips due to its simple structure and excellent performance.
An LDO is a linear regulator, which generally includes an error amplifier and a feedback resistor network, and when an output load of the LDO changes, an output voltage also changes. The feedback resistance network collects the output voltage of the LDO, feeds the output voltage back to the input end of the error amplifier, compares the output voltage with the reference voltage input from the outside, the output end of the error amplifier is connected to the grid electrode of the power adjusting tube, and the output of the LDO reaches the steady state through adjusting the grid electrode voltage of the power adjusting tube.
If the supply voltage of the LDO exceeds the withstand voltage of the MOS device serving as the power regulating tube, for example, if the supply voltage is 3.3V, and the withstand voltage of the adopted power regulating tube is less than 3.3V (e.g., 1.8V), the MOS device is easily damaged due to overvoltage operation, and a cascode structure is usually adopted to avoid the problem of the overvoltage operation of the MOS device. However, the cascode architecture increases the power-up time of the LDO. In order to realize rapid power-on, the existing method generates a control signal through digital sequential logic, generally generates a pulse signal for a period of time after being enabled, and the pulse width is the rapid power-on time.
Disclosure of Invention
The invention provides a low dropout regulator in order to enable the low dropout regulator to have real-time rapid power-on capability.
The invention provides a low dropout linear regulator, which comprises an error amplifying circuit, a voltage sampling circuit, an electrifying control circuit, a power adjusting device and a current adjusting device, wherein the error amplifying circuit is connected with the voltage sampling circuit; the error amplifying circuit obtains feedback voltage associated with the output voltage of the low dropout linear regulator through the voltage sampling circuit, and outputs an error amplifying signal to a control node of the power adjusting device, the current adjusting device is connected with the power adjusting device in series, the output node of the current adjusting device is connected with a load node of the low dropout linear regulator, and the power-on control circuit obtains the feedback voltage through the voltage sampling circuit and outputs a power-on control signal to the control node of the current adjusting device so as to adjust the output current of the current adjusting device.
Optionally, the input end of the power adjusting device is connected to a power supply, and the power supply voltage V isDDThe voltage resistance of the low-dropout linear regulator is larger than the withstand voltage of the power adjusting device, the output of the low-dropout linear regulator adopts a cascode structure, and the current adjusting device is a cascode device.
Optionally, the power adjusting device and the current adjusting device are selected from one of PMOSFET, NMOSFET, NPN, PNP, JFET, IGBT, and darlington.
Optionally, the power adjusting device and the current adjusting device are both PMOSFETs, an input terminal of the power adjusting device is connected to a power supply, a drain terminal of the power adjusting device is connected to a source terminal of the current adjusting device, a drain terminal of the current adjusting device is connected to a load node of the low dropout linear regulator, and a control node of the power adjusting device and a control node of the current adjusting device are gate terminals of PMOS transistors.
Optionally, the supply voltage VDDThe voltage resistance of the power adjusting device and the voltage resistance of the current adjusting device are both 1.8V, and the output voltage of the low dropout linear regulator is 1V-2.5V.
Optionally, the power-on control circuit adopts a voltage comparator or a schmitt trigger.
Optionally, the input end of the schmitt trigger is connected to the feedback voltage, and outputs a voltage signal as the power-on control signal; the Schmitt trigger is provided with a trigger threshold, when the feedback voltage is larger than the trigger threshold, an output voltage signal of the Schmitt trigger is inverted from a high-level output voltage to a low-level output voltage, the potential of a control node of the current adjusting device is reduced, and the output current is increased.
Optionally, the high-level output voltage is a power voltage VDD1/2, the low output voltage is 0.
Optionally, the error amplifying circuit includes a differential input single-ended output error amplifier, an inverting input terminal of the error amplifier is connected to the reference voltage, and a non-inverting input terminal of the error amplifier is connected to the feedback voltage.
Optionally, the voltage sampling circuit includes a first resistor and a second resistor, and the first resistor and the second resistor are connected in series between the output node of the current adjusting device and ground; the feedback voltage is acquired from a voltage at a series point of the first resistor and the second resistor.
The low dropout regulator comprises an error amplifying circuit, a voltage sampling circuit, a power-on control circuit, a power adjusting device and a current adjusting device, wherein the power-on control circuit obtains feedback voltage related to output voltage of the low dropout regulator through the voltage sampling circuit and outputs a power-on control signal to a control node of the current adjusting device so as to adjust the output current of the current adjusting device, and therefore real-time rapid power-on capacity can be achieved.
Further, in the low dropout regulator provided by the present invention, the power-on control circuit includes a schmitt trigger, an input end of the schmitt trigger is connected to the feedback voltage, and when the feedback voltage is greater than the trigger threshold, an output voltage of the schmitt trigger is inverted from a high level output voltage to a low level output voltage, so that a potential of a control node of the current adjusting device is reduced, an on-resistance of the current adjusting device is reduced, and a power-on speed is increased. The Schmitt trigger is used for power-on control, so that the power consumption is low and the occupied chip area is small.
Drawings
Fig. 1 is a system block diagram of a low dropout linear regulator according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a low dropout linear regulator according to an embodiment of the present invention.
Description of reference numerals:
100-an error amplification circuit; 200-a voltage sampling circuit; 300-a power-on control circuit; 10-a control node of the power regulating device; 20-a control node of the current regulation device; 21-the output node of the current regulation device; 30-load node of low dropout linear regulator.
Detailed Description
The low dropout linear regulator of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a system block diagram of a low dropout linear regulator according to an embodiment of the present invention. Referring to fig. 1, the input terminal of the low dropout linear regulator is connected to a reference voltage VREFOutputting a stable output voltage V by internal feedback regulationout(i.e., regulated voltage). In addition, in the embodiment of the invention, the voltage detection technology and the power-on control technology are utilized to enable the low dropout linear regulator to have the rapid power-on capability, so that the purpose of rapid power-on can be realized through real-time ground voltage detection and power-on control even if a cascode structure which can increase the power-on time is adopted in the low dropout linear regulator.
Fig. 2 is a circuit diagram of a low dropout linear regulator according to an embodiment of the present invention. The low dropout linear regulator according to an embodiment of the present invention is described with reference to fig. 2.
In an embodiment of the present invention, the low dropout regulator includes an error amplifying circuit 100, a power adjusting device M1, a current adjusting device M2, a voltage sampling circuit 200, and a power-on control circuit 300. Specifically, the error amplifying circuit 100 obtains the output voltage V of the low dropout linear regulator through the voltage sampling circuit 200outThe associated feedback voltage and outputs an error amplified signal to the control node 10 of the power regulation device M1; the current adjusting device M2 is connected in series with the power adjusting device M1, and the output node 21 of the current adjusting device M2 is connected with the load node 30 of the low dropout linear regulator; the power-up control circuit 300 obtains the feedback voltage through the voltage sampling circuit 200, and outputs a power-up control signal to the control node 20 of the current adjusting device M2 to adjust the output current of the current adjusting device M2.
In the low dropout regulator of the present embodiment, the power-on control circuit 300 obtains the output voltage V from the low dropout regulator through the voltage sampling circuit 20outThe associated feedback voltage and the output power-on control signal are transmitted to the control node 20 of the current adjusting device M2, and when the potential of the control node 20 of the current adjusting device M2 changes, the on-resistance changes, so that the output current changes, and the real-time fast power-on capability can be realized.
Referring to fig. 2, in the present embodiment, the error amplifying circuit 100 includes a differential-input single-ended-output error amplifier, and the inverting input terminal of the error amplifier is connected to the reference voltage VREFThe same-direction input end of the error amplifier is connected with the feedback voltage fed back by the voltage sampling circuit 200. The error amplifier can compare the feedback voltage and the reference voltage VREFAnd after amplifying the difference signal, outputting an error amplification signal to a control node 10 of the power adjusting device M1 to realize the adjustment of the output current of the power adjusting device M1, so as to promote the output voltage V of the low dropout linear regulatoroutAnd (4) stabilizing.
Specifically, in the low dropout regulator, the input terminal of the power adjusting device is connected to a power supply, and the power supply voltage V isDDThe voltage resistance of the low dropout regulator may be greater than the withstand voltage of the power regulator, and in order to avoid overvoltage operation of the power regulator, the output of the low dropout regulator of this embodiment adopts a cascode structure, and the current regulator M2 is a cascode device. The driving capability is adjusted through the control node of the cascode device, the output current (or the charging current of the LDO) can be increased without adding an additional transistor, and the design is simpler.
The power adjusting device M1 and the current adjusting device M2 may be selected from PMOSFET, NMOSFET, NPN, PNP, JFET, IGBT, Darlington (Darlington) tube, and the like. In consideration of the combination of static power consumption, conductivity, speed, and manufacturing process, the power adjustment device M1 and the current adjustment device M2 in this embodiment are both PMOSFETs (referred to as PMOS transistors), and the control node 10 of the power adjustment device M1 and the control node 20 of the current adjustment device M2 are both gate control nodes of PMOS transistors. Control node 10 of power adjustment device M1 is connected to the output of the error amplifier to receive the error amplified signal, and control node 20 of current adjustment device M2 is connected to the output of power-up control circuit 300 to receive the power-up control signal. Referring to fig. 2, in the present embodiment, the source of the power adjustment device M1 is connected to the power supply, i.e. the input power voltage VDDThe drain terminal of the power adjusting device M1 is connected to the source terminal of the current adjusting device M2, and the drain terminal of the current adjusting device M2 is the output node thereof, so that the load paths of the power adjusting device M1 and the current adjusting device M2 are connected in series. The output node 21 of the current adjusting device M2 is connected to the load node 30 of the low dropout regulator, and the voltage at the load node 30 of the low dropout regulator, i.e. the output voltage V thereofout。
The low dropout regulator can be suitable for the regulated output of various specifications according to the requirements of specific applications. As an example, the low dropout regulator according to the embodiment of the present invention may have a regulated voltage output of 0 to 3.3V, specifically, the regulated voltage may range from 1V to 2.5V, and the output regulated voltage may be, for example, about 2.5V, and correspondingly,supply voltage V of input power adjusting device M1DDAbout 3.3V (may have a variation range of plus or minus 10%), the power adjusting device M1 and the current adjusting device M2 may employ CMOS devices having a withstand voltage of about 1.8V, for example, the power adjusting device M1 and the current adjusting device M2 may each employ PMOS transistors having a maximum gate-source voltage Vgs of 1.8V. The invention is not limited in this regard and in other embodiments, the supply voltage V of the low dropout linear regulatorDDOr more than 3.3V, and according to the requirement of overvoltage protection, the power adjusting device M1 and the current adjusting device M2 which meet the voltage withstanding specification can be selected to obtain an output voltage range meeting the design requirement.
The voltage sampling circuit 200 may include a plurality of resistors. In this embodiment, the voltage sampling circuit 200 includes a first resistor R1 and a second resistor R2 connected in series between the output node 21 of the current adjusting device M2 and the ground, and since the output node 21 of the current adjusting device M2 is connected to the load node 30 of the low dropout linear regulator, the first resistor R1 and the second resistor R2 can be used for the output voltage V of the low dropout linear regulatoroutPerforming voltage division feedback to obtain output voltage V of low dropout regulatoroutThe proportional feedback voltage can avoid the problem of overvoltage operation of the error amplifying circuit and the power-on control circuit. In this embodiment, the feedback voltage output by the voltage sampling circuit 200 is collected from the voltage at the series point of the first resistor R1 and the second resistor R2. That is, the voltage sampling circuit 200 converts the output voltage V of the low dropout linear regulatoroutR2/(R1+ R2) is used as a feedback coefficient and is fed back to the error amplifying circuit100 and a power-up control circuit 300.
Referring to fig. 2, the low dropout linear regulator of the present embodiment may further include a load capacitor C connected between the output node 21 of the current adjusting device M2 and ground. The load capacitor C can be used as an on-chip decoupling capacitor of the low dropout linear regulator.
In this embodiment, the power-on control circuit 300 adjusts the power-on speed of the low dropout linear regulator by determining the feedback voltage and outputting the power-on control signal to the current adjusting device M2 to adjust the output current. Specifically, the power-up control circuit 300 may employ a voltage comparator, which compares an input feedback voltage (i.e., a sampling voltage) with a reference voltage to output a power-up control signal to the control node 20 of the current regulating device M2. The voltage comparator has two input terminals of non-inverting and inverting phases and an output terminal, and is further connected to a power supply voltage and ground. Under normal operation, as long as the voltage applied to the in-phase end is higher than the voltage of the anti-phase end, a high level is output; conversely, if the in-phase terminal voltage is lower than the reverse-phase terminal voltage, a low level is output. When the voltage comparator is used for power-on control, the output current of the current adjusting device M2 can be adjusted more accurately under the condition that the response time is met, so as to adjust the power-on speed. It should be noted that, because the size and power consumption of the conventional voltage comparator are large, the low dropout regulator is easy to generate much extra power consumption, and the chip area of the configuration is also large.
In order to reduce power consumption and reduce chip area, the power-on control circuit 300 may perform power-on control using a Schmidt trigger (Schmidt trigger). As an example, an input terminal of the schmitt trigger may be connected to the feedback voltage collected by the voltage sampling circuit 200, and output a voltage signal as the power-on control signal, and the schmitt trigger is further connected to a power voltage and ground. A schmitt trigger is a trigger triggered by an input potential whose output level is inverted when the received voltage decreases negatively or increases positively and exceeds a certain range. That is, when the feedback voltage changes beyond the trigger threshold, the output voltage of the schmitt trigger will flip. By using this feature, the potential of the control node 20 of the current adjusting device M2 can be controlled, and specifically, when the potential of the control node 20 of the current adjusting device M2 decreases, the on-resistance of the current adjusting device M2 decreases, so that the output current increases and the power-on speed increases. Compared with a common voltage comparator, the power-on control is carried out by utilizing the Schmitt trigger, so that the power consumption and the area of a chip can be effectively reduced. In addition, the Schmitt trigger is beneficial to enhancing the noise suppression capability and the anti-interference capability of the low dropout linear regulator.
In this embodiment, the schmitt trigger is, for example, a normal phase schmitt trigger. In another embodiment, the schmitt trigger is an inverted schmitt trigger, and the output terminal of the schmitt trigger is connected to an inverter. Taking the normal phase schmitt trigger as an example, the operation mode of the power-on control circuit 300 is as follows: when the feedback voltage is in a normal range, namely is smaller than a trigger threshold value, the output voltage of the Schmitt trigger is kept at a high level, and the power-on speed is a normal value at the moment; when the feedback voltage is increased in the forward direction until the feedback voltage is larger than the trigger threshold of the Schmitt trigger, the output voltage of the Schmitt trigger is converted from the high-level output voltage to the low-level output voltage, so that the potential of the current adjusting device M2 of the current adjusting device M2 is reduced, the output current is increased, and the power-on is accelerated. The appropriate schmitt trigger can be selected according to the output performance of the low dropout linear regulator and the performance of the current adjusting device, and a specific threshold voltage can be set.
In this embodiment, the power supply voltage VDDThe source electrode of the power adjusting device M1 is connected, and when the low dropout linear regulator works normally (at the moment, the output voltage V is outputoutUnchanged or equal to 0), the potential (i.e., the gate potential) of the control node 20 of the cascode device, i.e., the current regulation device M2, is 1/2 (i.e., V) of the supply voltage of the low dropout linear regulatorDD/2). Here, 1/2 of the power supply voltage of the schmitt trigger being the power supply voltage of the low dropout regulator and the high level output voltage being V may be providedDDAnd/2, the low level output voltage is 0.
Further calculations show that the power-up time is reduced to about 400 mus when the schmitt trigger is used for power-up control, i.e. the power-up speed is improved by 60%, compared to the power-up time (about 1ms) when no power-up speed control is used. Therefore, the power-on control circuit arranged in the low dropout regulator can accelerate the power-on speed.
In summary, the low dropout regulator of the present embodiment utilizes the voltage sampling circuit 200 to obtain the output voltage V of the low dropout regulatoroutThe associated feedback voltage is output to the power-up control circuit 300, so that the power-up control circuit 300 outputs a power-up control signal to a control node of the current adjusting device to adjust the output current of the current adjusting device, thereby realizing real-time rapid power-up capability. The power-on control circuit can be realized by adopting a voltage comparator or a Schmitt trigger, wherein the power consumption and the chip area can be effectively saved by utilizing the Schmitt trigger to carry out power-on control.
In different circuit implementations, the structures of the error amplifying circuit, the voltage sampling circuit and the power-on control circuit of the present invention may be different, but it should be understood that circuits formed by changing their implementations without departing from the technical principles of the present invention also belong to the protection scope of the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (9)
1. A low dropout regulator is characterized by comprising an error amplifying circuit, a voltage sampling circuit, a power-on control circuit, a power adjusting device and a current adjusting device; wherein the power regulator and the current regulator are both PMOS transistors, the power regulatorThe input end of the device being connected to the supply voltage VDDThe output of the low dropout linear regulator adopts a cascode structure, the current adjusting device is a cascode device, the error amplifying circuit obtains a feedback voltage associated with the output voltage of the low dropout linear regulator through the voltage sampling circuit and outputs an error amplifying signal to a control node of the power adjusting device, the current adjusting device is connected in series with the power adjusting device, the output node of the current adjusting device is connected with a load node of the low dropout linear regulator, the power-on control circuit obtains the feedback voltage through the voltage sampling circuit and outputs a power-on control signal associated with the magnitude of the feedback voltage to the control node of the current adjusting device so as to adjust the output current of the current adjusting device; when the control node of the current adjusting device is switched from a high potential to a low potential, the on-resistance of the current adjusting device is reduced, so that the output current is increased, and the power-on speed is increased.
2. The low dropout regulator of claim 1 wherein said supply voltage VDDIs larger than the withstand voltage of the power adjusting device.
3. The low dropout linear regulator of claim 2 wherein a source terminal of said power regulating device is connected to a power source, a drain terminal of said power regulating device is connected to a source terminal of said current regulating device, a drain terminal of said current regulating device is connected to a load node of said low dropout linear regulator, and a control node of said power regulating device and a control node of said current regulating device are gate terminals of PMOS transistors.
4. The low dropout regulator of claim 3 wherein said supply voltage VDDThe voltage resistance of the power adjusting device and the voltage resistance of the current adjusting device are both 1.8V, and the output voltage of the low dropout linear regulator is 1V-2.5V.
5. The low dropout regulator of claim 2 wherein said power-on control circuit employs a voltage comparator or a schmitt trigger.
6. The low dropout regulator of claim 5 wherein an input of said schmitt trigger is coupled to said feedback voltage and outputs a voltage signal as said power-on control signal; the Schmitt trigger is provided with a trigger threshold, when the feedback voltage is larger than the trigger threshold, an output voltage signal of the Schmitt trigger is inverted from a high-level output voltage to a low-level output voltage, the potential of a control node of the current adjusting device is reduced, and the output current is increased.
7. The LDO of claim 6 wherein said high level output voltage is said supply voltage VDD1/2, the low output voltage is 0.
8. The low dropout regulator according to any one of claims 1 to 7, wherein said error amplifying circuit comprises a differential input single-ended output error amplifier, wherein a reference voltage is coupled to an inverting input of said error amplifier, and wherein said feedback voltage is coupled to a non-inverting input of said error amplifier.
9. The low dropout linear regulator of any one of claims 1 to 7, wherein said voltage sampling circuit comprises a first resistor and a second resistor connected in series between an output node of said current regulation device and ground; the feedback voltage is acquired from a voltage at a series point of the first resistor and the second resistor.
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| EP1669831A1 (en) * | 2004-12-03 | 2006-06-14 | Dialog Semiconductor GmbH | Voltage regulator output stage with low voltage MOS devices |
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| CN104010415B (en) * | 2014-05-20 | 2017-01-04 | 矽力杰半导体技术(杭州)有限公司 | Load current method of adjustment and circuit and the Switching Power Supply with this circuit |
| CN205142258U (en) * | 2015-09-25 | 2016-04-06 | 上海矽昌通信技术有限公司 | Go up electronic control system |
| US9857818B1 (en) * | 2017-03-06 | 2018-01-02 | Peregrine Semiconductor Corporation | Biasing for lower RON of LDO pass devices |
| CN208226983U (en) * | 2018-06-15 | 2018-12-11 | 思力科（深圳）电子科技有限公司 | The multiplex circuit of LDO and POR |
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