JP2014176040A - Differential output circuit, semiconductor ic for high speed serial communication, and high speed serial communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential output circuit that maintains a constant output amplitude.SOLUTION: A resistor variation detection circuit 11 is used to detect product variations of output resistors R1, R2, and a current regulation circuit 12 is used to control currents of a current source I1 for data and a current source I2 for emphasis data in accordance with the detection results, so that a constant output amplitude can be maintained irrespective of product variations of internal resistors in the differential output circuit of a current mode logic type. The differential output circuit can be used to provide a high speed serial interface and a communication system therewith.

Description

  The present invention relates to a differential output circuit, a semiconductor IC for high-speed serial communication, and a high-speed serial communication system, and more particularly to a differential output circuit used to configure an interface employing a current mode logic system, and the differential The present invention relates to a semiconductor IC for high-speed serial communication using an output circuit and a high-speed serial communication system.

  2. Description of the Related Art In recent years, with the increase in interface communication between products such as personal computers, communication devices, and digital home appliances, development of high-speed serial interfaces and communication systems including them has been underway. In the high-speed serial interface, for example, current mode logic (CML) type small amplitude differential transmission is adopted.

  An interface that employs a current mode logic system is configured using a differential current output circuit (also simply referred to as a differential output circuit) having high noise resistance. However, in the conventional differential output circuit, for example, a manufacturing variation of 15 to 30% occurs in the internal resistance (output resistance) of the semiconductor IC. Similarly, a manufacturing variation also occurs in the termination resistor. There was a problem that the amplitude of the output signal (output amplitude) fluctuated.

  Patent Document 1 includes a detection unit that detects an output amplitude in order to obtain an output amplitude that conforms to the interface standard, and controls a current supplied to a differential output unit (output resistor) according to the detection result. A differential output circuit is disclosed. However, the problem that the output amplitude fluctuates due to the manufacturing variation of the internal resistance is not solved.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a differential output circuit that maintains an output amplitude constant regardless of manufacturing variations in internal resistance.

  A differential output circuit according to the present invention is a differential output circuit that converts an input signal into a differential signal, transmits the differential signal, and outputs an output signal, and outputs the output signal to the output resistor. A current supply circuit that supplies current according to an input signal, a main body that outputs the output signal from one end of the output resistor, a detection unit that detects a resistance value of the output resistor, and the detection unit And an adjustment unit that controls the current supply circuit in accordance with the detection result to adjust the current supplied to the output resistor.

  According to the differential output circuit of the present invention, it is possible to keep the amplitude (output amplitude) of the output signal constant regardless of the manufacturing variation of the output resistance.

It is a figure which shows the general structure of a differential output circuit. It is a figure which shows the waveform of data, emphasis data, and an output amplitude (output current). 1 is a diagram illustrating a basic configuration of a differential output circuit according to a first embodiment. It is a figure which shows the structure of the differential output circuit which concerns on 2nd Embodiment. It is a figure which shows arrangement | positioning of an output resistance. It is a figure which shows the structure of the differential output circuit which concerns on 3rd Embodiment. It is a figure which shows the structure of the differential output circuit which concerns on 4th Embodiment. It is a figure which shows the deformation | transformation structure with respect to the differential output circuit of FIG.

<< First Embodiment >>
A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a general configuration of the differential output circuit 10. The differential output circuit 10 includes a data current source I1, an emphasis data current source I2, transistors (FETs) P1 to P4, and output resistors R1 and R2 (for example, 50Ω).

  The sources of the transistors P1 and P2 are the data current source I1, the sources of the transistors P3 and P4 are the emphasis data current source I2, the drains of the transistors P1 and P3 are one end of the output resistor R1, and the drains of the transistors P2 and P4 are Each is connected to one end of the output resistor R2. Further, one ends of the output resistors R1 and R2 are connected to a receiving circuit including a termination resistor R3. Note that the receiving circuit is provided outside the semiconductor IC. The termination resistor R3 is 100Ω when the output resistors R1 and R2 are 50Ω. On the other hand, the other ends of the output resistors R1 and R2 are clamped to the signal ground.

  The differential output circuit 10 is configured in one semiconductor IC except for the termination resistor R3, and the termination resistor R3 is provided outside the semiconductor IC.

  In the differential output circuit 10 having the above-described configuration, data (D) and its inverted signal (DB) are input to the gates of the transistors P1 and P2, respectively, and emphasis data (E) and gates are respectively input to the gates of the transistors P3 and P4. The inverted signal (EB) is input.

The output amplitude of the differential output circuit 10 is given by the product Iout · R3 of the resistance (R3) of the termination resistor R3 and the current (output current) Iout flowing therethrough. Here, assuming that the resistances (R1, R2) of the output resistors R1, R2 are equal to each other (R1 = R2), the output current Iout is the current (I1, I2) of the data current source I1 and the emphasis data current source I2. make use of,
Iout = (I1 + I2) R1 / (R1 + R3) (1)
Is required. From equation (1), it can be seen that the output amplitude becomes larger (smaller) when the resistances of the output resistors R1 and R2 are larger (smaller) than designed due to manufacturing variations.

  FIG. 2 shows an example of waveforms of data (D), emphasis data (E), and output current (Iout). Emphasis data is obtained by shifting the data by 1 bit and inverting it. Since the currents (I1, I2) have the same waveform as that of the data and the emphasis data, respectively, the output current Iout has a waveform obtained by superimposing the data and the emphasis data according to the equation (1). In the example illustrated in FIG. 2, the waveform of the output current Iout is a waveform in which a high frequency is emphasized with respect to the data waveform by emphasis.

  FIG. 3 shows a basic configuration of the differential output circuit 20 of the first embodiment. The differential output circuit 20 includes the above-described differential output circuit (referred to as a main body section) 10, a resistance variation detection circuit 11, and a current adjustment circuit 12.

  The resistance variation detection circuit 11 detects the resistances of the output resistors R 1 and R 2, that is, their manufacturing variations, and sends the detection result to the current adjustment circuit 12. The current adjustment circuit 12 controls the currents of the data current source I1 and the emphasis data current source I2 in accordance with the detection result of the manufacturing variation of the output resistors R1 and R2. When the resistances of the output resistors R1 and R2 are larger (smaller) than the design, the currents (I1, I2) are made smaller (larger). As a result, the current Iout flowing through the termination resistor R3, that is, the output amplitude is maintained constant regardless of manufacturing variations of the output resistors R1 and R2.

<< Second Embodiment >>
A second embodiment of the present invention will be described with reference to FIGS. In addition, about the component similar to 1st Embodiment, it represents using the same code | symbol and the description is abbreviate | omitted.

  If the output resistors R1 and R2 are directly detected, parasitic capacitance is generated at one end of the output resistors R1 and R2 connected to the receiving circuit, which may hinder high-speed operation of the interface. Therefore, in this embodiment, the differential output circuit 10 is simulated using the output resistors R4 independent of the output resistors R1 and R2, and the output resistor R4 is detected so that the output resistor R4 is generated without generating parasitic capacitance. Consider detecting R1 and R2.

  FIG. 4 shows a configuration of the differential output circuit 30 according to the second embodiment. The differential output circuit 30 includes the differential output circuit (main body portion) 10 and the constant current circuit 31 described above.

  In the main body 10, the data current source I1 and the emphasis data current source I2 are specifically configured by using transistors (FETs) M1 and M2, respectively. The sources of the transistors M1 and M2 are clamped to the frame ground.

  The constant current circuit 31 includes the resistance variation detection circuit 11 and the current adjustment circuit 12 described above, and includes a transistor (FET) M3, an output resistor R4, and an amplifier (differential amplifier circuit) AMP.

  A circuit simulating the main body 10 is constituted by the transistor M3 and the output resistor R4. In this circuit, the transistor M3 and the output resistor R4 are connected in series. That is, the drain of the transistor M3 and one end of the output resistor R4 are connected. Further, the source of the transistor M3 is clamped to the frame ground, and the other end of the output resistor R4 is clamped to the signal ground. The resistance of the output resistor R4 is preferably larger than that of the output resistors R1 and R2. Thereby, the power consumption of the constant current circuit 31 (particularly the portion corresponding to the resistance variation detection circuit 11) is reduced.

  FIG. 5 shows an example of the arrangement of the output resistors R1, R2, and R4. By disposing the output resistor R4 between the output resistors R1 and R2 and adjoining them, the difference in resistance between the output resistors R1 and R2 and the output resistor R4 due to in-plane variation of the semiconductor IC can be reduced. Further, by arranging dummy resistors on both sides of the output resistors R1 and R2, the difference in resistance can be further reduced.

  The amplifier AMP is configured using an operational amplifier. By using an operational amplifier, the detection result of the manufacturing variation of the output resistor R4 by the constant current circuit 31 (particularly the portion corresponding to the resistance variation detection circuit 11) can be output (current output). Therefore, the constant current circuit 31 (particularly the current adjustment circuit 12). This is suitable for controlling the currents of the data current source I1 and the emphasis data current source I2 (transistors M1 and M2).

The inverting input terminal of the amplifier AMP, one end of the output resistor R4 in series to the transistor M3 is connected, the potential V ₄ is inputted. A reference potential _VREF is input to the non-inverting input terminal of the amplifier AMP. Thereby, the amplifier AMP functions as a differential amplifier circuit. In other words, the amplifier AMP amplifies the differential input V _REF −V ₄ and outputs the potential (current proportional to this) (also referred to as a reference current) as the output of the constant current circuit 31. Input to the gate of M2.

The reference potential V _REF is generated by the resistance voltage dividing circuit 32, for example. The resistance voltage dividing circuit 32 is simply configured from two resistors r1 and r2 connected in series. Here, one ends of the resistors r1 and r2 are clamped to the signal ground and the frame ground, respectively. The resistance voltage dividing circuit 32 generates a reference potential V _REF = Vcc · r2 (r1 + r2) with respect to the signal ground potential Vcc. The constant current circuit 31 may be configured including the resistance voltage dividing circuit 32.

In the constant current circuit 31 of the construction described above, the amplifier AMP, the amount of current I4 potential _{V 4} is equal to the reference potential _{V REF (= (Vcc-V} REF) / R4) is supplied to the output resistor R4. When the output resistance R4 is large (small), the current I4 becomes small (large). Since the gate of the transistor M3 and the gates of the transistors M1 and M2 are connected, the currents I1 and I2 supplied by the transistors M1 and M2 are small when the output resistance R4 is large (small) (like the current I4) ( growing. As a result, the current Iout flowing through the termination resistor R3, that is, the output amplitude, is maintained constant regardless of manufacturing variations of the output resistor R4, that is, the output resistors R1 and R2.

«Third embodiment»
A third embodiment of the present invention will be described with reference to FIG. In addition, about the component similar to 1st and 2nd embodiment, it represents using the same code | symbol and the description is abbreviate | omitted.

  In the present embodiment, it is considered that the output resistance, the emphasis gain, and the output amplitude of the differential output circuit are switched by using the current output from the constant current circuit 31 as a reference current.

  FIG. 6 shows a configuration of the differential output circuit 40 according to the third embodiment. The differential output circuit 40 includes a main body 10 ′, a constant current circuit 31, and an output amplitude switching unit 41 similar to the differential output circuit 10 described above.

  The basic configuration of the main body 10 'is substantially the same as that of the differential output circuit 10 described above. However, each of the output resistors R1 and R2 is configured using two parallel resistors. The configuration is not limited to two, and a plurality of parallel resistors may be used. Here, a changeover switch (also referred to as an output resistance changeover switch) SW1 is connected in series to each of the four resistors constituting the output resistors R1 and R2. The resistances of the output resistors R1 and R2 are increased or decreased by switching and connecting the resistors using the changeover switch SW1. As a result, even when the wiring resistance of the transmission line, the termination resistance R3, etc. are different, it is possible to obtain a constant design output amplitude by increasing or decreasing the resistances of the output resistances R1 and R2 accordingly.

  The emphasis data current source I2 is configured by using transistors M2 and M4 arranged in parallel. Here, a changeover switch (also referred to as an emphasis gain changeover switch) SW2 is connected in series to each of the transistors M2 and M4. By switching and connecting the transistors M2 and M4 using the changeover switch SW2, the current for emphasis data, that is, the emphasis gain is increased or decreased. As a result, even when the transmission characteristics are poor, such as when the transmission line is long, it is possible to obtain a constant design output amplitude by increasing or decreasing the emphasis gain accordingly.

The configuration of the constant current circuit 31 is the same as described above. However, in FIG. 6, the resistance voltage dividing circuit 32 that generates the reference potential V _REF is omitted. The output of the constant current circuit 31 is input to the output amplitude switching unit 41 via the transistors M5 and M6.

  The output amplitude switching unit 41 includes three parallel transistors M7, M8, and M9. The sources of transistors M7, M8 and M9 are clamped to signal ground. The outputs of the constant current circuit 31 are input to the gates of the transistors M7, M8, and M9, and the outputs from these drains are combined and output as the output of the output amplitude switching unit 41 via the transistor M10. Input to the gates (data current source I1 and emphasis data current source I2).

  The transistor M6 forms a current mirror circuit with each of the transistors M7, M8, and M9. Here, it is assumed that the electrical characteristics of the transistors M7, M8, and M9 are equal to those of the transistor M6. Thereby, the transistors M7, M8, and M9 each output an amount of current equal to the current output from the transistor M6.

  Similarly, the transistor M10 forms a current mirror circuit with each of the transistors M1, M2, and M4. Here, it is assumed that the electrical characteristics of the transistors M1, M2, and M4 are equal to those of the transistor M10. Thereby, the transistors M1, M2, and M4 each output a current equal to the current output from the transistor M10.

  Here, a changeover switch (also referred to as an output amplitude changeover switch) SW3 is connected in series to each of the transistors M7, M8, and M9. By switching and connecting the transistors M7, M8, and M9 using the changeover switch SW3, the output of the constant current circuit 31 is amplified and the transistors M1, M2, and M4 (data current source I1 and emphasis data current source I2). To increase or decrease the output amplitude. Thereby, for example, when the loss of the transmission line is small, the output amplitude can be reduced accordingly to reduce the power consumption.

<< Fourth Embodiment >>
A fourth embodiment of the present invention will be described with reference to FIGS. In addition, about the component similar to 1st-3rd embodiment, it represents using the same code | symbol and the description is abbreviate | omitted.

  From the expression (1), the output current Iout (and output amplitude) depends on the manufacturing variation of the termination resistor R3 as well as the output resistors R1 and R2. Therefore, in the present embodiment, it is considered to keep the output amplitude more constant by taking into account the manufacturing variation of the termination resistor R3.

  FIG. 7 shows a configuration of the differential output circuit 50 according to the fourth embodiment. The differential output circuit 50 includes the above-described differential output circuit (main body portion) 10 and two constant current circuits 31 and 51.

  The configurations of the main body 10 and the constant current circuit 31 are the same as described above.

  The constant current circuit 51 is configured in the same manner as the constant current circuit 31. However, the resistor R5 is included instead of the output resistor R4. The resistor R5 is a high-precision resistor whose resistance value is determined with high accuracy, and is disposed outside the semiconductor IC in the same manner as the termination resistor R3. Thereby, it is possible to detect the manufacturing variation of the termination resistor R3 by simulating the termination resistor R3 using the resistor R5 and detecting the resistor R5.

  The outputs (output currents) of the two constant current circuits 31 and 51 are combined via the transistors M12 and M13, respectively, and the gates of the transistors M1 and M2 (the data current source I1 and the emphasis) via the transistor M11 are combined as reference currents. Input to the data current source I2).

  The transistor M11 forms a current mirror circuit with each of the transistors M1 and M2. Here, it is assumed that the electrical characteristics of the transistors M1 and M2 are equal to those of the transistor M11. Thereby, the transistors M1 and M2 each output a current equal to the current output from the transistor M11.

  The differential output circuit 50 having the above-described configuration uses the current obtained by synthesizing the output currents of the two constant current circuits 31 and 51 as the reference current, thereby manufacturing the termination resistor R3 as well as the output resistors R1 and R2. The output amplitude can be kept more constant regardless of variations.

  Note that, as in the modification shown in FIG. 8, when the main body 10 is configured in different semiconductor ICs on the receiving side including the termination resistor R3 and the other transmitting side (the two semiconductor ICs depend on the transmission line). The resistor R5 included in the constant current circuit 51 may be disposed in the receiving-side semiconductor IC in which the termination resistor R3 is disposed. As a result, the resistance R5 exhibits the same manufacturing variation as the termination resistance R3, so that the output amplitude can be kept more constant.

  As described above in detail, the differential output circuits 10 to 60 according to the first to fourth embodiments allow the data current source I1 and the emphasis data current source I2 according to the product variation of the output resistors R1 and R2. Therefore, in the current mode logic type differential output circuit, the output amplitude can be kept constant regardless of the product variation of the internal resistance.

  In addition, by configuring the high-speed serial communication semiconductor IC or the high-speed serial communication system including the differential output circuits 10 to 60 according to the above-described embodiment, a semiconductor IC capable of high-speed communication without fluctuation in output amplitude, and A communication system can be configured.

Incidentally, in the constant current circuit 31 and 51, the output of the bandgap reference circuit can be used as a reference potential _{V REF.} As a result, the influence of the power supply voltage, temperature, process variation, etc. of the semiconductor IC can be further suppressed.

  I1 ... current source for data, I2 ... current source for emphasis data, M1 to M14, P1 to P4 ... transistor, R1, R2, R4 ... output resistance, R3 ... termination resistance, R5 ... resistance, SW1 to SW3 ... changeover switch, DESCRIPTION OF SYMBOLS 10,10 '... Differential output circuit (main part) 20, 30, 40, 50, 60 ... Differential output circuit, 11 ... Resistance variation detection circuit, 12 ... Current adjustment circuit, 31, 51 ... Constant current circuit, 32. Resistance voltage dividing circuit, 41 ... Output amplitude switching unit.

Japanese Patent No. 4798618

Claims (9)

A differential output circuit that converts an input signal into a differential signal, transmits the differential signal, and outputs an output signal,
An output resistor, and a current supply circuit that supplies current to the output resistor in accordance with the input signal, and a main body that outputs the output signal from one end of the output resistor;
A detector for detecting a resistance value of the output resistor;
An adjustment unit that controls the current supply circuit according to a detection result of the detection unit to adjust a current supplied to the output resistor;
A differential output circuit comprising:   The differential output circuit according to claim 1, wherein the detection unit detects a resistance value of the output resistor by detecting a resistance value of a first resistor different from the output resistor.   The differential output circuit according to claim 2, wherein the first resistor is disposed adjacent to the output resistor. The main body further includes a receiving circuit that receives the output signal,
The differential output circuit according to claim 1, wherein the detection unit further detects a resistance value of a second resistor included in the reception circuit.   5. The differential output circuit according to claim 1, wherein the output resistor includes a plurality of resistors in parallel and a switch for switching the plurality of resistors. 6. .   The difference according to any one of claims 1 to 5, wherein the current supply circuit includes a plurality of parallel current sources and a switch that switches the plurality of current sources. Dynamic output circuit.   The said adjustment part is comprised including the another several current source paralleled, and the switch which switches this another several current source, It is characterized by the above-mentioned. The differential output circuit described.   A semiconductor IC for high-speed serial communication using the differential output circuit according to claim 1.   A high-speed serial communication system using the differential output circuit according to claim 1.

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