JP5477435B2 - Stability determination method, power conversion device - Google Patents

Description

  The present invention relates to a power converter that once converts alternating current to direct current, and further converts the direct current to alternating current, and a technique for determining its stability.

  2. Description of the Related Art Conventionally, power converters that rectify AC power to obtain DC power, perform switching on the DC, and convert it into AC power of variable voltage and variable frequency are widely used. The said power converter device contributes to variable-speed control of a three-phase alternating current rotating machine with the alternating current power after conversion, for example.

  As one type of such a power converter, a configuration is known in which a converter and an inverter are connected to each other via a pair of DC buses, and a capacitor is connected between the pair of DC buses.

  The converter performs full-wave rectification on an AC voltage, for example, a three-phase AC voltage supplied from a commercial power source, and converts it into a DC voltage. For example, a diode bridge is employed as the converter.

  The inverter switches the DC voltage obtained by the converter and converts it into a three-phase AC voltage. The three-phase AC voltage is supplied to a three-phase AC rotating machine that is a load.

  The inverter has a switching element. By controlling the operation of the switching element, the inverter outputs a three-phase AC voltage having a desired frequency to the load.

  When the capacitor is employed as a smoothing circuit or a part thereof, the capacitor is required to have a large capacitance in order to improve the driving performance of the AC rotating machine. An electrolytic capacitor is suitable for obtaining a capacitor having such a large capacitance, but a large capacitance is also desired because of the limitation due to the withstand capability of the ripple current.

  However, the use of such a large-capacity capacitor has problems that the power conversion device becomes large and the manufacturing cost increases.

  On the other hand, there is a technique that uses a capacitor with a small capacity of about several tens of μF without giving priority to the smoothing function, and is disclosed in Patent Documents 1 and 2 and Non-Patent Document 1 listed below.

In Patent Documents 1 and 2, the system becomes unstable due to the impedance of an AC power source including a power transformer (hereinafter referred to as power source impedance) and the impedance of wiring (hereinafter referred to as wiring impedance) by reducing the capacitance of the capacitor. Has been shown to be. Patent Documents 1 and 2 also show that the conditions under which the system becomes unstable are mainly as follows.
(A) The smaller the capacitance of the capacitor, the more likely to become unstable.
(B) The smaller the resistance component of the power supply and wiring, the more likely to become unstable.
(C) The larger the inductance of the power supply and wiring, the more likely it becomes unstable.
(D) The lower the DC voltage, the more likely to become unstable.
(E) The larger the motor output, the more likely to become unstable.

  In Patent Document 1, in view of the fact that the voltage between the DC buses tends to vibrate depending on the impedance condition on the power source side, and the control system becomes unstable, the output voltage command correction is controlled to keep the control system stable. The technology is described.

JP 2009-17673 A JP 2007-181358 A

Isao Takahashi and Yoichi Ito "Control Method of Capacitorless Inverter" National Conference of the Institute of Electrical Engineers of Japan, Vol.5, No.527, p624

  In the method described in Patent Document 1, in addition to the state of power supply impedance and wiring impedance, when the voltage of the AC power supply is low, the DC voltage may vibrate and the system may become unstable.

  And since the instability is not detected in the method of Patent Document 1, when the system becomes unstable, the DC voltage greatly oscillates to shorten the life of the components and capacitors constituting the inverter. Will cause those breakdowns.

  The present invention has been made to solve the above-described problems. In the power converter, the capacitance of the capacitor is small, and the DC voltage vibrates due to various conditions, and the operation of the power converter becomes unstable. The purpose is to provide a technology to detect this when it becomes.

  The stability determination method according to the present invention includes a converter (8), an inverter (1), a pair of DC buses (70, 71) connecting the converter and the inverter, and the pair of DC buses. It is a method of determining the stability of operation in a power converter (5) provided with a capacitor (72) connected.

  The operation of the power converter is unstable because the amplitude (| Vdcr |) of the pulsation (Vdcr) of the DC voltage (Vdc) between the pair of DC buses exceeds a predetermined value (Q). It is determined that there is.

  And when it determines with operation | movement of the said power converter device being unstable, the electric power output from the said inverter is reduced.

  In the first aspect, a signal (SJ) that increases corresponding to the length of the period in which the operation of the power converter is determined to be unstable is changed to a command value (f *, Subtract from (T *, I *, V *).

  In the second aspect, the signal (SJ) that increases corresponding to the length of the period in which the operation of the power converter is determined to be unstable is a predetermined threshold (TH0, TH1, TH2, TH3, TH4). ), The power is reduced.

  A third aspect of the stability determination method according to the present invention is the first aspect or the second aspect, wherein the predetermined value (Q) is increased by an average value (Vdcb) of the DC voltage (Vdc). Is set to a non-increasing value.

The power conversion device (5 ) according to the present invention includes a converter (8), an inverter (1), a pair of DC buses (70, 71) connecting the converter and the inverter, and the pair of DC buses. A capacitor (72) connected therebetween, and further includes a stability determination circuit (6) and a correction circuit (2). The stability determination circuit includes an average value acquisition circuit (12) for obtaining an average value (Vdcb) of a DC voltage between the pair of DC buses, and a pulsation component of the DC voltage by subtracting the average value from the DC voltage. A subtractor (13) for obtaining (Vdcr), an absolute value acquisition circuit (15) for obtaining the amplitude (| Vdcr |) for the pulsation, and a predetermined value setter (14) for setting a predetermined value (Q). Have. When the amplitude is larger than the predetermined value, the correction circuit (2) corrects the command value (f *, T *, I *, V *) on which the power output from the inverter depends to be small, and Output to the inverter.

In a first aspect of that, the predetermined value (Q) is set to the non-increase value serving relative increase of the average value (Vdcb).

In a second aspect of that, the signal the amplitude increases in response to the length of the larger period than the predetermined value (SJ) exceeds a predetermined threshold value (TH0, TH1, TH2, TH3 , TH4) The command values (f *, T *, I *, V *) are corrected to be small.

In a third aspect of that, a signal (SJ) in which the amplitude increases in response to the length of the larger period than the predetermined value, the command value (f *, T *, I *, V *) Subtract from.

When the operation of the power conversion device becomes unstable, the pulsation of the DC voltage increases compared to when the operation of the power conversion device becomes stable. Therefore, according to the first to third aspects of the stability determination method according to the present invention and the first to third aspects according to the power conversion apparatus according to the present invention, the pulsation component exceeds a predetermined value, thereby It can be determined that the operation is unstable.

The smaller the power output from the inverter, the more stable the operation of the power converter is. Therefore, according to the first to third aspects of the stability determination method according to the present invention and the first to third aspects of the power conversion apparatus according to the present invention, the operation of the power conversion apparatus can be stabilized.

The power output from the inverter is reduced as the command value on which the power depends is smaller. Therefore, according to the 1st aspect of the stability determination method concerning this invention, and the 2nd thru | or 3rd aspect of the power converter device concerning this invention, the operation | movement of a power converter device can be stabilized.

Even when the operation of the power converter is stable, the amplitude of the DC voltage pulsation decreases as the average value of the DC voltage increases. Therefore, according to the third aspect of the stability determination method according to the present invention and the first aspect of the power converter according to the present invention, when the average value of the DC voltage is small, the operation of the power converter is actually stable. This reduces the possibility of misjudging this as unstable despite being, or misjudging it as stable despite the fact that the operation of the power converter is actually unstable To do.

It is a circuit diagram which illustrates the composition of the power converter concerning a 1st embodiment. It is a block diagram which illustrates the composition of a stability judgment circuit. It is a wave form chart which illustrates operation of a stability judgment circuit. It is a graph which shows the relationship between the average value of DC voltage, and a predetermined value. It is a graph which shows the relationship between the average value of DC voltage, and a predetermined value. It is a circuit diagram which illustrates the composition of the power converter concerning a 3rd embodiment. It is a circuit diagram which illustrates the composition of the power converter concerning a 4th embodiment thru / or a 6th embodiment. It is a circuit diagram which illustrates the composition of the command value correction circuit concerning a 4th embodiment. It is a wave form diagram which illustrates operation of the command value correction circuit concerning a 4th embodiment. It is a circuit diagram which illustrates the composition of the command value correction circuit concerning a 5th embodiment. It is a wave form diagram which illustrates operation of the command value correction circuit concerning a 5th embodiment. It is a wave form diagram which illustrates other operations of the command value correction circuit concerning a 5th embodiment. It is a circuit diagram which illustrates the composition of the command value correction circuit concerning a 6th embodiment. It is a wave form diagram which illustrates operation | movement of the command value correction circuit concerning 6th Embodiment. It is a wave form diagram which illustrates other operations of the command value correction circuit concerning a 6th embodiment.

First embodiment.
FIG. 1 illustrates the configuration of a power conversion device 5 according to the first embodiment. The power conversion device 5 includes a converter 8, an inverter 1, and a DC link unit 7 that connects the converter 8 and the inverter 1.

  Converter 8 rectifies an AC voltage obtained from AC power supply 10 (here, a three-phase AC power supply) and converts it into a DC voltage. Here, a three-phase full-wave rectifier diode bridge is employed as the converter 8, but other rectifier circuits may also be employed.

  Here, the converter 8 is illustrated as receiving a phase voltage from the AC power supply 10 via the reactor group 9. The reactor group 9 may be included in the power conversion device 5 and grasped.

  The DC link unit 7 has a pair of DC buses 70 and 71, and the DC bus 71 is applied with a higher potential than the DC bus 70. DC buses 70 and 71 connect converter 8 and inverter 1. A capacitor 72 is connected between the DC buses 70 and 71. A DC voltage Vdc is applied between the DC buses 70 and 71, and thus across the capacitor 72. In FIG. 1, a parasitic inductor 73 and a parasitic resistance 74 in the DC link unit 7 are also shown.

  As the capacitor 72, a capacitor having a capacitance smaller than the capacitance required for the smoothing circuit, for example, about several tens of μF, as shown in Patent Documents 1 and 2 and Non-Patent Document 1, is employed. .

  The inverter 1 switches the DC voltage Vdc to output an AC voltage having a desired frequency, here, a three-phase AC voltage. And the said alternating voltage is applied to the load 11 (here AC rotating machine).

  The AC rotating machine includes a synchronous machine, an induction machine, or other types of motors.

  For the sake of simplicity, the inverter 1 grasps the switching element that performs the switching as well as a circuit that generates a control signal that controls the switching.

  The stability determination circuit 6 receives the DC voltage Vdc and outputs a stability determination signal J. The stability determination circuit 6 determines whether or not the DC voltage Vdc is not in an oscillation state. If the DC voltage Vdc is not in an oscillation state, the operation of the power converter is determined to be stable, and if it is in the oscillation state, the operation is unstable. judge.

  Specifically, it is determined that the DC voltage Vdc is in an oscillating state when the amplitude | Vdcr | of the pulsating component Vdcr of the DC voltage Vdc exceeds a predetermined value Q.

  The stability determination circuit 6 contributes to the determination by adopting, for example, the configuration shown in FIG. That is, the stability determination circuit 6 includes an average value acquisition circuit 12, a subtracter 13, a predetermined value setter 14, an absolute value acquisition circuit 15, and a comparator 16.

  The average value acquisition circuit 12 has a function of inputting a DC voltage Vdc, obtaining and outputting the average value Vdcb, and a low-pass filter, for example, is employed. The transfer function of the low-pass filter is represented by, for example, 1 / [1 + s · (1/30 / (2π)] (“s” is a differential operator), where the cutoff frequency is set to 30 Hz. This is because the main frequency component of the pulsation component Vdcr is 300 Hz, which is six times the three-phase power supply frequency 50 Hz, so that the gain at 300 Hz is significantly attenuated.

  Since the technique for measuring the DC voltage Vdc is well known, the details are omitted here.

  The subtractor 13 receives the DC voltage Vdc and the average value Vdcb, subtracts the average value Vdcb from the DC voltage Vdc, obtains a DC voltage pulsation component Vdcr, and outputs this.

  The absolute value acquisition circuit 15 receives the pulsation component Vdcr and takes the absolute value to obtain and output the vibration | Vdcr |.

  The predetermined value setter 14 stores or generates a predetermined value Q and outputs it to the comparator 16.

  The comparator 16 is. The predetermined value Q output from the predetermined value setter 14 and the amplitude | Vdcr | of the pulsation component Vdcr are input, and the comparison result between them is output as the stability determination signal J.

  FIG. 3 shows the waveforms of the DC voltage Vdc, the pulsation component Vdcr, its amplitude | Vdcr |, and the stability determination signal J. Here, a case where the DC voltage Vdc oscillates at time t1 is illustrated.

  When the DC voltage Vdc oscillates, the vibration width increases rapidly. However, the average value Vdcb hardly fluctuates, and the amplitude | Vdcr | of the pulsation component Vdcr increases rapidly. In other words, when the operation of the power conversion device 5 becomes unstable, the pulsation component Vdcr of the DC voltage Vdc increases compared to when the operation of the power conversion device 5 becomes stable. Therefore, when the amplitude | Vdcr | obtained from the absolute value acquisition circuit 15 is lower than the predetermined value Q (or “is equal to or lower than the predetermined value Q”), the direct current tsutsu Vdc is not oscillating (of the power converter 5). The stability determination circuit 6 determines that the operation is stable, and sets the stability determination signal J to “L”. When the amplitude | Vdcr | is equal to or greater than the predetermined value Q (or “larger than the predetermined value Q”), the DC power tsu Vdc is oscillating (the operation of the power converter 5 is unstable) and the stability determination is made. The circuit 6 makes the determination and sets the stability determination signal J to “H”.

  The inverter 1 inputs the stability determination signal J, and if it is “H”, the operation of the inverter 1 and then the operation of the power converter 5 is stopped. Alternatively, an unstable (oscillation) state may be indicated by outputting an error signal to the outside.

  As described above, when the DC voltage Vdc vibrates and the operation of the power converter 5 becomes unstable, this can be detected or the operation can be stopped. This is desirable from the viewpoint of avoiding failure of the power conversion device 5 and shortening of the life of its components.

  Here, the stability determination signal J does not faithfully represent the fluctuation of the magnitude relationship between the amplitude | Vdcr | and the predetermined value Q, and once the stability determination signal J becomes “H”, a mode of maintaining this is exemplified. Yes. For example, once the stability determination signal J becomes “H”, the stability determination signal J is not “only” until the amplitude | Vdcr | becomes smaller than the predetermined value Q over a period longer than 1/6 of the power supply period. L ”. Thereby, it is possible to detect the oscillation of the DC voltage Vdc in consideration of the waveform of the amplitude | Vdcr |.

  The correspondence between “L” / “H” of the stability determination signal J and the stability / unstableness of the DC voltage Vdc may be opposite to the above-described correspondence.

Second embodiment.
The predetermined value Q described above may be a fixed value, but is preferably set to a value that does not increase with respect to an increase in the average value Vdcb. This is because even when the operation of the power converter 5 is stable, the amplitude | Vdcr | of the pulsation component Vdcr tends to decrease as the average value Vdcr of the DC voltage Vdc increases. Because of this tendency, if the predetermined value Q is a fixed value, the power converter 5 operating stably when the average value Vdcb is small is erroneously detected as unstable or the average value Vdcb is large. May erroneously detect that the power converter 5 whose operation is unstable is operating stably.

  Hereinafter, the reason why the above tendency occurs will be described. Now, the power Pin input to the converter 8 is expressed by Expression (1) considering that it is a three-phase power source.

  E: effective value of input voltage, I: effective value of input current, φ: phase difference between input voltage and input current, and ω: angular frequency of input power source.

  Considering that the inductance in the converter 8 is small and the power factor is approximately 1, it can be approximated as cosφ = 1. Therefore, the second term of Equation (1) is a constant term, and the first term is a pulsation term. That is, when the pulsation component of the electric power Pin is Pinr, this is expressed by Expression (2).

  On the other hand, it is considered that the pulsation of the DC voltage Vdc does not affect the load 11, and the expression (3) is established with the capacitance of the capacitor 72 as C.

  By substituting Equation (2) into Equation (3), the differential equation represented by Equation (4) is established with respect to the DC voltage Vdc.

  When the differential equation of Equation (4) is solved using the average value Vdcb of the DC voltage Vdc as an initial value, a solution represented by Equation (5) is obtained. However, since the second term in the square root of the upper formula is smaller than the first term, the lower formula is approximated (√ (1 + ε) = 1 + ε when ε is sufficiently smaller than 1) Similar to the approximation of / 2.

  The second term in the lower equation of equation (5) represents the pulsation component Vdcr. The product E · I does not depend on the DC voltage Vdc, and the capacitance C of the capacitor 72 does not fluctuate. Therefore, although the pulsation component Vdcr fluctuates at a frequency six times the power supply frequency, its amplitude | Vdcr | is inversely proportional to the average value Vdcb. I know that As described above, it can be seen that the above-mentioned tendency exists.

  In view of this tendency, when determining the presence or absence of oscillation of the DC voltage Vdc, and hence the stability of the power conversion device 5, the predetermined value Q becomes smaller as the average value Vdcb increases in order to avoid erroneous detection. Is set. FIG. 4 illustrates a case where the predetermined value Q decreases linearly with respect to the increase of the average value Vdcb. Of course, in view of Equation (5), the predetermined value Q may be inversely proportional to the average value Vdcb.

  Alternatively, as shown in FIG. 5, an upper limit value Q1 and a lower limit value Q2 may be set for the predetermined value Q. When the average value Vdcb is between the values B1 and B2 (> B1), the predetermined value Q is set smaller as the average value Vdcb increases between the upper limit value Q1 and the lower limit value Q2. When the average value Vdcb takes a value less than or equal to the value B1, the predetermined value Q takes the upper limit value Q1, and when the average value Vdcb takes a value greater than or equal to the value B2, the predetermined value Q takes the lower limit value Q2.

  In order to set the predetermined value Q in this way, it is desirable that the average value Vdcb is input to the predetermined value setter 14 as indicated by a broken line in FIG. The predetermined value setter 14 may have, for example, a table that associates the average value Vdcb with the predetermined value Q, and has an arithmetic function that calculates using a mathematical formula for obtaining the predetermined value Q as a function of the average value Vdcb. It may be.

  As described above, according to the second embodiment, although the operation of the power conversion device is stable, it is erroneously determined as unstable or the operation of the power conversion device is unstable. Nevertheless, the possibility of misjudging it as stable is reduced.

Third embodiment.
FIG. 6 illustrates the configuration of the power conversion apparatus according to the third embodiment. The power converter is modified with respect to the power converter 5 shown in the first embodiment in that an inductor 3 and a variable resistor 4 are provided in the DC link unit 7. The third embodiment is different from the first embodiment in that the stability determination signal J is not supplied to the inverter 1 but is used for controlling the variable resistor 4.

  More specifically, in DC bus 71, a parallel connection is interposed between converter 8 and inverter 1. The parallel connection body is a parallel connection of an inductor 3 and a variable resistor 4.

  The inductor 3 forms a low-pass filter together with the capacitor 72. The resistance value of the variable resistor 4 is reduced when it is determined that the operation of the power converter is unstable.

  Specifically, as described in the first embodiment and the second embodiment, the magnitude of the pulsation amplitude | Vdcr | is compared with a predetermined value Q, and the stability determination signal J is “ Take the value of L "/" H ". The variable resistor 4 receives the value of the stability determination signal J when the amplitude of the pulsation amplitude | Vdcr | is larger than the predetermined value Q (or “more than the predetermined value Q”), and the resistance value is decreased. .

  By reducing the resistance value of the variable resistor 4 in this way, the current flowing through the inductor 3 is reduced and the oscillation of the DC voltage Vdc is suppressed. That is, when it is determined that the operation of the power converter is unstable, the variable resistor 4 can be controlled to stabilize the power converter.

  At this time, the current flowing through the variable resistor 4 is small, and the influence on the direct current Vdc is small. Therefore, the control of the variable resistor 4 does not hinder the stability determination.

  Of course, the state of the stability determination signal J may be output to the outside to indicate an unstable (oscillation) state.

Fourth embodiment.
FIG. 7 illustrates the configuration of the power conversion device 5 according to the fourth embodiment. The power converter differs from the power converter 5 shown in the first embodiment in that the stability determination signal J is not supplied to the inverter 1 but is input to the command value correction circuit 2. .

  The command value correction circuit 2 is illustrated as the frequency command correction circuit 2 in FIG. The frequency command correction circuit 2 corrects the frequency command f * based on the stability determination signal J, and gives the corrected frequency command (hereinafter referred to as “revised frequency command”) f ** to the inverter 1.

  A torque command correction circuit may be employed as the frequency command correction circuit 2. In this case, the torque command correction circuit corrects the torque command T * based on the stability determination signal J, and gives the corrected torque command (hereinafter, “revised torque command”) T ** to the inverter 1.

  Although not described in the first to third embodiments, the inverter 1 normally receives a frequency command f * or a torque command T * and operates based on these command values. The electric power output from the inverter 1 depends on these command values.

  For example, when the rotational frequency f of the AC rotating machine 11 (the command value of which is the frequency command f *), the output torque T (the command value of which is the torque command T *), and the pole pair number Pm are introduced, the electric power W becomes It is expressed by 2π · f · T / Pm (π: pi). That is, as these command values are larger, the power output from the inverter 1, that is, the power supplied to the AC rotating machine 11 as a load is larger. As described in (e) above, the larger the output of the AC rotating machine 11, the more likely the operation of the power converter 5 becomes unstable.

  Then, when it determines with operation | movement of the power converter device 5 being unstable, operation | movement is guide | induced to stability by reducing the electric power output from the inverter 1. FIG. In order to reduce the electric power, specifically, an inverter is used by using a command value, here, a revised frequency command f ** or a revised torque command T ** obtained by correcting the frequency command f * or the torque command T * to be small. Give to 1.

  Naturally, the power output from the inverter 1 is proportional to the current and voltage output from the inverter 1. The inverter 1 operates based on the command value of the current or the command value of the voltage. Therefore, the electric power depends on the command value I * of the current output from the inverter 1. Alternatively, the electric power depends on the command value V * of the voltage output from the inverter 1.

  Therefore, a current command correction circuit can be adopted as the frequency command correction circuit 2. In this case, the current command correction circuit corrects the current command I * based on the stability determination signal J, and gives the corrected current command (hereinafter referred to as “reformed current command”) I ** to the inverter 1.

  Alternatively, a voltage command correction circuit can be adopted as the frequency command correction circuit 2. In this case, the voltage command correction circuit corrects the voltage command V * based on the stability determination signal J, and gives the corrected voltage command (hereinafter referred to as “revision voltage command”) V ** to the inverter 1.

  In the fourth to sixth embodiments, the case where the command value correction circuit 2 is the frequency command correction circuit 2 will be described. However, a torque command correction circuit, a current command correction circuit, and a voltage command correction circuit may be employed as the command value correction circuit 2 from the above-described viewpoint regarding power.

  FIG. 8 is a circuit diagram illustrating the configuration of the frequency command correction circuit 2 according to the fourth embodiment. The frequency command correction circuit 2 includes a correction request circuit 21 and a command reduction circuit 22.

  The correction request circuit 21 receives the stability determination signal J and outputs a correction request signal K0. The command reduction circuit 22 inputs the frequency command f * and the correction request signal K0 and outputs the revised frequency command f **.

  The correction request circuit 21 includes an integrator 210 and a comparator 211. The integrator 210 integrates the stability determination signal J with a predetermined time constant and outputs an integration signal SJ. As described above, the stability determination signal J is “H” when it is determined that the operation of the power conversion device 5 is unstable. Therefore, the integration signal SJ is a period during which the stability determination signal J is “H”. Increases with length. For example, if it is grasped that the stability determination signal J is activated when the operation of the power converter 5 is unstable, the integration signal SJ corresponds to the length of the period during which the stability determination signal J is activated. It can be grasped that it increases.

  The comparator 211 activates the correction request signal K0 when the integration signal SJ exceeds the threshold value TH0.

  The command reduction circuit 22 includes a multiplier 220 and a changeover switch 221. The multiplier 220 multiplies the frequency command f * by a value larger than 0 and smaller than 1, for example, a value (1/2) and outputs the result.

  The changeover switch 221 has a contact A, a contact B, and a common contact C. The frequency command f * is given to the contact A, and the output of the multiplier 220 is given to the contact B. If the symbol f * is adopted as the value of the frequency command f *, the value given to the contact A is f * / 2.

  The common contact C is connected to the contact B / contact A corresponding to activation / inactivation of the correction request signal K0. Then, the revised frequency command f ** is taken out from the common contact C.

  FIG. 9 is a waveform diagram illustrating the operation of the frequency command correction circuit 2 according to the fourth embodiment. 4A shows the stability determination signal J, FIG. 2B shows the integration signal SJ, FIG. 2C shows the correction request signal K0, and FIG. 2D shows the counterpart connected to the common contact C. FIG. 5E shows the frequency change command f **. However, in FIG. 5C, the activation / inactivation of the correction request signal K0 is indicated by an integer value 1/0. Further, in FIG. 6D, the fact that the other party connected to the common contact C is the contact A is indicated by a smaller value than the case where the other party is the contact B.

  In the illustration of FIG. 9, it is determined that the operation of the power conversion device 5 is stable before time t11, and the stability determination signal J is “L” (inactive). Here, it is assumed that at time t11, the operation of the power converter 5 continues to be stable for a time sufficiently longer than the time constant for the integration of the integrator 210, and the integration signal SJ takes the value 0. . Therefore, the correction request signal K0 is inactive (value 0), the common contact C is connected to the contact A, and the revised frequency command f ** takes a value f * equal to the frequency command f *.

  When the operation of the power conversion device 5 is determined to be unstable at time t11 and the stability determination signal J becomes “H” (active), the integration signal SJ increases. Even if the integration signal SJ reaches the threshold value TH0 at time t12, if the stability determination signal J remains “H”, the integration signal SJ exceeds the threshold value TH0, and the correction request signal K0 becomes active (value 1). The common contact C is connected to the contact B, and the revised frequency command f ** takes the value f ** / 2.

  When the revised frequency command f ** is thus reduced, the power output from the inverter 1 is reduced, and the operation of the power converter 5 is led to stabilization. By reducing the command value in this way, it is possible to reduce the power and thereby stabilize the operation of the power conversion device 5.

  As a result, the operation of the power conversion device 5 is determined to be stable at time t13, the stability determination signal J becomes “L” (inactive), and the integral signal SJ decreases.

  When the integration signal SJ falls below the threshold value TH0 at time t14, the correction request signal K0 is deactivated, the common contact C is connected to the contact A, and the revised frequency command f ** takes the value f *. As a result, the operation of the power converter 5 operates again based on the original frequency command f *.

  Of course, the operation of the power converter 5 becomes unstable again by maintaining the command value once lowered due to the unstable operation of the power converter 5 even after the operation of the power converter 5 is stabilized. Can also be prevented. Such processing is easily realized by increasing the time constant of the integrator 210.

Fifth embodiment.
FIG. 10 is a circuit diagram illustrating the configuration of the frequency command correction circuit 2 according to the fifth embodiment. The frequency command correction circuit 2 includes a correction request circuit 26 and a command reduction circuit 25.

  The correction request circuit 26 receives the stability determination signal J and outputs correction request signals K1, K2, K3, and K4. The command reduction circuit 25 inputs the frequency command f * and the correction request signals K1, K2, K3, and K4 and outputs the revised frequency command f **.

  The correction request circuit 26 includes an integrator 260 and comparators 261, 262, 263, and 264. The integrator 260 integrates the stability determination signal J with a predetermined time constant in the same manner as the integrator 210 (see the fourth embodiment), and outputs an integrated signal SJ.

  The comparator 261 activates the correction request signal K1 when the integration signal SJ exceeds the threshold value TH1. The comparator 262 activates the correction request signal K2 when the integration signal SJ exceeds the threshold value TH2. The comparator 263 activates the correction request signal K3 when the integration signal SJ exceeds the threshold value TH3. The comparator 264 activates the correction request signal K4 when the integration signal SJ exceeds the threshold value TH4.

  However, the threshold value TH2 is larger than the threshold value TH1, the threshold value TH3 is larger than the threshold value TH2, and the threshold value TH4 is larger than the threshold value TH3. Therefore, the correction request signals K1, K2, K3 are always activated when the correction request signal K4 is activated, and the correction request signals K1, K2 are always activated when the correction request signal K3 is activated. When K2 is activated, the correction request signal K1 is always activated.

  The command reduction circuit 25 includes multipliers 255, 256, 257 and changeover switches 251, 252, 253, 254. Multipliers 255, 256, and 257 multiply the respective inputs by a value larger than 0 and smaller than 1, for example, all multiplied by a value (1/2) and output.

  The multiplier 255 is given a frequency command f * taking the value f * and outputs the value f * / 2. Multiplier 256 is supplied with the output of multiplier 255 and outputs the value f * / 4. Multiplier 257 is given the output of multiplier 256 and outputs the value f * / 8.

  Each of the changeover switches 251, 252, 253, and 254 has a contact A, a contact B, and a common contact C.

  In the changeover switch 251, the frequency command f * is given to the contact A, and the output from the common contact C of the changeover switch 252 is given to the contact B. In the changeover switch 252, the output from the multiplier 255 is given to the contact A, and the output from the common contact C of the changeover switch 253 is given to the contact B, respectively. In the changeover switch 253, the output of the multiplier 256 is given to the contact A, and the output from the common contact C of the changeover switch 254 is given to the contact B, respectively. In the changeover switch 254, the output of the multiplier 257 is given to the contact A. The contact B is given a value smaller than the output of the multiplier 257, here a value 0 smaller than the value f * / 8.

  In the changeover switch 251, the common contact C is connected to the contact B / contact A in response to the activation / inactivation of the correction request signal K1. In the changeover switch 252, the common contact C is connected to the contact B / contact A in response to the activation / deactivation of the correction request signal K2. In the changeover switch 253, the common contact C is connected to the contact B / contact A in response to the activation / inactivation of the correction request signal K3. In the changeover switch 254, the common contact C is connected to the contact B / contact A in response to activation / deactivation of the correction request signal K4.

  Since the activation / inactivity of the correction request signals K1, K2, K3, and K4 has the above-described relationship, the revised frequency command f ** takes values classified as follows: correction request signals K1, K2, and so on. Value f * when all of K3 and K4 are inactive; value f * / 2 when only correction request signal K1 is active; value f * / 4 when only correction request signals K1 and K2 are active; correction request signal K1 , K2, K3 only when the value is f * / 8; when the correction request signals K1, K2, K3, K4 are all active, the value is 0.

  11 and 12 are waveform diagrams illustrating the operation of the frequency command correction circuit 2 according to the fifth embodiment. However, in the case illustrated in FIG. 11, the instability of the operation of the power conversion device 5 is more remarkable than in the case illustrated in FIG. 12.

  11 and 12, (a) shows the stability determination signal J, (b) shows the integration signal SJ, and (c), (d), (e), and (f) show the correction request signals K1, respectively. K2, K3, and K4, and (g) indicate the frequency change command f **. However, in (c) to (f), the activation / deactivation of the modification request signals K1, K2, K3, and K4 is indicated by an integer value 1/0, respectively.

  In the illustration of FIG. 11, it is determined that the operation of the power converter 5 is stable before time t21, and the stability determination signal J is “L”. Here, it is assumed that at time t21, the operation of the power converter 5 continues to be stable for a time sufficiently longer than the time constant for the integration of the integrator 260, and the integration signal SJ takes the value 0. . Therefore, the correction request signals K1, K2, K3, and K4 are inactive, and the revised frequency command f ** takes a value f * that is equal to the frequency command f *.

  When the operation of the power converter 5 is determined to be unstable at time t21 and the stability determination signal J becomes “H”, the integral signal SJ increases. At time t22, the integration signal SJ reaches the threshold value TH1, the correction request signal K1 is activated, and the revised frequency command f ** takes the value f * / 2.

  Further, after time t22, the stability determination signal J remains “H” and the integration signal SJ continues to rise. At time t23, the integration signal SJ reaches the threshold value TH2, the correction request signal K2 is also activated, and the frequency change command f ** takes the value f * / 4.

  Further, after time t23, the stability determination signal J remains “H” and the integration signal SJ continues to rise. At time t24, the integration signal SJ reaches the threshold value TH3, the correction request signal K3 is also activated, and the frequency change command f ** takes the value f * / 8.

  Further, after time t24, the stability determination signal J remains “H” and the integration signal SJ continues to rise. At time t25, the integration signal SJ reaches the threshold value TH4, the correction request signal K4 is also activated, and the frequency change command f ** takes the value 0.

  If the frequency change command f ** takes a value of 0, if the loss of the AC rotating machine 11 is ignored, the power output from the inverter 1 is 0, so the operation of the power converter 5 is stabilized. Therefore, after time t25, the stability determination signal J becomes inactive, and the integral signal SJ decreases.

  In the illustration of FIG. 12, it is determined that the operation of the power conversion device 5 is stable before time t31, and the integral signal SJ takes a value of 0. Therefore, the correction request signals K1, K2, K3, and K4 are inactive, and the revised frequency command f ** takes a value f * that is equal to the frequency command f *.

  When the operation of the power conversion device 5 is determined to be unstable at time t31 and the stability determination signal J becomes “H”, the integral signal SJ increases. At time t32, the integration signal SJ reaches the threshold value TH1, the correction request signal K1 is activated, and the revised frequency command f ** takes the value f * / 2.

  Further, after time t32, the stability determination signal J remains “H” and the integration signal SJ continues to rise. At time t33, the integration signal SJ reaches the threshold value TH2, the correction request signal K2 is also activated, and the frequency change command f ** takes the value f * / 4.

  Thereafter, even after time t33, the stability determination signal J maintains “H” and the integration signal SJ continues to rise, but does not reach the threshold value TH3. At time t34, the stability determination signal J takes “L” and integration. The signal SJ decreases.

  At time t34, the integration signal SJ falls below the threshold value TH2, the correction request signal K2 is also deactivated, and the revised frequency command f ** takes the value f * / 2.

  Further, at time t35, the stability determination signal J remains “L” and the integrated signal SJ continues to decrease. At time t36, the integrated signal SJ falls below the threshold value TH1, the correction request signal K1 becomes inactive, and the frequency change command f ** takes the value f *.

  In this way, by providing a plurality of threshold values to be compared with the integration signal SJ and setting the value taken by the revised frequency command f ** corresponding to the interval between the threshold values, the command value is not unnecessarily lowered, The operation of the power conversion device 5 can be led stably.

  Of course, for example, as shown in FIG. 12, even if the operation of the power converter 5 is stabilized by taking the value f ** / 4 of the revised frequency command f **, the revised frequency is different from the case shown in FIG. When the command f ** takes the value f * / 2, the operation of the power converter 5 may become unstable again. In this case, the revised frequency command f ** may alternately take values f * / 2 and f * / 4.

  However, as explained in the fourth embodiment, by maintaining the command value once decreased due to the unstable operation of the power converter 5, even after the operation of the power converter 5 is stabilized, It is also possible to prevent the operation of the power converter 5 from becoming unstable again.

Sixth embodiment.
FIG. 13 is a circuit diagram illustrating the configuration of the frequency command correction circuit 2 according to the sixth embodiment. The frequency command correction circuit 2 includes an integrator 23 and a subtracter 24.

  The integrator 23 inputs the stability determination signal J and outputs an integration signal SJ. The subtracter 23 inputs the frequency command f * and the integration signal SJ and outputs the revised frequency command f **. That is, in the sixth embodiment, the integral signal SJ that increases according to the length of the period in which the operation of the power conversion device 5 is determined to be unstable (that is, the stability determination signal J is activated) It will be subtracted from the command value on which the power depends.

  Such subtraction is different from stepwise switching of the revised frequency command f ** as shown in the fourth embodiment or the fifth embodiment. That is, since the revised frequency command f ** can be obtained with a reduction amount necessary for the operation of the power converter 5 to be stable, the revised frequency command f ** is not excessively lowered.

  14 and 15 are waveform diagrams illustrating the operation of the frequency command correction circuit 2 according to the sixth embodiment. However, in the case illustrated in FIG. 15, the instability of the operation of the power conversion device 5 is more remarkable than in the case illustrated in FIG. 14.

  14 and 15, (a) shows the stability determination signal J, (b) shows the integration signal SJ, and (c) shows the revised frequency command f **.

  In the example of FIG. 14, it is determined that the operation of the power conversion device 5 is stable before time t41, and the stability determination signal J is “L”. Here, it is assumed that at time t41, the operation of the power converter 5 continues to be stable for a time sufficiently longer than the time constant for the integration of the integrator 23, and the integration signal SJ takes the value 0. . Therefore, the revised frequency command f ** takes a value f * equal to the frequency command f *.

  When the operation of the power conversion device 5 is determined to be unstable at time t41 and the stability determination signal J becomes “H”, the integral signal SJ increases. Along with this, the revised frequency command f ** decreases.

  As the revised frequency command f ** decreases, the operation of the power conversion device 5 is led to stability, and it is determined that the operation of the power conversion device 5 is stable at time t42. As a result, the stability determination signal J becomes “L” and the integral signal SJ decreases. Along with this, the revised frequency command f ** increases. Thereafter, when it is determined that the operation of the power conversion device 5 is unstable again, the revised frequency command f ** decreases.

  With the above operation, the revised frequency command f ** is set to such a large extent that the operation of the power converter 5 can be stabilized.

  In the example of FIG. 15, it is determined that the operation of the power conversion device 5 is stable before time t51, and the stability determination signal J is “L”. Here, it is assumed that at time t51, the operation of the power converter 5 continues to be stable for a time sufficiently longer than the time constant for the integration of the integrator 23, and the integration signal SJ takes the value 0. . Therefore, the revised frequency command f ** takes a value f * equal to the frequency command f *.

  Then, when it is determined that the operation of the power conversion device 5 is unstable at time t51 and the stability determination signal J becomes “H”, the integral signal SJ increases. Along with this, the revised frequency command f ** decreases.

  Further, the stability determination signal J is maintained at “H”, and the integration signal SJ continues to rise, and the revised frequency command f ** takes the value 0 at time t52.

  If the frequency change command f ** takes a value of 0, if the copper loss of the AC rotating machine 11 is ignored, the power output from the inverter 1 is 0, so the operation of the power converter 5 is stabilized. Therefore, after time t52, the stability determination signal J becomes inactive, the integral signal SJ decreases, and the revised frequency command f ** increases.

<Deformation>
In the fourth embodiment and the fifth embodiment, it has been exemplified that the decrease in the revised frequency command f ** is halved, but it may be decreased at a reduction rate other than this. That is, the multipliers 250, 255, 256, and 257 can employ values other than the value (1/2) and larger than 0 and smaller than 1. Further, the thresholds TH1 to TH4 can be set appropriately as long as the magnitude relationship between them is not impaired.

  In the fifth embodiment and the sixth embodiment, it may be notified that the revised frequency command f ** is zero. This is because it is often difficult to drive the load 11 appropriately in such a situation.

  In the sixth embodiment, the amount of decrease in the revised frequency command f ** is proportional to the integrated signal SJ. However, if both are in a positive correlation, that is, the revised frequency command f ** and the integrated signal SJ are There should be a negative correlation between the two. For example, the subtractor 24 may add a positive weight to the integration signal SJ and subtract it from the frequency command f *.

  Also for the above-described modification, as in the fourth to sixth embodiments, the revised torque command T **, the revised current command I **, and the revised voltage command V ** can be used instead of the revised frequency command f **. .

  The operation of the stability determination circuit 6 can be grasped as a stability determination method. The power converter 5 described above is clearly different from the conventional technique in that such a stability determination method is adopted.

  Alternatively, the converter 8, the inverter 1, the DC buses 70 and 71, the capacitor 72, and the stability determination circuit 6 can be grasped as a power converter. The correction circuit 2 can also be grasped as a power conversion device for such a configuration.

DESCRIPTION OF SYMBOLS 1 Inverter 2 Frequency command (or torque command, current command, voltage command) correction circuit 3 Inductor 4 Variable resistance 5 Power converter 6 Stability determination circuit 12 Average value acquisition circuit 13 Subtractor 15 Absolute value acquisition circuit 16 Comparator 70, 71 DC bus 72 Capacitor I * Current command I ** Revised current command f * Frequency command f ** Revised frequency command J Stability judgment signal SJ Integral signal TH0, TH1, TH2, TH3, TH4 Threshold value T * Torque command T ** Revised Torque command Q Predetermined value Vdc DC voltage Vdcb (DC voltage) average value Vdcr (DC voltage) pulsation V * Voltage command V ** Revised voltage command

Claims (6)

A converter (8), an inverter (1), a pair of DC buses (70, 71) connecting the converter and the inverter, and a capacitor (72) connected between the pair of DC buses. A method for determining operational stability in a power converter (5), comprising:
If the amplitude (| Vdcr |) of the pulsation (Vdcr) of the DC voltage (Vdc) between the pair of DC buses exceeds a predetermined value (Q), the operation of the power converter is unstable. Judgment,
When it is determined that the operation of the power converter is unstable, the power output from the inverter is reduced,
A signal (SJ) that increases corresponding to the length of the period during which the operation of the power converter is determined to be unstable is changed to a command value (f *, T *, I *, V * on which the power depends. Stability judgment method subtracted from A converter (8), an inverter (1), a pair of DC buses (70, 71) connecting the converter and the inverter, and a capacitor (72) connected between the pair of DC buses. A method for determining operational stability in a power converter (5), comprising:
If the amplitude (| Vdcr |) of the pulsation (Vdcr) of the DC voltage (Vdc) between the pair of DC buses exceeds a predetermined value (Q), the operation of the power converter is unstable. Judgment,
When it is determined that the operation of the power converter is unstable, the power output from the inverter is reduced,
Corresponding to the signal (SJ) increasing corresponding to the length of the period during which the operation of the power converter is determined to be unstable exceeds a predetermined threshold (TH0, TH1, TH2, TH3, TH4). A stability determination method for reducing the power.   The stability determination method according to claim 1 or 2, wherein the predetermined value (Q) is set to a value that does not increase with respect to an increase in the average value (Vdcb) of the DC voltage (Vdc). A converter (8);
An inverter (1);
A pair of DC buses (70, 71) connecting the converter and the inverter;
A capacitor (72) connected between the pair of DC buses;
A stability determination circuit (6);
A correction circuit (2),
The stability determination circuit includes:
An average value acquisition circuit (12) for obtaining an average value (Vdcb) of a DC voltage between the pair of DC buses;
A subtractor (13) for subtracting the average value from the DC voltage to obtain a pulsation (Vdcr) of the DC voltage;
An absolute value acquisition circuit (15) for obtaining an amplitude (| Vdcr |) of the pulsation;
A predetermined value setter (14) for setting the predetermined value (Q),
When the amplitude is larger than the predetermined value, the correction circuit (2) corrects the command value (f *, T *, I *, V *) on which the power output from the inverter depends to be small, so that the inverter output to the predetermined value (Q) is Ru is set to the non-increase value serving relative increase of the average value (Vdcb), power converter. A converter (8);
An inverter (1);
A pair of DC buses (70, 71) connecting the converter and the inverter;
A capacitor (72) connected between the pair of DC buses;
A stability determination circuit (6);
Correction circuit (2)
With
The stability determination circuit includes:
An average value acquisition circuit (12) for obtaining an average value (Vdcb) of a DC voltage between the pair of DC buses;
A subtractor (13) for subtracting the average value from the DC voltage to obtain a pulsation (Vdcr) of the DC voltage;
An absolute value acquisition circuit (15) for obtaining an amplitude (| Vdcr |) of the pulsation;
A predetermined value setter (14) for setting a predetermined value (Q);
Have
When the amplitude is larger than the predetermined value, the correction circuit (2) corrects the command value (f *, T *, I *, V *) on which the power output from the inverter depends to be small, so that the inverter Output to
In response to the signal (SJ) increasing corresponding to the length of the period in which the amplitude is greater than the predetermined value exceeding a predetermined threshold (TH0, TH1, TH2, TH3, TH4), the command value ( f *, T *, I *, V *) is corrected to be small . A converter (8);
An inverter (1);
A pair of DC buses (70, 71) connecting the converter and the inverter;
A capacitor (72) connected between the pair of DC buses;
A stability determination circuit (6);
Correction circuit (2)
With
The stability determination circuit includes:
An average value acquisition circuit (12) for obtaining an average value (Vdcb) of a DC voltage between the pair of DC buses;
A subtractor (13) for subtracting the average value from the DC voltage to obtain a pulsation (Vdcr) of the DC voltage;
An absolute value acquisition circuit (15) for obtaining an amplitude (| Vdcr |) of the pulsation;
A predetermined value setter (14) for setting a predetermined value (Q);
Have
When the amplitude is larger than the predetermined value, the correction circuit (2) corrects the command value (f *, T *, I *, V *) on which the power output from the inverter depends to be small, so that the inverter Output to
The power converter which subtracts the signal (SJ) which increases according to the length of the period when the amplitude is larger than the predetermined value from the command value (f *, T *, I *, V *) .

Images