JP5476435B2 - Drive circuit, driver IC chip, drive device, print head, image forming apparatus, display device, and control method - Google Patents

Description

The present invention selectively and cycles a group of driven elements, for example, a light emitting element array such as an LED (light emitting diode) array in an electrophotographic printer, a row of heating resistors in a thermal printer, a row of display elements in a display device, and the like. The present invention relates to a driving circuit, a driver IC chip, and a driving apparatus including the driver IC chip.
The present invention also relates to a print head provided with a driving device for driving a row of LED arrays and heating resistors used in an electrophotographic process.
The present invention further relates to an image forming apparatus provided with a print head.
The invention further relates to a display device comprising a drive device.
The invention further relates to a method for controlling a drive circuit.

  In an image forming apparatus such as a printer using an electrophotographic process, a plurality of light emitting elements such as an LED array are linearly arranged as an exposure device, and a light emitting element array head that selectively emits light to form an image; There is what is called.

  In the light emitting element array head, blinking data (driving data) of the light emitting elements is stored in advance for one column using a shift register, and then switching elements composed of transistors corresponding to each of the light emitting elements are turned on / off. (For example, refer to Patent Document 1).

Hereinafter, an electrophotographic printer including a print head formed using an LED array will be described, and problems of the related art will be described.
In the following description, the light emitting diode may be abbreviated as LED, the monolithic integrated circuit as IC, the N channel MOS transistor as NMOS, and the P channel MOS transistor as PMOS. Furthermore, the MOS transistor may be simply abbreviated as “MOS” without being aware of the channel type.

Further, the signal level High (“high” level) may be described in association with the logical value “1”, and Low (“low” level) in association with the logical value “0”.
Furthermore, when it is necessary to clarify the logic of a signal, “−P” is added to the end of the code representing the signal to indicate that it is a positive logic signal, and “−N” is added to the end of the code representing the signal. To indicate a negative logic signal. Further, as a symbol representing a signal, the same symbol as that of a terminal to which a signal is input or output or an element or a circuit from which a signal is output may be used.

  In a conventional electrophotographic printer, an electrostatic latent image is formed by selectively irradiating light to a charged photosensitive drum according to printing information, and toner is attached to the electrostatic latent image and development is performed. An image is formed, and the toner image is transferred to a sheet and fixed.

FIG. 1 is a block diagram of a printer control circuit in a conventional electrophotographic printer.
In FIG. 1, reference numeral 1 denotes a print control unit which includes a microprocessor, a ROM, a RAM, an input / output port, a timer, and the like.
The printing control unit 1 is arranged inside the printing unit of the printer, and the entire printer is sequenced by a control signal SG1 from a host controller (not shown), a video signal (one-dimensional arrangement of dot map data) SG2, and the like. Control and perform printing operations.

  When the print instruction is received by the control signal SG1, the print controller 1 first detects whether or not the fixing device 22 including the heater 22a is within the usable temperature range by the fixing device temperature sensor 23, and the temperature range. If not, the heater 22a is energized to heat the fixing device 22 to a usable temperature. Next, the development / transfer process motor (PM) 3 is rotated via the driver 2, and at the same time, the charging voltage power supply 25 is turned on by the charging signal SGC to charge the developing device 27.

  The presence / absence of a sheet (not shown) (whether a sheet is set in a sheet feeding unit (not shown)) and the type thereof are detected by the sheet remaining amount sensor 8 and the sheet size sensor 9, and sheet feeding suitable for the sheet is started. Here, the paper feed motor (PM) 5 can be rotated in both directions via the driver 4, and the paper that has been set is preset until it is first reversed and detected by the paper suction sensor 6. The sheet can be fed by the amount and then rotated forward to transport the paper into the printing mechanism inside the printer.

  When the paper reaches a printable position, the print control unit 1 transmits a timing signal SG3 (including a main scanning synchronization signal and a sub scanning synchronization signal) to the host controller and receives a video signal SG2. The video signal SG2 edited for each page in the upper controller and received by the print control unit 1 is transferred to the LED head 19 as print data signals HD-DATA3 to HD-DATA0. The LED head 19 has a plurality of LEDs arranged for printing one dot (pixel), and is used as a print head.

When the print control unit 1 receives the video signal SG2 for one line, the print control unit 1 transmits a latch signal HD-LOAD to the LED head 19 (HD-LOAD is set to High), and sends the print data signal HD-DATA to the LED head 19. To hold. In addition, the print control unit 1 performs printing based on the print data signals HD-DATA3 to HD-DATA0 held in the LED head 19 even during reception of the next video signal SG2 from the host controller (drive LED). can do.
HD-CLK-P and HD-CLK-N are clock signals for transmitting the print data signals HD-DATA3 to HD-DATA0 to the LED head 19, and small-amplitude differential signals are used. Note that the differential signals HD-CLK-P and HD-CLK-N may be simply referred to as HD-CLK unless there is a particular need for distinction.
HD-HSYNC-N is a main scanning synchronization signal, and HD-STB-N is a strobe signal.

Transmission / reception of the video signal SG2 is performed for each print line. Information printed by the LED head 19 is formed into a latent image as a dot with an increased potential on a photosensitive drum (not shown) charged to a negative potential. Then, in the developing device 27, the toner for image formation charged to a negative potential is attracted to each dot by an electrical attraction force to form a toner image.
Thereafter, the toner image is sent to the transfer unit 28, while the transfer signal SG4 turns on the high-voltage power supply 26 for positive transfer, and the transfer unit 28 passes through the interval between the photosensitive drum and the transfer unit 28. Transfer the toner image on top.

  The sheet having the transferred toner image is conveyed in contact with a fixing device 22 having a built-in heater 22a, and is fixed on the sheet by the heat of the fixing device 22. The sheet having the fixed image is further conveyed and passed through the sheet discharge sensor 7 from the printing mechanism of the printer, and the print is discharged to the outside.

In response to detection by the paper size sensor 9 and the paper suction sensor 6, the print control unit 1 applies a voltage from the transfer high-voltage power supply 26 to the transfer device 28 only while the paper passes through the transfer device 28. When printing is completed and the paper passes through the paper discharge sensor 7, the application of voltage to the developing device 27 by the charging high-voltage power supply 25 is finished, and at the same time, the rotation of the development and transfer process motor 3 is stopped.
Thereafter, the above operation is repeated.

  Next, the LED head 19 will be described. FIG. 2 is a diagram showing the structure of a conventional general LED head. In the description of the conventional example and the embodiments described later, an LED head capable of printing at a resolution of 600 dots per inch on an A4 size sheet is assumed as an example. In this case, the total number of LED elements is 4992 dots, and for example, 26 LED array chips each having 192 LED elements are arranged linearly.

However, in FIG. 2, only two LED array chips CHP1 and CHP2 and two driver IC chips DIC1 and DIC2 arranged corresponding to these are shown for simplification of illustration. In other words, the third to 26th LED array chips CHP3 to CHP26 and the third to 26th driver IC chips DIC3 to DIC26 are not shown. The LED array chips CHP1 to CHP26 are configured by the same circuit, and the driver IC chips DIC1 to DIC26 are configured by the same circuit and are cascade-connected to each other.
In the following description, the reference DIC may be used in descriptions that apply to all driver IC chips. Similarly, in the description that applies to all LED array chips, the symbol CHP may be used.

101-108 are LED elements, and 192 are arranged for each LED array chip.
The drain of the power MOS 109 constituting the first common switch is connected to the cathodes of the LEDs 101, 103, 105, 107, etc., and the drain of the power MOS 110 constituting the second common switch is the cathode of the LEDs 102, 104, 106, 108, etc. Connected with. The sources of the power MOSs 109 and 110 are connected to the ground.

  Thus, the odd-numbered LED elements 101,... 103, 105,... 107 in each LED array CHP1, CHP2 are connected to each other, that is, all connected to the common cathode node CCo. The power MOS 109 is connected to the ground GND. On the other hand, the cathodes of the even-numbered LED elements 102,... 104, 106,... 108 are connected to each other, that is, all are connected to the common cathode node CCe. By turning on the power MOS 109 and the power MOS 110 at different timings, the odd-numbered LED elements 101, ... 103, 105, ... 107 and the even-numbered LED elements 102, ... 104, 106, ... 108 are time-shared. Driven.

The power MOS 109 has a gate connected to the common switch control signal output terminal KDR of the first stage driver IC chip DIC1, and is supplied from the common switch control signal output terminal KDR of the first stage driver IC chip DIC1. Controlled by signal KDR1.
The power MOS 110 has its gate connected to the common switch control signal output terminal KDR of the second stage driver IC chip DIC2, and the control signal KDR2 supplied from the common switch control signal output terminal KDR of the second stage driver IC chip DIC2. Controlled by

  In the configuration shown in FIG. 2, four (four) print data signals HD-DATA 3 to 0 are input and used to drive each LED element. The odd-numbered LED elements and the even-numbered LED elements are driven in a time division manner. Therefore, among the eight adjacent LED elements, the data for four odd-numbered or even-numbered pixels can be simultaneously transmitted for each clock signal HD-CLK.

  For this reason, the print data signals HD-DATA 3 to 0 output from the print control unit 1 are input to the LED head 19 together with the clock signal HD-CLK, and each driver IC chip DIC1 and DIC2 described later with reference to FIG. The dot data for 4992 dots is sequentially transferred through the four shift registers provided in parallel with each other. In this sequential transfer, for example, dot data of all odd-numbered dots (2496 dots) is transferred first, and then dot data of all even-numbered dots (2496 dots) are transferred.

When the transfer of dot data of all odd-numbered dots is completed, the latch signal HD-LOAD is input to the LED head 19 (HD-LOAD is set to High), and these dot data are stored in a plurality of stages constituting the shift register. Latches are respectively latched by latch elements provided corresponding to the flip-flops.
When the transfer of dot data of all even-numbered dots is completed, the latch signal HD-LOAD is input to the LED head 19 (HD-LOAD is set to High), and these dot data are stored in a plurality of stages constituting the shift register. Latches are respectively latched by latch elements provided corresponding to the flip-flops.
When the dot data latches for all the odd-numbered dots and the dot-data latches for all the even-numbered dots are finished, the data for all the dots are aligned (when latched), the dot data and the print drive signal HD By -STB-N, among the light emitting elements (LEDs in this example), those corresponding to dot data at a high (high) level are turned on. Note that VDD is a power supply, and GND is a ground (ground potential node).

  HD-HSYNC-N is the above-described main scanning synchronization signal, and a period from when this main scanning synchronization signal HD-HSYNC-N is generated once to when it is generated next can be called a main scanning period. In one main scanning period, 1-bit print data, that is, 26 × 24 × 4 × 2 (= 4996) bits in total is transferred to each of all LED elements. For example, 26 × 24 × 4 (= 2496) -bit print data for odd-numbered dots is transferred in the first half of each main scanning period, and 26 × 24 × 4 (= 2496) for even-numbered dots in the second half. ) Bit print data is transferred.

  VREF is a reference voltage for instructing a driving current value for LED driving, and is generated by a reference voltage generating circuit (not shown) provided in the LED head 19.

  Prior to execution of printing as described above (transfer of print data and LED driving based on print data), correction data is transferred using the same shift register used for transfer of print data and stored in the memory. When the LED is driven based on the print data, the drive current value is corrected based on the correction data.

FIG. 3 is a block diagram showing a detailed configuration of the driver IC chip shown in FIG.
FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are flip-flops, and constitute four mutually parallel shift registers SFRa, SFRb, SFRc, and SFRd.
LTA1 to LTD1,... LTA24 to LTD24 are latch elements, and constitute a latch circuit as a whole.

  MEM is a memory circuit (the same sign is assigned to (24 × 4) memory circuits), and the memory circuit MEM has correction data (dot correction data) for correcting the variation in the amount of light of the LEDs. Stored. The correction data for each dot stored in the memory circuit MEM is read out at the time of printing and used for correcting the LED drive current.

  Each of the memory circuits MEM stores correction data of odd-numbered and even-numbered LEDs (dots) adjacent to each other, and can be read from two sets of data output terminals Mo and Me.

  The MCM is a memory circuit that stores light amount correction data (chip correction data) for each LED array chip or correction data Hc for each driver IC chip, and can be read from the data output terminal Mc.

  The MOE is also a memory circuit, and the memory circuit MOE stores data (common switch control data) Hk for determining the value of the common switch control signal KDR output from the common switch control signal output terminal KDR of the driver IC chip. Is done. Data Hk stored in the memory circuit MOE is read at the time of printing (when the LED is driven based on the print data) and used to generate the common switch control signal KDR.

  The (24 × 4) memory circuits MEM receive outputs from the Q terminals (data output terminals) of the flip-flops FFA1 to FFA24, FFB1 to FFB24, FFC1 to FFC24, and FFD1 to FFD24, respectively, while the memory circuit MCM is a flip-flop The memory circuit MOE receives the output from the Q terminal of the flip-flop FFC25.

  MUX is a multiplexer circuit (the same sign is assigned to (24 × 4) multiplexer circuits), each of which is read from two sets of output terminals Mo and Me of the corresponding memory circuit MEM. Two sets of correction data (that is, correction data Ho for odd-numbered dots and correction data He for even-numbered dots) are received by two sets of input terminals Xo and Xe, and one of them is selected. Output from the output terminal XQ.

  DRV is an LED drive unit, and the latch elements LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, LTD1 to LTD24 (with the same reference numerals attached to (24 × 4) LED drive units) Based on the blinking data from the corresponding one and the correction data supplied from the corresponding multiplexer circuit MUX, the LED driving current is output.

CTR1 is a first control circuit, and generates write command signals (memory cell selection signals W0 to W3 and enable signals E1 and E2) when correction data is written to the memory circuit MEM and the memory circuit MCM. As will be described later, the enable signal E2 is used to control the selection circuit SEL, but is also used to control memory writing, and is therefore referred to as an “enable signal” for convenience. The first control circuit CTR1 is also called a memory control circuit.
Writing of the common switch control data to the memory circuit MOE is controlled by any one of the memory cell selection signals W0 to W3, for example, W3.
CTR2 is a second control circuit, which is a data selection signal (switching command signal) S1P, S1N, S2P, S2N of data for odd-numbered dots and data for even-numbered dots to the multiplexer circuit MUX. Is generated. The second control circuit CTR2 is also called a multiplexer control circuit.
CTR3 is a third control circuit and generates a common switch control signal KDR. The third control circuit is also called a common switch control circuit.

  ADJ is a control voltage generation circuit that receives a reference voltage value VREF input from a reference voltage terminal VREF and generates a control voltage Vcont for LED driving. At this time, the value of the control voltage is corrected based on the correction data supplied from the memory circuit MCM via the terminal Mc. The reference voltage value VREF is generated by a regulator circuit (not shown), and the reference voltage VREF may be kept at a predetermined value even in a situation where the power supply voltage drops momentarily as in the case of driving all the LEDs on. The LED drive current is not reduced.

Reference numeral 201 denotes an input circuit for small-amplitude differential signals CLK-P and CLK-N for converting the small-amplitude signals CLK-P and CLK-N into logical amplitude signals used inside the driver IC chip.
A buffer circuit 202 receives an output signal from the input circuit 201 and drives a clock signal CK of a shift register including flip-flops FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25. Since the buffer circuit 202 drives a large number of flip-flops, it has a large driving capability and a relatively large delay time.

  Reference numerals 203 to 206 denote delay circuits, which also give the data signal a delay time substantially equal to the signal delay by the small amplitude differential input circuit 201, the buffer circuit 202, etc. In order to prevent a significant difference in signal delay, the supply of the clock signal and the supply of the data signal have an appropriate timing (phase) relationship for each flip-flop FF.

  Reference numeral SEL denotes a selection circuit, and reference numerals 207 to 210 denote buffer circuits, which receive an output signal from the selection circuit SEL and drive the data output terminals DATAO3 to DATAO0.

  Reference numeral 211 denotes a resistor, which is connected between the strobe terminal STB and the power supply VDD to constitute a pull-up element. 212 and 213 are inverter circuits, and 214 is a NAND circuit.

  The flip-flops FFA1 to FFA25 are cascade-connected, the data input terminal DATAI0 of the driver IC chip is connected to the D terminal (data input terminal) of the flip-flop FFA1 via the delay circuit 203, and the Q terminals of the flip-flops FFA24 and FFA25. Are respectively input to the input terminals A0 and B0 of the selection circuit SEL and corresponding to these input terminals (that is, one of the inputs to these input terminals A0 and B0 is selected and output). The terminal Y0 is connected to the data output terminal DATAO0 of the driver IC chip via the buffer circuit 207.

  Similarly, the flip-flops FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are also cascade-connected, and the data input terminals DATAI1, DATAI2, and DATAI3 of the driver IC chip are flip-flops FFB1 and FFC1 via the delay circuits 204 to 206, respectively. , FFD1 is connected to the D terminal.

  Outputs from the Q terminals of the flip-flops FFB24 and FFB25, flip-flops FFC24 and FFC25, flip-flops FFD24 and FFD25 are also connected to the input terminals A1, B1, A2, B2, A3, and B3 of the selection circuit SEL, and outputs corresponding thereto Terminals Y1, Y2, and Y3 are connected to data output terminals DATAO1, DATAO2, and DATAO3 of the driver IC chip through buffer circuits 208 to 210, respectively.

  Accordingly, the flip-flops FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 constitute shift registers SFRa, SFRb, SFRc, and SFRd each having 25 stages of cascaded flip-flops. The number of shift stages can be switched between 24 and 25 by the circuit SEL.

  The selection circuit SEL performs the above selection operation under the control of the enable signal E2. That is, when the enable signal E2 is High, the input terminals B0 to B3 are connected to the output terminals Y0 to Y3, the shift registers SFRa, SFRb, SFRc, and SFRd are operated as a 25-stage shift register, and the enable signal E2 is When Low, the input terminals A0 to A3 are connected to the output terminals Y0 to Y3, and the shift registers SFRa, SFRb, SFRc, and SFRd are operated as a 24-stage shift register.

Data output terminals DATAO0 to DATAO3 of the stages other than the last stage among the 26 stages of cascaded driver IC chips, that is, the i-th stage (i is any one of 1 to 25) driver IC chip DICi (I + 1) stage) driver IC chip DIC (i + 1) is connected to data input terminals DATAI0 to DATAI3, respectively.
Accordingly, the flip-flops FFA1 to FFA25 of the driver IC chips DIC1 to DIC26 shift the data signal HD-DATA0 input from the print control unit 1 to the first stage driver IC chip DIC1 in synchronization with the clock signal or 24 × 26 stages. A 25 × 26 stage shift register SFRa is configured.

  Similarly, the flip-flops FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 of the driver IC chips DIC1 to DIC26 are supplied with data signals HD-DATA1, HD-DATA2, 24 × 26 stage or 25 × 26 stage shift registers SFRb, SFRc, and SFRd are configured to shift the HD-DATA 3 in synchronization with the clock signal.

  The latch elements LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, LTD1 to LTD24 perform a latch operation by a latch signal LOAD-P input to the control terminal G. Latch elements LTA1 to LTA24 latch data signal HD-DATA0 stored in flip-flops FFA1 to FFA24. Similarly, the latch elements LTB1 to LTB24 latch the data signal HD-DATA1 stored in the flip-flops FFB1 to FFB24. The latch elements LTC1 to LTC24 latch the data signal HD-DATA2 stored in the flip-flops FFC1 to FFC24. The latch elements LTD1 to LTD24 latch the data signal HD-DATA3 stored in the flip-flops FFD1 to FFD24.

The NAND circuit 214 receives the strobe signal HD-STB-N input to the terminal STB and the latch signal LOAD-P input from the load terminal LOAD via the inverter circuits 212 and 213, respectively, and the LED driver DRV A signal (driving timing signal) DST for determining the driving timing of the LED is generated.
The drive timing signal DST is Low when both the strobe signal HD-STB-N and the latch signal LOAD-P are Low, and at this time, the LED is driven by the LED drive unit DRV.

4 is a schematic plan view showing the arrangement of terminals of the driver IC chip DIC shown in FIG.
In the configuration of FIG. 4, in order to perform time-division driving by dividing 192 LED elements into two, 96 LED driving terminals DO1 to DO96 are provided, and driving provided in one-to-one correspondence with the terminals. Part DRV.

In FIG. 4, reference numeral 121 denotes the outer shape (contour) of the surface on which the terminal pads (connection pads) of the driver IC chip DIC are formed. As shown in the drawing, the surface on which the terminal pad is formed is generally rectangular in the driver IC chip DIC, and a pair of long sides, that is, a first long side 121a and a second long side 121b, and a pair of short sides. It has a side, that is, a first short side 121c and a second short side 121d.
DO1 to DO96 are terminal pads for supplying a driving current to the LEDs as driven elements, and are arranged along the first long side 121a.

Reference numerals 122, 123, and 124 denote VDD power supply terminal pads, and reference numeral 125 denotes a VDD power supply wiring, which is disposed on an insulating layer located on the LED drive unit DRV disposed adjacent to the LED drive terminal pads DO1 to DO96. Portion 125a and branch portions 125b, 125c, and 125d for connecting to VDD power supply terminal pads 122, 123, and 124, and is formed of a substantially E-shaped strip-like wiring as a whole.
Reference numeral 126 denotes pads other than the VDD power supply terminal pads 122, 123, and 124, that is, DATAI0 to DATAI3, DATAO3 to DATAO0, HSYNC, LOAD, CLKP, CLKN, GND, VREF, STB, KDR, etc. The whole terminal pad (control terminal pad, power supply terminal pad) for this purpose. The pads 122, 123, 124, and 126 are disposed along the second long side 121b of the driver IC chip DIC.

FIGS. 5A to 5C show the configuration of an LED head configured by cascading a plurality of LED drivers having the configuration of FIG.
5A is a schematic plan view schematically showing the overall configuration of the printed circuit board of the LED head, FIG. 5B is a partially enlarged schematic plan view showing a connection state between the driver IC chip and the LED array, and FIG. (C) is a schematic sectional drawing which follows the 5C-5C line | wire of FIG.5 (b).

  Reference numeral 151 denotes a printed wiring board on which the circuit wiring of the LED head is formed. Reference numeral 152 denotes a row of driver IC chips, which includes driver IC chips DIC1 to DIC26. In FIG. 5B, three driver IC chips DIC1 to DIC3 are provided. The portion of is shown enlarged.

Reference numeral 153 denotes a row of LED array chips. In FIG. 5B, the portions of the LED array chips CHP1 to CHP3 are enlarged.
Reference numeral 150 denotes an LED head connector terminal, which includes an LED head control signal and a power supply terminal.

Reference numerals 154, 155, and 156 denote bonding wires. The bonding wires 154 connect common cathode nodes (CCo and CCe in FIG. 2) of LED elements to cathode pads (not shown) provided on the printed wiring board 151.
The bonding wire 155 connects the LED driving terminal pads DO1 to DO96 (FIG. 4) arranged along the first long side 121a of the surface on which the anode terminal pad of the LED element and the terminal pad of the driver IC chip are formed. The bonding wire 156 is a signal represented by VDD power supply terminal pads 122, 123, and 124 of the driver IC chip, and symbols DATAI0 to DATAI3, DATAO3 to DATAO0, HSYNC, LOAD, CLKP, CLKN, GND, VREF, STB, and KDR. Pads for power supply voltage and the like (those generally denoted by reference numeral 126 in FIG. 4), in other words, in FIG. 4, pads arranged along the second long side 121b and pads of the printed wiring board 151 The column 157 is connected.

  Reference numeral 158 denotes a wiring pattern provided on the printed wiring board 151. For example, the bonding wires 156 connected to the DATAO3 to DATAO0 terminal pads of the driver IC chip DIC1 are temporarily connected to the terminal pads 157 of the printed wiring board 151, It is connected to another terminal pad 157 of the printed wiring board 151 via the wiring pattern 158, and again connected to the DATAI3 to DATAI0 terminal pads of the driver IC chip DIC2 by the bonding wires 156.

  FIG. 6 is a circuit formed by cascading the driver IC chips DIC shown in FIG. 3. In order to make it easy to understand the outline of the operation in print data transfer, the first-stage driver IC chip DIC1 and the second-stage driver IC chip. It is the circuit diagram which extracted and described the principal part of DIC2. For the sake of common explanation, and in order to make the relationship between the first-stage driver IC chip DIC1 and the second-stage driver IC chip DIC2 easier to understand, the reference numerals are changed. Only one of four shift registers SFRa, SFRb, SFRc, and SFRd provided in parallel in each driver IC chip is shown.

The data input terminal of the first-stage driver IC chip DIC1 is abbreviated as DATAI.
The clock signal terminals of the first-stage and second-stage driver IC chips DIC1 and DIC2 are CLKP and CLKN, and the signals for driving them are CLK-P and CLK-N. Since it is a motion signal, only one of them is taken and abbreviated as CLK-P.

DTI1 is a delay circuit of a data input terminal of the driver IC chip DIC1, and corresponds to any one of those indicated by reference numerals 203 to 206 in FIG. Similarly, DTI2 is a delay circuit of the data input terminal of the driver IC chip DIC2.
CK1 corresponds to the combination of the clock input circuit 201 and the buffer circuit 202 shown in FIG. 3 of the driver IC chip DIC1, and this combination may be simply referred to as “buffer circuit”. Similarly, CK2 corresponds to a combination of the clock input circuit 201 and the buffer circuit 202 of the driver IC chip DIC2, and this combination may be simply referred to as a “buffer circuit”.

  FF1 to FF24 are flip-flops and correspond to the flip-flops FFA1 to FFA24, FFB1 to FFB24, FFCI to FFC24, or FFD1 to FFD24 in FIG.

  SEL1 is a selection circuit for the driver IC chip DIC1, and corresponds to the selection circuit SEL in FIG. Similarly, SEL2 is a selection circuit corresponding to the selection circuit SEL of the driver IC chip DIC2.

  FIG. 3 shows the flip-flops FFA25, FFB25, FFC25, and FFD25. When print data is transferred, the output of the flip-flops FFA24, FFB24, FFC24, and FFD24 is selected by the selection circuit SEL. Therefore, the flip-flops FFA25, FFB25, FFC25, and FFD25 are not shown in FIG.

  In FIG. 6, the clock circuit of 24 flip-flops FF1 to FF24 is simplified so as to be driven by the buffer circuit CK1, but actually 100 flip-flop elements in total are formed by the buffer circuit CK1. Driven.

  Similarly, FF25 to FF48 are flip-flops provided in the driver IC chip DIC2, and correspond to the flip-flops FFA1 to FFA24, FFB1 to FFB24, FFC1 to FFC24, FFD1 or FFD24 in FIG.

  DTO1 is an output buffer of the driver IC chip DIC1, and corresponds to any one of those indicated by reference numerals 207 to 210 in FIG. Similarly, DTO2 is an output buffer corresponding to one of the output buffers 207 to 210 of the driver IC chip DIC2.

FIG. 7 is a time chart showing the operation of the circuit of FIG.
In FIG. 7, data d48 is input to the DATAI terminal, which is a data input signal of the LED head, at time taA, followed by data d49, d50,.
Further, the transfer clock signal of the data string composed of the data d48, d49, d50,... Is CLK-P, and the time taB of the falling edge of the transfer clock signal CLK-P for every cycle TCLK of the transfer clock signal CLK-P. In addition, data is taken into the shift register.

  The setup time of the data input signal DATAI at this time is shown in the drawing as Ts0 and hold time Th0. That is, the data signal is input with a predetermined setup time Ts0 and hold time Th0 with reference to the time taB of the falling edge of the transfer clock signal CLK-P.

  In order to increase the print data transfer speed of the LED head, it is desirable that the setup time Ts0 and hold time Th0 of these DATAI signals be as small as possible. However, since it is actually impossible to set these times to zero, after the input data DATAI signal is determined, the clock signal is transited, whereby the data is read into the flip-flop elements in the shift register, and the read operation is performed. It is necessary to hold the data DATAI signal until completion.

  For this reason, neither the setup time Ts0 nor the hold time Th0 is set to zero, and a minimum value for normal operation is defined as a use condition of the LED head.

The data input signal DATAI input to the driver IC chip DIC1 is delayed by time TDI by the delay circuit DTI1. The output DTI1 of the delay circuit DTI1 is sequentially input to the flip-flop FF1 as a data string including data d48, d49, d50,.
On the other hand, the clock signal CLK-P is delayed by a certain time TCK by the buffer circuit CK1 and input to the flip-flops FF1 to FF24.

  At the input portion of the flip-flop FF1, the data signal and the clock signal are delayed by the time indicated by TDI and TCK, respectively, and the setup time and hold time of the data signal with respect to the falling edge of the clock signal in the flip-flop FF1. Becomes Ts1 and Th1.

In order to obtain the relationship between the setup time Ts0 and the hold time Th0 in the signal input section (input connector section) of the LED head, the following expression (1) is obtained when the time taA is considered as a starting point.
Ts0 + TCK-Ts1-TDI = 0 (1)
Further, considering the time taB as a starting point, the following equation (2) is obtained.
Th0 + TDI-Th1-TCK = 0 (2)
By arranging these, the following equations (3) and (4) are obtained.
Ts1 = Ts0 + TCK−TDI (3)
Th1 = Th0 + TDI−TCK (4)

  On the other hand, the output signal of the flip-flop changes after a certain time TFF from the clock signal CK1 in the driver IC chip DIC1. 7, data d47, d48, d49, d50,... Are described as output data strings of the flip-flop FF1, and data d24, d25, d26, d27,.

  The output signal of the flip-flop FF24 is output with a delay of TSEL by the selection circuit SEL1.

  In FIG. 7, a data string composed of data d24, d25, d26,... Is described as the output SEL1 of the selection circuit SEL1.

The output signal of the selection circuit SEL1 (corresponding to SEL in FIG. 3) is output as an output waveform DTO1 after being TDO delayed by the output buffer circuit DTO1 (207 to 210 in FIG. 3) of the driver IC chip DIC1.
This signal is input to the driver IC chip DIC2 at the next stage, and is output with a delay of time TDI by the delay circuit DTI2 in the driver IC chip DIC2.

  On the other hand, the clock signal input to the driver IC chip DIC2 is delayed by TCK by the buffer circuit CK2 and input to the flip-flops FF25 to FF48.

When the data setup time Ts2 at the input portion of the flip-flop FF25 of the driver IC chip DIC2 is obtained, the following equation (5) is obtained with the time taB as a starting point.
TCK + TFF + TSEL + TDO + TDI + Ts2−TCLK−TCK = 0 (5)
Organize
Ts2 = TCLK− (TFF + TSEL + TDO + TDI) (6)
It becomes.

  Note that the driver IC chips DIC1 and DIC2 in FIG. 6 are elements having the same circuit configuration, and although there are some variations in characteristics for each element, the characteristics are seen in the same LED head unit. The difference is small. For this reason, the delay times of the buffer circuits CK1 and CK2 in FIG. 6 are simplified as being substantially the same, and are indicated as TCK in FIG.

In order to operate the flip-flop normally, it is necessary to secure a desired setup time Ts and hold time Th.
In data transfer between the first-stage driver IC chip DIC1 and the second-stage driver IC chip DIC2, it is necessary to give a desired setup time to the flip-flop at the shift register input stage of the second-stage driver IC chip DIC2. Yes, if Ts2> 0,
TCLK> TFF + TSEL + TDO + TDI (7)
Thus, it can be seen that data transfer cannot be performed under a clock cycle shorter than TFF + TSEL + TDO + TDI.

  When a simple buffer circuit (assuming no delay time) is used instead of the delay circuits 203 to 206, the total value of the signal delays by the small amplitude differential input circuit 201 and the buffer circuit 202 is the buffer circuit. Greater than the delay time.

  In such a configuration, the signal of the data terminal (DATAI0 to DATAI3) which is the input terminal of the IC is changed with respect to the effective signal transition (in this case, the falling edge of the clock) of the clock terminal (CLKP, CLKN) signal. When the predetermined setup time and hold time are input, the data signal arrives earlier than the clock signal in the flip-flops (FFA1 to FFD1). In such a situation, when viewed from the D input terminal of the flip-flop, the setup time increases and a timing shift occurs on the side where the hold time decreases. In order to prevent such malfunction due to timing shift, it is necessary to give a delay time to the data terminals (DATAI0 to DATAI3) in advance with respect to the clock signals (CLKP and CLKN) on the print control unit 1 side. However, since the delay time described above varies due to manufacturing variations of driver ICs, it is difficult to set an appropriate value in advance on the print control unit 1 side. Therefore, a delay time corresponding to the delay time of the clock signal is also given to the data signal side so as not to cause a timing shift due to manufacturing variations of the driver IC. In this way, even if the delay time of the clock signal varies due to manufacturing variations in the driver IC, the delay time on the data signal side can be expected to vary at the same rate. The timing difference that occurs between the data terminals can be canceled out.

Japanese Patent Laid-Open No. 2001-199096

In the driver IC chip in the conventional configuration, the selection circuit SEL and the output buffer circuits 207 to 210 are provided in the subsequent stage of the cascade-connected flip-flops, and when the driver IC chip is connected in cascade,
TCLK> TFF + TSEL + TDO + TDI (7)
Therefore, data transfer could not be performed under a clock cycle shorter than the total value of TFF + TSEL + TDO + TDI.
That is, in the input circuit 201 and the buffer circuit 202 for the small amplitude differential clock signal described above, the delay time between input and output is large, and the supply of the clock signal to the flip-flop FF and the supply of the data signal to the flip-flop FF are performed. In order to make the timing (phase) relationship appropriate, it is necessary to provide delay circuits 203 to 206 for adjusting the propagation delay time in the data signal path, and the delay time TDI of such delay circuits 203 to 206 is a flip-flop. In addition to the delay TSEL in the selection circuit SEL on the output side of the cascade connection and the delay TDO in the output buffers 207 to 210, the flip-flop FF at the last stage of one driver IC chip changes to the flip-flop at the first stage of the next driver IC chip. The delay time between data signal transmissions can be further reduced Scratches, for this reason, the lower limit of the period of the clock signal is limited.

  On the other hand, in the LED head on which the driver IC chip is mounted, it is desirable that the timing of the data signal with respect to the clock signal is synchronized with the signal timing in the connector terminal portion (input connector portion) 154 of the LED head. If a large value is requested as a hold time for a signal, the next data transmission cannot be started until the hold time has elapsed.

For this reason, it is necessary to provide delay circuits 203 to 206 having a relatively large delay time at the input portion of the first-stage driver IC chip of the LED head, and the second-stage and subsequent driver IC chips are the first-stage driver IC chips. It is desirable to have the same circuit configuration and to be manufactured by the same manufacturing process (to minimize variation in characteristics and to suppress manufacturing costs). The delay circuits 203 to 206 also have the same delay circuit as the delay circuits 203 to 206 in the input section of the first stage driver IC chip.
As a result, it takes a long time to transfer the print data for one line in the printer apparatus, and there is a problem that the printing speed in the printer becomes low.
Further, in a drive circuit that drives a large number of driven elements, the circuit scale of the drive circuit becomes large due to the correction data memory used for storing correction data for each driven element, and the drive circuit is formed by an IC. In addition, there is a problem that the area of the IC chip increases.

  The drive device for driving the LED array by the drive device has been described above. However, a row of light emitting elements other than LEDs, a row of heating resistors used in a thermal printer, a row of display elements in a display device, and the like are the same drive device. It can be driven and has similar problems.

A driving circuit according to one aspect of the present invention includes:
A correction data memory having a correction data input terminal and first and second memory cell circuits for storing correction data for the first and second driven elements, respectively;
A drive unit that drives the first and second driven elements based on a drive data signal and correction data read from the correction data memory ;
Correction data for each of the first and second driven elements comprises a plurality of bits;
Each of the first and second memory cell circuits includes :
Each is composed of a first and a second inverter ,
The output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the first inverter,
Each storing one of the plurality of bits
A plurality of memory cells;
First and second switches of first conductivity type connected in series between the correction data input terminal and the input terminal of the first inverter of each of the plurality of memory cells and transmitting data to the memory cell Elements,
An output terminal of the first inverter of each of the plurality of memory cells, and a third switch element of the first conductivity type connected between a ground,
Each of the plurality of memory cells of the first memory cell circuit
A first enable signal is input to the control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal, and the first enable signal The on / off of the first switch element is switched by
The control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of the second memory cell circuit includes: 2 enable signal is input, and the second switch signal is turned on and off by the second enable signal,
Control input of the second switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of each of the first and second memory cell circuits. A memory cell selection signal for selecting the memory cell is input to the terminal, and the second switch element is turned on and off by the memory selection signal.
An erase signal is input to the control input terminal of the third switch element of the first and second memory cell circuits, and the on / off state of the third switch element is switched by the erase signal.
The first and second enable signals determine which of the first and second memory cell circuits to write correction data,
The memory cell selection signal determines which of the plurality of memory cells in each of the first and second memory cell circuits is to write correction data,
By the erase signal, it wherein the memory cells is reset.
The drive circuit according to another aspect of the present invention includes:
A correction data memory having a correction data input terminal and first and second memory cell circuits for storing correction data for the first and second driven elements, respectively;
A drive unit that drives the first and second driven elements based on a drive data signal and correction data read from the correction data memory;
Correction data for each of the first and second driven elements comprises a plurality of bits;
Each of the first and second memory cell circuits includes:
Each is composed of a first and a second inverter,
The output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the first inverter,
Each storing one of the plurality of bits
A plurality of memory cells;
First and second switches of first conductivity type connected in series between the correction data input terminal and the input terminal of the first inverter of each of the plurality of memory cells and transmitting data to the memory cell Elements,
An output terminal of the first inverter of each of the plurality of memory cells, and a third switch element of the second conductivity type connected between a power source,
Each of the plurality of memory cells of the first memory cell circuit
A first enable signal is input to the control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal, and the first enable signal The on / off of the first switch element is switched by
The control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of the second memory cell circuit includes: 2 enable signal is input, and the second switch signal is turned on and off by the second enable signal,
Control input of the second switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of each of the first and second memory cell circuits. A memory cell selection signal for selecting the memory cell is input to the terminal, and the second switch element is turned on and off by the memory selection signal.
An erase signal is input to the control input terminal of the third switch element of the first and second memory cell circuits, and the on / off state of the third switch element is switched by the erase signal.
The first and second enable signals determine which of the first and second memory cell circuits to write correction data,
The memory cell selection signal determines which of the plurality of memory cells in each of the first and second memory cell circuits is to write correction data,
The memory cell is reset by the erase signal.
It is characterized by that.

  According to the present invention, the correction data memory can be configured with a small number of elements, and thus the scale of the drive circuit including the correction data memory can be reduced.

It is a block diagram of a printer control circuit in a conventional electrophotographic printer. FIG. 2 is a diagram showing the structure of a conventional general LED head. FIG. 3 is a block diagram showing a detailed configuration of a driver IC chip shown in FIG. 2. FIG. 4 is a schematic plan view showing an arrangement of terminals of the LED driver IC chip DIC shown in FIG. 3. (A) thru | or (c) is a figure which shows the structure of the LED head provided with two or more LED driver DIC of the structure of FIG. In the circuit formed by cascading the driver IC chips DIC shown in FIG. 3, the main parts of the first stage driver IC chip and the second stage driver IC chip are shown in order to make it easy to understand the outline of the operation in print data transfer. It is the circuit diagram extracted and described. 7 is a time chart showing the operation of the circuit of FIG. 6. It is a block diagram which shows the detailed structure of the driver IC chip by Embodiment 1 of this invention. FIG. 9 is a circuit configuration diagram of the memory circuit MEM in FIG. 8. FIG. 9 is a circuit diagram showing the memory circuit MCM of FIG. 8. FIG. 9 is a circuit diagram illustrating the memory circuit MOE of FIG. 8. FIG. 9 is a circuit diagram illustrating a multiplexer circuit MUX in FIG. 8. FIG. 9 is a circuit diagram illustrating the LED drive unit DRV of FIG. 8. FIG. 9 is a circuit diagram showing a configuration of a memory control circuit CTR1 of FIG. 15 is a time chart showing the operation of the memory control circuit CTR1 of FIG. 10 is a schematic diagram showing a configuration of a multiplexer control circuit CTR2 of FIG. 16 is a time chart showing the operation of the multiplexer control circuit CTR2 of FIG. FIG. 9 is a circuit diagram showing a configuration of a common switch control circuit CTR3 of FIG. FIG. 9 is a time chart illustrating an operation of the driving device when a printing operation is performed using an LED head in which 24 driver IC chips DIC having the configuration of FIG. 8 are cascade-connected. In the time chart in FIG. 19, the time chart is simplified by assuming that the number of driver IC chips is one, and the waveforms are shown in more detail. The operation of the driving device when supplying correction data to an LED head formed by cascading 24 driver IC chips having the configuration of FIG. 8 and writing data to a memory cell in the correction memory circuit MEM in the driving device is shown. It is a time chart. In the time chart shown in FIG. 21, the time chart is simplified by assuming that the number of driver IC chips is one, and the waveforms are shown in more detail, and details of the portions of the periods tcA and tcB in FIG. 21 are shown. In the time chart shown in FIG. 21, the time chart is simplified by assuming that the number of driver IC chips is one, and the waveforms are shown in more detail, and details of the portions of the periods tcC and tcD in FIG. 21 are shown. In the time chart shown in FIG. 21, the time chart is simplified by assuming that the number of driver IC chips is one, and the waveforms are shown in more detail, and details of the portions of the periods tcE and tcF in FIG. 21 are shown. In the time chart shown in FIG. 21, the time chart is simplified by assuming that the number of driver IC chips is one, and the waveforms are shown in more detail, and details of portions tcG and tcH in FIG. 21 are shown. In the circuit formed by cascading the driver IC chips DIC shown in FIG. 8, the main parts of the first stage driver IC chip and the second stage driver IC chip are shown in order to make it easy to understand the outline of the operation in print data transfer. It is the circuit diagram extracted and described. 27 is a time chart showing the operation of the circuit of FIG. It is a block diagram which shows the detailed structure of the driver IC chip by Embodiment 2 of this invention. It is a figure which shows the structure of the LED head which uses the driver IC chip shown in FIG. FIG. 29 is a circuit diagram showing a configuration of each of delay circuits 331 to 334 shown in FIG. 28. FIG. 29 is a circuit diagram showing a modification of each of the delay circuits 331 to 334 shown in FIG. 28. It is a time chart which shows the operation | movement of FIG. FIG. 29 is a schematic plan view showing the arrangement of terminals of the LED driver IC chip DIC shown in FIG. 28. (A) thru | or (c) show the structure of the LED head comprised by cascading several LED drivers of the structure of FIG. FIG. 10 is a block diagram illustrating a detailed configuration of a driver IC chip according to a fourth embodiment. FIG. 10 is a block diagram showing a configuration of a memory circuit MDM that forms part of a driver IC chip DIC used in the fourth embodiment. FIG. 36 is a circuit diagram showing a configuration of delay circuits 331 to 334 shown in FIG. 35. 10 is a time chart showing the operation of the LED head of the fourth embodiment. It is a time chart which shows the detail of the period tcA of FIG. 38, and tcB. FIG. 10 is a block diagram showing a memory circuit MDM that forms part of a driver IC chip DIC used in a fifth embodiment. FIG. 41 is a circuit diagram showing a configuration of a power-on reset circuit 425 of FIG. 40. It is a figure which shows the waveform of the signal which appears in each part of the power-on reset circuit of FIG. 10 is a time chart illustrating the operation of the LED head according to the fifth embodiment. 10 shows a memory circuit MEM used in the sixth embodiment. FIG. 20 is a circuit diagram showing a configuration of a memory control circuit CTR1 used in the sixth embodiment. 14 is a time chart showing correction data transfer performed to the LED head having the configuration of the sixth embodiment after the printer is turned on and print data transfer performed thereafter. 47 is a time chart showing details of periods Ta and Tb in FIG. 46. FIG. 45 is a circuit diagram showing in detail a configuration of a part related to generation of correction data Mo3 in the memory circuit MEM of FIG. 44. 47 is a time chart for explaining operations of the memory circuit MEM of FIGS. 44 and 48 and the memory control circuit CTR1 of FIG. FIG. 20 is a circuit diagram showing a memory circuit MEM used in the seventh embodiment. FIG. 20 is a circuit diagram showing a configuration of a memory control circuit CTR1 used in the seventh embodiment. 10 is a time chart showing correction data transfer performed to the LED head having the configuration of the seventh embodiment after the printer is turned on and print data transfer performed thereafter. 50 shows details of a part related to generation of the correction data Mo3 in the memory circuit MEM of FIG. 54 is a time chart for explaining operations of the memory circuit MEM of FIGS. 50 and 53 and the memory control circuit CTR1 of FIG. It is a circuit diagram which shows the other example of the multiplexer circuit MUX which can be used in Embodiment 1-7. FIG. 56 is a circuit diagram showing a configuration of a multiplexer control circuit CTR2 used together with the multiplexer circuit MUX of FIG. 55.

Embodiment 1 FIG.
FIG. 8 is a block diagram showing a detailed configuration of the driver IC chip according to the first embodiment.
The driver IC chip shown in FIG. 8 can be used in place of the driver IC chip shown in FIG. 3, and a plurality of driver IC chips shown in FIG. An LED head similar to that described with reference to FIG. 5 can be configured, and an image forming apparatus similar to that described with reference to FIG. 1 is configured using such an LED head. You can also. The driver IC chip shown in FIG. 8 is generally the same as the driver IC chip shown in FIG. 3, but there are differences as will be understood from the following description. In addition, about the point which is the same as a prior art example, some description is abbreviate | omitted.

  FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are flip-flops, and constitute four mutually parallel shift registers SFRa, SFRb, SFRc, and SFRd.

SEL is a selection circuit. By selecting the output of the 23rd stage flip-flop elements FFA23, FFB23, FFC23, FFD23 or the output of the 24th stage flipflop elements FFA24, FFB24, FFC24, FFD24, the 25th stage flipflop elements FFA25, FFB25, FFC25 , Supplied to the FFD 25.
LTA1 to LTD1,... LTA24 to LTD24 are latch elements, and constitute a latch circuit as a whole.

  The latch elements LTA1 to LTD1,... LTA23 to LTD23 receive outputs from the Q terminals of the flip-flops FFA1 to FFA23, FFB1 to FFB23, FFC1 to FFC23, and FFD1 to FFD23, respectively, while the latch elements LTA24 to LTD24 respectively The output from the Q terminal of FFA25-FFD25 is received.

  MEM is a memory circuit (the same sign is assigned to (24 × 4) memory circuits), and the memory circuit MEM has correction data (dot correction data) for correcting the variation in the amount of light of the LEDs. Stored. The correction data for each dot stored in the memory circuit MEM is read out at the time of printing and used for correcting the LED drive current.

  Each of the memory circuits MEM stores correction data of odd-numbered and even-numbered LEDs (dots) adjacent to each other, and can be read from two sets of data output terminals Mo and Me. The data output terminal set Mo is composed of terminals Mo0, Mo1, Mo2, and Mo3 and outputs 4-bit dot correction data Ho3, Ho2, Ho1, and Ho0 in parallel, as will be described later with reference to FIG. . The set Me of data output terminals includes terminals Me0, Me1, Me2, and Me3, and outputs 4-bit dot correction data He3, He2, He1, and He0 in parallel.

  The MCM is a memory circuit that stores light amount correction data (chip correction data) for each LED array chip or correction data (chip correction data) Hc for each driver IC chip, and can be read from the data output terminal Mc. The data output terminal set Mc is composed of terminals Mc0, Mc1, Mc2, and Mc3, as will be described later with reference to FIG. 10, and outputs 4-bit chip correction data Hc3, Hc2, Hc1, and Hc0 in parallel. . The chip correction data Hc stored in the memory circuit MCM is also read out at the time of printing and used for correcting the LED driving current.

  The MOE is also a memory circuit, and the memory circuit MOE stores data (common switch control data) Hk for determining the value of the common switch control signal KDR output from the common switch control signal output terminal KDR of the driver IC chip. Is done. Data Hk stored in the memory circuit MOE is read at the time of printing (when the LED is driven based on the print data) and used to generate the common switch control signal KDR.

  The (24 × 4) memory circuits MEM receive outputs from the Q terminals of the flip-flops FFA1 to FFA24, FFB1 to FFB24, FFC1 to FFC24, and FFD1 to FFD24, respectively, while the memory circuit MCM receives the Q terminal of the flip-flop FFD25. The memory circuit MOE receives the output from the Q terminal of the flip-flop FFC25.

  MUX is a multiplexer circuit (the same sign is assigned to (24 × 4) multiplexer circuits), each of which is read from the two output terminals Mo and Me of the corresponding memory circuit MEM. A set of correction data (that is, correction data Ho for odd-numbered dots (comprising 4-bit Ho3, Ho2, Ho1, Ho0) and correction data He for even-numbered dots (4-bit He3, He2, Is received by two sets of input terminals Xo and Xe, and one of them is selected and output from the output terminal XQ.

The data input terminal set Xo is composed of four terminals Xo3, Xo2, Xo1, and Xo0, as will be described later with reference to FIG. 12. The 4-bit dot correction data Ho3, Ho2, Ho1, and Ho0 are arranged in parallel. input. The data input terminal set Xe is composed of four terminals Xe0, Xe1, Xe2, and Xe3, and inputs 4-bit dot correction data He3, He2, He1, and He0 in parallel.
The data output terminal set XQ includes four terminals XQ3, XQ2, XQ1, and XQ0, and outputs selected 4-bit dot correction data in parallel.

  DRV is an LED drive unit, and the latch elements LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, LTD1 to LTD24 (with the same reference numerals attached to (24 × 4) LED drive units) Based on the blinking data from the corresponding one and the correction data supplied from the corresponding multiplexer circuit MUX, the LED driving current is output.

  CTR1 is a first control circuit, and generates write command signals (memory cell selection signals W0 to W3 and enable signals E1 and E2) when correction data is written to the memory circuit MEM and the memory circuit MCM. As will be described later, the enable signal E2 is used to control the selection circuit SEL, but is also used to control memory writing, and is therefore referred to as an “enable signal” for convenience. The first control circuit CTR1 is also called a memory control circuit.

Writing of the common switch control data to the memory circuit MOE is controlled by any one of the memory cell selection signals W0 to W3, for example, W3.
CTR2 is a second control circuit, which is a data selection signal (switching command signal) S1P, S1N, S2P, S2N of data for odd-numbered dots and data for even-numbered dots to the multiplexer circuit MUX. Is generated. The second control circuit CTR2 is also called a multiplexer control circuit.
CTR3 is a third control circuit and generates a common switch control signal KDR. The third control circuit is also called a common switch control signal generation circuit.

  ADJ is a control voltage generation circuit that receives a reference voltage value VREF input from a reference voltage terminal VREF and generates a control voltage Vcont for LED driving. At this time, the value of the control voltage is corrected based on the correction data supplied from the memory circuit MCM via the terminal Mc. The reference voltage value VREF is generated by a regulator circuit (not shown), and the reference voltage VREF may be kept at a predetermined value even in a situation where the power supply voltage drops momentarily as in the case of driving all the LEDs on. The LED drive current is not reduced.

Reference numeral 201 denotes an input circuit for small-amplitude differential signals CLK-P and CLK-N for converting the small-amplitude signals CLK-P and CLK-N into logical amplitude signals used inside the driver IC chip.
A buffer circuit 202 receives a signal from the input circuit 201 and drives a clock signal CK of a shift register including flip-flops FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25. Since the buffer circuit 202 drives a large number of flip-flops, it has a large driving capability and a relatively large delay time.

  Reference numerals 203 to 206 denote delay circuits, which also give the data signal a delay time substantially equal to the signal delay by the small amplitude differential input circuit 201, the buffer circuit 202, etc. In order to prevent a significant difference in signal delay, the supply of the clock signal and the supply of the data signal have an appropriate timing (phase) relationship for each flip-flop FF.

  207 to 210 are buffer circuits, which receive output signals from the Q terminals of the flip-flops FFA25, FFB25, FFC25, and FFD25, and drive the data output terminals DATAO3 to DATAO0.

Reference numeral 211 denotes a resistor, which is connected between the strobe terminal STB and the power supply VDD to constitute a pull-up element.
212 and 213 are inverter circuits, and 214 is a NAND circuit.

  The flip-flops FFA1 to FFA25 are cascade-connected, the data input terminal DATAI0 of the driver IC chip is connected to the D terminal of the flip-flop FFA1 via the delay circuit 203, and the output (flip-flop FFA24) from the Q terminal of the flip-flop FFA23. And the output from the Q terminal of the flip-flop FFA24 are input to the input terminals A0 and B0 of the selection circuit SEL and correspond to these input terminals (that is, either of the inputs to these input terminals). The output terminal YO is connected to the D terminal of the flip-flop FFA25, and the output from the Q terminal of the flip-flop FFA25 is connected to the data output terminal DATAO0 of the driver IC chip via the buffer circuit 207. Yes.

  Similarly, the flip-flops FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are also cascade-connected, and the data input terminals DATAI1, DATAI2, and DATA13 of the driver IC chip are connected to the flip-flops FFB1 and FFC1 via the delay circuits 204 to 206, respectively. , FFD1 is connected to the D terminal.

  Outputs from the Q terminals of the flip-flops FFB23 and FFB24, flip-flops FFC23 and FFC24, and flip-flops FFD23 and FFD24 are also connected to the input terminals A1, B1, A2, B2, A3, and B3 of the selection circuit SEL, and outputs corresponding thereto. The terminals Y1, Y2, and Y3 are connected to the D terminals of the flip-flops FFB25, FFC25, and FFD25, respectively, and the output from the Q terminal of the flip-flops FFB25, FFC25, and FFD25 is output to the driver IC chip through the buffer circuits 208 to 210. The terminals DATAO1, DATAO2, and DATAO3 are connected to each other.

  Accordingly, the flip-flops FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 constitute shift registers SFRa, SFRb, SFRc, and SFRd each having 25 stages of cascaded flip-flops. The number of shift stages can be switched between 24 and 25 by the circuit SEL.

  The selection circuit SEL performs the above selection operation under the control of the enable signal E2. That is, when the enable signal E2 is High, the input terminals B0 to B3 are connected to the output terminals Y0 to Y3, the shift registers SFRa, SFRb, SFRc, and SFRd are operated as a 25-stage shift register, and the enable signal E2 is When Low, the input terminals A0 to A3 are connected to the output terminals Y0 to Y3, and the shift registers SFRa, SFRb, SFRc, and SFRd are operated as a 24-stage shift register.

Data output terminals DATAO0 to DATAO3 of the stages other than the last stage among the 26 stages of cascaded driver IC chips, i.e., the i-th stage (i is any one of 1 to 25) driver IC chip DICi are connected to the next stage ( The driver IC chip DIC (i + 1) of the (i + 1) th stage is connected to the data input terminals DATAI0 to DATAI3.
Accordingly, the flip-flops FFA1 to FFA25 of the driver IC chips DIC1 to DIC26 shift the data signal HD-DATA0 input from the print control unit 1 to the first stage driver IC chip DIC1 in synchronization with the clock signal or 24 × 26 stages. A 25 × 26 stage shift register SFRa is configured.

  Similarly, the flip-flops FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 of the driver IC chips DIC1 to DIC26 are supplied with data signals HD-DATA1, HD-DATA2, 24 × 26 stage or 25 × 26 stage shift registers SFRb, SFRc, and SFRd are configured to shift the HD-DATA 3 in synchronization with the clock signal.

  The latch elements LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, LTD1 to LTD24 perform a latch operation in response to a latch signal LOAD-P input to the control terminal G. The latch elements LTA1 to LTA24 latch the data signal HD-DATA0 stored in the flip-flops FFA1 to FFA23 and FFA25. Similarly, the latch elements LTB1 to LTB24 latch the data signal HD-DATA1 stored in the flip-flops FFB1 to FFB23 and FFB25. The latch elements LTC1 to LTC24 latch the data signal HD-DATA2 stored in the flip-flops FFC1 to FFC23 and FFC25. The latch elements LTD1 to LTD24 latch the data signal HD-DATA3 stored in the flip-flops FFD1 to FFD23 and FFD25.

The NAND circuit 214 receives the strobe signal HD-STB-N input to the terminal STB and the latch signal LOAD-P input from the load terminal LOAD via the inverter circuits 212 and 213, respectively, and the LED driver DRV A signal (driving timing signal) DST for determining the driving timing of the LED is generated.
The drive timing signal DST is Low when both the strobe signal HD-STB-N and the latch signal LOAD-P are Low, and at this time, the LED is driven by the LED drive unit DRV.

FIG. 9 is a circuit configuration diagram of the memory circuit MEM shown in FIG.
In the configuration of the present embodiment, the dot correction data for LED light amount correction is 4 bits, and light amount correction is performed by adjusting the LED drive current in 16 steps for each dot.

  The memory circuit MEM shown in FIG. 9 stores correction data for two adjacent LEDs (2 dots), and includes a first memory cell circuit 251, a second memory cell circuit 252, and The dot correction data Hb (Ho or He) from the buffer 221, the inverter 222, and the corresponding flip-flops (corresponding to FFA1 to FFA24, FFB1 to FFB24, FFC1 to FFC24, and FFD1 to FFD24 in FIG. 8). The received correction data input terminal MD, an enable terminal E1 for instructing data write enable for odd-numbered dots, an enable terminal E2 for instructing data write enable for even-numbered dots, memory cell selection terminals W0 to W3, and odd-numbered dots Correction data output terminals Mo0 to Mo3 and the even-numbered docks. And a correction data output terminal Me0~Me3 about.

  The first memory cell circuit 251 stores correction data of odd-numbered dots (for example, k-th (k is odd-numbered) dots), and the second memory cell circuit 252 is an even-numbered dot (for example, (( This is for storing correction data of k + 1) th dot).

The buffer circuit 221 receives the correction data input via the correction data input terminal MD, and the inverter 222 generates a data signal complementary to the output of the buffer circuit 221.
The first memory cell circuit 251 includes inverters 223 to 230 and NMOSs 231 to 246. The second memory cell circuit 252 is similarly configured.

Memory cell selection terminals W0 to W3 are supplied with memory cell selection signals W0 to W3 from the memory control circuit CTR1, respectively.
Write enable signals E1 and E2 from the memory control circuit CTR1 are input to the write enable terminals E1 and E2 of the memory circuit MEM.

  The output terminal of the buffer circuit 221 is connected not only to the inverter 222 as described above, but also to the first main terminals (one of the source and drain) of the NMOS 231, 235, 239, and 243. An output terminal of the inverter 222 is connected to first main terminals (one of a source and a drain) of the NMOSs 234, 238, 242 and 246.

  The other main terminal (the other of the source and drain) of the NMOS 231, 235, 239, 243, 234, 238, 242, 246 is the first main terminal of the NMOS 232, 236, 240, 244, 233, 237, 241 and 245. The NMOS 231 and the NMOS 232, the NMOS 235 and the NMOS 236, the NMOS 239 and the NMOS 240, the NMOS 243 and the NMOS 244, the NMOS 234 and the NMOS 233, the NMOS 238 and the NMOS 237, the NMOS 242 and the NMOS 241, the NMOS 246 and the NMOS 245, respectively, The output of 224 is connected to the other main terminal of the NMOS 233, and the output of the inverter 223 and the input of the inverter 224 are the other main terminal of the NMOS 232. It is connected, in this way, the inverters 223 and 224 are each output is connected to the other input, constitute a memory cell.

  Similarly, inverters 225 and 226, inverters 227 and 228, and inverters 229 and 230 are connected between the second main terminals of NMOS 236 and 237, NMOS 240 and 241, and NMOS 244 and 245, respectively, and each output is connected to the other input. Connected to form a memory cell.

  The control terminals (gate terminals) of the NMOSs 232 and 233 are connected to the memory cell selection terminal W0. The control terminals (gate terminals) of the NMOSs 236 and 237 are connected to the memory cell selection terminal W1. The control terminals (gate terminals) of the NMOSs 240 and 241 are connected to the memory cell selection terminal W2. The control terminals (gate terminals) of the NMOSs 244 and 245 are connected to the memory cell selection terminal W3.

The enable terminal E1 is connected to the gate terminals of NMOS 231, 234, 235, 238, 239, 242, 243, 246.
Outputs of the inverters 224, 226, 228 and 230 are connected to correction data output terminals Mo0, Mo1, Mo2 and Mo3, respectively.

  Although the first memory cell circuit 251 has been described above, the second memory cell circuit 252 is completely the same except that the connected enable terminal is represented by E2 and the output signal is represented by the symbols Me0 to Me3. It has the same configuration.

  FIG. 10 shows the memory circuit MCM. The memory circuit MCM shown in FIG. 9 includes the first memory cell circuit 251, the buffer circuit 221, the inverter 222, and the same terminal as those connected to them, and can be written and read by the enable signal E1. Configured to be. Instead of configuring the memory circuit MCM as described above, the memory circuit MCM includes the second memory cell circuit 252, the buffer circuit 221, the inverter 222, and the same terminals as those connected thereto, and the write is performed by the enable signal E2. Further, it may be configured to enable reading.

  FIG. 11 shows the memory circuit MOE. The memory circuit MOE shown in FIG. 9 is one memory cell of the first memory cell circuit 251 in FIG. 9, for example, the memory cell (229, 230) selected by the memory cell selection signal W3 and the data to the memory cell. The MOS (243 to 246) that performs transmission, the buffer circuit 221, the inverter 222, and the same terminals as those connected thereto are provided, and writing and reading are enabled by an enable signal E1. Instead of configuring the memory circuit MOE as described above, one memory cell of the second memory cell circuit 252, a MOS that transmits data to the memory cell, a buffer circuit 221, and an inverter 222 and the same terminal as those connected thereto may be provided so that writing and reading can be performed by the enable signal E2.

  FIG. 12 shows the multiplexer circuit MUX of FIG. During printing, the multiplexer circuit MUX selects either correction data Ho3 to Ho0 for odd-numbered dots or correction data He3 to He0 for even-numbered dots in the memory circuit MEM to drive LEDs. Supply to the section DRV. The illustrated multiplexer circuit MUX includes four multiplexers 260 to 263. The multiplexers 260 to 263 are used for selection for bit0 to bit3 (0th to 3rd bits), respectively.

The multiplexer 260 includes PMOSs 264, 265, 268, 269 and NMOSs 266, 267, 270, 271.
The first main terminal of the PMOS 264 is connected to the power supply VDD, the second main terminal of the PMOS 264 is connected to the first main terminal of the PMOS 265, and the second main terminal of the PMOS 265 is connected to the second main terminal of the NMOS 266. The first main terminal of the NMOS 266 is connected to the second main terminal of the NMOS 267, and the first main terminal of the NMOS 267 is connected to the ground.
The control terminals (gate terminals) of the PMOS 265 and the NMOS 266 are connected to the data input terminal Xe0 of the multiplexer circuit MUX, and the node connecting the second main terminal of the PMOS 265 and the second main terminal of the NMOS 266 is the multiplexer circuit MUX. It is connected to the data output terminal XQ0.

  The circuits composed of the PMOSs 268 and 269 and the NMOSs 270 and 271 are configured in the same manner. The control terminals (gate terminals) of the PMOS 269 and the NMOS 270 are connected to the data input terminal Xo0 of the multiplexer circuit MUX, and the second main terminal of the PMOS 269 A node connecting the second main terminal of the NMOS 270 follows the data output terminal XQ0 of the multiplexer circuit MUX.

  Further, the data selection signals S2N and S2P of the multiplexer circuit MUX are connected to the control terminals (gate terminals) of the PMOS 264 and NMOS 267, and the data selection signals S1N and S2N of the multiplexer circuit MUX are connected to the control terminals (gate terminals) of the PMOS 268 and NMOS 271. Each S1P is connected.

  A circuit 260e for selecting data for even-numbered dots is configured by the MOSs 264, 265, 266, and 267 of the multiplexer 260, and a circuit 260o for selecting data for odd-numbered dots is configured by the MOSs 268, 269, 270, and 271. It is configured.

  The multiplexers 261, 262, and 263 are configured similarly to the multiplexer 260. However, instead of data from the data input terminals Xe0 and Xo0, data from the data input terminals Xe1, Xo1, Xe2, Xo2, Xe3 and Xo3 are received.

  FIG. 13 shows the LED driving unit indicated by DRV in FIG. The illustrated LED driving unit includes PMOSs 280 to 284 and 286, an NMOS 287, NAND circuits 290 to 293, a NOR circuit 285, a print data input terminal PDN, and a signal (driving timing signal) DST for determining LED driving timing. A receiving input terminal S, a control voltage input terminal V, a correction data input terminal DQ (consisting of DQ0 to DQ3), and a drive current output terminal DO are provided.

The print data input terminal PDN of the LED driver DRV is connected to the QN terminals (inverted data output terminals) of the latch elements (LTA1 to LTD1, LTA12 to LTD12, etc.) in FIG. PDN is supplied.
The correction data input terminal DQ (consisting of DQ3 to DQ0) is connected to the correction data output terminal XQ (consisting of XQ3 to XQ0) of the multiplexer circuit MUX shown in FIG.

A signal (drive timing signal) DST for determining the LED drive timing output from the NAND circuit 214 of FIG. 8 is input to the terminal S.
A control voltage Vcont from the control voltage generation circuit ADJ of FIG.
The drive current output terminal DO is connected to the anode of the LED element by a bonding wire (not shown).
The two input terminals of the NOR circuit 285 are connected to the terminal S and the terminal PDN, respectively.
The first input terminals of the NAND circuits 290 to 293 are connected to the output terminal of the NOR circuit 285. The second input terminals of the NAND circuits 293 to 290 are connected to the correction data input terminals DQ3 to DQ0, respectively.

The control terminals (gate terminals) of the PMOSs 280 to 283 are connected to the output terminals of the NAND circuits 290 to 293, respectively.
The first main terminals (source terminals) of the PMOSs 280 to 284 are connected to the power supply VDD, and the second main terminals (drain terminals) of the PMOSs 280 to 284 are connected to the drive current output terminal DO.
On the other hand, the power supply terminals of the NAND circuits 290 to 293 and the NOR circuit 285 are connected to the power supply VDD, and the ground terminals of these circuits are connected to the control voltage terminal V and kept at the control voltage Vcont.

  As will be described later, the potential difference between the potential of the power supply VDD and the potential of Vcont is substantially equal to the gate-source voltage when the PMOS 280 to 284 is turned on, and the drain current of the PMOS 280 to 284 can be adjusted by changing this voltage. It becomes possible. The control voltage generation circuit ADJ of FIG. 8 is provided for receiving the reference voltage VREF and controlling the control voltage Vcont so that the drain current of the PMOSs 280 to 284 becomes a predetermined value.

The print data HD-DATA is High (the print data PDN input to the terminal PDN is Low), and the drive ON is commanded by the LED drive ON / OFF command signal HD-STB-N, and the terminal S When the drive timing signal DST is Low, the output of the NOR circuit 285 is High.
At this time, according to the correction data from the correction data terminals DQ3 to DQ0, the output signal level of the NAND circuits 290 to 293 and the output of the inverter composed of the PMOS 286 and the NMOS 287 become the VDD potential or the Vcont potential.
The PMOS 284 is a main drive transistor for supplying a main drive current to the LED, and the PMOSs 280 to 283 are auxiliary drive transistors for adjusting the LED drive current for each dot to correct the light amount.

The main drive transistor 284 is driven according to the print data PDN. That is, when the print data PDN is Low and the drive timing signal DST is Low, the output is turned on when the output of the NOR circuit 285 becomes High.
The auxiliary drive transistors 290 to 293 are driven according to the outputs XQ3 to XQ0 of the multiplexer circuit MUX when the output of the NOR circuit 285 is at a high level. As will be described later, the outputs XQ3 to XQ0 of the multiplexer circuit MUX correspond to a correction memory output in which correction data for correcting the light emission variation of each LED dot is stored.
That is, the auxiliary drive transistors 280 to 283 are selectively driven according to the correction data together with the main drive transistor 284, and a drive current obtained by adding the drain current of the selected auxiliary drive transistor to the drain current of the main drive transistor 284 is obtained. , And supplied from the terminal DO to the LED.

  When the PMOSs 280 to 283 are driven, the outputs of the NAND circuits 290 to 293 are at a low level (that is, a level approximately equal to the control voltage Vcont), so that the gate potential of the PMOSs 280 to 283 is approximately equal to the control voltage Vcont. Become. At this time, the PMOS 286 is in the off state, the NMOS 267 is in the on state, and the gate potential of the PMOS 284 is also approximately equal to the control voltage Vcont. Therefore, the drain current values of the PMOSs 280 to 284 can be collectively adjusted by the control voltage Vcont.

  At this time, since the NAND circuits 290 to 293 operate using the power supply potential VDD and the ground potential Vcont as the power supply and the ground potential, respectively, the potential of the input signal also corresponds to the power supply potential VDD and the ground potential Vcont. The Low level may not be 0V.

FIG. 14 is a circuit diagram showing a configuration of memory control circuit CTR1 shown in FIG. The illustrated memory control circuit CTR1 includes flip-flops 301 to 305, a NOR circuit 306, and AND circuits 307, 308, 310 to 313.
The latch signal LOAD-P is input to the reset terminals R of the flip-flops 301 to 305, the strobe signal STB-P is input to the clock terminals of the flip-flops 301 and 302, and the Q outputs of the flip-flops 301 and 302 are NOR circuits. The output of the NOR circuit 306 is connected to the D input of the flip-flop 301.

The clock terminal of the flip-flop 303 is connected to the Q output terminal of the flip-flop 301, and the QN output of the flip-flop 303 is connected to the D input terminal of the flip-flop 303.
The Q output of the flip-flop 303 is connected to one input terminal of the AND circuit 307, the QN output Mizuko of the flip-flop 303 is connected to one input terminal of the AND circuit 308, and the other input terminals of the AND circuits 307 and 308 are connected. The latch signal LOAD-P is input.
The outputs of the AND circuits 307 and 308 are connected to the terminals E1 and E2, and the write enable signal (the signal (E1) instructing to enable writing of the data of odd-numbered dots) of the memory circuit MEM in FIG. This is a signal (E2) instructing to enable data writing.

  The clock terminals of the flip-flops 304 and 305 are connected to the output of the AND circuit 307, the D terminal of the flip-flop 304 is connected to the Q output terminal of the flip-flop 305, and the D input terminal of the flip-flop 305 is the QN output of the flip-flop 304. Connected to the terminal.

The first input terminal of the AND circuit 313 is connected to the Q terminal of the flip-flop 305, the second input terminal is connected to the QN terminal of the flip-flop 304, and the first input terminal of the AND circuit 312 is connected to the Q terminal of the flip-flop 305. And the second input terminal is the Q terminal of the flip-flop 304, the first input terminal of the AND circuit 311 is the QN terminal of the flip-flop 305, the second input terminal is the Q terminal of the flip-flop 304, and the AND circuit. The first input terminal of 310 is connected to the QN terminal of the flip-flop 305, the second input terminal is connected to the QN terminal of the flip-flop 304, and the third input terminals of the AND circuits 310 to 313 are connected to the QN of the flip-flop 302. Connected with output.
The output terminals of the AND circuits 310 to 313 are connected to the memory cell selection terminals W0 to W3, and become the memory cell selection signals W0 to W3 of the memory circuit MEM of FIG.

  The flip-flops 301 and 302 and the NOR circuit 306 constitute a ternary first counter CNTa, and the flip-flops 304 and 305 constitute a quaternary second counter CNTb. The flip-flop 303 performs a toggle operation, and constitutes a binary third counter CNTc.

  The latch signal LOAD-P supplied to the reset terminal R of the flip-flops of the first, second, and third counters CNTa, CNTb, and CNTc is maintained high when the correction data is transferred by the shift register. When the print data is transferred by the register, it is generally Low, but becomes High when the print data is taken into the latch element.

Hereinafter, the operation of the memory control circuit CTR1 will be described with reference to FIG.
In the first counter CNTa, the Q terminal of the flip-flop 301, the Q terminal of the flip-flop 302, and the output terminal of the NOR circuit 306 constitute 3-bit output terminals CQ1, CQ2, and CQ3 of the first counter CNTa. FIG. 15 shows the signal levels of the output terminals CQ1 and CQ2.

  The flip-flops 301 and 302 of the first counter CNTa are reset when the latch signal LOAD-P is Low, and in this state, the output terminals CQ1, CQ2, and CQ3 are Low (logical value “0”), Low, and High ( When the latch signal LOAD-P is High, the rising edge of the strobe signal STB-P (falling edge of HD-STB-N) is counted. That is, once the strobe signal STB-P rises, the output terminals CQ1, CQ2, and CQ3 become High, Low, and Low, respectively, and when the strobe signal STB-P rises again, the output terminals CQ1, CQ2, and CQ3 become Low, High, respectively. When the strobe signal STB-P rises once again, the output terminals CQ1, CQ2, and CQ3 become Low, Low, and High, respectively.

  The print control unit 1 transfers a series of correction data (1 bit correction data for all odd-numbered dots of the LED head or 1 bit correction data for all even-numbered dots). Each time it is finished, three strobe signals HD-STB-N are continuously set to Low three times (a Low level pulse is generated three times), so that the first counter CNTa operates as described above. To generate signals CQ1 and CQ2. Note that the memory cell selection signals W3 to W0 are generated in synchronization with the signal CQ2, but the generation of the memory cell selection signals W3 to W0 (accordingly, writing to the memory cell) is performed by using the ternary first counter. ) Is slightly delayed from the switching of the enable signals E1 and E2 and the memory cell selection signals W3 to W0 are generated after the enable signal is stabilized, so that erroneous writing to different memory cells can be more reliably prevented. .

  The output CQ1 of the first counter CNTa is supplied to the clock terminal of the flip-flop 303 constituting the third counter CNTc. The output CQ2 of the first counter CNTa becomes one input of each of the AND circuits 310 to 313.

  The Q terminal of the flip-flop 303 constitutes the output terminal CQ6 of the third counter CNTc. The flip-flop 303 is reset when the latch signal LOAD-P is Low, and in that state, the Q terminal (the output terminal CQ in FIG. 15) is Low, and when the latch signal LOAD-P is High, the counter CNTa The rising edge of the output CQ1 is counted. That is, once the output CQ1 of the first counter CNTa rises, the output terminal CQ6 becomes High, and when the output CQ1 of the first counter CNTa rises once again, the output terminal CQ6 becomes Low. Thereafter, the same operation is repeated.

  As described above, the outputs of the Q terminal (terminal CQ6) and the QN terminal which alternately become High by the toggle operation of the flip-flop 303 are output as the enable signals E1 and E2 via the AND circuits 307 and 308.

  When the dot correction data Hb (Ho, He), the chip correction data Hc, and the common switch control data Hk are transferred and written to the memory circuits MEM, MCM, and MOE, the latch signal LOAD-P is set to High. Accordingly, the outputs of the Q and QN terminals of the flip-flop 303 are output as they are as the enable signals E1 and E2.

  In the period Ta from when the latch signal LOAD-P changes from Low to High until the terminal CQ1 becomes High for the first time, the enable signal E1 is Low and the enable signal E2 is High. Correction data Ho, chip correction data Hc, and common switch control data Hk are transferred. At this time, since the enable signal E2 is High, the shift register has 25 stages.

  In the period Tb from when the terminal CQ1 rises, the enable signal E1 becomes High and the enable signal E2 becomes Low, and then the terminal CQ1 rises, the enable signal E1 becomes Low, and the enable signal E2 becomes High, the memory cell The selection W3 becomes High only for a relatively short time, and then the correction data Ho, the chip correction data Hc, and the common switch control data Hk for the odd-numbered dots are written to the memory circuits MEM, MCM, and MOE. Subsequently, correction data He for even-numbered dots is transferred. At this time, since the enable signal E2 is Low, the shift register has 24 stages.

In the period Tc following the period Tb in which the enable signal E1 is Low and the enable signal E2 is High, the memory cell selection W3 is High for a relatively short time, and at that time, the correction data Ho for the even-numbered dots is high. Writing to the memory circuit MEM is performed, and subsequently, correction data Ho, chip correction data Hc, and common switch control data Hk for odd-numbered dots are transferred. At this time, since the enable signal E2 is High, the shift register has 25 stages.
Thereafter, the same operation is repeated, and the correction data He for even-numbered dots is written into the memory circuit MEM in the period Tj.

In the period Tk during which the print data is transferred, the latch signal LOAD-P is kept low, so both the enable signals E1 and E2 are kept low, and the shift register has 24 stages.
When the print data is latched into the latch circuit (time Tm), the latch signal LOAD-P becomes High, the enable signal E2 becomes High, and the shift register has 25 stages. At this time, the data transfer is There is no effect because it is not done.

  The counter CNTb is reset when the Q terminal of the flip-flop 305 and the Q terminal of the flip-flop 304 constitute the 4-bit output terminals CQ4 and CQ5 of the counter, and is reset when the latch signal LOAD-P is Low. As shown in FIG. 4, when the output terminals CQ4 and CQ5 are Low and Low and the latch signal LOAD-P is High, the rising edge of the enable signal E1 is counted. That is, when the strobe signal STB-P rises once, the output terminals CQ4 and CQ5 become High and Low, respectively, and when the enable signal E1 rises again, the output terminals CQ4 and CQ5 become High and High, respectively, and the enable signal E1 rises again. When the output terminals CQ4 and CQ5 become Low and High, respectively, and the enable signal E1 rises again, the output terminals CQ4 and CQ5 become Low and Low, respectively. Thereafter, the same operation is repeated.

  The enable signals E1 and E2 alternately become High once while the output terminals CQ4 and CQ5 are High and Low, respectively, and the enable signals E1 and E2 while the output terminals CQ4 and CQ5 are High and High, respectively. Becomes alternately High once, while the output terminals CQ4 and CQ5 are Low and High, respectively, and the enable signals E1 and E2 are alternately High once and the output terminals CQ4 and CQ5 are Low and Low, respectively. The enable signals E1 and E2 are alternately High once each.

  The AND circuits 310 to 313 decode the outputs Q and QN of the flip-flops 305 and 304 and sequentially set the memory cell selection signals W3 to W0 to High. That is, on condition that the output CQ2 of the counter CNTa is High, if the outputs CQ4 and CQ5 of the counter CNTb are High and Low, respectively, only the memory cell selection signal W3 is High, and the outputs CQ4 and CQ5 are High, respectively. If it is High, only the memory cell selection signal W2 is High. If the outputs CQ4 and CQ5 are Low and High, respectively, only the memory cell selection signal W1 is High and if the outputs CQ4 and CQ5 are Low and Low, respectively. Only the memory cell selection signal W0 becomes High.

  As a result, the memory cell selection signal W3 becomes High in synchronization with the signal CQ2 during the period when the signal E1 is High, and then the memory cell selection signal W3 becomes High in synchronization with the signal CQ2 during the period when the signal E2 is High. become. That is, the memory cell selection signal W3 is generated twice in succession. Then, correction data for odd-numbered dots is written at the first occurrence, and correction data for even-numbered dots is written at the second occurrence. Similarly, the memory cell selection signals W2, W1, and W0 are generated twice.

  FIG. 16 is a schematic diagram showing the configuration of the multiplexer control circuit CTR2 shown in FIG. The illustrated control circuit CTR2 is for controlling the selection operation of the multiplexer circuit MUX, and includes a flip-flop 321, buffer circuits 322 and 323, and inverters 324 and 325.

The latch signal LOAD-P is input to the clock terminal of the flip-flop 321, the main scanning synchronization signal HSYNC-N is input to the reset terminal R, the D terminal is connected to the QN terminal, and the input terminal of the buffer circuit 322 is the flip-flop. The input terminal of the buffer circuit 323 is connected to the QN terminal of the flip-flop 321.
The input terminals of the inverters 324 and 325 are connected to the output terminals of the buffer circuits 322 and 323, respectively.

  The outputs of the buffer circuits 322 and 323 and the inverters 324 and 325 are connected to data selection signal output terminals S1P, S2P, S1N, and S2N, respectively, and supplied as data selection command signals to the multiplexer circuit MUX in FIG.

Hereinafter, the operation of the multiplexer control circuit CTR2 will be described with reference to FIG. FIG. 17 is the same as the right end of FIG. 15, but shows only the relevant parts.
In the illustrated circuit, as shown in FIG. 17, when the main scanning synchronization signal HSYNC-N becomes Low, the flip-flop 321 is reset, and the outputs of the Q and QN terminals become Low and High, respectively. The signal S1P is Low, the data selection signal S1N is High, the data selection signal S2P is High, and the data selection signal S2N is Low.

  When the transfer of the print data for the odd-numbered dots is completed, the latch signal LOAD-P (the same waveform as HD-LOAD) rises, and when the shift register data is latched by the latch circuit, 321 is inverted, and the outputs of the Q and QN terminals are High and Low, respectively, the data selection signal S1P is High, the data selection signal S1N is Low, the data selection signal S2P is Low, and the data selection signal S2N is High.

  As a result, the MOSs (268, 271) that receive the data selection signals S1P, S1N in the circuits 260o, 261o, 262o, 263o that select correction data for odd-numbered dots in the multiplexer circuit MUX shown in FIG. Etc.) is turned on, and the MOSs (264, 267, etc.) receiving the data selection signals S2P, S2N in the circuits 260e, 261e, 262e, 263e for selecting correction data for even-numbered dots are turned off. As a result, the output of the inverter that receives the correction data Ho3, Ho2, Ho1, Ho0 for the odd-numbered dots supplied from the terminals Xo3, Xo2, Xo1, Xo0 is the selected data XQ3, XQ2, XQ1, XQ0. Is output.

  Next, after the print data is transferred for the even-numbered dots, when the latch signal LOAD-P rises, the state of the flip-flop 321 is inverted, and the outputs of the Q terminal and the QN terminal are low. , High, the data selection signal S1P is Low, the data selection signal S1N is High, the data selection signal S2P is High, and the data selection signal S2N is Low. As a result, the MOSs (264, 267) that receive the data selection signals S2P, S2N in the circuits 260e, 261e, 262e, 263e that select correction data for even-numbered dots in the multiplexer circuit MUX shown in FIG. Etc.) is turned on, and MOSs (268, 271 etc.) receiving the data selection signals S1P, S1N in the circuits 260o, 261o, 262o, 263o for selecting correction data for odd-numbered dots are turned off. As a result, the output of the inverter that receives the correction data He3, He2, He1, He2 for even-numbered dots supplied from the terminals Xe3, Xe2, Xe1, and Xe0 is selected data XQ3, XQ2, XQ1, and XQ0. Is output.

  FIG. 18 is a schematic diagram showing the configuration of the common switch control circuit CTR3. The illustrated common switch control circuit CTR3 performs printing (when driving the LED elements based on the print data), and the first common switch 109 connected to the odd-numbered LED elements and the first common switch 109 connected to the even-numbered LED elements. The control signal KDR (KDR1, KDR2) is generated to turn on only one of the two common switches 110. That is, the common switch control circuit CTR3 in the first-stage driver IC chip DIC1 generates a control signal KDR1 for controlling on / off of the common switch 109 connected to the odd-numbered LED elements during printing. The common switch control circuit CTR3 in the driver IC chip DIC2 of the stage generates a control signal KDR2 for controlling on / off of the common switch 110 connected to the even-numbered LED elements in printing.

The illustrated common switch control circuit CTR 3 includes a flip-flop 401 and a selection circuit 402.
The flip-flop 401 is reset when the HSYNC-N signal is Low, and the Q terminal is Low in the reset state. When the HSYNC-N signal is High, the output is inverted every time the rising edge of the LOAD-P signal occurs.

  The outputs of the Q terminal and the QN terminal of the flip-flop 401 are supplied to the selection circuit 402. The selection circuit 402 selects one of the two inputs in response to the switching command signal Hk from the memory circuit MOE, and uses it as a control signal. Output. This control signal is output from the common switch control signal output terminal KDR of the driver IC chip.

  In the above example, the memory circuit MOE in the driver IC chip DIC1 selects the output of the Q terminal of the flip-flop 401 and supplies the switching command signal Hk to be output as the control signal KDR1, and the memory in the driver IC chip DIC2 The circuit MOE supplies a switching command signal Hk that causes the output of the QN terminal of the flip-flop 401 to be selected and output as the control signal KDR2.

  Since the common switch control signal output terminal KDR of the driver IC chips other than the driver IC chips DIC1 and DIC2 is not connected to the common switch control, no matter what signal the common switch control circuit CTR3 outputs, the circuit operation is not performed. There is no influence, and there is no need to control what signal is output.

  FIG. 19 shows the operation of the driving device when a printing operation is performed using an LED head formed by cascading 26 driver IC chips DIC configured as shown in FIG. 8, that is, time taN in FIG. 15 (corresponding to tbA in FIG. 19). It is a time chart showing subsequent operations. FIG. 20 is a time chart in which the number of driver IC chips in the time chart in FIG. 19 is simplified and the waveforms are shown in more detail.

  Prior to the start of the LED time-division driving, at time tbA, the main scanning synchronization signal HD-HSYNC-N (HSYNC in FIG. 20) is input.

  Next, in order to transfer drive data (print data PDo: DOT1, DOT3, DOT5, DOT7, DOT9,... DOT191) of odd-numbered LEDs in the period tbB, the data is synchronized with the clock signal HD-CLK (CLKI in FIG. 20). Signals HD-DATA 3 to 0 are input.

  In this LED head, 26 driver IC chips DIC are cascade-connected as described above, and each driver IC chip DIC is provided with 96 LED drive terminals DO0 to DO96. Print data for four pixels is transferred at a time. During the transfer of the print data, as described with reference to FIG. 14 and as shown in FIG. 19, the enable signal E2 is Low, so that the selection circuit SEL outputs the output of the 23rd flip-flop. This is selected and supplied to the 25th stage flip-flop to form a 24 stage shift register. Therefore, the number of clock pulses necessary for one data transfer is (96/4) × 26 = 24 × 26 = 624, and FIG. 19 shows that 24 × 26 clock pulses are supplied in the period tbB. Show. On the other hand, in FIG. 20, since the number of driver IC chips is simplified as one, 24 clock pulses are supplied in the period tbB.

When the transfer of data for odd-numbered dots of data for one line is completed in the period tbB, a latch signal HD-LOAD (LOAD in FIG. 20) is input as shown at time tbC, and the shift register The data input via the is latched in the latch circuit.
Next, in a period tbD, a strobe signal HD-STB 1 N (STB in FIG. 20) for instructing LED driving is input (the level of the strobe signal HT-STB-N is set to Low).

  As a result, if the drive timing signal DST supplied to the LED drive unit DRV shown in FIG. 13 becomes Low and the print data PDN is also Low (a value indicating that the corresponding LED should be turned on), the NOR circuit 285 Not only does the output become High and the PMOS 284 is turned on, but one or more of the PMOSs 280 to 283 are turned on or none of them are turned on according to the correction data supplied from the terminals DQ3 to DQ0. Is supplied from the DO to the LED. An odd numbered LED and an even numbered LED are connected to DO, but only one of the common switches 109 and 110 (FIG. 2) is turned on by the control signals KDR1 and KDR2. The drive current flows through only one of the odd-numbered LED and the even-numbered LED (only the one connected to the ON side of the common switch control).

  At time tbC, the states of the control signals KDR1 and KDR2 of the common switches 109 and 110 are switched, and the odd-numbered LED elements are driven. That is, in FIG. 19, when the control signal KDR1 from the first stage driver IC chip DIC1 is at a high level and the control signal KDR2 from the second stage driver IC chip DIC2 is at a low level, the MOS 109 in FIG. The MOS 110 is turned off, and a flow path from the cathode terminals of the odd-numbered LED elements 101, 103, 105, and 107 to the ground GND is formed.

  At this time, the MOS 110 is in an off state, and a flow path from the cathode terminals of the even-numbered LED elements 102, 104, 106, 108 and the like to the ground is not formed. For this reason, when an LED drive current flows out from, for example, the DO1 terminal of the driver IC chip DIC1, a current path is formed from the anode and cathode terminals of the LED element 101 to the ground via the drain and source of the MOS 109, and the LED. The element 101 emits light (not shown in FIG. 1) to form an electrostatic latent image on the photosensitive drum, thereby generating printed dots. At this time, since no current flow path is formed in the LED element 102, the light emitting state of the LED 101 is not hindered.

  Returning to FIG. 19 (and FIG. 20), in order to transfer drive data (print data PDe: DOT2, DOT4, DOT6, DOT8, DOT10,... DOT192) of even-numbered LEDs in the period tbE, the clock signal HD-CLK (FIG. 20, data signals HD-DATA3 to 0 are input in synchronization with CLKI).

When the data transfer for the even-numbered dots is completed in the data for one line in the period tbE, the latch signal HD-LOAD (LOAD in FIG. 20) is input as shown at time tbF, and the shift register The data input via the is latched in the latch circuit.
Next, at time tbG, a strobe signal HD-STB-N (STB in FIG. 20) for instructing LED driving is input (strobe signal HD-STB-N is Low).

  At time tbF, the states of the control signals KDR1 and KDR2 of the common switches MOS 109 and 110 are switched, and the even-numbered LED elements are driven. That is, in FIG. 19, when the control signal KDR2 from the second stage driver IC chip DIC2 is at a high level and the control signal KDR1 from the first stage driver IC chip DIC1 is at a low level, the MOS 110 in FIG. The MOS 109 is turned off, and a flow path from the cathode terminals of the even-numbered LED elements 102, 104, 106, 108 to the ground GND is formed.

  On the other hand, the flow path from the cathode terminals of the odd-numbered LED elements 101, 103, 105, 107 and the like to the ground is not formed. For this reason, when an LED drive current flows out from, for example, the DO1 terminal of the driver IC chip DIC1, a current path is formed through the anode and cathode terminals of the LED element 102 to the ground through the drain and source of the MOS 110, and the LED. The element 102 emits light (not shown in FIG. 1) to form an electrostatic latent image on the photosensitive drum, thereby generating printed dots. At this time, since a current path is not formed in the LED element 101, the light emission state of the LED 102 is not hindered.

  In this way, by driving the odd-numbered LED elements and the even-numbered LED elements in order in a time-division manner in the LED element array, by the number of drive elements that is half the number of LED elements in one line, One line of LEDs can be driven.

  FIG. 21 shows the operation of the driving apparatus when supplying correction data to the LED head formed by cascading 24 driver IC chips having the configuration of FIG. 8 and writing data to the correction memory circuit MEM in the driving apparatus. It is a time chart which shows the operation | movement to 15 time taM (it is also shown with the same code | symbol taM also in FIG. 21).

  FIG. 22 to FIG. 25 are time charts showing the waveforms in more detail by simplifying the number of driver IC chips as one in the time chart shown in FIG. 22 shows details of the portions of the periods tcA and tcB in FIG. 21, FIG. 23 shows details of the portions of the periods tcC and tcD in FIG. 21, and FIG. 24 shows details of the portions of the periods tcE and tcF in FIG. FIG. 25 shows details of the portions of the periods tcG and tcH in FIG.

  The differential clock pair signal is representatively shown as HD-CLKI in FIG. 21 and CLKI in FIGS.

The print control unit 1 sets the latch signal HD-LOAD (LOAD in FIGS. 22 to 25) to the high level (taD) at the start of the correction data transfer and writing operations, and the latch signal HD-LOAD is at the high level. It indicates that the data transferred inside is correction data.
The correction data is supplied from the print control unit 1 to the LED head 19 as HD-DATAI3 to HD-DATAI0 (DATAI3 to DATAI0 in FIGS. 22 to 25).

  The correction data is composed of 4 bits per dot, and correction data for odd-numbered and even-numbered dots adjacent to each other is transferred using the same shift register. This is done in steps. In each step, 1-bit correction data is transferred to each odd-numbered dot or each even-numbered dot and stored in the corresponding memory circuit MEM.

  Chip correction data set for each driver IC chip DIC is either correction data transfer for odd-numbered dots (for example, period tcA) or correction data transfer for even-numbered dots (for example, period tcB). But it only needs to be done once. Similarly, the common switch control data Hk includes correction data transfer periods (periods tcA, tcC, tcE, tcG) for odd-numbered dots and correction data transfer periods (period tcB, tcG, even-numbered dots). tcD, tcF, tcH) may be performed only once. In this example, when correction data for odd-numbered dots is transferred, chip correction data Hc and common switch control data Hk are transferred together.

  In the example shown in FIG. 8, the chip correction data Hc is stored in the memory circuit MCM connected to the flip-flop FFD25 in the final stage of the shift register SFRd, and the common switch control data Hk is also in the first and second stage driver ICs. Since it is stored in the memory circuit MOE connected to the flip-flop FFC25 at the final stage of each shift register SFRc of each of the chips DIC1 and DIC2, a column of correction data Ho for all odd-numbered dots in each driver IC chip The chip correction data Hc and the common switch control data Hk or invalid data DMY instead thereof are positioned and transferred in order. Therefore, at the time of transferring correction data Ho for odd-numbered dots, the number of shift register stages is increased by one to switch to 25 stages, and each driver IC chip DIC consists of 25 data bits. 4 bit strings are formed, and 26 driver IC chips are sequentially transferred (4 bit strings each consisting of 25 × 26 data bits are transferred to 26 driver IC chips). . On the other hand, when transferring the column of the correction data He for the even-numbered dots, the shift register is switched to 24 stages, and four bit sequences each including 24 correction data bits for each driver IC chip. The 26 driver IC chips are sequentially transferred (4 bit strings each consisting of 24 × 26 data bits are transferred to the 26 driver IC chips).

  As described above, the number of shift register stages is switched by controlling the selection circuit SEL with the enable signal E2. When the correction data Ho for the odd-numbered dots is transferred, as described with reference to FIGS. 14 and 15, the enable signal E2 is High, thereby switching the shift register to 25 stages. It has been. On the other hand, when the correction data He for the even-numbered dots is transferred, the enable signal E2 is Low as described with reference to FIGS. 14 and 15, so that the shift register has 24 stages. It has been switched to.

  22 to 25, DOTx-by (x = 1 to 192, y = 0, 1, 2, 3) is the correction of the yth bit for the xth dot driven by each driver IC chip. Means data, where x is an odd set of data, or any of them is represented by the symbol Ho, and x is an even set of data, or any of them is represented by the symbol He.

First step:
In the period tcA, the correction data Hc3 of bit3 of the chip correction data Hc, the common switch control data Hk, the invalid data DMY, and the correction data Ho3 of bit3 of the correction data Ho for odd-numbered dots are transmitted.
More specifically, the data DATAI3 is a series of 26 driver IC chips, each of which includes a chip correction data Hc3 positioned at the head for each driver IC chip, followed by a sequence of 24 dot correction data Ho3. Is sent out. FIG. 22 shows only data for the first-stage driver IC chip DIC1.

As the data DATAI2 for the first and second stage driver IC chips, the common switch control data Hk located at the head for each driver IC chip and the subsequent 24 dot correction data Ho3 are sent. The data DATAI2 for the third to 26th driver IC chips is sent as invalid data DMY located at the head for each driver IC chip, followed by a string of 24 dot correction data Ho3. To do. FIG. 22 shows only data for the first-stage driver IC chip DIC1.
As data DATAI1, the invalid data DMY positioned at the head for each driver IC chip and the subsequent 24 dot correction data Ho3 are continuously sent for 26 driver IC chips. FIG. 22 shows only data for the first-stage driver IC chip DIC1.
As data DATAI0, the invalid data DMY positioned at the head for each driver IC chip, followed by a series of 24 dot correction data Ho3, which are continuous for 26 driver IC chips, is transmitted. FIG. 22 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is performed, the enable signal E2 is High and the shift register is switched to 25 stages. When the transfer of these data by the shift register is completed, the three strobe signals HD-STB-N are transferred. (STB in FIG. 22) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to High and the enable signal E2 is switched to Low by the memory control circuit CTR1 in FIG. Then, the memory cell selection signal W3 is generated, and the correction data Hc3, the control data Hk, and the correction data Ho3 are stored. Further, the shift register is switched to 24 stages when the enable signal E2 is changed to Low.

Second step:
In the period tcB, the bit 3 data He3 of the correction data He for the even-numbered dots is transmitted. More specifically, as the data DATAI3, DATAI2, DATAI1, and DATAI0, a series of 24 dot correction data He3, each of which is continuous for 26 driver IC chips, is transmitted. FIG. 22 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is being performed, the enable signal E2 is Low and the shift register is switched to 24 stages, but when the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 22). STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to Low and the enable signal E2 is switched to High by the memory control circuit CTR1 in FIG. A selection signal W3 is generated and correction data He3 is stored. Further, the shift register is switched to 25 stages when the enable signal E2 is changed to High.

Third step:
In period tcC, bit2 correction data Hc2 of chip correction data Hc, invalid data DMY, and bit2 data Ho2 of correction data Ho for odd-numbered dots are transmitted.
More specifically, the data DATAI3 is a series of 26 driver IC chips in which the head correction data Hc2 positioned at the head for each driver IC chip and the subsequent 24 dot correction data Ho2 are continuously arranged. Is sent out. FIG. 23 shows only data for the first-stage driver IC chip DIC1.
As each of the data DATAI2, DATAI1, and DATAI0, the invalid data DMY located at the head for each driver IC chip and the subsequent 24 dot correction data Ho2 columns are continuously connected for 26 driver IC chips, respectively. To send out. FIG. 23 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is performed, the enable signal E2 is High and the shift register is switched to 25 stages, but when the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 23). STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to High and the enable signal E2 is switched to Low by the memory control circuit CTR1 in FIG. A selection signal W2 is generated, and correction data Hc2 and Ho2 are stored. Further, the shift register is switched to 24 stages when the enable signal E2 is changed to Low.

Fourth step:
In period tcD, bit2 data He2 of correction data He for even-numbered dots is transmitted. More specifically, as the data DATAI3, DATAI2, DATAI1, and DATAI0, a series of 24 dot correction data He2 is continuously sent for each of 26 driver IC chips. FIG. 23 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is performed, the enable signal E2 is Low and the shift register is switched to 24 stages, but when the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 23). STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to Low and the enable signal E2 is switched to High by the memory control circuit CTR1 in FIG. The selection signal W2 is generated and the correction data He2 is stored. Further, the shift register is switched to 25 stages when the enable signal E2 is changed to High.

5th step:
In period tcE, bit1 correction data Hc1 of chip correction data Hc, invalid data DMY, and bit1 data Ho1 of correction data Ho for odd-numbered dots are transmitted.
More specifically, the data DATAI3 is a series of the chip correction data Hc1 positioned at the head for each driver IC chip, followed by a series of 24 dot correction data Ho1 for 26 driver IC chips. Is sent out. FIG. 24 shows only data for the first-stage driver IC chip DIC1.
As each of the data DATAI2, DATAI1, and DATAI0, the invalid data DMY located at the head for each driver IC chip and the subsequent 24 dot correction data Ho1 columns are continuously connected for 26 driver IC chips, respectively. To send out. FIG. 24 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is being performed, the enable signal E2 is High and the shift register is switched to 25 stages, but when the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 24). STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to High and the enable signal E2 is switched to Low by the memory control circuit CTR1 in FIG. A selection signal W1 is generated, and correction data Hc1 and Ho1 are stored. Further, the shift register is switched to 24 stages when the enable signal E2 is changed to Low.

Sixth step:
In the period tcF, bit1 data He1 of the correction data He for the even-numbered dots is transmitted. More specifically, as the data DATAI3, DATAI2, DATAI1, and DATAI0, a series of 24 dot correction data He1 is continuously sent for each of 26 driver IC chips. FIG. 24 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is performed, the enable signal E2 is Low and the shift register is switched to 24 stages. When the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 24) are displayed. STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to Low and the enable signal E2 is switched to High by the memory control circuit CTR1 in FIG. The selection signal W1 is generated and the correction data He1 is stored. Further, the shift register is switched to 25 stages when the enable signal E2 is changed to High.

Seventh step:
In period tcG, bit0 correction data Hc0 of chip correction data Hc, invalid data DMY, and bit0 data Ho0 of correction data Ho for odd-numbered dots are transmitted.
More specifically, the data DATAI3 is a series of 26 driver IC chips in which the head correction data Hc0 located at the head for each driver IC chip and the subsequent 24 dot correction data Ho0 are continuously arranged. Is sent out. FIG. 25 shows only data for the first-stage driver IC chip DIC1.
As each of the data DATAI2, DATAI1, and DATAI0, the invalid data DMY located at the head for each driver IC chip and the subsequent 24 dot correction data Ho0 are continuously connected for 26 driver IC chips. To send out. FIG. 25 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is being performed, the enable signal E2 is High and the shift register is switched to 25 stages, but when the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 25). STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to High and the enable signal E2 is switched to Low by the memory control circuit CTR1 in FIG. A selection signal W0 is generated, and correction data Hc0 and Ho0 are stored. Further, the shift register is switched to 24 stages when the enable signal E2 is changed to Low.

Eighth step:
In period tcH, bit 0 data He0 of correction data He for even-numbered dots is transmitted. More specifically, as the data DATAI3, DATAI2, DATAI1, and DATAI0, a series of 24 dot correction data He0, each corresponding to 26 driver IC chips, is transmitted. FIG. 25 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is performed, the enable signal E2 is Low and the shift register is switched to 24 stages. When the transfer of these data is completed, three strobe signals HD-STB-N (FIG. 25) are transferred. STB) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to Low and the enable signal E2 is switched to High by the memory control circuit CTR1 in FIG. A selection signal W0 is generated, and correction data He0 is stored.

  As described above, the correction data Ho, He, Hc and the common switch control data Hk are transferred and stored in the memory by the 8-step operation (the 4-bit correction data for each dot in the memory circuit MEM, the memory circuit). When the 4-bit correction data to the MCM and the 1-bit common switch control data to the memory circuit MOE are written), the print control unit 1 returns the latch signal HD-LOAD signal to Low and the series of sequences is completed.

  The frequency of the clock HD-CLKI differs between correction data transfer (until time taM in FIG. 15) and print data transfer (after time taN in FIG. 15). When correction data is transferred, print data is transferred. It is about ½ compared to the time. The print data transfer is repeated during the printing operation, whereas the correction data transfer is performed only once when the power is turned on. It doesn't matter much.

  FIG. 26 is a circuit formed by cascading the driver IC chips DIC shown in FIG. 8. In order to make it easy to understand the outline of the operation in print data transfer, the first-stage driver IC chip DIC1 and the second-stage driver IC chip. It is the circuit diagram which extracted and described the principal part of DIC2, and corresponds to FIG. 6 about a prior art example. For the sake of common explanation, and in order to make the relationship between the first-stage driver IC chip DIC1 and the second-stage driver IC chip DIC2 easier to understand, the reference numerals are changed. Only one of four shift registers SFRa, SFRb, SFRc, and SFRd provided in parallel in each driver IC chip is shown.

The data input terminal of the first stage driver IC chip DIC1 is abbreviated as DATAI.
The clock signal terminals of the first-stage and second-stage driver IC chips DIC1 and DIC2 are CLKP and CLKN, and the signals for driving them are CLK-P and CLK-N. Since it is a motion signal, only one of them is taken and abbreviated as CLK-P.

DTI1 is a delay circuit of a data input terminal of the driver IC chip DIC1, and corresponds to any one of those indicated by reference numerals 203 to 206 in FIG. Similarly, DTI2 is a delay circuit of the data input terminal of the driver IC chip DIC2.
CK1 corresponds to the combination of the clock input circuit 201 and the buffer circuit 202 shown in FIG. 8 of the driver IC chip DIC1, and this combination is sometimes called a “buffer circuit”. Similarly, CK2 corresponds to a combination of the clock input circuit 201 and the buffer circuit 202 of the driver IC chip DIC2, and this combination may be referred to as a “buffer circuit”.

  FF1 to FF24 are flip-flops, and correspond to the flip-flops FFA1 to FFA23 and FFA25, FFB1 to FFB23 and FFB25, FFC1 to FFC23 and FFC25, or FFD1 to FFD23 and FFD25 in FIG.

  SEL1 is a selection circuit for the driver IC chip DIC1, and corresponds to the selection circuit SEL in FIG. Similarly, SEL2 is a selection circuit corresponding to the selection circuit SEL of the driver IC chip DIC2.

  In FIG. 8, flip-flops FFA24, FFB24, FFC24, and FFD24 are shown. When print data is transferred, outputs from the flip-flops FFA23, FFB23, FFC23, and FFD23 are selected by the selection circuit SEL. Thus, the flip-flops FFA24, FFB24, FFC24, and FFD24 are not shown in FIG.

  In FIG. 26, the buffer circuit CK1 is illustrated in a simplified manner so that the clock terminals of the 24 flip-flops FF1 to FF24 are driven. In practice, however, a total of 100 flip-flop elements are formed by the buffer circuit CK1. Driven.

  Similarly, FF25 to FF48 are flip-flops provided in the driver IC chip DIC2, and the flip-flops FFA1 to FFA23 and FFA25, FFB1 to FFB23 and FFB25, FFC1 to FFC23 and FFC25, or FFD1 to FFD23 and FFD25 in FIG. It corresponds to.

  DTO1 is an output buffer of the driver IC chip DIC1, and corresponds to any one of those indicated by reference numerals 207 to 210 in FIG. Similarly, DT02 is an output buffer corresponding to one of the output buffers 207 to 210 of the driver IC chip DIC2.

FIG. 27 is a time chart showing the operation of the circuit of the first embodiment shown in FIG.
It is desirable that the clock CK1 generated from the buffer circuit CK1 in the driver IC chip DIC1 and the clock CK2 generated from the buffer circuit CK2 in the driver IC chip DIC2 are synchronized. Due to variations, there is a slight deviation. This deviation is, for example, 1 nsec. This is sufficiently smaller than the sum (for example, 10 nsec. Or more) of the delay TDO in the output buffer DTO1 or DTO2, the delay TDI in the input buffer DTI1 or DTI2, and the delay TFF in the flip-flop FF.

27, data d48 is input to the DATAI terminal, which is a data input signal of the LED head, at time tdA, and subsequently data d49, d50,...
Further, the transfer clock signal of the data string composed of the data d48, d49, d50,... Is CLK-P, and the time tdB of the falling edge of the transfer clock signal CLK-P every cycle TCLK of the transfer clock signal CLK-P. In addition, data is taken into the shift register.
At this time, the setup time of the data input signal DATAI is shown in the drawing as Ts0 and hold time Th0.

  The data input signal DATAI input to the driver IC chip DIC1 is delayed by time TDI by the delay circuit DTI1. The output DTI1 of the delay circuit DTI1 is sequentially input to the flip-flop FF1 as a data string including data d48, d49, d50,.

  On the other hand, the clock signal CLK-P is delayed by a certain time TCK by the buffer circuit CK1 and input to the flip-flops FF1 to FF24.

  At the input part of the flip-flop FF1, the data signal and the clock signal are delayed by the time indicated by TDI and TCK, respectively, and the setup time and hold time of the data signal with respect to the falling edge of the clock signal are Ts1, Th1.

In order to obtain the relationship between the setup time Ts0 and the hold time Th0 in the signal input unit (input connector unit) of the LED head, considering the time tdA as a starting point, the conventional example is similar to that described with reference to FIG. The following formula (1) is obtained.
Ts0 + TCK-Ts1-TDI = 0 (1)
Further, considering the time tdB as a starting point, the following equation (2) is obtained in the same manner as the conventional example described with reference to FIG.
Th0 + TDI-Th1-TCK = 0 (2)
By arranging these, the following equations (3) and (4) are obtained in the same manner as the conventional example described with reference to FIG.
Ts1 = Ts0 + TCK−TDI (3)
Th1 = Th0 + TDI−TCK (4)

  On the other hand, the output signal of the flip-flop changes after a certain time TFF from the clock signal CK1 in the driver IC chip DIC1. In FIG. 27, data d47, d48, d49, d50,... Are output as the output data string of the flip-flop FF1, and data d24, d25, d26, d27,. It is shown.

The output signal of the flip-flop FF24 (FFA25, FFB25, FFC25, FFD25 in FIG. 8) is output as an output waveform DTO1 with a TDO delay by the output buffer circuit DTO1 (207 to 210 in FIG. 8) of the driver IC chip DIC1.
This signal is input to the driver IC chip DIC2 at the next stage, and is output with a delay of time TDI by the delay circuit DTI2 in the driver IC chip DIC2.

  On the other hand, the clock signal input to the driver IC chip DIC2 is delayed by TCK by the buffer circuit CK2 and input to the flip-flops FF25 to FF48.

When the data setup time Ts2 at the input part of the flip-flop FF25 of the driver IC chip DIC2 is obtained, the following equation (8) is obtained with the time tdB as a starting point.
TCK + TFF + TDO + TDI + Ts2-TCLK-TCK = 0 (8)
Organize
Ts2 = TCLK− (TFF + TDO + TDI) (9)
It becomes.

In order to operate the flip-flop normally, it is necessary to secure a desired setup time Ts and hold time Th.
In data transfer between the first-stage driver IC chip DIC1 and the second-stage driver IC chip DIC2, it is necessary to give a desired setup time to the flip-flop at the shift register input stage of the second-stage driver IC chip DIC2. Yes, if Ts2> 0,
TCLK> TFF + TDO + TDI (10)
It becomes.
The same applies to data transfer between the driver IC chips of the i-th stage (i is any one of 2 to 24) (and the (i + 1) -th) driver IC chip.

Under the configuration according to the prior art, TCLK> TFF + TSEL + TDO + TDI (7)
Compared to the above, it can be seen that the delay time TSEL by the selection circuit is reduced, so that the limit value of the clock cycle can be shortened and the maximum operation clock frequency can be increased.

In the LED head formed by cascading driver IC chips in the configuration of the first embodiment, the condition to be satisfied by the clock cycle at the time of data transfer is TCLK> TFF + TDO + TDI (10)
Under the configuration according to the prior art, TCLK> TFF + TSEL + TDO + TDI (7)
Compared to the above, since the delay time TSEL by the selection circuit is reduced, the limit value of clock synchronization can be shortened, and the maximum operating clock frequency can be greatly increased.

  The reason why the delay time TSEL by the selection circuit can be reduced is that the flip-flops are operated simultaneously by the clocks CK1 and CK2. That is, the selection circuit SEL also has a delay time TSEL in this embodiment, but the 25th stage flip-flops FFA25, FFB25, FFC25, and FFD25 that receive the output of the selection circuit are also the 1st to 24th stage flip-flops. Even if there is a delay time due to the selection circuit, the operation of the flip-flop is not affected.

  As described above, the dot (LED) of each driver IC chip is divided into odd-numbered dots and even-numbered dots, and the common switch 109 for odd-numbered dots and the common switch 110 for even-numbered dots are respectively provided. The case of driving at different timing and transferring correction data for odd-numbered dots and correction data for even-numbered dots at different timings has been described. The present invention can also be applied to the case of dividing into two groups by this method.

Embodiment 2. FIG.
FIG. 28 is a block diagram showing a detailed configuration of the driver IC chip according to the second embodiment. The driver IC chip shown in FIG. 28 can be used instead of the driver IC chip shown in FIG. 3, and a plurality of driver IC chips shown in FIG. An LED head similar to that described with reference to FIG. 1 can be configured, and an image forming apparatus similar to that described with reference to FIG. 1 can be configured using such an LED head. The driver IC chip shown in FIG. 28 is generally the same as the driver IC chip shown in FIG. 3, but there are differences as will be understood from the following description. In addition, about the point which is the same, some description is abbreviate | omitted.

FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are flip-flops, and constitute four mutually parallel shift registers SFRa, SFRb, SFRc, and SFRd.
SEL is a selection circuit.
LTA1 to LTD1,... LTA24 to LTD24 are latch elements, and constitute a latch circuit as a whole.

  MEM is a memory circuit (the same sign is assigned to (24 × 4) memory circuits), and the memory circuit MEM has correction data (dot correction data) for correcting the variation in the amount of light of the LEDs. Stored. The correction data for each chip stored in the memory circuit MEM is also read at the time of printing and used for correcting the LED drive current.

  Each of the memory circuits MEM stores correction data of odd-numbered and even-numbered LEDs (dots) adjacent to each other, and can be read from two sets of data output terminals Mo and Me. As shown in FIG. 9, the set Mo of data output terminals comprises terminals Mo0, Mo1, Mo2, and Mo3, and outputs 4-bit dot correction data Ho3, Ho2, Ho1, and He0 in parallel. The set Me of data output terminals includes terminals Me0, Me1, Me2, and Me3, and outputs 4-bit dot correction data He3, He2, He1, and He0 in parallel.

  The MCM is a memory circuit that stores light amount correction data (chip correction data) or chip correction data Hc for each LED array chip, and can be read from the data output terminal Mc. As described above with reference to FIG. 10, the set of data output terminals Mc includes terminals Mc0, Mc1, Mc2, and Mc3, and outputs 4-bit correction data Hc3, Hc2, Hc1, and Hc0 in parallel. . The chip correction data Hc stored in the memory circuit MCM is also read out at the time of printing and used for correcting the LED driving current.

  The MOE is also a memory circuit, and the memory circuit MOE stores data (common switch control data) Hk for determining the value of the common switch control signal KDR output from the common switch control signal output terminal KDR of the driver IC chip. Is done. Data Hk stored in the memory circuit MOE is read at the time of printing (when the LED is driven based on the print data) and used to generate the common switch control signal KDR.

  MUX is a multiplexer circuit (the same sign is assigned to (24 × 4) multiplexer circuits), each of which is read from the two output terminals Mo and Me of the corresponding memory circuit MEM. A set of correction data (that is, correction data Ho (consisting of Ho3, Ho2, Ho1, Ho0) for odd-numbered dots and correction data He (consisting of He3, He2, He1, He0) for even-numbered dots ) Is received by two sets of input terminals Xo and Xe, and one of them is selected and output from the output terminal XQ.

As shown in FIG. 12, the data input terminal set Xo includes four terminals Xo3, Xo2, Xo1, and Xo0, and inputs 4-bit dot correction data Ho3, Ho2, Ho1, and Ho0 in parallel. The data input terminal set Xe is composed of four terminals Xe0, Xe1, Xe2, and Xe3, and inputs 4-bit dot correction data He3, He2, He1, and He0 in parallel.
A set XQ of data output terminals includes four terminals XQ3, XQ2, XQ1, and XQ0, and outputs selected 4-bit correction data in parallel.

  DRV is an LED drive unit, and the latch elements LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, LTD1 to LTD24 (with the same reference numerals attached to (24 × 4) LED drive units) Based on the blinking data from the corresponding one and the correction data supplied from the corresponding multiplexer circuit MUX, the LED driving current is output.

CTR1 is a first control circuit, and generates write command signals (memory cell selection signals W0 to W3 and enable signals E1 and E2) when correction data is written to the memory circuit MEM and the memory circuit MCM. As will be described later, the enable signal E2 is used to control the selection circuit SEL, but is also used to control memory writing, and is therefore referred to as an “enable signal” for convenience. The first control circuit CTR1 is also called a memory control circuit.
Writing of the common switch control data to the memory circuit MOE is controlled by any one of the memory cell selection signals W0 to W3, for example, W3.
CTR2 is a second control circuit, which is a data selection signal (switching command signal) S1P, S1N, S2P, S2N of data for odd-numbered dots and data for even-numbered dots to the multiplexer circuit MUX. Is generated. The second control circuit CTR2 is also called a multiplexer control circuit.
CTR3 is a third control circuit and generates a common switch control signal KDR. The third control circuit is also called a common switch control circuit.

  ADJ is a control voltage generation circuit that receives a reference voltage value VREF input from a reference voltage terminal VREF and generates a control voltage Vcont for LED driving. At this time, the value of the control voltage is corrected based on the correction data supplied from the memory circuit MCM via the terminal Mc. The reference voltage value VREF is generated by a regulator circuit (not shown), and the reference voltage VREF may be kept at a predetermined value even in a situation where the power supply voltage drops momentarily as in the case of driving all the LEDs on. The LED driving current is not reduced.

Reference numeral 201 denotes an input circuit for small-amplitude differential signals CLK-P and CLK-N for converting the small-amplitude signals CLK-P and CLK-N into logic amplitude signals used inside the driver IC chip.
A buffer circuit 202 receives a signal from the input circuit 201 and drives a clock signal CK of a shift register including flip-flops FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25. Since the buffer circuit 202 drives a large number of flip-flops, it has a large driving capability and a relatively large delay time.

  Reference numerals 331 to 334 denote delay circuits, which also give the data signal a delay time substantially equal to the signal delay by the small amplitude differential input circuit 201, the buffer circuit 202, etc. In order to prevent a significant difference in signal delay, the supply of the clock signal and the supply of the data signal have an appropriate timing (phase) relationship for each flip-flop FF.

  207 to 210 are buffer circuits, which receive output signals from the Q terminals of the flip-flops FFA25, FFB25, FFC25, and FFD25, and drive the data output terminals DATAO3 to DATAO0.

Reference numeral 211 denotes a resistor, which is connected between the strobe terminal STB and the power supply VDD to constitute a pull-up element.
Reference numeral 335 denotes a resistor, which is connected between the delay time selection signal terminal DLY and the power supply VDD to constitute a pull-up element.
212 and 213 are inverter circuits, and 214 is a NAND circuit.

  The flip-flops FFA1 to FFA25 are cascade-connected, the data input terminal DATAI0 of the driver IC chip is connected to the D terminal of the flip-flop FFA1 via the delay circuit 331, and the output (flip-flop FFA24) from the Q terminal of the flip-flop FFA23. And the output from the Q terminal of the flip-flop FFA24 are input to the input terminals A0 and B0 of the selection circuit SEL and correspond to these input terminals (that is, either of the inputs to these input terminals). The output terminal YO is connected to the D terminal of the flip-flop FFA25, and the output from the Q terminal of the flip-flop FFA25 is connected to the data output terminal DATAO0 of the driver IC chip via the buffer circuit 207. Yes.

  Similarly, the flip-flops FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are also cascade-connected, and the data input terminals DATAI1, DATAI2, and DATAI3 of the driver IC chip are flip-flops FFB1, FFC1 via delay circuits 332 to 334, respectively. , FFD1 is connected to the D terminal.

  Outputs from the Q terminals of the flip-flops FFB23 and FFB24, flip-flops FFC23 and FFC24, and flip-flops FFD23 and FFD24 are also connected to the input terminals A1, B1, A2, B2, A3, and B3 of the selection circuit SEL, and outputs corresponding thereto. The terminals Y1, Y2, and Y3 are connected to the D terminals of the flip-flops FFB25, FFC25, and FFD25, respectively, and the output from the Q terminal of the flip-flops FFB25, FFC25, and FFD25 is output to the driver IC chip through the buffer circuits 208 to 210. The terminals DATAO1, DATAO2, and DATAO3 are connected to each other.

  Accordingly, the flip-flops FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 constitute shift registers SFRa, SFRb, SFRc, and SFRd each having 25 stages of cascaded flip-flops. The number of shift stages can be switched between 24 and 25 by the circuit SEL.

  The selection circuit SEL performs the above selection operation under the control of the enable signal E2. That is, when the enable signal E2 is High, the input terminals B0 to B3 are connected to the output terminals Y0 to Y3, the shift registers SFRa, SFRb, SFRc, and SFRd are operated as a 25-stage shift register, and the enable signal E2 is When Low, the input terminals A0 to A3 are connected to the output terminals Y0 to Y3, and the shift registers SFRa, SFRb, SFRc, and SFRd are operated as a 24-stage shift register.

Data output terminals DATAO0 to DATAO3 of the stages other than the last stage among the 26 stages of cascaded driver IC chips, i.e., the i-th stage (i is any one of 1 to 25) driver IC chip DICi are connected to the next stage ( The driver IC chip DIC (i + 1) of the (i + 1) th stage is connected to the data input terminals DATAI0 to DATAI3.
Accordingly, the flip-flops FFA1 to FFA25 of the driver IC chips DIC1 to DIC26 shift the data signal HD-DATA0 input from the print control unit 1 to the first stage driver IC chip DIC1 in synchronization with the clock signal or 24 × 26 stages. A 25 × 26 stage shift register SFRa is configured.

  Similarly, the flip-flops FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 of the driver IC chips DIC1 to DIC26 are supplied with data signals HD-DATA1, HD-DATA2, 24 × 26 stage or 25 × 26 stage shift registers SFRb, SFRc, and SFRd are configured to shift the HD-DATA 3 in synchronization with the clock signal.

The latch elements LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, LTD1 to LTD24 are latched by a latch signal LOAD-P. The latch elements LTA1 to LTA24 latch the data signal HD-DATA0 stored in the flip-flops FFA1 to FFA23 and FFA25.
Similarly, the latch elements LTB1 to LTB24 latch the data signal HD-DATA1 stored in the flip-flops FFB1 to FFB23 and FFB25.
The latch elements LTC1 to LTC24 latch the data signal HD-DATA2 stored in the flip-flops FFC1 to FFC23 and FFC25.
The latch elements LTD1 to LTD24 latch the data signal HD-DATA3 stored in the flip-flops FFD1 to FFD23 and FFD25.

The NAND circuit 214 receives the strobe signal HD-STB-N input to the terminal STB and the latch signal LOAD-P input from the load terminal LOAD via the inverter circuits 212 and 213, respectively, and the LED driver DRV A signal (driving timing signal) DST for determining the driving timing of the LED is generated.
The drive timing signal DST is Low when both the strobe signal HD-STB-N and the latch signal LOAD-P are Low, and at this time, the LED is driven by the LED drive unit DRV.

  The control terminals of the delay circuits 331 to 334 are connected to the delay time selection signal terminal DLY.

FIG. 29 is a diagram showing the structure of an LED head using the driver IC chip shown in FIG.
Also in this embodiment, an LED head capable of printing at a resolution of 600 dots per inch on A4 size paper is assumed. In this case, the total number of LED elements is 4992 dots, and for example, 26 LED array chips each having 192 LED elements are arranged linearly.

  However, in FIG. 29, for simplification of illustration, only two LED array chips CHP1 and CHP2 and two driver IC chips DIC1 and DIC2 arranged corresponding to these are shown. In other words, the third to 26th LED array chips CHP3 to CHP26 and the third to 26th driver IC chips DIC3 to DIC26 are not shown. The LED array chips CHP1 to CHP26 are configured by the same circuit, and the driver IC chips DIC1 to DIC26 are configured by the same circuit and are cascade-connected to each other.

101-108 are LED elements, and 192 are arranged for each LED array chip.
The drain of the power MOS 109 constituting the first common switch is connected to the cathodes of the LEDs 101, 103, 105, 107, etc., and the drain of the power MOS 110 constituting the second common switch is the cathode of the LEDs 102, 104, 106, 108, etc. Connected with. The sources of the power MOSs 109 and 110 are connected to the ground.

  Thus, the odd-numbered LED elements 101,... 103, 105,... 107 in each LED array CHP1, CHP2 are connected to each other, that is, all connected to the common cathode node CCo. It is connected to the ground GND via the MOS 109. On the other hand, the cathodes of the even-numbered LED elements 102,... 104, 106,... 108 are connected to each other, that is, all are connected to the common cathode node CCe, and the common cathode node CCe is connected to the ground GND through the power MOS 110. By turning on the first common switch 109 and the second common switch 110 at different timings, the odd-numbered LED elements 101, ... 103, 105, ... 107 and the even-numbered LED elements 102, ... 104 , 106... 108 are time-division driven.

  The delay time selection signal terminal DLY of the first-stage driver IC chip DIC1 is connected to the ground, and the delay time selection signals of the second and subsequent driver IC chips DIC2 to DIC26 (only DIC2 is shown in FIG. 29). The terminal DLY is opened. The delay time selection signal terminal DLY (the level of the delay time selection signal) of the driver IC chip DIC connected to the ground GND becomes the Low level. On the other hand, as described above, since the input of the delay time selection signal terminal DLY is pulled up to VDD inside the driver IC chips DIC1 to DIC26, the delay time of the driver IC chip DIC with the delay time selection signal terminal DLY opened. The selection signal terminal DLY (the level of the delay time selection signal) is High.

The power MOS 109 has a gate connected to the common switch control signal output terminal KDR of the first stage driver IC chip DIC1, and is supplied from the common switch control signal output terminal KDR of the first stage driver IC chip DIC1. Controlled by signal KDR1.
The power MOS 110 has its gate connected to the common switch control signal output terminal KDR of the second stage driver IC chip DIC2, and the control signal KDR2 supplied from the common switch control signal output terminal KDR of the second stage driver IC chip DIC2. Controlled by

  In the configuration shown in FIG. 29, four (four) print data signals HD-DATA 3 to 0 are input and used to drive each LED element. The odd-numbered LED elements and the even-numbered LED elements are driven in a time division manner. Therefore, among the eight adjacent LED elements, the data for four odd-numbered or even-numbered pixels can be simultaneously transmitted for each clock signal HD-CLK.

  Therefore, the print data signals HD-DATA 3 to 0 output from the print control unit 1 are input to the LED head 19 together with the clock signal HD-CLK, and have been described with reference to FIG. 8 in connection with the first embodiment. Similarly, the dot data for 4992 dots is sequentially transferred through four shift registers provided in parallel in each of the driver IC chips DIC1 and DIC2. In this sequential transfer, for example, dot data of all odd-numbered dots (2496 dots) is transferred first, and then dot data of all even-numbered dots (2496 dots) are transferred.

When the transfer of dot data of all odd-numbered dots is completed, the latch signal HD-LOAD is input to the LED head 19 (HD-LOAD is set to High), and these dot data are stored in a plurality of stages constituting the shift register. Latches are respectively latched by latch elements provided corresponding to the flip-flops.
When the transfer of dot data of all even-numbered dots is completed, the latch signal HD-LOAD is input to the LED head 19 (HD-LOAD is set to High), and these dot data are stored in a plurality of stages constituting the shift register. Latches are respectively latched by latch elements provided corresponding to the flip-flops.

  When the dot data latches for all the odd-numbered dots and the dot data for all the even-numbered dots are finished, the data for all the dots are aligned (when latched), the dot data and the print drive signal ( With the strobe signal HD-STB-N, among the light emitting elements (LEDs in the present example), those corresponding to dot data at a high (high) level are turned on. Note that VDD is a power supply, and GND is a ground (ground potential node).

HD-HSYNC-N is the above-described main scanning synchronization signal, and a period from when this main scanning synchronization signal HD-HSYNC-N is generated once to when it is generated next can be called a main scanning period. In one main scanning period, 1-bit print data, that is, 26 × 24 × 4 × 2 (= 4992) bits in total is transferred to each of all LED elements. For example, 26 × 24 × 4 (= 2496) -bit print data for odd-numbered dots is transferred in the first half of each main scanning period, and 26 × 24 × 4 (= 2496) for even-numbered dots in the second half. ) Bit print data is transferred.
VREF is a reference voltage for instructing a driving current value for LED driving, and is generated by a reference voltage generating circuit (not shown) provided in the LED head 19.

30 is a circuit diagram showing a configuration of each of delay circuits 331 to 334 shown in FIG.
Reference numerals 351 to 359 denote inverter circuits, 360 and 361 denote AND circuits, and 362 denotes an OR circuit.
The inverter circuits 351 to 357 are connected in series to constitute an inverter chain.
The input terminal Da of the delay circuit is connected to the input of the inverter 351.
One input terminal of the AND circuit 360 is connected to the output of the inverter 357, and the other input terminal is connected to the output of the inverter 359.
One input terminal of the AND circuit 361 is connected to the output of the inverter 351, and the other input terminal is connected to the delay time selection signal terminal DLY of the delay circuit.
The input terminal of the inverter 359 is connected to the delay time selection signal terminal DLY of the delay circuit.
Two input terminals of the OR circuit 362 are connected to output terminals of the AND circuits 360 and 361, respectively.
The output terminal of the OR circuit 362 is connected to the input terminal of the inverter 358, and the output of the inverter 358 is connected to the output terminal Dy of the delay circuit.

FIG. 31 shows a modification of the delay circuit that can be used in place of the delay circuit shown in FIG. 30 as each of the delay circuits 331 to 334 shown in FIG.
351 to 359 are inverter circuits, and 351 to 357 are connected in series to constitute an inverter chain.
Reference numerals 370 and 371 denote transmission gate circuits.
The input terminal Da of the delay circuit is connected to the input of the inverter 351.

The first main terminal of transmission gate circuit 370 is connected to the output terminal of inverter 357, the first main terminal of transmission gate circuit 371 is connected to the output terminal of inverter 351, and the second main terminals of transmission gate circuits 370 and 371 are connected. The main terminals are connected to each other, connected to the input terminal of the inverter 358, and the output of the inverter 358 is connected to the output terminal Dy of the delay circuit.
The input terminal of the inverter 359, the PMOS side gate terminal of the transmission gate circuit 370, and the NMOS side gate terminal of the transmission gate circuit 371 are connected to the delay time selection signal terminal DLY of the delay circuit, and the NMOS side gate terminal of the transmission gate circuit 370 The PMOS side gate terminal of the transmission gate circuit 371 is connected to the output of the inverter circuit 359.

  In the delay circuit shown in FIG. 30 and FIG. 31, a plurality of inverter circuits are connected in cascade, and the number of connection stages thereof can be switched. However, the inverter circuit is a kind of buffer circuit, and FIG. The delay circuit shown in FIG. 6 can be configured by connecting the buffer circuits other than the inverter circuit in cascade and switching the number of stages.

  In the circuit formed by cascading the driver IC chips DIC shown in FIG. 28, the main parts of the first stage driver IC chip and the second stage driver IC chip are shown in order to make it easy to understand the outline of the operation in print data transfer. The circuit diagram extracted and described is the same as FIG. However, the delay time is different between the delay circuit DTI1 in the first-stage driver IC chip and the delay circuit DTI2 in the second-stage driver IC chip DIC2.

FIG. 32 is a time chart showing the operation of the circuit of the second embodiment shown in FIG.
Unlike FIG. 27, the delay time of the delay circuit DTI1 is indicated by TDI1, and the delay time of the delay circuit DTI2 is indicated by TDI2.

32, data d48 is input to the DATAI terminal, which is a data input signal of the LED head, at time teA, followed by data d49, d50,.
Further, the transfer clock signal of the data string composed of the data d48, d49, d50,... Is CLK-P, and the time teB of the falling edge of the transfer clock signal CLK-P for every cycle TCLK of the transfer clock signal CLK-P. In addition, data is taken into the shift register.
At this time, the setup time of the data input signal DATAI is shown in the drawing as Ts0 and hold time Th0.

  The data input signal DTAT1 input to the driver IC chip DIC1 is delayed by time TDI1 by the delay circuit DTI1. The output DTI1 of the delay circuit DTI1 is sequentially input to the flip-flop FF1 as a data string including data d48, d49, d50,.

  As is apparent from FIG. 30 showing the configuration of the delay circuit, in the delay circuits DTI1 and DTI2 according to the present embodiment, when the signal level of the delay time selection signal terminal DLY is Low, the number of stages of the inverter chain is set to eight. When the delay time is lengthened and the signal level of the delay time selection signal terminal DLY is High, the number of stages of the inverter chain is set to two, so that the delay time can be shortened, that is, the switching can be performed, whereby the delay circuit DTI1, The signal delay time due to DTI2 can be switched between two stages. As shown in FIG. 28, the delay time selection signal terminal DLY of each driver IC chip DIC is connected to the power supply VDD by the pull-up resistor 335. Therefore, when the delay time selection signal terminal DLY is open, The potential becomes High, and when the delay time selection signal terminal DLY is grounded, the potential becomes Low. In the present embodiment, as described above, in the first-stage driver IC chip DIC1, the delay time selection signal terminal DLY is grounded, the delay time of the delay circuit DT1 (331 to 334) is increased, and the second stage In the driver IC chips DIC2, DIC3,... After the first, the delay time selection signal terminal DLY is opened to shorten the delay time of the delay circuit DT2 (331 to 334).

  On the other hand, the clock signal CLK-P is delayed by a certain time TCK by the buffer circuit CK1 and input to the flip-flops FF1 to FF24.

  At the input portion of the flip-flop FF1, the data signal and the clock signal are delayed by the time indicated by TDI1 and TCK, respectively, and the setup time and hold time of the data signal with respect to the falling edge of the clock signal are Ts1, Th1. It becomes.

In order to obtain the relationship between the setup time Ts0 and the hold time Th0 in the signal input portion (input connector portion) of the LED head, the following equation is obtained when the time teA is considered as the starting point.
Ts0 + TCK-Ts1-TDI1 = 0 (1A)
Further, considering the time teB as a starting point, the following equation (2A) is obtained.
Th0 + TDI1-Th1-TCK = 0 (2A)
By arranging these, the following equations (3A) and (4A) are obtained.
Ts1 = Ts0 + TCK−TDI1 (3A)
Th1 = Th0 + TDI1-TCK (4A)

  On the other hand, the output signal of the flip-flop changes after a certain time TFF from the clock signal CK1 in the driver IC chip DIC1. 32, d47, d48, d49, d50,... Are output as the output data sequence of the flip-flop FF1, and d24, d25, d26, d27,. ing.

The output signal of the flip-flop FF24 (FFA25, FFB25, FFC25, and FFD25 in FIG. 28) is output as an output waveform DTO1 after being delayed by a time TDO by the output buffer circuit DTO1 (207 to 210 in FIG. 28) of the driver IC chip DIC1. .
This signal is input to the driver IC chip DIC2 at the next stage, and is output with a delay of time TDI2 by the delay circuit DTI2 in the driver IC chip DIC2.

As described with reference to FIG. 29, the delay time selection signal terminal DLY of the driver IC chip DIC1 is set to the Low level, and the delay time selection signal terminals DLY of the driver IC chips DIC2 to DIC26 are set to the High level.
As described with reference to FIG. 30, by setting the delay time selection signal terminal DLY of the driver IC chip DIC2 to the high level, the number of stages of the inverter chain provided therein is switched to two.

  On the other hand, the clock signal input to the driver IC chip DIC2 is delayed by a certain time TCK by the buffer circuit CK2, and input to the flip-flops FF25 to FF48.

When the data setup time Ts2 at the input part of the flip-flop FF25 of the driver IC chip DIC2 is obtained, the following equation (8B) is obtained with the time teB as a starting point.
TCK + TFF + TDO + TDI2 + Ts2-TCLK-TCK = 0 (8B)
Organize
Ts2 = TCLK− (TFF + TDO + TDI2) (9B)
It becomes.

Note that the driver IC chips DIC1 and DIC2 in FIG. 26 are chips having the same circuit configuration, and although there are some characteristic variations for each chip, the characteristic difference is small when viewed in the same head unit. .
Therefore, the delay times of the buffer circuits CK1 and CK2 in FIG. 26 are simplified to be substantially the same, and are shown as TCK in FIG.

Similarly, when the data hold time Th2 at the input part of the flip-flop FF25 of the driver IC chip IC2 is obtained, the following equation (9C) is obtained with the time teC as a starting point.
TFF + TDO + TDI2-Th2 = 0 (9C)
Organize
Th2 = TFF + TDO + TDI2 (9D)
Get.

In order to operate the flip-flop normally, it is necessary to secure a desired setup time Ts and hold time Th at the input portion of the flip-flop.
In data transfer between the first-stage driver IC chip DIC1 and the second-stage driver IC chip DIC2, it is necessary to give a desired setup time to the flip-flop at the shift register input stage of the second-stage driver IC chip DIC2. Yes, if Ts2> 0,
TCLK> TFF + TDO + TDI2 (10B)
It becomes.
The same applies to data transfer between the driver IC chips of the i-th stage (i is any one of 2 to 24) (and the (i + 1) -th) driver IC chip.

Under the configuration of the prior art,
TCLK> TFF + TSEL + TDO + TDI (7)
Compared to the above, it can be seen that the delay time TSEL by the selection circuit is reduced, so that the limit value of the clock cycle can be shortened and the maximum operation clock frequency can be increased.

  In addition, in the configuration of the second embodiment, the delay time TDI2 can be shortened by setting the number of inverter chain stages of the delay circuit in the driver IC chips in the second and subsequent stages of the cascade connection, thereby shortening the clock cycle. The maximum operating clock frequency can be increased.

As described above in detail, in the configuration of the second embodiment, the condition for data transfer by cascaded driver IC chip arrays is TCLK> TFF + TDO + TDI2 (10B)
Under the configuration according to the prior art, TCLK> TFF + TSEL + TDO + TDI (7)
Compared to the above, since the delay time TSEL by the selection circuit is reduced, the limit value of the clock cycle can be shortened, and the maximum operation clock frequency can be increased.
In addition, in the configuration of the second embodiment, the delay time TDI2 can be shortened by setting the number of inverter chain stages of the delay circuit in the driver IC chips in the second and subsequent stages of the cascade connection, thereby further reducing the clock cycle. The maximum operating clock frequency can be further increased.

Embodiment 3 FIG.
The third embodiment relates to the terminal arrangement of the driver IC chip provided with the driving device shown in the second embodiment.

FIG. 33 is a schematic plan view showing the arrangement of terminals of the driver IC chip DIC shown in FIG.
In the configuration of FIG. 33, in order to perform time-division driving by dividing 192 LED elements into two, 96 LED driving terminals DO1 to DO96 are provided, and driving provided in one-to-one correspondence with the terminals. Part DRV.

In FIG. 28, 121 indicates the outer shape (contour) of the surface on which the terminal pads of the driver IC chip are formed. As illustrated, the surface of the driver IC chip on which the terminal pad is formed is generally rectangular, and a pair of long sides, that is, a first long side 121a and a second long side 121b, and a pair of short sides, That is, it has the 1st short side 121c and the 2nd short side 121d.
DO1 to DO96 are LED drive terminal pads, which are arranged along the first long side 121a.
122, 123, and 124 are VDD power supply terminal pads,
Reference numeral 125 denotes a VDD power supply wiring, a portion 125a disposed on an insulating layer located on the LED drive unit DRV disposed adjacent to the LED drive terminal pads DO1 to DO96, a VDD power supply terminal pad 122, It has branch portions 125b, 125c, and 125d for connecting to 123 and 124, and is formed of a substantially E-shaped strip-shaped wiring.
Reference numeral 126 denotes pads other than the VDD power supply terminal pads 122, 123, and 124, that is, DATAI0 to DATAI3, DATAO3 to DATAO0, HSYNC, LOAD, CLKP, CLKN, GND, VREF, STB, KDR, etc. The whole terminal pad (control terminal pad, power supply terminal pad) for this purpose. The pads 122, 123, 124, and 126 are arranged along the second long side 121b of the driver IC chip DIC.
The data input terminals DATAI0 to DATAI3 are arranged in a portion close to the first short side 121c, and the data output terminals DATAO0 to DATAO3 are arranged in a portion close to the second short side 121d.

DLY is an input terminal for a delay time selection signal of the delay circuit, and is arranged at the first short side of the driver IC chip 121 (the short side closer to the portion where the data input terminals DATAI0 to DATAI3 are provided) 121c. ing.
This arrangement is advantageous in that, when a plurality of driver IC chips DIC are cascade-connected, the bonding wires that connect the input terminal DLY and the ground pad 382 can be arranged without obstruction.

  In FIG. 33, the input terminal DLY is arranged in the vicinity of the LED drive terminals DO1 to DO96, that is, on the first long side 121a side, but on the terminal pad 124 side other than the LED drive terminals DO1 to DO96, that is, It is also possible to arrange it on the second long side 121b side.

FIGS. 34A to 34C show the configuration of an LED head configured by cascading a plurality of LED drivers (that is, driver chips having the same configuration) shown in FIG.
34 (a) is a schematic plan view schematically showing the overall configuration of the printed circuit board of the LED head, FIG. 34 (b) is a partially enlarged schematic plan view showing a connection state between the driver IC chip and the LED array, and FIG. (C) is a schematic sectional drawing which follows the 34C-34C line | wire of FIG.34 (b).

Reference numeral 151 denotes a printed wiring board on which the circuit wiring of the LED head is formed. Reference numeral 152 denotes a row of driver IC chips, which includes driver IC chips DIC1 to DIC26. In FIG. 34B, three driver IC chips DIC1 to DIC3 are provided. The portion of is shown enlarged.
Reference numeral 153 denotes a row of LED array chips, and the portion of the LED array chips CHPI to CHP3 in FIG. 34B is enlarged.
Reference numeral 150 denotes an LED head connector terminal, which includes an LED head control signal and a power supply terminal.

  As shown in FIG. 34 (a), when a plurality of, for example, 26 driver IC chips are arranged in a straight line for cascade connection, any one of the stages other than the last stage (i-th stage ( When 26 driver IC chips are cascade-connected, i is 1 to 25)), and the second short side 121d of the driver IC chip is the second stage (i + 1) stage driver IC chip. Adjacent to one short side 121c, the first short side 121c of the first-stage driver IC chip constitutes a first end of a row of a plurality of cascaded driver IC chips, and the last stage, For example, the second short side 121d of the twenty-sixth stage driver IC chip constitutes a second end of a row of a plurality of driver IC chips connected in cascade.

Reference numerals 154, 155, and 156 denote bonding wires, and the bonding wires 154 connect the common cathode nodes (CCo and CCe in FIG. 29) of the LED elements to a cathode pad (not shown) provided on the printed wiring board 151.
The bonding wire 155 connects the LED driving terminal pads DO1 to DO96 (FIG. 33) arranged along the first long side 121a of the surface on which the anode terminal pad of the LED element and the terminal pad of the driver IC chip are formed. The bonding wire 156 is a signal represented by VDD power supply terminal pads 122, 123, and 124 of the driver IC chip, and symbols DATAI0 to DATAI3, DATAO3 to DATAO0, HSYNC, LOAD, CLKP, CLKN, GND, VREF, STB, and KDR. Pads for power supply voltage and the like (indicated by reference numeral 126 in FIG. 33 as a whole), in other words, in FIG. 33, pads arranged along the second long side 121b and pads of the printed wiring board 151 The column 157 is connected.

  Reference numeral 158 denotes a wiring pattern provided on the printed wiring board 151. For example, the bonding wires 156 connected to the DATAO3 to DATAO0 terminal pads of the driver IC chip DIC1 are temporarily connected to the terminal pads 157 of the printed wiring board 151, It is connected to another terminal pad 157 of the printed wiring board 151 via the wiring pattern 158, and again connected to the DATAI3 to DATAI0 terminal pads of the driver IC chip DIC2 by the bonding wires 156.

382 is a terminal pad provided on the printed wiring board 151 and is connected to the ground by a wiring pattern (not shown).
Reference numeral 383 denotes a bonding wire, which is wired to connect the delay time selection signal terminal DLY of the first-stage driver IC chip DIC1 and the ground pad 382 on the wiring board 151.

  The delay time selection signal terminals DLY of the driver IC chips DIC2 to DIC26 in the second and subsequent stages are opened, and no bonding wires are connected to the delay time selection signal terminals DLY of the driver IC chips DIC2 and DIC3 in FIG. .

  As described above, in only the first-stage driver IC chip among the plurality of driver IC chips, the delay time selection signal terminal DLY is connected to the ground pad 382 on the wiring board 151. Therefore, the delay time selection signal terminal DLY The increase in the number of bonding pads on the wiring board 151 due to the addition is one. Further, since the delay time selection signal terminal DLY is provided on the short side of the surface on which the terminal pad of the driver IC chip is formed, the number of terminal pads along the long side does not increase, and the arrangement of the terminal pads is not increased. It becomes easy. In addition, in the first stage driver IC chip, the delay time selection signal terminal DLY is located on the side of the data input terminals DATAI0 to DATAI3, that is, the end of the first stage driver IC chip that constitutes one end of the driver IC chip row (other Since it is provided at the edge (not adjacent to the driver IC chip) 121c, it is easy to connect the delay time selection signal terminal DLY on the driver IC chip and the bonding wire on the wiring board 151.

  As in the second embodiment, the delay time by the delay circuit can be reduced by setting the number of inverter chain stages of the delay circuit in the driver IC chips in the second and subsequent stages of the cascade connection, and the maximum operation can be achieved by reducing the clock cycle. The clock frequency can be increased. As a result, the data transfer time at the time of printing by the printer using the LED head is shortened, and the printing process can be performed at high speed.

  In the above description, in FIG. 2 for the conventional example and FIG. 29 for the second embodiment, two LED array chips and two driver IC chips are shown, and the common switches 109 and 110 have two pieces. One LED array chip is shown for each. When 26 LED array chips and 26 driver IC chips are provided, one common switch 109 and 110 is provided for each LED array chip, that is, the first common switch. One switch 109 is provided for all odd-numbered LEDs of the 26 LED array chips, and a second common switch 110 is provided for all even-numbered LEDs of the 26 LED array chips. The control signal KDR1 is supplied from the common switch control signal output terminal KDR of the first-stage driver IC chip DIC1 to the first common switch 109 provided for the odd-numbered LEDs. The second common switch 110 provided for the LED includes a common switch of the second stage driver IC chip DIC2. Pitch control signal output terminal KDR from the control signal KDR2 has been described as being supplied. However, instead of doing this, one common switch 109 and 110 can be provided for 2n (n is an integer from 1 to 13) LED array chips among all LED array chips. May be. In that case, the control signal (KDR1, KDR3, KDR5) is sent from the common switch control signal output terminal KDR of the driver IC chip corresponding to one of the 2n LED array chips to the first common switch 109 for the odd-numbered LEDs. ,..., And a control signal from the common switch control signal output terminal KDR of the driver IC chip corresponding to the other one of the 2n LED array chips to the second common switch 110 for even-numbered LEDs. (KDR2, KDR4, KDR6,...) Are supplied. For example, when n is 1, from the common switch control signal output terminal KDR of the (2m + 1) th (m is an integer of 0 to 12) driver IC chip, the (2m + 1) th and (2m + 2) th LED array chips The control signal (KDR (2m + 1)) is supplied to the common switch 109 for the odd-numbered LEDs, and the (2m + 1) th and (2m + 2) th from the common switch control signal output terminal KDR of the (2m + 2) th driver IC chip. The control signal (KDR (2m + 2)) is supplied to the common switch 109 for the even-numbered LEDs of the LED array chip. In this case, the common switch control data Hk is transferred to and stored in the memory circuits MOE in all the driver IC chips that supply the control signal KDR to the common switch.

Embodiment 4 FIG.
FIG. 35 is a block diagram illustrating a detailed configuration of the driver IC chip according to the fourth embodiment. The driver IC chip shown in FIG. 35 can be used instead of the driver IC chip shown in FIG. 3 or FIG. 28, and a plurality of driver IC chips shown in FIG. An LED head similar to that described with reference to FIG. 2 can be configured, and an image forming apparatus similar to that described with reference to FIG. 1 is configured using such an LED head. You can also. The driver IC chip shown in FIG. 35 is generally the same as the driver IC chip shown in FIG. 28, but there are differences as will be understood from the following description. In addition, about the point which is the same, some description is abbreviate | omitted.

  In the second embodiment, as described above, the delay times of the delay circuits 331 to 334 in the driver IC chip are determined depending on whether the delay time selection signal terminal DLY terminal of each driver IC chip DIC is grounded or opened. In this embodiment, the delay times of the delay circuits 331 to 334 in the driver IC chip are switched according to the delay time designation data written in the memory in each driver IC chip.

  In FIG. 35, MDM is a memory circuit, and delay time designation data Hd for selecting the delay times of the delay circuits 331 to 334 in the same driver IC chip is stored in the memory circuit MDM. Therefore, the memory circuit MDM is also called a delay time designation data memory circuit.

  The memory circuit MDM has an AND circuit 411 and a latch element 412 as shown in FIG. The first and second input terminals of the AND circuit 411 are connected to the enable signal E1 and the memory cell selection signal W3 output from the memory control circuit CTRL1. The D input of the latch element 412 is connected to the Q terminal of the flip-flop FFB 25, and the G input is connected to the output of the AND circuit 411. The signal output from the Q terminal of the latch element 412 has the same logical value as that of the delay time designation data Hd after the delay time designation data Hd is latched. The OR circuit 413 serves as the delay time setting data DLYB. Is supplied to one of the input terminals. The other input terminal of the OR circuit 413 is connected to receive the LOAD-P signal, and the output of the OR circuit 413 is supplied to the delay time selection signal terminal DLYC of the delay circuits 331 to 334 as the delay time selection data DLYC. The

FIG. 37 is a circuit diagram showing the configuration of the delay circuits 331 to 334 shown in FIG. 35. In FIG. 37, 351 to 359 are inverter circuits, 360 and 361 are AND circuits, and 362 is an OR circuit. The inverter circuits 351 to 357 are connected in series to constitute an inverter chain. The input terminal Da of the delay circuit is connected to the input of the inverter 351.
One input terminal of the AND circuit 360 is connected to the output of the inverter 357, and the other input terminal is connected to the delay time selection signal terminal DLYC.
One input terminal of the AND circuit 361 is connected to the output of the AND circuit 351, and the other input terminal of the AND circuit 361 is connected to the output of the inverter 359.
Further, the delay time selection signal terminal DLYC of the delay circuit of the inverter 359 is connected.
Two input terminals of the OR circuit 362 are connected to output terminals of the AND circuits 360 and 361, respectively.
The output terminal of the OR circuit 362 is connected to the input terminal of the inverter 358, and the output of the inverter 358 is connected to the output terminal Dy of the delay circuit.

  As described above, the delay circuit in FIG. 37 is the same as the delay circuit in FIG. 30, but in FIG. 30, the signal of the delay time selection signal terminal DLY is directly supplied to the AND circuit 361 and In contrast, in FIG. 37, the signal of the delay time selection signal terminal DLYC is supplied to the AND circuit 361 via the inverter 359 and directly supplied to the AND circuit 360 in FIG. This is because the logical values of the signals for increasing the delay time are opposite in FIG. 30 and FIG. That is, in FIG. 30, when the delay time is increased, the delay time selection signal terminal DLY is set to Low. However, in FIG. 37, when the delay time is increased, the delay time selection signal terminal DLYC is set to High. It is said.

  In the present embodiment, delay time setting data DLYB having the same logical value as the delay time designation data Hd stored in the memory circuit MDM is supplied as delay time selection data DLYC to the delay circuits 331 to 334 via the OR circuit 413. Thus, the delay time of the delay circuits 331 to 334 is switched. Specifically, in the first-stage driver IC chip DIC1, in order to lengthen the delay time, the high-level delay time designation data Hd is written in the memory circuit MDM, and in the second-stage and subsequent driver IC chips DIC2 to DIC26. In order to shorten the delay time, Low level delay time designation data Hd is written into the memory circuit MDM.

  The delay time designation data Hd is written at the time of writing correction data, read out at the time of printing (when the LED is driven based on the print data), and is used for selecting the delay time of the delay circuits 331 to 334. Used. Further, in the present embodiment, the delay time designation data Hd is written at the beginning (first cycle) of writing correction data, and the delay time written at the subsequent writing of correction data (second and subsequent cycles). The correction data is transferred according to the delay time specified by the specified data Hd.

  The delay time designation data Hd of the memory circuit MDM is transferred and written together with the correction data. The outline of the transfer and writing is the same as that described with reference to FIGS. 21 to 25 regarding the first embodiment. Differences will be described with reference to FIGS. 38 and 39. FIG.

First step:
In the period tcA, the correction data Hc3 of bit3 of the chip correction data Hc, the common switch control data Hk, the invalid data DMY, and the correction data Ho3 of bit3 of the correction data Ho for odd-numbered dots are transmitted.
More specifically, the data DATAI3 is a series of 26 driver IC chips, each of which includes a chip correction data Hc3 positioned at the head for each driver IC chip, followed by a sequence of 24 dot correction data Ho3. Is sent out. FIG. 39 shows only data for the first-stage driver IC chip DIC1.

As the data DATAI2 for the first and second stage driver IC chips, the common switch control data Hk located at the head for each driver IC chip and the subsequent 24 dot correction data Ho3 are sent. The data DATAI2 for the third to 26th driver IC chips is sent as invalid data DMY located at the head for each driver IC chip, followed by a string of 24 dot correction data Ho3. To do. FIG. 39 shows only data for the first-stage driver IC chip DIC1.
The data DATAI1 is a series of 26 driver IC chips in which the delay time designation data Hd positioned at the head for each driver IC chip and the subsequent 24 dot correction data Ho3 are continuously sent for 26 driver IC chips. . FIG. 39 shows only data for the first-stage driver IC chip DIC1.

  As data DATAI0, the invalid data DMY positioned at the head for each driver IC chip, followed by a series of 24 dot correction data Ho3, which are continuous for 26 driver IC chips, is transmitted. FIG. 39 shows only data for the first-stage driver IC chip DIC1.

  While the above data transfer is performed, the enable signal E2 is High and the shift register is switched to 25 stages. When the transfer of these data by the shift register is completed, the three strobe signals HD-STB-N are transferred. (STB in FIG. 39) is generated (the strobe signal HD-STB-N becomes Low three times), and the enable signal E1 is switched to High and the enable signal E2 is switched to Low by the memory control circuit CTR1 in FIG. Then, the memory cell selection signal W3 is generated, and the correction data Hc3, the control data Hk, the correction data Ho3, and the delay time designation data Hd are stored. Further, the shift register is switched to 24 stages when the enable signal E2 is changed to Low.

  The operation after the period tcB in FIG. 38 is the same as that described with reference to FIGS. 23 to 25 regarding the first embodiment.

Operations during printing (print data transfer and LED element driving) are the same as those described in the first embodiment with reference to FIG.
However, it differs in the following points. That is, in the configuration of the fourth embodiment, the delay time designation data Hd having different values is stored in the memory circuit MDM provided in each driver IC chip, so that the previous stage of the shift register in each driver IC chip is stored. Since the delay time of the delay circuit can be set to a different value, the delay time TDI2 of the delay circuits in the driver IC chips DIC2 to DIC26 in the second and subsequent stages is set to the delay time TDI1 of the delay circuit of the first stage driver IC chip DIC1. Can be set short. As previously calculated, the clock cycle of the shift register is TCLK> TFF + TDO + TDI2 (10B)
Since the delay time TDI2 is set to a short value, the lower limit value of the clock cycle can be further shortened, and the maximum operation clock frequency at the time of print data transfer can be increased.

  The switching for setting the delay times of the delay circuits 331 to 334 to different values between the first-stage driver IC chip DIC1 and the second-stage and subsequent driver IC chips DIC2 to DIC26 is a correction prior to the start of print data transfer. Performed during data transfer.

At the start of correction data transfer (for example, taD in FIG. 15), the delay time designation data (Hd in FIG. 35) is indefinite because the High / Low state is not fixed.
The delay time designation data Hd signal is connected to one input of the OR circuit 413 in FIG. 35, and the LOAD-P signal is input to the other input terminal.
During the correction data transfer described above, the HD-LOAD signal is at a high level (FIG. 15), so the load terminal LOAD signal (LOAD-P) of each driver IC chip (DIC1 to DIC26) is also at a high level. Therefore, the output of the OR circuit 413 becomes High level, and the delay circuits 331 to 334 are set to a value with a long delay time.

As described above, the setup time and hold time for the clock signal at the input portion of the driver IC chip IC1 are given by the following equations (3A) and (4A).
Ts1 = Ts0 + TCK−TDI1 (3A)
Th1 = Th0 + TDI1-TCK (4A)
The delay time designation data (Hd in FIG. 35) is indefinite because the High / Low state is not yet determined, but the output DLYC of the OR circuit 413 is at the High level, and the delay circuits 331 to 334 have their delay times. Set to a long value.

For this reason, signals (HD-DATA3 to 0, HD-CLK-) sent from the print control unit 1 (FIG. 1) so as to have a hold time longer than the hold time Th1 obtained by assuming that the delay time TDI1 is a long value. P, HD-CLK-N) is set.
Usually, for this purpose, the correction data is transferred by increasing the period of the clock signal. In the operation shown in FIG. 15, the correction data can be normally transferred by setting the clock frequency at the time of correction data transfer to ½ (that is, the clock cycle is doubled) compared to the print data transfer.

In the second and subsequent driver IC chips DIC2 to DIC26, the setup time is given by the following equation (9B).
Ts2 = TCLK− (TFF + TDO + TDI2) (9B)
As is clear from the above equation, even when the delay time of the delay circuits of the driver IC chips DIC2 to DIC26 in the second and subsequent stages is set to a long value, the correction data transfer is performed with a sufficiently long clock cycle. By doing so, it is possible to secure the setup time in the shift register input unit, and correct data transfer can be performed normally.

Regarding the hold time Th2 of the driver IC chips DIC2 to DIC26 in the second and subsequent stages,
Th2 = TFF + TDO + TDI2 (9D)
Therefore, even if the delay time of the delay circuits of the driver IC chips DIC2 to DIC26 in the second and subsequent stages is set to a long value, the hold time is set to a long value and the operation is hindered. There is no.

  Further, when the High / Low state of the delay time designation data (Hd in FIG. 35) for setting the delay time in each stage of the cascade connection is determined by completion of the correction data transfer, a desirable delay time distribution for the high-speed data transfer is set. Therefore, in the subsequent print data transfer, data transfer can be performed at a desired high-speed clock frequency (with a small clock signal period).

  In the description of the present embodiment, the correction data can be transferred normally by setting the clock frequency at the time of correction data transfer to ½ (that is, the clock cycle is doubled) compared to the print data transfer. It is only an example, and it is of course possible to set the clock frequency at the time of correction data transfer to 1/3 or other values, and various settings are possible depending on the configuration.

Embodiment 5 FIG.
The fifth embodiment is generally the same as the fourth embodiment, but differs in the following points. That is, in the configuration of the fourth embodiment, the delay time designation data Hd of the delay circuit is indefinite immediately after the power is turned on. In contrast, in the fifth embodiment, a power-on reset circuit is provided in the driver IC chip DIC, and the delay time designation data Hd immediately after power-on is set to a predetermined value.

  FIG. 40 shows a memory circuit MDM that forms part of the driver IC chip DIC used in the fifth embodiment. The memory circuit MDM shown in FIG. 40 is generally the same as the memory circuit MDM of FIG. 36 used in the fourth embodiment, but differs in the following points. That is, as a latch element, a latch element 423 with a set input terminal S is used instead of the latch element 413 in FIG. 36, and a power-on reset circuit 425 is further provided. The power-on reset circuit 425 outputs a power-on reset signal when the power is turned on, the latch element 423 is set by this power-on reset signal, and the signal (Q output) at the output terminal Q becomes High.

  When the set input terminal S becomes High level, the latch element 423 can set the Q output to High in preference to the setting of the D terminal input or G terminal input, and even after the set input terminal S returns to Low level. The Q output is held until setting of a new state value is instructed by the D terminal input or the G terminal input.

FIG. 41 shows the configuration of the power-on reset circuit 425 of FIG. 40, and FIG. 42 shows the waveforms of signals appearing in the respective parts.
The power-on reset circuit 425 shown in FIG. 41 includes a resistor 481, a capacitor 482, and an inverter circuit 483.
One end of the resistor 481 is connected to the power supply VDD, and the other end of the resistor 481 is connected to one electrode of the capacitor 482 and the input terminal of the inverter 483. The other electrode of the capacitor 482 is connected to the ground.
A power-on reset signal RST is output from the output terminal of the inverter 483.

  42 (a) to 42 (c) show the reset signal RST when the printer apparatus is turned on (the LED head is also turned on at this time, and the power supply VDD in the driver IC chip DIC is also turned on). This shows how this occurs. The power supply voltage VDD shown in FIG. 42A is approximately 0 V before the power is turned on, a predetermined voltage is generated after the power is turned on, and is continuously output until the power is turned off thereafter.

The terminal voltage of the capacitor 482 (potential at the connection point between the resistor 481 and the capacitor 482) V482 is approximately 0 V before the power is turned on, and as a result of the power on, the capacitor 482 is charged via the resistor 481 connected to the power supply VDD. And rises with a predetermined time constant.
The power-on reset signal RST is an output waveform of the inverter 483. When the terminal voltage V482 of the capacitor 482 is less than the predetermined threshold V482th, the High level is output, and when the terminal voltage V482th reaches the predetermined threshold V482th, the power-on reset signal RST transitions to the Low level.

FIG. 43 is a time chart showing the operation of the LED head of the fifth embodiment, and corresponds to FIG. 15 used for the description of the first embodiment. In the following, description will be given in order.
Time tfA indicates the time when the power is turned on.
At this time, a reset pulse RST is generated from the power-on reset circuit 425 illustrated in FIG. 40 (period tfB).
In FIG. 43, the reset pulse RST generated at this time is shown as having a pulse width Trst.
When the reset signal RST is generated, it is input as a set signal to the set terminal S of the latch element 423 shown in FIG. 40, and the Q output DLYB of the latch element 423 shifts to a high level. These operations are performed in all of the driver IC chips DIC1 to DIC26. In FIG. 43, the delay time setting signal DLYB in the driver IC chip DIC1 is described as DLYB (DIC1), and the delay time setting signal DLYB in the driver IC chips DIC2 to DIC26 is described as DLYB (DIC2 to 26).

Prior to the start of transfer of correction data to be subsequently performed, the HD-LOAD signal is set to High to indicate that the data to be transferred is correction data (tfD).
Next, among the odd-numbered dots, correction data consisting of 4 bits per dot, bit 3 data is input from HD-DATA 3 to 0 in synchronization with clock HD-CLK-P, and the flip-flop ( Shift input is performed into a shift register composed of FFA1 to FFD25).

  When the shift input is completed, three pulses of the HD-STB-N signal are input in the period tfE, and the data write operation to the memory circuits MEM, MCM, MOE, and MDM is performed as shown in FIG.

At this time, the data written to the memory circuit MDM of the driver IC chips DIC1 to DIC26 is logic “1” in the driver IC chip DIC1 and logic “0” in the driver IC chips DIC2 to DIC26.
As a result, as shown in the time tfM part of FIG. 43, the delay time setting data DLYB (DIC1) signal remains at the high level, whereas the delay time setting data DLYB (DIC2 to 26) transitions to the low level. It will be.

  During the transfer of the bit3 correction data Ho3 for the odd-numbered dots performed after time tfD in FIG. 43, the delay time setting data DLYB is at the High level in all the driver IC chips DIC1 to DIC26, and the shift register The delay time of the delay circuit interposed in the data input section is set to a long value. At this time, it is preferable that the frequency of the transfer clock (HD-CLK-P) is lower than that at the time of print data transfer.

  On the other hand, at time tfM in FIG. 43, the delay time designation data Hd is written into the memory circuit MDM of each driver IC chip DIC. Thereafter, the delay circuit of each driver IC chip DIC responds to the delay time designation data Hd. It will work with the delay time. That is, the delay circuit of the first-stage driver IC chip DIC1 operates with a relatively long delay time, and the second-stage and subsequent driver IC chips DIC2 to 26 operate with a relatively short delay time. Accordingly, transfer of correction data and transfer of print data after time tfM are performed at the originally desired maximum frequency without reducing the frequency.

After time tfM, the bit 3 correction data He3 for even-numbered dots is sequentially transferred from the bit 0 correction data He0 for even-numbered dots, and the transferred correction data is stored in the corresponding memory in the periods tfF to tfL. Written to the circuit.
When the transfer of the correction data and the writing to the memory are completed, the HD-LOAD signal is returned to the low level again, and the print data can be transferred.

  At the start of one-line printing (print data transfer and LED element drive), the HD-HSYNC-N signal is input (tfN (FIG. 15) to indicate that the subsequent data transfer is for odd-numbered dots. corresponding to taN)). Next, the print data PDo for odd-numbered dots is transferred in the period tfO, and the data shifted into the shift registers (FFA1 to FFD1,... FFA24 to FFD24) by the HD-LOAD signal pulse at time tfP is latched. (LTA1 to LTD1,... LTA24 to LTD24).

Further, in the period tfQ, the HD-STB-N signal transitions to Low, and the LED element is driven to emit light. When the print data is on, the LED element is driven to emit light during the period when the HD-STB-N signal is Low.
At this time, the LED elements subject to light emission control have an odd dot position number, and are LED elements denoted by reference numerals 101, 103, 105, 107, etc. in FIG.
Similarly, print data of even-numbered dots is transferred in the period tfR, the print data is latched by the HD-LOAD signal pulse at time tfS, and the HD-STB-N signal transitions to Low in the period tfT. The LED element is driven to emit light. When the print data is on, the LED element is driven to emit light during the period when the HD-STB-N signal is Low.
At this time, the LED elements to be subjected to light emission control have even dot position numbers, and are LED elements denoted by reference numerals 102, 104, 106, 108, etc. in FIG.

  As described above in detail, in the configuration of the fifth embodiment, the clock frequency when transferring the correction data of bit3 for the odd-numbered dots is about ½ compared to when transferring the print data. The data is transferred after setting, and other correction data and print data are transferred without reducing the clock frequency.

In the LED head formed by cascading driver ICs having the configuration of the fifth embodiment, different values of delay time designation data Hd are stored in the memory circuit MDM in each driver IC chip, as in the fourth embodiment. Therefore, the delay time TDI2 of the delay circuits of the second and subsequent driver IC chips DIC2 to DIC26 can be set to a shorter value than the delay time TDI1 of the delay circuit of the first-stage driver IC chip DIC1. As previously calculated, the clock cycle of the shift register is TCLK> TFF + TDO + TDI2 (10B)
Since the delay time TDI2 is set to a short value, the lower limit value of the clock cycle can be further shortened, and the maximum operation clock frequency at the time of print data transfer can be increased.

  In addition, in the configuration of the fifth embodiment, when the power is turned on, the storage content of the memory circuit MDM before the delay time designation data is written is set to a predetermined value that designates a relatively long delay time ( The initial correction data can be transferred more reliably. Thereby, subsequent correction data and print data can be transferred in a short cycle, and the printing speed of a printer equipped with an LED head can be improved.

  In the fourth and fifth embodiments, as shown in FIG. 35, the selection circuit SEL of the shift registers SFRa to SFRd outputs the outputs of the flip-flops FFA23, FFB23, FFC23, and FFD23 and the flip-flops FFA24, FFB24, FFC24, and FFD24. It is configured to be selected and supplied to the flip-flops FFA25, FFB25, FFC25, and FFD25. The features described in the fourth and fifth embodiments are the same as the selection circuit SEL shown in FIG. However, the present invention is also applicable to the case where the outputs of the flip-flops FFA24, FFB24, FFC24, and FFD24 and the flip-flops FFA25, FFB25, FFC25, and FFD25 are selected and output.

Embodiment 6 FIG.
Although the overall configuration of the driver IC chip of the sixth embodiment is the same as that of the conventional example shown in FIG. 3, the memory circuit MEM and the memory control circuit CTR1 are different.

  FIG. 44 shows a memory circuit MEM used in the sixth embodiment. The memory circuit MEM shown in FIG. 44 is generally the same as that described with reference to FIG. 9 with respect to the first embodiment, but there are differences as will be understood from the following description. Also in the configuration of the present embodiment, the dot correction data for LED light amount correction is 4 bits, and light amount correction is performed by adjusting the LED drive current in 16 steps for each dot.

  The memory circuit MEM shown in FIG. 44 stores correction data for two adjacent LEDs (2 dots), and includes a first memory cell circuit 251, a second memory cell circuit 252, Correction data input for receiving dot correction data Hb (Ho or He) from the buffer 221 and the corresponding flip-flop (corresponding one of FFA1 to FFA24, FFB1 to FFB24, FFC1 to FFC24, and FFD1 to FFD24 in FIG. 8) Terminal MD, enable terminal E1 for instructing data write enable for odd-numbered dots, enable terminal E2 for instructing data write enable for even-numbered dots, memory cell selection terminals W0 to W3, and correction data output for odd-numbered dots Correction data for terminals Mo0 to Mo3 and even-numbered dots And an output terminal Me0～Me3.

  The first memory cell circuit 251 stores correction data of odd-numbered dots (for example, k-th (k is odd-numbered) dots), and the second memory cell circuit 252 is an even-numbered dot (for example, (( This is for storing correction data of k + 1) th dot).

The buffer circuit 221 receives correction data input via the correction data input terminal MD. The first memory cell circuit 251 includes inverters 223 to 230, NMOSs 231, 232, 235, 236, 239, 240, 243, and NMOSs 500 to 503. As described above, in the memory circuit 251 in FIG. 44, the inverter 222 and the NMOSs 233, 234, 237, 238, 241, 242, 245, and 246 in the memory circuit in FIG. 9 are not provided, and the NMOSs 500, 501, 502 and 503 are provided. The sources of the NMOSs 500, 501, 502, and 503 are connected to the ground.
The second memory cell circuit 252 is similarly configured.

Memory cell selection terminals W0 to W3 are supplied with memory cell selection signals W0 to W3 from the memory control circuit CTR1, respectively.
Write enable signals E1 and E2 from the memory control circuit CTR1 are input to the write enable terminals E1 and E2 of the memory circuit MEM.

  The output terminal of the buffer circuit 221 is connected to the first main terminal (one of source and drain) of the NMOS 231, 235, 239 and 243.

  The other main terminals (the other of the source and drain) of the NMOSs 231, 235, 239, and 243 are connected to the first main terminals of the NMOSs 232, 236, 240, and 244, respectively. NMOS 240, NMOS 243 and NMOS 244 are connected in series, the input of inverter 223 and the output of inverter 224 are connected to the other main terminal of NMOS 232, the output of inverter 223 and the input of inverter 224 are connected to the drain of NMOS 500, In this way, the NMOSs 223 and 224 each have an output connected to the other input to constitute a memory cell. Similarly, the inverters 225 and 226, the inverters 227 and 228, and the inverters 229 and 230 are also connected to the second main terminals of the NMOSs 236, 240, and 244 and the drains of the NMOSs 501, 502, and 503, respectively, to form a memory cell. ing.

  The control terminal (gate terminal) of the NMOS 232 is connected to the memory cell selection terminal W0. The control terminal (gate terminal) of the NMOS 236 is connected to the memory cell selection terminal W1. The control terminal (gate terminal) of the NMOS 240 is connected to the memory cell selection terminal W2. The control terminal (gate terminal) of the NMOS 244 is connected to the memory cell selection terminal W3.

The enable terminal E1 is connected to the gate terminals of NMOS 231, 235, 239, and 243.
Outputs of the inverters 224, 226, 228 and 230 are connected to correction data output terminals Mo0, Mo1, Mo2 and Mo3, respectively.
The control terminals (gate terminals) of the NMOSs 500 to 503 are connected to the erase terminal ER.

  Although the first memory cell circuit 251 has been described above, the second memory cell circuit 252 is completely the same except that the connected enable terminal is represented by E2 and the output signal is represented by the symbols Me0 to Me3. It has the same configuration.

  FIG. 45 is a circuit diagram showing a configuration of memory control circuit CTR1 used in the sixth embodiment. The memory control circuit CTR1 shown in FIG. 45 is generally the same as the memory control circuit CTR1 shown in FIG. 14, but is different in that flip-flops 546 and 547, an inverter 551, and an AND circuit 564 are added.

The D terminal of the flip-flop 546 is connected to the load terminal LOAD and the LOAD-P signal is input. The clock terminal of the flip-flop 546 is connected to the strobe terminal STB and the STB-P signal is input. Is also input, and its output is connected to the clock terminal of the flip-flop 547.
The D terminal of the flip-flop 547 is connected to the Q output of the flip-flop 546. Each input of the AND circuit 564 is connected to the load terminal LOAD, the Q terminal of the flip-flop 546, and the QN terminal of the flip-flop 547. ER is output and connected to the erase terminal ER of the memory circuit MEM.

FIG. 46 is a time chart showing correction data transfer performed to the LED head having the configuration of the sixth embodiment after the printer is turned on, and print data transfer performed thereafter. FIG. 47 shows details of periods Ta and Tb in FIG.
46 and 47 are generally the same as FIGS. 15 and 22, respectively, except that an erase signal ER is shown.

  FIG. 48 is a diagram for explaining the operation of the memory circuit MEM according to the sixth embodiment, and shows in detail the configuration of the part involved in the generation of the correction data Mo3 in FIG. The configuration of the part involved in the generation of the correction data Mo2 to Mo0 and Me3 to Me0 is the same.

  In FIG. 48, the inverter circuit 230 has a PMOS 230p and an NMOS 230n, and the inverter circuit 229 has a PMOS 229p and an NMOS 229n. The buffer circuit 221 includes a first inverter circuit 221i and a second inverter circuit 221j configured by a PMOS 221p and an NMOS 221n.

  FIG. 49 is a time chart for explaining operations of the memory circuit MEM of FIGS. 44 and 48 and the memory control circuit CTR1 of FIG. 45. In the time chart of FIG. The operation during the period in which three pulses of -STB-N are generated is shown in detail.

  49, CQ7 and CQ8 indicate the waveforms of the Q terminals of the flip-flops 546 and 547 in FIG. 45, and CQ8-N indicates the QN terminal signal of the flip-flop 547.

In FIG. 49, at the time tiI when the correction data transfer is started, the signal LOAD-P of the load terminal LOAD is set to the high level. Thereby, a signal is transmitted to the reset terminal R of the flip-flops 546 and 547 in FIG. 45, and the reset state is released.
Subsequently, the correction data Ho3 is transferred as shown in FIG. 46, but is not shown in FIG.

When the transfer of the correction data Ho3 is completed, three pulses of the signal STB-N are input to the strobe terminal STB (period tiA).
The signal STB-N is logically inverted by the inverter circuit 551 in FIG. 45 and is input to the clock terminal of the flip-flop 547 as an STB-P signal.
At this time, the signal CQ7 rises and transitions by the first fall of the STB-N signal, the signal CQ8 rises and the signal CQ8-N falls by the subsequent rise of the STB-N signal.

These signals CQ7 and CQ8-N are input to the AND circuit 564, and the erase signal ER output from the AND circuit 564 becomes High in a pulse form as indicated at time tiN.
The enable signal E1 rises and transitions at the rise of the first pulse of the STB-N signal at time tiA.
Next, the memory cell selection signal W3 is generated at the falling edge of the second pulse of the STB-N signal as shown at time tiO.

The circuit operation of FIG. 48 by the generation of the erase signal pulse ER in the period tiN is as follows.
The inverters 230 and 229 are connected in cascade, and the output of the inverter 229 is connected to the input of the inverter 230.
For this reason, if the output level of the inverter 230 is High, the output of the inverter 229 is Low, and this output is fed back to the input of the inverter 230 to maintain the High output of the inverter 230.
Similarly, when the output level of the inverter 230 is Low, the output of the inverter 229 is High, and this output is fed back to the input of the inverter 230, and the Low output of the inverter 230 is maintained.
However, immediately after the power is turned on, the logical state of each node of the inverters 230 and 229 is indefinite, and it is unknown whether the node is in the High or Low state.

Assume that the output node of the inverter 230 is High.
As shown in FIG. 49, the erase signal ER is generated during the period tiN prior to writing the transferred correction data into the memory. This signal is input to the gate terminal of the NMOS 503 in FIG. 48 to turn on the NMOS 503.
The transistor size is set so that the on-resistance of the NMOS 503 is smaller than the on-resistance of the PMOS 230p, and the output potential of the inverter 230 is lowered to the Low level by the input of the erase signal ER. When the output of the inverter 230 becomes low level, the output of the inverter 229 transits to high level, the signal transition is transmitted to the inverter 230, the NMOS 230n constituting the inverter 230 is turned on, the PMOS 230p is turned off, and the inverter The output state (Low) of 230 can be maintained.

As a result, even if the erase signal ER in FIG. 49 returns from High to Low, the logic state in which the output of the inverter 230 is Low and the output of the inverter 229 is High is maintained as it is.
Next, consider a case where the memory cell selection signal W3 becomes High as at time tiO.
At this time, the correction data transfer by the shift register is completed, and the logic state of the signal at the correction data input terminal MD in FIG. 48 is determined based on the input data to the shift register.

  Assume that the signal at the correction data input terminal MD is at a low level. In this case, the output of the buffer circuit 221 is also Low, and the enable E1 is High as shown in FIG. 49, so that the NMOS 243 in FIG. 48 is on. At this time, when the memory cell selection signal W3 transits to High (time tiO), the NMOS 244 in FIG. 48 is also turned on, and the Low output from the buffer circuit 221 is transmitted to the inverter 230.

Although the output of the inverter 229 is at a high level, as a result of the NMOSs 243 and 244 being turned on, the output level of the inverter 229 is lowered by the low output of the buffer circuit 221.
The size of each transistor is set so that the series addition value of the on-resistances of the NMOSs 221n, 243, and 244 is smaller than the on-resistance of the PMOS 229p.

As a result, the output of the inverter 229 is shifted to the low level according to the output value of the buffer circuit 221.
As a result, the output of the inverter 230 is high, the output of the inverter 229 is low level, and the output state is maintained even after the enable signal E1 and the memory cell selection signal W3 are low level.

  As another case, assume that the signal at the correction data input terminal MD is at a high level. In this case, since the output of the buffer circuit 221 is also high and the enable signal E1 is high as shown in FIG. 49, the NMOS 243 in FIG. 48 is on. At this time, when the memory cell selection signal W3 transits to High (time tiO), the NMOS 244 in FIG. 48 is also turned on, and the High output from the buffer circuit 221 is transmitted to the inverter 230.

Since the output of the inverter 229 is at the high level, even if the NMOSs 243 and 244 are turned on and the high output of the buffer circuit 221 is transmitted, the level of the output signal of the inverter 229 does not change.
As a result, the output of the inverter 230 remains low and the output of the inverter 229 remains at the high level, and the output state is maintained even after the enable signal E1 and the memory cell selection signal W3 are at the low level.

As described above in detail, in the memory circuit having the configuration shown in FIG. 48, an erase signal (memory erase command signal) ER is input and set to a predetermined logic state prior to data writing based on externally input data. Is done.
As a result, data writing to a desired logic state can be performed regardless of the value of signal data input externally.

In the LED head, for example, 4992 LED elements are provided, and it is necessary to perform LED light amount correction with correction data of 4 bits for each LED element, and the total number of memory elements reaches 4992 × 4 = 19968 bits. In need of.
As described for the memory circuit shown in FIG. 9, data writing to each memory element is performed by selecting memory cell selection signals W3 to W0 indicating bit positions, and selecting either odd-numbered dots or even-numbered dots. Two data lines (a line connected to the output of the buffer circuit 221 and a line connected to the output of the inverter 222) are transmitted in a time-sharing manner using the signals E1 to E2 and transmit signals of complementary values to each other. ) And these lines and a memory cell formed of cascade-connected inverters (for example, 230 and 229), the above-mentioned signal E1 or E2 and W3, W2, W1 or W0 are used as a control signal as a switch 2 It was necessary to have two NMOSs (for example, 243, 244, 245, 246).

  The total number of these switch elements and elements provided for driving the data lines is enormous, and the chip area of the driver IC in which these are integrated and arranged requires a large area. This has led to a rise in IC manufacturing costs, such as a reduction in chip yield, and is a major limitation in reducing the cost of LED heads on which these are mounted.

As apparent from comparison with the memory circuit shown in FIG. 9, in the memory circuit shown in FIG. 44, the inverter circuit 222 and an NMOS (for example, an output of the inverter circuit 222) connected to one data signal (for example, the output of the inverter circuit 222). 245, 246) is removed, while an NMOS 503 is added to erase the memory data. In one memory circuit MEM (the whole of FIGS. 9 and 44), the number of NMOSs (245, 246, etc.) to be removed is 2 × 4 × 2 = 16, and the number of NMOSs (503, etc.) to be added is 1 × 4 × 2 = 8. In addition, two MOSs are required for the inverter circuit (such as 222). Therefore, the difference between the number of removed MOSs and the number of added MOSs is 16 + 2−8 = 10
This is the reduction number in the whole of FIG. 9 and FIG. 44, that is, the circuit portion (first memory cell circuit 251 and second memory cell circuit 252) for two LED elements. When 4992 LED elements are mounted on the LED head as in the above example, 10 × 4992/2 = 24960 MOSs can be reduced. Therefore, the area of the IC chip for forming these MOSs can be saved, and the IC manufacturing cost can be greatly reduced.

Embodiment 7 FIG.
Although the seventh embodiment is generally the same as the sixth embodiment, the memory circuit MEM and the memory control circuit CTR1 are different.

  FIG. 50 shows a memory circuit MEM used in the seventh embodiment. Also in the configuration of the present embodiment, the dot correction data for LED light amount correction is 4 bits, and light amount correction is performed by adjusting the LED drive current in 16 steps for each dot.

The memory circuit MEM shown in FIG. 50 stores correction data for two adjacent LEDs (2 dots), and includes a first memory cell circuit 251, a second memory cell circuit 252, Correction data input for receiving dot correction data Hb (Ho or He) from the buffer 221 and the corresponding flip-flop (corresponding one of FFA1 to FFA24, FFB1 to FFB24, FFC1 to FFC24, and FFD1 to FFD24 in FIG. 8) Terminal MD, enable terminal E1 for instructing data write enable for odd-numbered dots, enable terminal E2 for instructing data write enable for even-numbered dots, memory cell selection terminals W0 to W3, and correction data output for odd-numbered dots Correction data for terminals Mo0 to Mo3 and even-numbered dots And an output terminal Me0～Me3.
The first memory cell circuit 251 is generally the same as that shown in FIG. 44, but the NMOSs 500 to 503 in FIG. 44 are not provided, but PMOSs 580 to 583 are provided instead.

In the PMOSs 580 to 583, the source terminals are connected to the power supply VDD, the drain terminals are connected to the input terminals of the inverters 224, 226, 228, and 230, respectively, and the gate terminals are connected to the erase terminal ER.
The second memory cell 252 is similarly configured.

  FIG. 51 is a circuit diagram showing a configuration of memory control circuit CTR1 used in the seventh embodiment. The memory control circuit CTR1 shown in FIG. 51 is generally the same as the memory control circuit CTR1 shown in FIG. 45, except that a NAND circuit 565 is used instead of the AND circuit 564 of FIG.

  FIG. 52 is a time chart showing correction data transfer performed to the LED head having the configuration of the seventh embodiment after the printer is turned on and print data transfer performed thereafter. FIG. 52 is generally the same as FIG. 46 except that the erase signal ER is always at the high level and is at the low level at time tgN.

  FIG. 53 is a diagram for explaining the operation of the memory circuit MEM according to the seventh embodiment, and shows details of a part related to generation of the correction data Mo3 in FIG. The configuration of the part involved in the generation of the correction data Mo2 to Mo0 and Me3 to Me0 is the same.

  FIG. 53 is generally the same as FIG. 48 except that a PMOS 583 is provided instead of the NMOS 503. The source terminal of the PMOS 583 is connected to the power supply VDD, and the drain terminal is connected to the input terminal of the inverter 230 and the output terminal of the inverter 229.

  FIG. 54 is a time chart for explaining the operation of the memory circuit MEM of FIGS. 50 and 53 and the memory control circuit CTR1 of FIG. 53. In the time chart of FIG. The operation during the period in which three pulses of -STB-N are generated is shown in detail.

  54, CQ7 and CQ8 indicate the waveforms of the Q terminals of the flip-flops 546 and 547 in FIG. 50, and CQ8-N indicates the QN terminal signal of the flip-flop 547.

In FIG. 54, at the time tiI when the correction data transfer is started, the signal LOAD-P of the load terminal LOAD is set to the high level. Thereby, a signal is transmitted to the reset terminal R of the flip-flops 546 and 547 of FIG. 51, and the reset state is released.
Subsequently, the correction data Ho3 is transferred as shown in FIG. 52, but is not shown in FIG.

When the transfer of the correction data Ho3 is completed, three pulses of the signal STB-N are input to the strobe terminal STB (period tiA).
The signal STB-N is logically inverted by the inverter circuit 551 in FIG. 51 and is input to the clock terminal of the flip-flop 547 as an STB-P signal.
At this time, the signal CQ7 rises and transitions by the first fall of the STB-N signal, the signal CQ8 rises and the signal CQ8-N falls by the subsequent rise of the STB-N signal.

These signals CQ7 and CQ8-N are input to the NAND circuit 565, and the erase signal ER output from the NAND circuit 565 becomes a negative pulse at time tiN.
The enable signal E1 rises and transitions at the rise of the first pulse of the STB-N signal at time tiA.
Next, the memory cell selection signal W3 signal is generated at the falling edge of the second pulse of the STB-N signal as shown at time tiO.

The circuit operation of FIG. 53 by generation of the negative erase signal pulse ER in the period tiN is as follows.
The inverters 230 and 229 are connected in cascade, and the output of the inverter 229 is connected to the input of the inverter 230.
For this reason, if the output level of the inverter 230 is High, the output of the inverter 229 is Low, and this output is fed back to the input of the inverter 230 to maintain the High output of the inverter 230.
Similarly, when the output level of the inverter 230 is Low, the output of the inverter 229 is High, and this output is fed back to the input of the inverter 230, and the Low output of the inverter 230 is maintained.
However, immediately after the power is turned on, the logical state of each node of the inverters 230 and 229 is indefinite, and it is unknown whether the node is in the High or Low state.

Assume that the output node of the inverter 230 is High.
As shown in FIG. 54, the negative erase signal ER is generated in the period tiN prior to writing the transferred correction data into the memory. This signal is input to the gate terminal of the PMOS 583 in FIG. 53, and turns on the PMOS 583.
The transistor size is set so that the on-resistance of the PMOS 583 is smaller than the on-resistance of the NMOS 229n, and the output potential of the inverter 229 is raised to the high level by the input of the erase signal ER. When the output of the inverter 229 becomes high level, the output of the inverter 230 changes to low level, the signal transition is transmitted to the inverter 229, the PMOS 229p constituting the inverter 229 is turned on, the NMOS 229n is turned off, and the inverter The output state (High) of 229 can be maintained.

As a result, even if the erase signal ER in FIG. 53 returns from Low to High, the logic state in which the output of the inverter 230 is Low and the output of the inverter 229 is High is maintained as it is.
Next, consider a case where the memory cell selection signal W3 becomes High as at time tiO.
At this time, the correction data transfer by the shift register is completed, and the logic state of the signal of the correction data input terminal MD in FIG. 53 is determined based on the input data to the shift register.

  Assume that the correction data input terminal MD signal is at the low level. In this case, since the output of the buffer circuit 221 is also Low and the enable signal E1 is High as shown in FIG. 54, the NMOS 243 in FIG. 53 is on. At this time, when the memory cell selection signal W3 transits to High (time tiO), the NMOS 244 in FIG. 53 is also turned on, and the Low output from the buffer circuit 221 is transmitted to the inverter 230.

Although the output of the inverter 229 is at a high level, as a result of the NMOSs 243 and 244 being turned on, the output level of the inverter 229 is lowered by the low output of the buffer circuit 221.
The size of each transistor is set so that the series addition value of the on-resistances of the NMOSs 221n, 243, and 244 is smaller than the on-resistance of the PMOS 229p.

As a result, the output of the inverter 229 is shifted to the low level according to the output value of the buffer circuit 221.
As a result, the output of the inverter 230 is high, the output of the inverter 229 is low level, and the output state is maintained even after the enable signal E1 and the memory cell selection signal W3 are low level.

As another case, assume that the signal at the correction data input terminal MD is at a high level.
In this case, the output of the buffer circuit 221 is also High, and the enable signal E1 is High as shown in FIG. 54, so that the NMOS 243 in FIG. 53 is on. At this time, when the memory cell selection signal W3 transits to High (time tiO), the NMOS 244 in FIG. 53 is turned on, and the High output from the buffer circuit 221 is transmitted to the inverter 230.

Since the output of the inverter 229 is at the high level, even if the NMOSs 243 and 244 are turned on and the high output of the buffer circuit 221 is transmitted, the output signal level of the inverter 229 does not change.
As a result, the output of the inverter 230 remains low and the output of the inverter 229 remains at the high level, and the output state is maintained even after the enable signal E1 and the memory cell selection signal W3 are at the low level.

As described above in detail, in the memory circuit having the configuration shown in FIG. 50, an erase signal (memory erase command signal) ER is input and set to a predetermined logic state prior to data writing based on externally input data. Is done.
As a result, data writing to a desired logic state can be performed regardless of the value of signal data input externally.

  The configuration of the seventh embodiment can also reduce the number of MOSs that constitute the memory circuit as in the case of the sixth embodiment.

  As described above, the memory circuit MEM shown in FIG. 44 is connected to the memory cell composed of the first and second inverters (for example, 230 and 229) and the input terminal of the first inverter (230). The NMOS (243, 244) as the first switch element for transmitting data to the memory cell, and the NMOS as the second switch element connected between the output terminal of the first inverter (230) and the ground (503), the output terminal of the first inverter (230) is connected to the input terminal of the second inverter (229), and the output terminal of the second inverter (229) is the input terminal of the first inverter Although connected to (230), the conductivity types of the first and second switch elements may be opposite to those in the illustrated example.

  Similarly, in the memory circuit MEM shown in FIG. 50, a memory cell configured by first and second inverters (for example, 230 and 229) and an input terminal of the first inverter (230) are connected to each other. NMOS (243, 244) as a first switch element for transmitting data to the cell, PMOS (second switch element connected between the input terminal of the first inverter (230) and the power supply VDD ( 580), the output terminal of the first inverter (230) is connected to the input terminal of the second inverter (229), and the output terminal of the second inverter (229) is the input terminal of the first inverter ( 230), the conductivity types of the first and second switch elements may be opposite to those in the illustrated example.

Modified example.
Instead of the multiplexer circuit MUX in the above embodiment, the one shown in FIG. 55 may be used.
The multiplexer circuit MUX shown in FIG. 55 is composed of four independent multiplexers 660, 661, 662, and 663. Multiplexers 660 to 663 are used to select bit 0 to bit 3 (0th to 3rd bits), respectively. The multiplexer 660 includes a PMOS 611 and a PMOS 612. The multiplexer 661 includes a PMOS 613 and a PMOS 614. The multiplexer 662 includes a PMOS 615 and a PMOS 616. The multiplexer 663 includes a PMOS 617 and a PMOS 618.
The control terminals (gates) of the PMOSs 611, 613, 615, and 617 are connected to the data selection signal terminal S1N, and the control terminals (gates) of the PMOSs 612, 614, 616, and 618 are connected to the data selection signal terminal S2N. Is connected to the data input terminal Xo0, and the first main terminal of the PMOS 612 (one of the source and the drain) is connected to the data input terminal Xe0, and the second main terminals of the PMOSs 611 and 612 are connected. Both terminals (the other of the source and the drain) are connected to the data output terminal XQ0.

Similarly, the first main terminal (one of the source and the drain) of the PMOS 613 is connected to the data input terminal Xo1, and the first main terminal (one of the source and the drain) of the PMOS 614 is connected to the data input terminal Xe1, and the PMOS 613 The second main terminal (the other of the source and the drain) of the PMOS 614 is connected to the data output terminal XQ1.
Similarly, the first main terminal (one of the source and the drain) of the PMOS 615 is connected to the data input terminal Xo2, and the first main terminal (one of the source and the drain) of the PMOS 616 is connected to the data input terminal Xe2, and the PMOS 615 616 and the second main terminal (the other of the source and the drain) are both connected to the data output terminal XQ2. Similarly, the first main terminal (source or drain) of the PMOS 617 is connected to the data input terminal Xo3, and the first main terminal (source or drain) of the PMOS 618 is connected to the data input terminal Xe3. And the second main terminal (the other of the source and the drain) of 618 are connected to the data output terminal XQ3.

  The PMOSs 611, 613, 615, and 617 form a circuit for selecting data for odd-numbered dots, and the PMOSs 612, 614, 616, and 618 form a circuit for selecting data for even-numbered dots. doing.

In the configuration of the multiplexer circuit MUX described above, if PMOS is used as the switch element, it is possible to reduce the number of elements used while preventing operational troubles.
That is, when the data selection signal S1N is set to the low level to turn on the PMOS 611, if the data Xo0 is at the high level, a voltage substantially equal to the signal level of the data Xo0 is output from the data output terminal XQ0. In this way, if the transmission is at a high level, there is no problem even if the PMOS is used as a switching element.

Similarly, if the data Xo0 is at the low level (approximately 0V), the second main terminal of the PMOS 611 falls to a potential close to the threshold voltage of the transistor, but does not decrease to the low level (approximately 0V). Absent.
Thus, the low-level transmission function has a drawback that is not perfect.
In order to eliminate such drawbacks, in the configuration according to the prior art, an analog switch in which NMOS is connected in parallel with PMOS is configured as switch means for data selection. In this configuration, an output potential substantially equal to the input signal potential to be transmitted can be obtained, and there is no difference between the input potential and the output potential due to the presence of the switch means.

  On the other hand, it is necessary to provide a pair of PMOS and NMOS transistors for each data signal, which requires twice the number of elements as compared with the configuration of FIG. 55, and increases the chip area of the IC for arranging them. It has the disadvantage of occupying.

On the other hand, the configuration of FIG. 55 has the advantage that only half the number of elements is required compared with a circuit configured using a general analog switch, but the low-level transmission function has a disadvantage that is not perfect. doing. However, when the LED drive circuit DRV at the subsequent stage to which the output of the multiplexer circuit MUX is connected, for example, the one described with reference to FIG. 13 is used, the LED drive circuit DRV has a substantially VDD potential as the High level. While the same input voltage is required, it is sufficient for the Low level to drop to the control potential Vcont, and a Low level potential that drops to approximately 0 V is not required.
For this reason, even a multiplexer circuit composed only of PMOS can be operated without any trouble.

  FIG. 56 is a circuit diagram showing a configuration of a multiplexer control circuit CTR2 used together with the multiplexer circuit MUX of FIG. The illustrated multiplexer control circuit CTR2 is generally the same as the multiplexer control circuit CTR2 shown in FIG. 16, but differs in the following points. That is, the inverters 324 and 325 provided in the multiplexer control circuit CTR2 shown in FIG. 16 are not provided, and the outputs of the buffer circuits 322 and 323 are connected to the data selection signal output terminals S2N and S1N, respectively. Is supplied as a data selection command signal for the multiplexer circuit MUX.

  In the sixth embodiment and the seventh embodiment, as shown in FIG. 3, the selection circuit SEL of the shift registers SFRa to SFRd outputs the outputs of the flip-flops FFA24, FFB24, FFC24, and FFD24 and the flip-flops FFA25, FFB25, FFC25, and FFD25. Although it is configured to select and output, the feature described in the sixth and seventh embodiments is that, as shown in FIG. 35, the selection circuit SEL includes flip-flops FFA23, FFB23, FFC23, and FFD23. The present invention is also applicable to the case where the outputs of the flip-flops FFA24, FFB24, FFC24, and FFD24 are selected and supplied to the flip-flops FFA25, FFB25, FFC25, and FFD25.

  In the first to seventh embodiments, the case of an electrophotographic printer using an LED as a light source as a driving device has been described. The present invention can also be applied to driving a heating resistor and a display element row in a display device.

  101-108 LED, 109, 110 common switch (power MOS), 201 input circuit, 202 buffer circuit, 203-206 delay circuit, 207-210 buffer circuit, 331-334 delay circuit, CHP1-CHP26 LED array chip, DIC1- DIC26 Driver IC chip, DLY delay time selection signal terminal, DRV LED drive unit, FFA1-FFA25, FFB1-FFB25, FFC1-FFC25, FFD1-FFD25 flip-flop, LTA1-LTA25, LTB1-LTB25, LTC1-LTC25, LTD1-LTD25 Latch element, MEM memory circuit, MCM memory circuit, MUX multiplexer circuit, SEL selection circuit.

Claims (15)

A correction data memory having a correction data input terminal and first and second memory cell circuits for storing correction data for the first and second driven elements, respectively;
A drive unit that drives the first and second driven elements based on a drive data signal and correction data read from the correction data memory ;
Correction data for each of the first and second driven elements comprises a plurality of bits;
Each of the first and second memory cell circuits includes :
Each is composed of a first and a second inverter ,
The output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the first inverter,
Each storing one of the plurality of bits
A plurality of memory cells;
First and second switches of first conductivity type connected in series between the correction data input terminal and the input terminal of the first inverter of each of the plurality of memory cells and transmitting data to the memory cell Elements,
An output terminal of the first inverter of each of the plurality of memory cells, and a third switch element of the first conductivity type connected between a ground,
Each of the plurality of memory cells of the first memory cell circuit
A first enable signal is input to the control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal, and the first enable signal The on / off of the first switch element is switched by
The control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of the second memory cell circuit includes: 2 enable signal is input, and the second switch signal is turned on and off by the second enable signal,
Control input of the second switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of each of the first and second memory cell circuits. A memory cell selection signal for selecting the memory cell is input to the terminal, and the second switch element is turned on and off by the memory selection signal.
An erase signal is input to the control input terminal of the third switch element of the first and second memory cell circuits, and the on / off state of the third switch element is switched by the erase signal.
The first and second enable signals determine which of the first and second memory cell circuits to write correction data,
The memory cell selection signal determines which of the plurality of memory cells in each of the first and second memory cell circuits is to write correction data,
A drive circuit , wherein the memory cell is reset by the erase signal . A correction data memory having a correction data input terminal and first and second memory cell circuits for storing correction data for the first and second driven elements, respectively;
A drive unit that drives the first and second driven elements based on a drive data signal and correction data read from the correction data memory ;
Correction data for each of the first and second driven elements comprises a plurality of bits;
Each of the first and second memory cell circuits includes :
Each is composed of a first and a second inverter ,
The output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the first inverter,
Each storing one of the plurality of bits
A plurality of memory cells;
First and second switches of first conductivity type connected in series between the correction data input terminal and the input terminal of the first inverter of each of the plurality of memory cells and transmitting data to the memory cell Elements,
An output terminal of the first inverter of each of the plurality of memory cells, and a third switch element of the second conductivity type connected between a power source,
Each of the plurality of memory cells of the first memory cell circuit
A first enable signal is input to the control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal, and the first enable signal The on / off of the first switch element is switched by
The control input terminal of the first switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of the second memory cell circuit includes: 2 enable signal is input, and the second switch signal is turned on and off by the second enable signal,
Control input of the second switch element connected between the input terminal of the first inverter and the correction data input terminal of each of the plurality of memory cells of each of the first and second memory cell circuits. A memory cell selection signal for selecting the memory cell is input to the terminal, and the second switch element is turned on and off by the memory selection signal.
An erase signal is input to the control input terminal of the third switch element of the first and second memory cell circuits, and the on / off state of the third switch element is switched by the erase signal.
The first and second enable signals determine which of the first and second memory cell circuits to write correction data,
The memory cell selection signal determines which of the plurality of memory cells in each of the first and second memory cell circuits is to write correction data,
A drive circuit , wherein the memory cell is reset by the erase signal . The drive circuit according to claim 1, wherein the first and second switch elements are n-type MOS transistors. The drive circuit according to claim 2, wherein the first switch element is an n-type MOS transistor, and the second switch element is a p-type MOS transistor. The drive circuit according to any one of claims 1 to 4, further comprising means for supplying a control signal for turning on the third switch element prior to data writing to the memory cell.   6. The drive circuit according to claim 1, wherein correction data stored in the memory cell is read from an input terminal of the first inverter of each of the plurality of memory cells. . A drive circuit according to any one of claims 1 to 6 ;
A driver IC chip comprising: a shift register including a plurality of stages of flip-flops for transferring the drive data signal.   The shift register also transfers the correction data,
  The correction data input terminal of the correction data memory receives the output of the flip-flop of the corresponding stage of the shift register,
  The driven elements are divided into a first group and a second group;
  When the correction data for the first group of driven elements is transferred by the shift register, the correction data for the second group of driven elements is not transferred, and the second group of driven elements is not driven. When correction data for an element is transferred by the shift register, correction data for the first group of driven elements is not transferred,
  The first driven element is any of the first group of driven elements, and the second driven element is any of the second group of driven elements.
  The driver IC chip according to claim 7.   The first group of driven elements comprises an odd number of driven elements;
  The second group of driven elements comprises even-numbered driven elements.
  The driver IC chip according to claim 8. 10. A drive device comprising a plurality of driver IC chips according to claim 7 connected in cascade. The driven element;
A drive device according to claim 10 ,
The print head, wherein the driven element is a driven element for printing. The print head according to claim 11 , wherein the driven element for printing is a light emitting element or a heating element. A print head according to claim 11 or 12 ,
An exposure device for forming an electrostatic latent image on the photosensitive drum;
A developing unit that forms a toner image corresponding to the electrostatic latent image on the photosensitive drum;
An image forming apparatus comprising: a transfer unit that transfers the toner image on the photosensitive drum to a printing paper. The driven element;
A drive device according to claim 10 ,
The display device, wherein the driven element is a light emitting element. A method of controlling a drive circuit according to claims 1 to 6,
Prior to writing data to the memory cell, a control signal for turning on the third switch element is supplied.

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