JPH03286494A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To exactly initialize a prescribed memory cell to prescribed data at high speed by providing a potential forcing means to force the memory node of the prescribed memory cell to a potential corresponding to the initializing data and a means to activate all the potential forcing means in response to the turn-on of a power source. CONSTITUTION:In response to a master reset signal MR, transistors TR3 and TR4 are turned to an OFF state and inverters INV1 and INV2 are electrically disconnected from a power source VCC and a ground GND. However, since the inverters INV1 and INV2 form a latch circuit, the potentials of these control points, namely, of memory nodes n1 and n2 are held at a level which is decided while the master reset signal MR is at an 'H' level. In such a way, the stored data of memory cells MC1 and MC2 are initialized to a logic value '0' when the power source is turned on. Thus, the stored data of the memory cells decided in advance can be initialized to the initializing data decided in advance at high speed than the conventional processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a function of initializing data stored in a memory cell.

[Prior Art] Currently, semiconductor memory devices such as RAM (Random Access Memory) are integrated into various semiconductor integrated circuits as a single chip, or are used as a single chip in various fields. Depending on the use of such semiconductor storage devices, the storage data pattern of the memory array may need to be set (initialized) to a predetermined value when the power is turned on (when the device starts to be used) for actual use. There may be cases. An example of such a semiconductor memory device is
There are cache memories, matching memories, etc. Cache memory is a very fast operating memory used to transfer and store the contents of main memory. Furthermore, a matching memory is a memory that stores an identifier in a computer system such as a data flow processor that requires an identifier, and performs various data processing according to this identifier. In semiconductor storage devices that require such "data initialization," all memory cells in the memory array or some memory cells (for example, in the case of cache memory, the memory cell at the address where the identifier is stored) ) is set to a logic value "1" or reset to a logic value "0" by this initialization.

FIG. 14 is a schematic block diagram showing an example of the overall configuration of a conventional SRAM (static random access memory) that has a function of performing such initialization. 1st
4, this SRAM consists of a memory array 1b consisting of a plurality of blocks in which memory cells for storing input data are arranged in a matrix in the row and column directions, and a data input array 1b for receiving input data and output data. Output terminal TD
and a row address input terminal Ar which receives from the outside a row address signal that selects any row in a block in memory array 1a, and a column address input terminal which receives from outside a row address signal that selects any column in a block in memory array 1b. The memory array 1b includes a column address input terminal Ac that receives a column address input terminal Ac, and a block address input terminal Ab that receives a block address selection signal for selecting one of the blocks in the memory array 1b from the outside.

FIG. 15 is a circuit diagram showing the internal configuration of memory array 1b. FIG. 9 representatively shows one memory cell column in an arbitrary block.

Referring to FIG. 15, memory cell MC is connected between two bit lines BIT forming a pair.

Memory cell MC includes two inverters INVI and INV2 connected in antiparallel, and this inverter INV2.
N-channel MOS transistor TR1 and inverter IN connected between the input terminal of BIT and bit line BIT
and an N-channel MO3 transistor TR2 connected between the input terminal of VI and the other no-hit line BIT. The gates of transistors TR1 and TR2 are both connected to the same word line WL. Word line WL is connected to row decoder 3 in FIG. 8, and bit line pair BIT, B
IT is connected to 110 circuit 6 in FIG.

110 circuit 6 provides a path for transmitting data read from memory array 1b from memory array lb to output buffer 9, and a path for transmitting data written to memory array 1b from input data control circuit 10 to memory array 1.
Form a route for transferring to b. Note that the former path includes a sense amplifier that amplifies data read from memory array lb.

During data writing, the row address signal applied to the row address input terminal Ar is taken in by the row address buffer 2.

Next, the row decoder 3 decodes the row address signal taken in by the row address buffer 2, and selectively writes/reads data into one row of memory cells corresponding to the row address specified by this row address signal. Make it possible.

That is, the row decoder 3 applies an "H" level voltage to the word line WL (see FIG. 15) corresponding to the memory cell row designated by the row address signal. by this,"
In all memory cells connected to word line WL at H'' level, transistors TRI and TR2 are turned on.
state, and all the memory cells are electrically connected to the corresponding bit line pair BIT, BIT.

At the same time, a block address signal input to the block address input terminal Ab is taken in by the block address buffer 7. Next, the block address signal fetched by the block decoder 8 or the block address buffer 7 is decoded, and the 110 circuit 6 decodes all the bit lines corresponding to one block indicated by the fetched block address signal. Select a pair. That is, block decoder 8 selects one block from among the blocks in memory array 1a.

Similarly, a column address signal applied to column address input terminal Ac is taken in by column address buffer 4. Next, the column address signal taken in by the column decoder 5 or the column address buffer 4 is decoded, and among the memory cells of the block selected by the block decoder 8, the column address corresponding to the column address indicated by this column address signal is assigned. Selectively enables data transmission to only one column of memory cells. That is, the column decoder 5 selects, in the 110 circuit 6, only the bit line pair corresponding to the column indicated by the column address signal among the bit line pairs BIT, BIT of the selected block connected to the 110 circuit 6. electrically connected to the input data control circuit 10. That is, column decoder 5 selects one of the bit line pairs in memory array 1b.

On the other hand, when writing data, the input buffer 11 is connected to the data input/output terminal T. The signals of each bit of data given to the input data control circuit 10 are input to the input data control circuit 10.

The input data control circuit 10 performs the following operations during normal data writing, not during data writing for "initialization".
The data given from the input buffer 11 is transferred to the 110 circuit 6.
give to

However, as described above, in the 110 circuit 6, only the bit line pair corresponding to the memory cell column selected by the column decoder 5 is electrically connected to the input data control circuit 10. Therefore, 110 circuit 6 is
Data applied from the input data control circuit 10 is applied as complementary level voltage signals to the bit line pair BIT, BIT in FIG. 15, respectively. Specifically, in the memory array 1b, all the transistors TRI and TR2 whose gates are connected to one word line (selected word line) WL to which an "H" level potential is applied by the row decoder 3 It becomes ON state. On the other hand, 110
The circuit 6 applies a logic value potential corresponding to the data given from the input data control circuit 10 and its inverted potential to two bit lines BIT and BIT constituting the bit line pair selected by the column decoder 5. . For this reason, referring to FIG. 15, the column decoder 5
In the memory cell arranged at the intersection of the column selected by and the row selected by the row decoder 3, the potential applied to one of the corresponding bit lines BIT is input to the inverter INVI via the transistor TR2. Inverter INV1 inverts this potential and inverts IN
Output to V2. On the other hand, a potential at a level opposite to the input potential of the inverter INVI is applied to the inverter INV2 from the other bit line BIT via the transistor TRI. Therefore, in this memory cell, the connection point between inverters INVI and INV2 is connected to bit line BI
A potential corresponding to a logical value opposite to the input data applied to T and a potential corresponding to input data applied to the bi-soto line BIT are determined. That is, input data is written into this memory cell. After that, the row decoder 3 sets the potential of the word line WL corresponding to this memory cell to "L".
lower it. As a result, transistors TR1 and TR2 are turned off in all memory cells connected to the selected word line WL, including this memory cell. However, the output of inverter INVI and I
Since the outputs of NV2 are fed back to each other's inputs, the potential at the connection point of inverters INVI and INV2 is held at the level at the time of data writing. In other words,
Write data is stored in this memory cell.

Hereinafter, a node where a potential corresponding to data is held, such as the connection point between inverters INVI and INV2, will be referred to as a storage node.

In this way, in the block specified by the block address signal among the blocks in memory array 1b, data is stored in the memory cell arranged at the intersection of the column specified by the column address signal and the row specified by the row address signal. Input/output terminal T. The data input from is written and stored.

FIG. 16 is a circuit diagram showing in more detail the structure of each memory cell included in memory array 1b in FIG. 14. Referring to FIG. 16, each memory cell MC in memory array 1b including the memory cell shown in FIG. N-channel MOS transistors 230 and 240. Transistors 210 and 230 are connected in series between power supply Vcc and ground GND,
Configure inverter INVI. A connection point n1 between transistors 210 and 230 is the output terminal of this inverter INVI. On the other hand, transistors 220 and 240 are also connected to the power source ■. 0 and the ground GND to constitute an inverter INV2. A connection point n2 between transistors 220 and 240 is the output terminal of this inverter INV2. Gate of transistor 210 and transistor 2
The 30 gates are connected to each other.

The gate connection point of transistors 210 and 230 is connected to the output edge n2 of inverter INV2 as the input end of inverter INVI. Meanwhile, the gate of transistor 220 and the gate of transistor 240 are also connected to each other. The gate connection point of transistors 220 and 240 is connected to inverter INVI as the input terminal of inverter INV2.
is connected to the output terminal n1 of.

When data continues to be written, row address buffer 2 and row decoder 3, column address buffer 4 and column decoder 5, and block address buffer 7 and block decoder 8 operate in the same way as when writing data. Among the memory cells, only the memory cells selected by the block address signal, column address signal, and row address signal become data writeable/readable.

That is, with reference to FIG. In one memory cell corresponding to the bit line pair, transistors TRI and TR2 are turned on, and the corresponding bit line pair BIT, BIT is electrically connected to the output buffer 9 via the 110 circuit 6. When the transistors TRI and TR2 are turned on, the corresponding bit line pair BIT,
The potential of BIT changes. That is, the data stored in the selected memory cell is read to the corresponding bit line pair. The potential change of this bit line pair BIT, BIT is ■/○70
After being sensed and amplified by the circuit 6 amplifier and converted to a potential corresponding to the stored data, the output buffer 9
given to. Output buffer 9 derives the potential corresponding to this stored data to data input/output terminal TD as read data.

In reality, this SR is used when writing and reading data.
In order for the AM to operate as described above, the row address buffer 2. Column address buffer 4°, block address buffer 7, output buffer 9° and input buffer 11
The operation timing of the chip is controlled by the chip and input/output control circuit 13.

This control circuit 13 receives a chip enable signal externally applied to a chip enable terminal CE.

This control is performed based on a write enable signal externally applied to write enable terminal WE and an output enable signal externally applied to output enable terminal OE. The chip enable signal selects which chip should currently operate in a device equipped with this SRAM, and when this SRAM chip should operate, this chip select signal goes to "L" level.

The write enable signal indicates whether or not this memory should currently be in the data write mode, and goes to the "L" level when it should be in the data write mode. The output enable signal indicates whether or not read data is currently to be output from this memory, and becomes "L" level when read data is to be output.

This SR whose chip enable signal is at “L” level
During the period when the AM chip is to operate, the control circuit 13 uses the row address buffers 2. Column address buffer 4. Activate the operation of block address buffer 7. In addition, during the period when the write enable signal is at the “L” level and data is to be written to this memory, the control circuit ↓3
activates the operation of the input buffer 11 so that the data applied to the input/output terminal TD is taken into the SRAM. Furthermore, during a period when the output enable signal is at the "L" level and read data is to be output, the control circuit 13 controls the operation of the output buffer 9 so that successive data from the memory array 1b is output to the outside. Activate.

The above-described operation of this SRAM is similar to that of a normal SRAM that does not have an initialization function.

However, in this SRAM, the normal SRAM as mentioned above
In addition to the functional units provided in M, an initialization data control circuit 12. A clock generation circuit 14 and an initialization address generation circuit 15 are added.

The initialization address generation circuit 15 generates a block address signal, a row address signal, and a column address signal each indicating a block address, a row address, and a column address corresponding to a predetermined address of a memory cell to be initialized. , these are each processed by a block decoder 8. Column decoder5. and is given to the row decoder 3.

The initialization data control circuit 12 creates predetermined data (initialization data) to be given to the memory cell to be initialized at the time of initialization, and supplies it to the input data control circuit 10.

The clock generation circuit 14 performs the following operations in the initialization address generation circuit 15 based on an initialization control signal (initialization signal) externally applied to the initialization signal input terminal T1.
A clock signal for generating a block address signal, a row address signal, a column address signal, and a clock signal for generating initialization data in the initialization data control circuit 2 are generated.

When the power is turned on, an initialization signal is applied to the initialization signal input terminal T. In response to this initialization signal, the clock generation circuit 14 generates the aforementioned black/y signal. next,
Based on this clock signal, initialization data control circuit 12 and initialization address generation circuit 15 operate as described above.

At the time of such initialization, the input buffer 11 that receives input data from the outside is still disabled by the control circuit 13, and normal write data is not input to the input data control circuit 10. 10 supplies data given from the initialization data control circuit 12 to the 110 circuit 6 as write data. Similarly, at this time, row address buffer 2. Column address buffer 4. and block address buffer 7 are still disabled by control circuit 13, and row decoder 3 . Column decoder5. Also, the block decoder 8 is not given an address signal input from the outside. Therefore, at initialization, row decoder 3. Column decoder5. The blower and block decoder 8 each receive only the row address signal, column address signal, and block address signal provided from the initialization address generation circuit 15, and decode them. Therefore, in this case, memory cells to be initialized in memory array 1b are sequentially selected one address at a time, and initialization data generated by initialization data control circuit 12 is written into them.

Note that the lock may be directly input to the initialization data control circuit 12 and the initialization address generation circuit 15 if necessary.

In this way, in this semiconductor memory device, when the power is turned on,
The data stored in a predetermined memory cell is initialized by a specially provided initialization circuit inside the device, that is, by hardware. Initialization data control circuit 12
．． A circuit for initializing the clock generation circuit 14 and the initialization address generation circuit 15 is built into this semiconductor memory device in advance. Therefore, only one address signal is generated for initialization. therefore,
It is not possible to initialize memory cells at different addresses or to use different data as initialization data each time the initialization is performed. Therefore, in general, when performing such irregular initialization, software initialization is performed instead of node initialization.

Software initialization is, for example, initialization performed by software such as a program in a system configured using a semiconductor memory device. Specifically, an initialization program that generates addresses and data is given to the system, and when the system executes this program, the addresses and initialization data that the system itself should initialize are transferred externally to the semiconductor storage device. is generated and applied to the semiconductor memory device. Then, the semiconductor memory device operates in the same manner as when writing normal data, and writes the generated data to the generated address. Such initialization does not require any initialization circuit as described above inside the semiconductor memory device. In other words, the semiconductor memory device performs the operation of writing given data to a given address without distinction in both data writing for initialization and normal data writing. Of course, in this case, the system
It is necessary to write a mode setting command for setting the semiconductor memory device in a write mode, a write address and write data to be appropriately given to the semiconductor memory device in a program or the like.

Now, when performing hardware initialization, the data bits to be initialized are fixed regardless of the address, and the addresses of the memory cells whose stored data should be initialized are, for example, all addresses in the memory array, all even addresses, etc. , all odd-numbered addresses, consecutive addresses from address 0 to a predetermined address, etc., and if the initialization data to be written is also regular such as the same for each address, then Initialization data control circuit 12. Clock generation circuit 14. The initialization address generation circuit 15 can be realized by a circuit with a relatively simple configuration. But the data bits that are initialized,
If the address to be initialized, the initialization data to be written, etc. are irregular, the circuit for these initializations will be complicated. For example, the initialization address generation circuit 15 is generally a circuit that generates an address signal by counting clocks from the clock generation circuit 14, and includes a counter for performing this counting. If the addresses to be generated are irregular, it is necessary to perform complex control over the counting operation of this counter. Therefore, if the address to be initialized becomes complex, the configuration of the initialization address generation circuit 15 becomes complicated. Therefore, in order to perform complicated initialization, the number of circuits for initialization becomes enormous, and it may be impossible to provide these circuits inside the semiconductor memory device.

Therefore, in such a case, it becomes necessary to specially configure these circuit sections separately from the semiconductor memory device. Therefore, complex initialization is generally performed by the aforementioned software initialization.

[Problems to be Solved by the Invention] As described above, conventional methods for initializing data stored in a semiconductor memory device include a hardware-based method and a software-based method.

When the former method is used, the time required for initialization depends on the initialization circuits provided inside the semiconductor memory device (initialization data control circuit 12, clock generation circuit 14, and initialization address generation circuit in FIG. 14). circuit 1
5) depends on the generation time of addresses and data and the time required for all generated data to be written to all generated addresses. When the latter method is used, the time required for initialization depends on the time required for a system equipped with the semiconductor memory device to execute a program for initialization. however,
In either case, the initialization data is written by a normal write operation of the semiconductor memory device.

In a semiconductor memory device such as an SRAM, when writing data, addresses to which data is to be written are sequentially selected one by one as described above, and corresponding input data is written to the selected addresses. Therefore, data cannot be written to multiple addresses simultaneously. Therefore, as the number of memory cells to be initialized increases, and as the number of addresses and data bits to be initialized increases, the time required to write initialization data increases. Therefore, the time required for initialization increases.

In recent years, the capacity of semiconductor memory devices has been increasing, and the number of memory cells to be initialized is also increasing. Therefore, according to such a conventional initialization method, the initialization time becomes longer, and as a result, the operating speed of the semiconductor memory device decreases.
As a result, a problem arises in that the operating speed of the system in which this is installed deteriorates.

Further, as described above, when data stored in a semiconductor memory device is initialized using hardware, there is a problem in that a large amount of additional circuitry is required if complicated initialization is to be performed. Such an increase in the number of additional circuits causes an increase in power consumption, an increase in chip area, etc., which is undesirable from the viewpoint of reducing power consumption and miniaturization of semiconductor integrated circuit devices. If such complicated initialization is performed using software, the program for this will be complicated, and as the program size increases, the execution time will also increase. As a result, initialization time also increases.

Therefore, an object of the present invention is to solve the above-mentioned problems, and even when the address to be initialized, the initialization data, etc. are irregular, the predetermined initialization can be performed without significantly increasing the number of additional circuits for initialization. An object of the present invention is to provide a semiconductor memory device that can quickly and accurately initialize memory cells to predetermined data.

[Means for Solving the Problems] In order to achieve the above-mentioned objects, a semiconductor memory device according to the present invention is capable of initializing stored data, and each memory data is held at a potential corresponding to the stored data. a plurality of memory cells each having a storage node to be set, and a predetermined memory cell of the plurality of memory cells corresponding to predetermined initialization data to initialize the storage node of the predetermined memory cell. The device includes potential forcing means for forcing a potential corresponding to data, and means for activating all of the potential forcing means in response to power-on.

[Operation] Since the semiconductor memory device according to the present invention is configured as described above, when power is applied to the semiconductor memory device, each memory note of a predetermined memory cell is simultaneously activated by the corresponding potential forcing means. is forced to the potential corresponding to the initialization data. That is, the data stored in a predetermined memory cell is initialized simultaneously in response to power-on.

[Embodiment] FIG. 1 is a partial circuit diagram of a memory array in an SRAM according to an embodiment of the present invention, and FIG. 7 is a partial circuit diagram of an SRAM according to an embodiment of the present invention.
FIG. 2 is a schematic block diagram showing the overall configuration of FIG. This SRAM
Now, it is assumed that the memory cells to be initialized and the initialization data to be written into them at the time of initialization do not differ each time the initialization is performed, but are fixed to predetermined values.

Referring to FIG. 12, the overall configuration of this SRAM is similar to that of a conventional general SRAM, that is, from the SRAM shown in FIG. initialization data control circuit 12, clock generation circuit 14° and initialization address generation circuit 15
) is removed. The operation of the functional blocks shown in FIG. 12 is as explained in "Prior Art".

However, unlike conventional SRAMs, this SRAM uses a reset signal (hereinafter referred to as "hard reset") to perform a reset (hard reset) for this SRAM or a system in which this SRAM is installed, in addition to initializing the data stored in the SRAM. (referred to as a mask reset signal) MR is input to the memory array 1a. The mask reset signal MR is a one-shot pulse that is generated inside the system or SRAM in response to power-on, or is input from the outside. This one-shot pulse forces the potential of a predetermined portion of the circuitry within the system to the predetermined potential it should be upon start-up. In this embodiment, this master reset signal M
It is assumed that R is generated inside the SRAM.

In FIG. 12, a reset signal generation circuit 16 is, for example, a circuit provided in many conventional semiconductor memory devices that generates a so-called power-on reset signal for internal reset. Reset signal generation circuit 1
6 is the power supply V. 0 and this power supply V. In response to the rise of the 0 potential, a signal at the "H" level for a predetermined short period of time is generated as the mask reset signal MR.

FIG. 13 is a diagram showing the waveforms of the mask reset signal MR and its inverted signal MR. Mask reset signal MR
As shown in FIG. 13(a), after rising to the "H" level in response to power-on, it falls to the "L" level after a certain period of time, and thereafter remains at the "L" level. Therefore, the inverted signal MR of this mask reset signal MR is:
As shown in FIG. 13(b), after falling to "L" level in response to power-on, it goes to "H" level after the certain period of time.
rise to the level. Thereafter, this inverted signal MR is held at the "H" level.

Next, the internal configuration of memory array 1a will be described.

FIG. 1 typically shows the internal configuration of this memory array 1a for one memory cell column.

Referring to FIG. 1, in this SRAM as well, one column of memory cells is connected between two bit lines BIT forming the same bit line pair. Also,
The memory cells in each row are connected to corresponding word lines WL.

However, each of the memory cells MCI and MC2 whose stored data is to be initialized to a logical value "0" has two inverters INVl and INV2 forming a latch circuit for holding the written data, unlike the conventional case. In addition to N-channel MOS transistors TRI and TR2, which are transfer gates for reading stored data onto the corresponding bit line pair and transmitting data applied to the corresponding bit line pair to the latch circuit,
N-channel MO8) transistor for initialization (hereinafter referred to as
It is called an initialization transistor. ) including TR3 and TR4.

The transistor TR3 is connected to the input terminal of one of the inverters INV2 constituting the latch circuit and the power supply (2). 0, and the transistor TR4 is provided between the input terminal of the other inverter INVI and the ground GND.

The aforementioned master reset signal MR is inputted to the gates of these transistors TR3 and TR4 from the reset signal generation circuit 16 shown in FIG. Mask reset signal M
When R is applied to the gates of transistors TR3 and TR4, transistors TR3 and TR4 are turned on in each of memory cells MCI and MC2. By making transistors TR4 and TR3 conductive,
The low potential of the ground GND causes a voltage drop at the input end of the inverter INVI, and the high potential of the power supply Vco causes a voltage rise at the input end of the inverter INV2.

As a result, the potential at the input terminal of inverter INVI exceeds the input inversion voltage of inverter INVI, and inverter 2N
V1 provides an "H" level potential to the input terminal of the inverter INV2. Similarly, the potential at the input terminal of the inverter INV2 exceeds the manual inversion voltage of the inverter INV2, and the inverter INV2 becomes "L" at the input terminal of the inverter INVI.
Give a level potential. This allows the inverter IN
The potentials at the output terminal of VI and the output terminal of inverter IN'V2 are each determined to be "H" level and L level.

Note that when the power is turned on, the row address buffer 2. of FIG. Column address buffer 4. Since the operation of block address buffer 7 is disabled, no word line WL or bit line pair is selected in memory array 1a.

Therefore, in any memory cell, transfer gates TRI and TR2 are in the OFF state, so in memory cells MCI and MC2 in FIG.
The potential at the connection point of inverters INVI and ■NV2 is O
It is determined only by the potential transmitted by transistors TR3 and TR4 in the N state.

Since the mask reset signal MR is a one-shot pulse, it goes to the "H" level for a predetermined short time and then returns to the "L" level. In response, the transistors TR3 and TR
4 is in the OFF state, and inverters INVI and IN
V2 is electrically cut off from the power supply CC and the ground GND. However, since the inverters INVI and INV2 form a latch circuit, the potentials at their connection points, that is, storage nodes n1 and n2, are at the level determined during the period when the mask reset signal MR is at the "H" level. is maintained. In this way, the data stored in memory cells MCI and MC2 are initialized to the logical value "0" when the power is turned on.

Next, the memory cell MC3 whose stored data is to be initialized to the logical value "1" receives a mask reset signal to the gate in addition to the inverters INVI and INV2 and the transfer gates TRI and TR2, similar to the aforementioned MCI and MC2. It includes transistors TR3 and TR4 that receive MR.

However, in memory cell MC3, memory cell MC
Contrary to the case of I and MC2, the power supply V.

. Transistor TR3 connected to inverter INV
A transistor TR4 connected to the ground GND is provided on the input side of the inverter INV2.

That is, transistor TR3 or power supply V. 0 and the input terminal of the inverter INVI, and the transistor T
R4 is connected between ground GND and the input terminal of inverter INV2. As a result, the mask reset signal MR
is applied, the potential of the storage node n1 is the ground GN.
The "L" level is determined by the low potential of D and the output potential of inverter INVI, and the potential of storage node n2 is at power supply ■. 0 and the output potential of the inverter INV2 are determined to be at the "H" level. Then, the mask reset signal MR returns to the L'' level and the transistor TR3
And when TR'4 becomes OFF state, inverter I
By the inversion operation of Nv1 and INV2, the potential levels of storage nodes n1 and n2 are held at the determined potential. In this way, in memory cell MC3,
In response to the mask reset signal MR, the potential held on the corresponding bit line BIT side (the potential at the input terminal of the inverter INVI) goes to "H" level, and the potential on the other corresponding bit line B becomes "H" level.
Holding potential on the IT side (potential held at storage node n1)
is “L” level. That is, the data stored in the memory cell MC3 is initialized to "1" when the power is turned on.

Note that the characteristics of the inverters INVI and INV2 and the transistors TR3 and TR4 are determined by the voltage drop and voltage rise in response to the input of the mask reset signal MR.
The potential at the input terminal of inverters INVI and INV respectively
2, and the time required for the level of the input terminal to be determined by the voltage drop or voltage rise is longer than the signal delay time of inverters INVI and INV・2, respectively. Designed. This causes inverter INVI and inverter INV2 to
Each of them reliably outputs a voltage at a level corresponding to the initialization data in response to the mask reset signal MR.

Next, memory cell MC4 is a memory cell that does not require initialization, and has the same configuration as the conventional one without transistors TR3 and TR4 for initialization. Therefore, by mask reset signal MR, memory cell MC4
is not affected in any way, and the data stored in memory cell MC4 is not initialized when the power is turned on, unlike the aforementioned memory cells MCI to MC3.

As described above, in this embodiment, among all the memory cells constituting the memory array 1a in FIG. two transistors TR3
and TR4, or at a position corresponding to the initialization data to be provided. Therefore, during the period when the mask reset signal MR is at the "H" level (initialization period τ in FIG. 13) immediately after the power is turned on, the data stored in the predetermined memory cells is initialized to the predetermined data all at once. be done. Therefore, the time required for initialization is constant regardless of the number of memory cells to be initialized. This fixed time is the time required for the initialization transistor to determine the potential of the storage node of one memory cell to a value corresponding to the initialization data. During normal data writing, the "H" and "L" level potentials, which are write data, are transferred from the data input/output terminal To in FIG. It is transmitted through many circuits.

On the other hand, during initialization, the "H" and L level potentials to be written are directly applied to the storage node via only the initialization transistors TR3 and TR4.Therefore, the initialization transistor TR3 and TR4
The time required to transmit "H" and "L" level potentials to the storage node is the time required to write data to one address during normal data writing in this SRAM (one read cycle period). ) is shorter than

Therefore, according to this embodiment, the time required to initialize the memory array 1a is significantly reduced compared to the conventional method.

In this embodiment, two initialization transistors are provided for each memory cell to be initialized, but even if one of these transistors is removed, the data stored in the memory cell cannot be initialized to arbitrary data. can do.

FIG. 2 is a circuit diagram showing the configuration of a memory cell when a single transistor is used for initialization, and shows another embodiment of the present invention. FIG. 2 shows the configuration of a memory cell whose stored data is to be initialized to a logical value "0", and
The configuration of a memory cell whose stored data is to be initialized to a logical value 41111 is shown.

Referring to FIG. 2(a), memory cell MC5 does not have initialization transistor TR3 included in memory cells MC1 and MC2 shown in FIG. However, when the mask reset signal MR rises to the "H" level, another initialization transistor TR4 is turned on, and the potential of the storage node n2 is lowered to the "L" level by the ground GND. “L” of this storage node n2
Since the inverter INVI inverts the level potential and outputs it to the other storage node n1, the potential of the storage node n1 is determined to be at the "H" level. When the mask reset signal MR falls to the "L" level, the initialization transistor TR4 is turned off, but the potential of the storage node n2 is changed by the output of the inverter INV1, which inverts the "H" level potential of the storage node n2. Maintain “L” level.

Therefore, even after mask reset signal MR falls, the potentials of storage nodes n1 and n2 are held at "H" level and "L" level, respectively.

In this way, the data stored in this memory cell MC5 is
It is initialized to logic value "O" in response to mask reset signal MR.

Note that the characteristics of the inverters INVI and INV2 and the initialization transistor TR3 are based on the mask reset signal M.
It is necessary for the potential of the storage node n2 to exceed the input inversion voltage of the inverter INVI during the period when R is at the "H" level, and for the potential of the storage node n2 to become the "L" level in response to the master reset signal MR. time is inverter INV
It is designed to be longer than the signal delay time at I. This ensures that the potentials of storage nodes n1 and n2 are at the "H" level and L level, respectively, during the period when the mask reset signal MR is at the "H" level.

Now, contrary to the above, regarding the memory cell MC6 whose stored data is to be initialized to the logical value "1", as shown in FIG.
As shown in FIG.
4 is used as an initialization transistor to connect storage node n1 and ground G.
It may be provided between the ND and the ND. In this case, during the period when the mask reset signal MR is at "H" level, the ON
The initialization transistor TR4 in the current state is pulled down to the "L" level by the potential of the ground GND. In response to this, the potential of the storage node n1 in which the output of the inverter INV2 is inverted to the "H" level is determined to be the "H" level. and,
When mask reset signal MR falls to the "L" level, the potentials of storage nodes n1 and n2 are held at the potential determined during the "H" level period of mask reset signal MR by the inverting operations of inverters INVI and INV2. In other words, the data in this memory cell MC6 has the logical value "
It is initialized to 1”.

Of course, in this case, inverters INVI and I
The characteristics of NV2 and initialization transistor TR4 are designed so that the potentials of storage nodes nl and n2 reliably change as described above during the period when mask reset signal MR is at "H" level.

In the above embodiment, the initialization transistor lowers the potential of the storage node, but it may conversely raise the potential of the storage node in response to the mask reset signal MR. FIGS. 3(a) and 3(b) are circuit diagrams showing the configuration of memory cells that require initialization in such a case, and show still another embodiment of the present invention.

Referring to FIG. 3(a), the memory cell MC7 whose stored data is to be initialized to a logical value "0" is connected to the initialization transistor TR from the memory cells MCI and MC2 in FIG.
4 is removed. In this memory cell MC7, the initialization transistor TR3 is conductive during the period when the mask reset signal MR is "H", and the storage node n1
The potential of is raised to the "H" level by the power supply VCC.

Therefore, the potential of the storage node n2 is brought to the "L" level by the output of the inverter INV2, which inverts the "H" level potential of the storage node n1. therefore. In this memory cell MC7 as well, the stored data is initialized to the logical value "0" in response to the mask reset signal MR.

Referring to FIG. 3(b), contrary to the above, for the memory cell MC8 whose stored data is initialized to the logical value "1", the transistor TR4 is connected to the storage node n2 and the power supply V. C
established between. Therefore, in this case, the potentials of storage nodes n1 and n2 are determined to be "L" and "H", respectively, during the period when mask reset signal MR is at "L" level.

Note that in this case as well, inverters INVI and INV
The characteristics of initialization transistor TR2 and initialization transistor TR3 are set so that the above-described potential change reliably occurs at storage nodes nl and n2 during the period when mask reset signal MR is at the "H" level.

In the embodiments shown in FIGS. 1 to 3, a case has been described where only an N-channel MOS transistor is used as the initialization transistor, but a P-channel MO3) transistor may also be used.

Figure 4 shows an N-channel MOS as an initialization transistor.
FIG. 7 is a circuit diagram showing a configuration of a memory cell using a transistor and a P-channel MOS transistor, and shows still another embodiment of the present invention.

Referring to FIG. 4(a), memory cell MC9 whose stored data is to be initialized to a logical value "O" is an N-channel M in memory cells MCI and MC2 in FIG.
It has a configuration in which the OS transistor TR3 is replaced with a P-channel MO8) transistor TR5. However, in this case, the mask reset signal MR is input as is to the gate of the transistor TR4, while the inverted signal MR of the mask reset signal MR is input to the gate of the transistor TR5. This inverted signal MR is the master reset signal M output from the reset signal generation circuit 16 in FIG.
This can be obtained by inverting R using an inverter (not shown) or by creating a mask reset signal as a complementary signal pair in the reset signal generation circuit 16.

In this embodiment, since the mask reset signal MR is a one-shot pulse of "H", the inverted signal MR is "L" during the period when the master reset signal MR is at the "H" level.
”, which is a one-shot pulse of “L” level.

Therefore, during the period when the mask reset signal MR is "H'', both transistors TR5 and TR4 are ON.
state.

As a result, the transistor TR5 supplies the potential of the power supply VCC to the storage node n1 and changes the potential of the storage node n1 to '
H'' level, transistor TR4 connects to storage node n2
The potential of the ground GND is lowered to the "L" level by the potential of the ground GND. Then, the mask reset signal MR becomes 11 L.
When the potential level of storage nodes nl and n2 falls to "H" level (when inverted signal MR rises to "H" level), the potential levels of storage nodes nl and n2 are maintained as they are. Therefore, even in a memory cell with such a configuration, the stored data is set to the logical value "0" when the power is turned on.
can be initialized to .

Referring to FIG. 4(b), conversely, the stored data is set to the logical value "1".
In the memory cell MC10 to be initialized to ``, the transistors TR4 and TR5 may be connected to the storage nodes n1 and n2, respectively, contrary to the above.Thereby, in response to power-on, the mask reset signal MR is set to ``. H
During the period when the storage nodes n1 and n2 are at the "L" level and the "H" level by the transistors TR4 and TR5, respectively.

In the embodiment shown in FIG. 4, a P-channel MO transistor and an N-channel MO transistor are used as initialization transistors.
8) Two transistors of transistors were used,
Of course, it is also possible to use only P-channel MOS transistors.

FIG. 5 is a circuit diagram showing the configuration of a memory cell that can be initialized using one P-channel MOS transistor, and shows still another embodiment of the present invention.

FIGS. 5(a) and 5(b) have a configuration in which the initialization transistor TR4 is removed from FIGS. 4(a) and 4(b), respectively. Therefore, a complementary mask reset signal is not required in this case.

Referring to FIG. 5(a), in the memory cell MCII whose stored data is to be initialized to the logical value "0", the inverted mask reset signal MR becomes "L" in response to power-on. During the period, the storage node n1 is supplied with the potential of the power supply Vcc and becomes "H" level. Therefore, the potential of storage node n2 becomes "L" level by inverter INV2 which is inverted to the potential of storage node n1.

Conversely, referring to FIG. 5(b), the stored data is converted into a logical value "
In the memory cell MC12 to be initialized to "1", the transistor TR5 is provided on the storage node n2 side. Therefore, in this memory cell MC12, the storage node is initialized during the period when the inverted mask reset signal MR is "L". nl
and the potential of n2 is "L" level and "H" level.

In this way, it is possible to initialize the data stored in the memory cell to arbitrary data using only the P-channel MO8) transistor. In this case as well, the inverters INVI and INV2 and the initialization transistor T
The characteristics of R5 and the like are designed so that the potentials of storage nodes n1 and n2 reliably change as described above during the period when mask reset signal MR is at "H" level.

In this way, in any of the above embodiments, desired initialization can be carried out by simply providing at least one initialization transistor in a position corresponding to the initialization data in any memory cell to be initialized when manufacturing the memory array. It can be done quickly. However, when two transistors are used, the potentials of the two storage nodes are simultaneously forced to correspond to the initialization data, whereas when one transistor is used, the potential of one storage node is forced to the one corresponding to the initialization data. The potential is determined after the potential of the other storage node is determined, so 2
Initialization time can be further reduced by using two transistors as initialization transistors. However, when one initialization transistor is used, the number of elements constituting the memory cell is reduced, so the area of the memory cell array that increases due to the addition of the initialization element becomes smaller.

Therefore, the configuration of the memory cell to be initialized may be arbitrarily selected depending on the application of the semiconductor memory device.

In any of the above embodiments, the mask reset signal MR and its inverted signal MR are used only to control ON10FF of the initialization transistor.

However, it is also possible to use this mask reset signal MR or its inverted signal 1 as data to be written into a memory cell for initialization.

FIG. 6 is a circuit diagram showing the configuration of a memory cell that can take in the mask reset signal MR and its inverted signal Hyakken as data for initialization, and shows still another embodiment of the present invention. .

Referring to FIG. 6(a), this memory cell MC13 is
Inverters INVI and INV2 and transfer gates hTRl and TR that constitute a flip-flop
2 plus a P-channel MO as an initialization transistor.
It includes an S transistor TR6 and an N channel MO8) transistor TR7. Transistor TR6 is inverter I
It is connected between the output terminal of NVI and the gate of transistor TR7. On the other hand, transistor 7 is inverter INV
The transistor TR6 is connected between the output terminal of the transistor TR6 and the gate of the transistor TR6. A mask reset signal M is applied to the gate of the transistor TR7 and the gate of the transistor TR6, respectively.
R and its inverted signal MR are applied.

When the power is turned on, the mask reset signal MR and its inverted signal MR go to H" level and "L" level, respectively, and the transistors TR6 and TR7 become conductive in response to the inverted signal 1 and the mask reset signal MR, respectively. As a result, The master reset signal MR is applied to the input terminal of the inverter rNV2 via the transistor TR6, and the inverted signal MR is applied to the input terminal of the inverter INV1 via the transistor TR7.As a result, the potential of the storage node n1 rises and the memory is stored. The potential of the node n2 decreases.Therefore, as in the embodiment shown in FIG. The time from when the potential of the storage node n2 starts to rise due to the potential of the inverted signal MR until it reaches the "H" level is longer than the signal delay time of the inverter INVI, and after the potential of the storage node n2 starts to fall due to the potential of the inverted signal MR, it reaches the "L" level. By setting the time to be longer than the signal delay time of inverter INV2, the potentials of storage nodes n1 and n2 reach "H" level and "H" level, respectively, during a short period when master reset signal MR is at "H" level. Forced to L” level. Mask reset signal MR and its inverted signal MR return to "L" and "H" levels, respectively, and transistors TR6 and TR7 become non-conductive. As a result, mask reset signal MR and its inverted signal 1
is electrically isolated from inverters INVI and INV2. However, the potentials of storage nodes n1 and n2 are held at the forced "H" level and "L" level, respectively, by the inverting operations of inverters INVI and INV2. That is, the data stored in this memory cell MC13 is initialized to a logical value of "0" in response to power-on.

On the other hand, the memory cell MC14 whose stored data should be initialized to the logical value "1" when the power is turned on is, for example, shown in FIG. 6(b).
) if it is configured as shown. Contrary to the above case, the transistor TR6 coupled to the mask reset signal MR is provided on the storage node n2 side, and the inverted signal MR of the mask reset signal MR is connected to the storage node n1.
installed on the side. In this memory cell MC14,
During the period when the mask reset signal MR is at “H” level,
The potential of the storage node n1 is forced to the "L" level by the potential of the inverted signal MR, and the potential of the storage node n2 is forced to the H level by the potential of the mask reset signal MR.

According to the embodiments described above, one of the two storage nodes of each memory cell whose storage data is to be initialized is directly forced to a potential corresponding to the initialization data. However, it is also possible to indirectly force the potential of at least one of these two storage nodes to a potential corresponding to the initialization data using the mask reset signal MR or its inverted signal 1.

FIG. 7 is a circuit diagram showing the configuration of a memory cell that can indirectly force the potential of a storage node to a potential corresponding to initialization data by being controlled by a mask reset signal MR or its inverted signal MR.

Referring to FIG. 7(a), this memory cell MC15 is
Memory cells MCI to MC shown in FIGS. 1 to 6
In place of the inverter INVI in 14, two-man power NA
Includes ND game hND1.

The structure of other parts of this memory cell MC15 is the same as that of the conventional memory cell MC shown in FIG. 15. NAND
One input terminal of the gate ND1 is connected to the storage node n2, and the output terminal of the NAND gate ND1 is connected to the storage node n1. An inverted signal MR of the mask reset signal MR is applied to the other input terminal of the NAND game (NDl).

If the potential of at least one of the input terminals of the NAND gate is at the "L" level, the output logic level of the NAND gate becomes the "H" level regardless of the potential of the other input terminals. Therefore, when the potential of the inverted signal MR is at the "L" level, the output potential of the NAND gate ND1 in this memory cell MC15 is fixed at the "H" level. Conversely, if the potential of the inverted signal is at the "H" level, the output potential of the NAND gate NDI is the potential level of the input terminal that does not receive the inverted signal MR of the NAND gate NDI, that is,
It depends on the potential level of storage node n2. That is, when the storage node n2 potential is at the "H" level, the NAND gate ND1 is at the "L" level, and when the storage node n2 potential is at the "L" level, the NAND gate NDI is at the "L" level.
In this way, the NAND game hN
D1 operates as an inverter when the potential of the inverted signal 1 is "H", and maintains the "H" level potential only during the period when the potential of the inverted signal MR is "L" regardless of the potential level of the storage node n2. Therefore, during the period when the inverted signal 1 is at "L" level in response to power-on,
The potential of storage node n1 is fixed at "H" level by the output potential of NAND gate ND1.

The potential level of this storage node n1 is determined by the inverter INV'
2 and transmitted to storage node n2. As a result, the potential of storage node n2 is fixed at "L" level. When the inverted signal 1 returns to “H” level, the NAND
The output potential of gate NDI is in a state where it can change depending on the potential level of storage node n2. However, the potential level of storage nodes n1 and n2 changes after that because
Transfer gates TRI and TR2 are applied to storage nodes n1 and n2, respectively, by external data writing.
This is only the case where the potentials of bit lines BIT and BIT are applied via the bit lines BIT and BIT. On the other hand, if the potential of the inverted signal ■ is "H", the NAND gate ND1 operates as an inverter. Therefore, the potentials of storage nodes n1 and n2 remain at the NAND gate N until new data is given to storage nodes n1 and n2 by external data writing.
The inverting operations of D1 and inverter INVI maintain them at the "H" level and the "L" level, respectively.

As described above, according to the present embodiment, the potential level of the storage node n1 is indirectly forced to the "H" level during the period when the inverted signal MR of the mask reset signal is at the "L" level, so that the memory cell The data stored in the MC 15 is initialized to a logical value of "0".

On the contrary, the memory cell MC16 whose stored data is to be initialized to the logical value "1" may be configured as shown in FIG. 7(b), for example. That is, the memory cell MC16 is the seventh
In figure (a), the NAND gate ND1 is replaced with a simple inverter, and the inverter INV2 is replaced with an inverted signal MR.
It has a configuration in which it is replaced with a two-manpower NAND gate NDI that receives as input. In this case, storage node n2
The potential of is fixed at "H" level. On the other hand, during other periods, the NAND gate NDI operates as a mere inverter. Therefore, storage nodes n1 and n2
The potentials of are once forced to the "L" level and "H" level in response to power-on, respectively, and then, when the transfer gates TR1 and TR2 are in the ON state, they are changed according to the potentials of the bit lines BIT and ■R1. It becomes a state that can change.

In the embodiment shown in FIG. 7, inverters I Nvl and I
One of NV2 was replaced with a NAND gate.

However, if the mask reset signal MR itself is used,
One of inverters INVI and TNV2 is set to NO
It is also possible to initialize the potential levels of storage nodes n1 and n2 by replacing them with R gates.

FIG. 8 is a circuit diagram showing the structure of a memory cell in which stored data can be initialized by such a method, and shows still another embodiment of the present invention.

Referring to FIG. 8(a), this memory cell MC17 is
In the memory cell MC16 of FIG. 7(b), the NAND gate NDI is replaced with a two-manufactured NOR gate, and the inverted signal MR is replaced with a master reset signal MR. During the period when the potential of mask reset signal MR is at "H" level, NOR gate NRI outputs "L" level potential regardless of the potential level of storage node n1.

During the period when the potential of the mask reset signal MR is at the "L" level, the NOR gate (NRI) operates as an inverter and outputs a potential at a logic level opposite to the potential level of the storage node n1. Therefore, during the period in which mask reset signal MR goes to "H" in response to power-on, the potential of storage node n2 is fixed to "L" level by the output potential of NOR gate NRI. In response, the potential of storage node n1 is also fixed at the "H" level by the output potential of inverter INVI. Mask reset signal MR
When the potential of storage nodes n1 and n2 returns to the "L" level, the potential levels of storage nodes n1 and n2 enter a state where they can change only in response to external data writing. In this way, the data stored in the memory cell can be initialized to the logical value "0" even by using the NOR gate.

Referring to FIG. 8(b), the memory cell MC18 whose stored data is to be initialized to the logical value "1" is shown in FIG. 7(a).
The memory cell MC15 shown in FIG. 1 has a configuration in which the NAND gate NDI is replaced with a two-manual NOR gate NR1, and the inverted signal MR is replaced with a mask reset signal MR. In this case, the potential of the storage node n1 is fixed at the "L" level by the output of the NOR gate NRI while the mask reset signal MR is at the "H" level in response to power-on. Therefore, contrary to the previous case, storage node n
The potentials of 1 and n2 are once forced to the "L" level and the "H" level in response to power-on, respectively.

As described above, in the embodiment shown in FIGS. 7 and 8, the logic circuit constituting the flip-flop for holding the potentials of storage nodes n1 and n2 receives the mask reset signal MR for initialization. Or its inverted signal MR
Directly controlled by. Therefore, the time required for the potentials of storage nodes n1 and n2 to be forced to a level corresponding to the initialization data is the time required for the potentials of storage nodes n1 and n2 to be INVI and INV2 and NAND
This is the time required to reach the output potential level of gate ND1 and NOR gate NR1). Therefore, the length of the period during which the potential of the mask reset signal MR is at the "H" level may be set to approximately the signal delay time in the logic circuit. Therefore, according to the embodiments shown in FIGS. 7 and 8, data stored in memory cells can be initialized more quickly.

NAND gate ND1 and NOR gate NRI in FIGS. 7 and 8 each require eight transistors, for example, if they are constructed from MOS transistors. However, if both the mask reset signal MR and its inverted signal MR are used, each of these logic gates becomes
It is also possible to configure it with seven MOS transistors.

FIG. 9 shows the memory cell MC shown in No. 81m(a).
17 is a circuit diagram showing in detail the configuration of a memory cell MC19 that realizes the same logical operation as MC17 with fewer transistors, and shows still another embodiment of the present invention. Referring to Figure 9,
The inverter INVI shown in FIG. 8(a) is connected to the power supply VC.
P channel M connected in series between C and ground GND
O8) This is a so-called CMOS inverter including a transistor 110 and an N-channel MOS transistor 120. The connection point between transistors 110 and 120 is storage node n1. On the other hand, NOR gate NR2 has a gate connected to storage node n1, and P-channel MO3
) A transistor 130, an N-channel MOS transistor 140, and an N-channel MOS transistor 150 provided between the transistor 130 and the ground GND.

Transistor 140 is connected to transistors 130 and 15
0 connection point and ground GND. The connection point of transistors 130 and 150 is connected to inverter INV
It is connected to the gate connection point of transistors 110 and 120, which is the input terminal of I. The connection point between transistors 130 and 150 is the output terminal of this NOR gate NR2, ie, storage node n2. A mask reset signal MR is applied to the gate of the transistor 150, and an inverted signal MR of the mask reset signal MR is applied to the source of the transistor 130.

In FIG. 9, transistor 150 is conductive during a period when mask reset signal MR is at "H" level. Therefore, even if the transistor 140 is in a non-conducting state,
A current flows from storage node n2 to ground GND. Also,
While the mask reset signal MR is at the "H" level, its inverted signal P' is at the "L" level. Therefore, even if the transistor 130 is conductive, the storage node n2
The "L" level potential is applied to the "L" level potential.

Therefore, during the period when mask reset signal MR is at "H" level, the potential of storage node n2 is at "L" level regardless of the gate potentials of transistors 130 and 140. When the potential of the storage node n2 goes to the "L" level, the transistor 110 in the inverter INV2 becomes conductive and transmits the potential of the power supply VCC to the storage node n1. As a result, the potential of storage node n1 becomes "H" level.

During the period when mask reset signal MR is at "L" level, transistor 150 is in a non-conductive state.

On the other hand, while the mask reset signal MR is at the "L" level, its inverted signal MR is at the "H" level, so the source potential of the transistor 130 is at the "H" level. Therefore, transistors 130 and 140, like transistors 110 and 120, operate as CMOS inverters.

In this way, according to this embodiment as well, a memory cell which is operationally equivalent to the memory cell MC17 shown in FIG. 8(a) can be obtained. Note that in order to realize the same logic operation as the memory cell MC18 shown in FIG. 8(b) with fewer transistors, the inverter INV2 and NOR gate NR1 in FIG. Inverter INVI and NOR gate NR2 having the configuration shown may be used.

FIG. 10 shows the memory cell MC15 shown in FIG. 7(a).
FIG. 3 is a circuit diagram showing in detail the configuration of a memory cell MC20 that realizes the same logical operation as with fewer transistors, and shows still another embodiment of the present invention. Referring to Figure 10,
The inverter INV2 in FIG. 7(a) has a power supply Vc
P channel M connected in series between C and ground GND
O8) A CMOS inverter including transistor 160 and N-channel MO3) transistor 170.

The connection point between transistors 160 and 170 is storage node n2. On the other hand, NAND gate ND2 includes N-channel MOS transistor 190 and P-channel MOS transistor 20 whose gates are connected to storage node n2.
0 and a P-channel MO8) transistor 180 provided between the power supply Vcc and the transistor 190. Transistor 200 is connected to power supply Vcc and inverter INV2.
It is provided between the gate connection point of transistors 160 and 170, which is the input terminal of the transistors 160 and 170. The connection point between transistors 180 and 190 is the output terminal of this NAND gate ND2, ie, storage node n1. transistor 1
A mask reset signal MR is applied to the source of 90,
A mask reset signal M is applied to the gate of the transistor 180.
An inverted signal MR of R is applied.

In FIG. 10, during the period when the inverted signal MR of the mask reset signal MR is at "L" level, the transistor 1
80 is conductive. Therefore, even if transistor 200 is non-conductive, current flows from power supply Vcc to storage node n1. On the other hand, while the inverted signal MR is at the "L" level, the mask reset signal MR is at the "H" level. Therefore, even if transistor 190 is conductive, the potential of storage node n1 is at "H" level. Therefore, during the period when the inverted signal MR is "L", the potential of the storage node nl becomes "H" level regardless of the gate potentials of transistors 190 and 200. Since the potential of the storage node n1 is at the "H" level and the transistor 170 in the inverter INV2 becomes conductive,
The potential of storage node n2 becomes "L" level.

During the period when the inverted signal MR is at the "H" level, the transistor 180 is in a non-conductive state.

On the other hand, since the mask reset signal MR is at the "L" level during this period, the source potential of the transistor 190 is at the "L" level. Therefore, transistors 190 and 200
are CMOS transistors like transistors 160 and 170.
Operates as an inverter.

Therefore, according to this embodiment as well, a memory cell which is operationally equivalent to the memory cell MC15 having the configuration shown in FIG. 7(a) can be obtained. Note that in order to realize the same logic operation as the memory cell MC16 shown in FIG. 7(b) with fewer transistors, the inverter IN shown in FIG. 7(b)
VI and NAND gate NDI are also connected to inverter INV2 and NAND, respectively, as shown in FIG. 10, for example.
It may be configured similarly to gate ND2.

In this way, according to the embodiment shown in FIGS. 9 and 10, although two control signals (MR and FISH1) are required, initialization of data stored in a memory cell can be realized with fewer elements. . Therefore, these embodiments can suppress an increase in memory cell size due to the addition of an initialization circuit to a conventional memory cell component.

In all of the above embodiments, the present invention was applied to an SRAM including a latch circuit constituted by two inverters, but the present invention is applied to a DRAM (
dynamic random access memory), etc.
It is also possible to apply the present invention to a semiconductor memory device in which the internal configuration of memory cells is fundamentally different from that of the present invention. FIG. 11 is a circuit diagram showing the internal structure of a memory cell when the present invention is applied to a DRAM, and shows still another embodiment of the present invention.

Referring to FIG. 11(a), a memory cell MCD1 of a normal DRAM is basically connected in series between a bit line BIT and a cell plate CP fixed at a predetermined low potential. It is composed of a channel MOS transistor TR8 and a memory capacitor C. The gate of the transistor TR6 is connected to the word line WL.

During normal data writing, as in the case of SRAM, an "H" level voltage is applied to the word line WL, and the transistor T
R8 becomes ON state. At the same time, a potential corresponding to the data to be written (potential level "L" corresponding to a logical value "0" or potential level "H" corresponding to a logical value "1") is applied to the bit line BIT. Therefore, during normal data writing, a potential corresponding to the write data is transmitted to the connection point n3 between the transistor TR8, which is a transfer gate connecting the bit line and the memory cell, and the memory capacitor C, via the transistor TR8. When this potential is at the "H" level, the memory capacitor C is charged, and conversely, when this potential is at the "L" level, the memory capacitor C is discharged. In this way, in a DRAM, storage node n3 is
Data is written to. When writing is completed, the word line W
Since the potential of L returns to the “L” level, the transistor TR8
is in the OFF state, but the potential of storage node n3 remains unchanged for a period of time (usually several hundred milliseconds) depending on the capacitance of memory capacitor C.
J seconds) is held.

Now, in order to initialize the storage data of the memory cell having such a configuration by applying the present invention, for example, the storage node n
3 is an N-channel MOS transistor TR whose gate and drain receive the mask reset signal MR as described above.
9 is connected. Mask reset signal MR when power is turned on
When the transistor TR9 rises to the "H" level, the transistor TR9 turns on and supplies this "H" level voltage to the storage node n3. As a result, the memory capacitor C is charged in the same manner as in normal writing, and the logical value "1" is written into this memory cell MCD1 as initialization data. Then, when the mask reset signal MR falls to the "L" level, the initialization transistor TR9 is turned off and does not force the potential of the storage node n3 to any level. However, as in normal data writing, the potential level of storage node n3 is maintained by memory capacitor C for the predetermined time.

Conversely, the data stored in the memory cells of DRA and M are set to the logical value “0”.
11(b), the master reset signal MR is applied to the gate of the transistor TR9 for initialization in the same way as before, while the gate of the transistor TR9 is Drain is cell play)
Connected to CP. As a result, the potential of storage node n3 is lowered by the potential of cell plate CP during the period when the mask reset signal is at the "H" level when the power is turned on. Therefore, in this case, the potential of storage node n3 is at the "L" level, and the data stored in memory cell MCD2 is initialized to the logical value "0".

In the above two examples, an N-channel MOS transistor was used as the initialization transistor, but a P-channel MOS transistor may also be used. In such a case, for example, as shown in FIG. 11(C), the gate receives the inverted signal MR of the mask reset signal MR, and the drain receives the mask reset signal MR.
P-channel MO8) transistor TR10 receiving the data is connected to storage node n3. As described above, the inverted signal MR is generated by converting the master reset signal MR into an inverter I, for example.
Obtained by inverting with NV3. When the mask reset signal MR is at the "H" level, its inverted signal MR is at the "L" level, so in this memory cell MCD3, the transistor TR10 is in the "H" level while the mask reset signal MR is at the "H" level. It is also in the ON state, and the potential “H” of the uninverted mask reset signal MR applied to the drain is transferred to the storage node n.
Supply to 3. Therefore, in this case, the data stored in this memory cell MCD3 is initialized to the logical value "1".

Furthermore, the complementary master reset signals MR, M
It is also possible to use R to initialize the data stored in the memory cell to a logical value of "0". In this case, for example, the drain of the transistor TR10 is set to "H" when the power is turned on.
Instead of the master reset signal MR that becomes the level, it is sufficient if its inverted signal MR is given.

Furthermore, when data stored in a memory cell is initialized to the logical value "O" using complementary mask reset signals in this manner, it is also possible to use an N-channel MOS transistor as the initialization transistor. For example, referring to FIG. 11(d), in memory cell MCD4, an N-channel MOS transistor TR9 is connected to storage node n3 as an initialization transistor. An inverted signal MR of the mask reset signal MR is applied to the drain of the transistor TR9, and this inverted signal MR is inverted again by an inverter INV4 and applied to the gate of the transistor TR9. Therefore, during the period when the master reset signal MR is at the "H" level, the transistor TR9 receives the "H" level voltage from the inverter INV4 and becomes conductive, and the potential of the storage node n3 is lowered by the "L" level signal MR. . Therefore, the data stored in this memory cell MCD4 is initialized to the logical value "On".

In addition, in FIGS. 11(a) to 11(d), the mask reset signal MR and its inverted signal MR are
As in the case of a RAM, for example, it may be applied to initialization transistors provided in one column of memory cells connected to the same bit line via a common connection line.

As mentioned above, in a DRAM as well, a transistor for initialization is provided for each memory cell to be initialized, and a mask reset signal MR or its inverse is applied to the gate and drain of the transistor for initialization according to the initialization data. By designing the memory array so that signal MR is applied, data stored in predetermined memory cells can be initialized all at once in response to power-on.

In this way, the present invention is also applicable to DRAM, but DRAM originally consists of a memory cell with very few circuit elements, one transistor and an artificial capacitor, thereby reducing the area occupied by the memory cell on the chip. It is designed to be as small as possible. Therefore, the application of the present invention to DRAM takes advantage of both the risk of increasing the area per memory cell caused by providing a transistor for initialization inside the memory cell and the advantage of shortening the initialization time. The emphasis should be given to the purpose of use and other factors.

In any of the embodiments described above, the mask reset signal MR is a one-shot pulse at the "H" level, or conversely, even if it is a one-shot pulse at the "L" level, the polarity of the initialization transistor used can be reversed. A similar effect can be obtained by doing so.

Furthermore, the signal used to instruct the initialization of the data stored in the memory cell is not limited to the mask reset signal;
The signal may be any signal generated within the chip or applied from outside the chip that is at a level that instructs the initialization for a certain period of time in response to power-on.

In this way, according to these embodiments, even complex initialization with no regularity in addresses to be initialized, initialization data, etc. can be performed more easily than before by simply adding a very simple circuit to a conventional memory array. It can also be done much faster and reliably.

[Effects of the Invention] As described above, according to the present invention, by adding a circuit for simple initialization in the memory cell, predetermined storage data of the memory cell can be converted to predetermined initialization data. can be initialized faster than before. Therefore, a semiconductor memory device is provided that can perform even complex initialization at high speed and with high reliability. As a result, by using such a semiconductor memory device in various semiconductor integrated circuit devices and systems, the functions of the semiconductor integrated circuit devices and systems can be improved.

[Brief explanation of the drawing]

FIG. 1 is a partial circuit diagram of a memory array in an SRAM according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the structure of a memory cell in another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a structure of a memory cell in another embodiment of the present invention. 4 is a circuit diagram showing the configuration of a memory cell in yet another embodiment of the present invention. FIG. 5 is a circuit diagram showing the configuration of a memory cell in yet another embodiment of the present invention. 6 is a circuit diagram showing the structure of a memory cell in yet another embodiment of the present invention; FIG. 7 is a circuit diagram showing the structure of a memory cell in yet another embodiment of the present invention. 8 is a circuit diagram showing the structure of a memory cell in still another embodiment of the invention, FIG. 9 is a circuit diagram showing the structure of a memory cell in still another embodiment of the invention, and FIG. 1O is a circuit diagram showing the structure of a memory cell in still another embodiment of the invention. A first circuit diagram showing the configuration of a memory cell in still another embodiment of the present invention.
FIG. 1 is a circuit diagram showing the configuration of a memory cell in a DRAM according to another embodiment of the present invention, FIG. 12 is a schematic block diagram showing the overall configuration of an SRAM according to an embodiment of the present invention, and FIG.
The figure shows the mask reset signal MR and its inverted signal MR.
14 is a schematic block diagram showing the overall configuration of a conventional SRAM having a function of hardware initializing data stored in a memory array, FIG. 15 is a partial circuit diagram of a memory array in a conventional SRAM, Figure 16 shows the conventional S
FIG. 2 is a circuit diagram showing in detail the configuration of a memory cell in a RAM. In the figure, MC, MCI to MC20, and MCD to MCD4 are memory cells, WL is a word line, BIT and BIT are bit lines, V(( is a power supply, GND is a ground, and C
P is a cell plate, TR1゜TR2 and TR6 are transfer gates, INv■ to INV4 are inverters, T
R3 to TR7゜TR9 and TR10 are initialization transistors, 1a and 1b are memory arrays, 2 is a row address buffer, 3 is a row decoder, 4 is a column address buffer, 5 is a column decoder, 6 is a 110 circuit, 7 is a block address Buffer, 8 block decoder, 9 output buffer, 10 input data control circuit, 1
1 is a large power buffer, 12 is an initialization data control circuit, 13 is a chip and input/output control circuit, 14 is a clock generation circuit, 15 is an initialization address generation circuit, n1 to n
3 is a storage node. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A plurality of memory cells each having a storage node to be held at a potential corresponding to storage data, and a predetermined portion of the plurality of memory cells corresponding to predetermined initialization data. potential forcing means, provided in each of the memory cells, for forcing the potential of the storage node of the predetermined memory cell to a potential corresponding to the initialization data; and in response to power-on, all of the potential forcing means What is claimed is: 1. A semiconductor memory device that is capable of initializing stored data and is provided with a means for activating data.