JP5463918B2 - Electrical component connection inspection method for electric component built-in substrate and electric component built-in substrate - Google Patents

Description

  The present invention relates to a method for inspecting the conduction state of a capacitor after the manufacture of the substrate with a built-in capacitor and the structure of the substrate with a built-in capacitor. In particular, it is possible to provide a capacitor-embedded substrate that enables connection inspection of individual capacitors in a state where a plurality of capacitors having different capacitance values are connected to the same power source.

  When conducting an electrical inspection of a capacitor built in a substrate, a method of measuring impedance at a single frequency using an external terminal taken out by a common power supply is generally used (FIG. 9). However, when multiple capacitors are hanging from a common power source, the combined capacitance measurement method uses a small capacitance when a large capacitance and a small capacitance (capacitance less than the tolerance of the large capacitance) are connected in parallel. Since the amount of change in the impedance value based on the presence of the capacitor is small, it was impossible to inspect.

  As an example, a method of individually inspecting each capacitor for a circuit in which a plurality of capacitors are connected in parallel has been proposed (see, for example, Patent Document 1).

  In the method disclosed in this patent document, a signal generator and its output terminal are connected to a power supply pattern, wiring is drawn out from the capacitor pad connected to the ground pattern to the substrate surface, and wiring is connected to a voltmeter. In addition, another electrode terminal of the voltmeter is connected to the ground pattern. In this case, a predetermined voltage is generated from the signal generator, and the voltage V is measured with a voltmeter. If the voltage value measured with the voltmeter is not 0 volts (V ≠ 0), it is determined that a capacitor is connected. If the voltage value measured with the voltmeter is 0 volts (V = 0), the capacitor Is determined to be unconnected.

  As another example, a method for inspecting a small-capacitance capacitor with respect to a circuit in which a large-capacity capacitor and a small-capacitance capacitor are connected in parallel has been proposed (see, for example, Patent Document 2).

  In this example, the frequency of the capacitor that can be removed differs depending on the capacitance. Therefore, a spike voltage waveform having a predetermined frequency is input to the signal line, and the spike voltage waveform remains in the signal measured at the external terminal of the board. It is possible to inspect individual capacitors by checking whether the

Japanese Patent Laid-Open No. 2004-221574 JP 2008-292399 A

  When the method of FIG. 10 (Patent Document 1) is applied to a substrate with a built-in capacitor, the measurement terminal cannot be brought into direct contact with the electrode of the capacitor. Therefore, it is necessary to draw out the wiring connected to the electrode to the surface of the substrate. is there.

  Therefore, it is necessary to draw extra wires as many as the number of capacitors, deterioration of electronic circuit characteristics due to the addition of extra wires, increase in board size, increase in cost due to increase of measurement terminals, and the number of measurements. There arises a problem that only the number of capacitors is required. Moreover, since the voltage is measured by this method, the capacitance of the actually built-in capacitor remains unknown.

  In addition, when inspecting a capacitor built in the substrate by the method of FIG. 11 (Patent Document 2), the frequency of the spike waveform must be determined by calculating the inductance component (L) and capacitance component (C) of the wiring. However, there is a problem that an accurate frequency cannot be calculated because the handling of the inductance (L) attributed to the wiring pattern is not considered.

  Therefore, in the present application, focusing on measuring the combined impedance including the inductance component (L) and the capacitance component (C) of the wiring pattern, it is possible to easily perform the inspection after the manufacture of the capacitor built-in substrate. An object of the present invention is to provide an electrical component built-in substrate inspection method and an electrical component built-in substrate structure.

  In order to solve the above problems, the present invention employs the following configuration.

That is, the invention according to claim 1 is an electrical component connection inspection method for an electrical component built-in board incorporating at least two or more capacitors. In the electrical component built -in substrate (1), one end of the capacitor is the Connected to a common power supply pattern (VP) of the electric component built-in substrate (1), and the other end of the capacitor is connected to a common ground pattern (GP) of the electric component built-in substrate (1). The above capacitors are mounted in parallel between the common power supply pattern (VP) and the common ground pattern (GP), and the common power supply pattern (VP) connected to the capacitor and the capacitor is mounted. ) And the combined impedance with the known inductance of each of the common ground patterns (GP) connected to the capacitor. Defined measurement terminal pads (P1a, P1b) for performing the impedance measurement the resonant frequency of each was measured for the frequency (2) separated by a time constant which is disposed on the surface of the electric component-embedded substrate (1) One end of the measurement terminal pad (P1a) and the capacitor (C2), and the other end of the other measurement terminal pad (P1b) and the capacitor (C2) are located inside the electric component built-in substrate (1). The capacitor (C2), which is connected through the conductors (V1a, V1b) penetrating, and disposed at a position closest to the measurement terminal pad (P1a) and the other measurement terminal pad (P1b), Among the capacitors mounted on the electric component built-in substrate (1), the capacitor (C2) has the smallest capacitance value. Characterized in that the said resonant frequency for electrical connection test individual internal components by performing the impedance measurement (2) as the measurement frequency.

According to a second aspect of the present invention, there is provided the electrical component connection inspection method according to the first aspect, wherein the conductors (V1a, V1b) penetrating the interior of the electrical component built-in substrate (1) are one end of the capacitor. Are connected directly between the common power supply pattern (VP) and the measurement terminal pad (P1a), and the other common end of the capacitor is directly connected to the common ground pattern (GP). The measurement terminal pads (P1b) are formed respectively .

Furthermore, the invention according to claim 3 is an electrical component connection inspection method for an electrical component built-in board having at least two or more capacitors built-in, and in the electrical component built-in substrate (1), one end of the capacitor is the Connected to a common power supply pattern (VP) of the electric component built-in substrate (1), and the other end of the capacitor is connected to a common ground pattern (GP) of the electric component built-in substrate (1). The above capacitors are mounted in parallel between the common power supply pattern (VP) and the common ground pattern (GP), and the common power supply pattern (VP) connected to the capacitor and the capacitor is mounted. ), And a combined impedance with each known inductance of each of the common ground patterns (GP) connected to the capacitor The measurement terminal pads (P1a, P1b) for performing the impedance measurement (2) using the respective resonance frequencies separated by a fixed time constant as measurement frequencies are the surfaces of the electric component built-in substrate (1). The other end of the measurement terminal pad (P1a) and the capacitor (C2) and the other end of the measurement terminal pad (P1b) and the capacitor (C2) are connected to the electric component built-in substrate (1). Connected via conductors (V1a, V1b) penetrating the inside, and further, one end of the capacitor is directly connected to the conductors (V1a, V1b) penetrating the inside of the electric component built-in substrate (1). Between the common power supply pattern (VP) and the measurement terminal pad (P1a), and the other end of the capacitor is directly connected. The impedance measurement (2) is performed between the ground pattern (GP) and the other measurement terminal pad (P1b), and each of the separated resonance frequencies is used as the measurement frequency. It is characterized by conducting an electrical connection inspection of individual built-in parts .

Furthermore, the invention according to claim 4 is the electrical component connection inspection method according to any one of claims 1 to 3 , wherein the magnitude relationship between the capacitance values of the at least two capacitors is as follows . When CV1 ≧ CV2 ≧ ・ ・ ・ ≧ CVn (CVn is a capacitor capacity value, n is a natural number), a time constant corresponding to the resonance frequency in the at least two capacitors mounted on the electric component built-in substrate (LV1 * CV1) ^1/2 > (LV2 * CV2) ^1/2 >...> (LVn * CVn) ^1/2 (LVn is the capacitor and the common connected to the capacitor. The impedance value at a position where the power supply pattern and the inductance value including the common ground pattern connected to the capacitor, n is a natural number) Characterized by placing the measurement terminal pads for the scan measurement.

Further, the invention according to claim 5 is a multilayer electric component built-in substrate (1) having at least two capacitors in the inner layer, and one end of the capacitor is in the inner layer of the electric component built-in substrate (1). The at least two or more capacitors are directly connected to a common power supply pattern (VP) and the other end of the capacitor is directly connected to a common ground pattern (GP) on the inner layer of the electric component built-in substrate (1). Are mounted in parallel between the common power supply pattern (VP) and the common ground pattern (GP), and one end of the capacitor is directly connected to the common power supply pattern (VP) and the electric The common ground between the measurement terminal pad (P1a) on the surface of the outermost layer of the component built-in substrate (1) and the other end of the capacitor is directly connected. Between the turn (GP) and the other measurement terminal pad (P1b) on the surface of the outermost layer of the electric component built-in substrate (1), a conductor penetrating through the electric component built-in substrate (1) ( V1a, V1b) are formed, and a capacitor (C2) having the smallest capacitance is disposed at a position closest to the measurement terminal pad (P1a) and the other measurement terminal pad (P1b), and the measurement terminal pad (P1a) and The magnitude relation of the time constant viewed from the other measurement terminal pad (P1b) is (LV1 * CV1) ^1/2 > (LV2 * CV2) ^1/2 >...> (LVn * CVn) ^1/2 (LVn is The capacitor, the common power supply pattern connected to the capacitor, and the inductance value including the common ground pattern connected to the capacitor, where n is a natural number) It is characterized in.

  According to the present invention, since the resonance frequency of each capacitor is separated, the electrical connection inspection of at least two capacitors can be performed in one step by performing impedance measurement.

It is a figure which shows the whole which concerns on embodiment of this invention. It is a figure which shows an example of the wiring pattern which concerns on embodiment of this invention. It is a figure which shows an example of the measurement result which concerns on embodiment of this invention. It is a figure which shows an example of the measurement result which concerns on embodiment of this invention. It is a figure which shows an example of the wiring pattern which concerns on embodiment of this invention. It is a figure which shows an example of the measurement result which concerns on embodiment of this invention. It is a figure which shows an example of the circuit model which concerns on embodiment of this invention. It is a figure which shows an example of the measurement result of the circuit model which concerns on embodiment of this invention. It is a figure which shows the concept of embodiment concerning a prior art. It is a figure which shows the concept of embodiment concerning a prior art (patent document 1). It is a figure which shows the concept of embodiment concerning a prior art (patent document 2). It is a figure which shows the measurement principle of the impedance by an impedance analyzer.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment)
In the present embodiment, in a substrate in which a plurality of capacitors having different capacitance values according to the present invention are incorporated, the impedance measurement is performed at a position where resonance caused by each capacitor is separated, thereby facilitating electrical inspection of the capacitor. Next, the method to be performed and the structure of the electric component built-in substrate such as a capacitor will be described.

  First, a configuration for exhibiting the function will be described with reference to FIG.

A substrate 1 shown in FIG. 1 is an electric component built-in substrate (multilayer substrate) 1 including a large-capacitance capacitor C1 and a small-capacitance capacitor C2. Here, as an example, the capacitance of the large-capacitance capacitor C1 is 33 μF, and the capacitance of the small-capacitance capacitor C2 is 2.2 μF, but the circuit is a combination of the inductances of the circuit patterns electrically connected to C1 and C2. If the time constants are separated, the capacitance value is not restricted. Here, the time constant of the capacitor is defined by the combined impedance with the inductance of each circuit pattern electrically connected to the capacitor, and ((capacitance of combined impedance (capacitor C1 or C2)) × (inductance of combined impedance ( each synthesis of the inductance) of the circuit pattern)) is represented by ^1/2, the time constant of both different value of the time constant for the values and the capacitor C2 of the time constant for the capacitor C1 will be separated. The multilayer substrate 1 in the present embodiment includes four layers of circuit patterns, and an insulator is sandwiched between the circuit patterns as an insulating layer. However, the multilayer substrate in the present application is not limited to this, and the number of circuit pattern layers can be any number, and an insulating layer can be sandwiched between the arbitrary circuit pattern layers.

  In the multilayer substrate 1 of FIG. 1, a large-capacitance capacitor C1 and a small-capacitance capacitor C2 are mounted on the third-layer circuit pattern (the inner layer of the multilayer substrate 1 between the second-layer circuit pattern and the third-layer circuit pattern). And a large-capacitance capacitor C1 and a small-capacitance capacitor C2 are built in).

  In FIG. 1, one end C2a of the small-capacitance capacitor C2 mounted on the multilayer substrate 1 is connected to the third-layer circuit pattern 3a and the via V1a (third-layer circuit pattern 3b) connected to the one-end C2a of the small-capacitance capacitor C2. A conductor electrically connecting the fourth layer circuit pattern 4b) and a fourth layer circuit pattern 4a (measurement terminal (measurement terminal pad P2a) for contacting the measurement probe of the impedance analyzer 2) It is connected to the measurement probe 2 a of the impedance analyzer 2.

  The other end C2b of the small-capacitance capacitor C2 mounted inside the multilayer substrate 1 is connected to the third-layer circuit pattern 3b and the via V1b (third-layer capacitor) connected to the other end C2b of the small-capacitance capacitor C2. A conductor electrically connecting the circuit pattern 3b and the circuit pattern 4b on the fourth layer), a circuit pattern 4b on the fourth layer (measurement terminal (measurement terminal pad P2b) for contacting the measurement probe of the impedance analyzer 2) Is connected to the measurement probe 2b of the impedance analyzer 2.

  Measurement probe 2a of impedance analyzer 2, circuit pattern 4a on the fourth layer, via V1a, circuit pattern 3a on the third layer, small-capacitance capacitor C2, circuit pattern 3b on the third layer, via V1b, circuit pattern 4b on the fourth layer There is a resonance frequency corresponding to the time constant determined by the circuit constituted by the measurement probe 2b.

In this case, the resonance frequency of the small-capacitance capacitor C2 is represented by 1 / 2π (LC2) ^1/2 (L is the inductance of the small-capacitance capacitor C2). In the present embodiment, the resonance frequency of the circuit including the small-capacitance capacitor C2 can be detected by the impedance analyzer 2 (details will be described later). Alternatively, it is also possible to detect the resonance frequency using the calculated impedance value of the circuit pattern obtained by accurately performing the three-dimensional electromagnetic field analysis using the circuit pattern extracted from the design data of the substrate.

  FIG. 12 shows a main configuration of the impedance analyzer 2 generally used in impedance measurement. When the impedance to be measured is Zx and the known resistance is R, the voltages applied to the impedance are Va and Vb, respectively. Since Va / Zx + Vb / R = 0 when the current flowing in the known resistor and the current flowing in the device under test (DUT) are equal, if the voltage of Va and Vb is measured when the potential of the detector becomes 0, The impedance of the DUT can be calculated from Zx = R × Va / Vb.

  In the present embodiment, the resonance frequency of the circuit including the small-capacitance capacitor C2 is calculated in advance, and the impedance of the electric component built-in substrate (multilayer substrate) 1 at the resonance frequency is measured by the impedance analyzer 2. When the capacitor corresponding to the resonance frequency is electrically connected to the electric component built-in substrate (multilayer substrate) 1 and is securely mounted, the impedance at the resonance frequency becomes a sufficiently small value (FIGS. 3 and 4). FIG. 6 and FIG. 8). However, when the capacitor corresponding to the resonance frequency is not electrically connected to the electric component built-in substrate (multilayer substrate) 1 and is not mounted, the capacitor is mounted at the resonance frequency. There is a difference in impedance.

  In this way, it is possible to inspect whether or not the capacitor is reliably mounted on the electric component built-in substrate (multilayer substrate) 1 by performing impedance measurement at the resonance frequency using the impedance analyzer 2.

  FIG. 2 shows a third-layer wiring pattern on which the large-capacitance capacitor C1 and the small-capacitance capacitor C2 are mounted.

  A via 1 composed of a pair of via V1a and via V1b and a via V2 composed of a pair of via V2a and via V2b are provided in the vicinity of the small capacitor C2, and each via is formed on the substrate surface (fourth layer circuit pattern). A measurement terminal connected to is arranged.

  The via V1a and the via V2a are connected to a common power pattern on the third layer, and the via V1b and the via V2b are connected to a common ground pattern on the third layer.

  The large-capacitance capacitor C1 and the small-capacitance capacitor C2 are connected in parallel to the third layer common ground pattern and the third layer common power supply pattern.

  In this case, the measurement probe 2a of the impedance analyzer 2 is connected to a measurement terminal (fourth-layer circuit patterns 4b and 4a) on the surface of the substrate connected to the via V1a or the via V1b, and the impedance analyzer 2 is used for impedance measurement from the measurement terminal. The measurement result is shown in FIG. 3 as measurement result 1 (solid line).

  In the measurement result 1 (solid line) in FIG. 3, the impedance changes at the resonance frequency f1 caused by the large-capacitance capacitor C1 and the resonance frequency f2 caused by the small-capacitance capacitor C2, and the impedance becomes lower than the other frequencies. It is shown.

  The resonance frequency f2 includes the influence of the impedance component of the circuit pattern formed on the multilayer substrate 1 connected to the small capacitance capacitor C2 and the measurement probe 2a to the measurement probe 2b.

  Similarly, the resonance frequency f1 includes the influence of the impedance component of the circuit formed on the multilayer capacitor 1 connected to the measurement probe 2b from the large capacitance capacitor C1 and the measurement probe 2a.

  Further, FIG. 3 shows the result of impedance measurement from a measurement terminal on the substrate surface connected to the via V2a and the via V2b using the impedance analyzer 2 and the measurement probes 2a and 2b as a result measurement 2 (broken line).

  The measurement result 2 (broken line) in FIG. 3 also shows that the resonance frequency f1 of the large-capacitance capacitor C1 and the resonance frequency (f2a, f2b) of the small-capacitance capacitor C2 are separated, and it is possible to measure fluctuations in impedance due to the capacitors. ing. The resonance frequency of the small-capacitance capacitor C2 was measured as a different value between the resonance frequency f2a of the measurement result 2 (broken line) and the resonance frequency f2b of the measurement result 1 (solid line) because of the difference in the inductance of the circuit pattern. It is shown.

  In both the measurement results 1 and 2, the resonance frequency caused by the large-capacitance capacitor C1 and the resonance frequency caused by the small-capacitance capacitor C2 are separated from each other. It is possible to detect (identify) whether it corresponds to C1 or the small-capacitance capacitor C2. Therefore, the large-capacitance capacitor C1 and the small-capacitance capacitor C2 can be inspected separately.

  However, the measurement result 1 measured using the pair of the via V1a and the via V1b is larger than the measurement result 2 measured using the pair of the via V2a and the via V2b. It is shown that the impedance change near the resonance frequency is large.

  Therefore, it is more accurate to separate the large-capacitance capacitor C1 and the small-capacitance capacitor C2 by measuring using a pair of the via V1a and the via V1b that are far from the large-capacity capacitor and in the vicinity of the small-capacitance capacitor. Inspection is easier.

  In other words, it is easier to inspect separately the resonance frequency of the large capacitor and the resonance frequency of the small capacitor by arranging the measurement terminal far from the large capacitor and in the vicinity of the small capacitor. Become.

  Next, only the large-capacitance capacitor C1 (33 μF) is mounted on the multilayer substrate 1 in FIG. 1, and impedance measurement is performed from the via V1a and the via V1b. FIG. FIG. 4 shows a result of impedance measurement from the via V1a and the via V1b by mounting only the small capacitor C2 (2.2 μF) on the multilayer substrate 1 of FIG. 4 and the small capacitor C2 (2.2 μF) are mounted, and the result of impedance measurement from the via V1a and the via V1b is shown by a thin broken line in FIG.

  From this result, the presence / absence of the large-capacitance capacitor C1 (the presence / absence of the resonance frequency caused by the large-capacitance capacitor) is determined from the fluctuation of the impedance in the band indicated by the frequency region W1 in FIG.

  In addition, the presence or absence of the small capacitor C2 (the presence or absence of the resonance frequency due to the small capacitor) is determined from the fluctuation of the impedance in the band indicated by the frequency region W2 in FIG. 4 (except the region where the thick solid line and the broken line overlap). Therefore, the electrical inspection of the capacitor becomes possible. That is, it is possible to confirm whether or not the large-capacitance capacitor C1 or the small-capacitance capacitor C2 is electrically mounted on the multilayer substrate 1.

  Thus, according to the electrical component connection inspection method of the electrical component built-in substrate incorporating at least two or more capacitors of the present application, the common power supply pattern connected to the capacitors (C1, C2) and the capacitors (C1, C2). (VP) and common ground pattern (GP) connected to the capacitor are inspected by impedance measurement using each resonance frequency separated by a time constant defined by a combined impedance with a known inductance of each common inductance (GP) as a measurement frequency. To do.

Here, the time constant is a time constant corresponding to each capacitor, and the combined impedance is the known inductance of the capacitor (C1 or C2) and the common power supply pattern (VP) connected to the capacitor (C1 or C2). , The impedance of the common ground pattern (GP) connected to the capacitor (C1 or C2) and the known inductance, and the time constant of the capacitor (C1 or C2) is ((capacitance of the combined impedance (capacitor C1 Or C2)) × (Inductance of combined impedance (combined inductance of known inductance of power supply pattern (VP) and known inductance of ground pattern (GP)))) expressed as ^1/2 , and the value of the time constant for capacitor C1 Time constant value for capacitor C2 So that the impedance-based separation constant difference when both are made Different.

  FIG. 5 shows vias (via V1 consisting of via V1a and via V1b, via V3a and via V3b) formed between the circuit pattern of the third layer and the circuit pattern of the fourth layer in the multilayer substrate 1 of FIG. FIG. 5 is a diagram showing a circuit pattern of a third layer when vias V3, vias V4a and vias V4b) are arranged little by little from the small-capacitance capacitor C2 and little by little from the large-capacitance capacitor C1.

  Each via (via V1a, via V1b, via V3a, via V3b, via V4a, via V4b) is connected to a measurement terminal (not shown) on the substrate surface (fourth layer circuit pattern) not shown in FIG. Therefore, FIG. 5 is a diagram showing a third-layer circuit pattern when vias are arranged by changing the distance between the small-capacitance capacitor C2 and the large-capacitance capacitor C1 and the measurement terminal.

  FIG. 6 shows the results of measuring the impedance of the multilayer substrate 1 using the impedance analyzer 2 from each measurement terminal in the multilayer substrate 1 having the circuit pattern of FIG.

  In FIG. 6, the result of the impedance measurement of the multilayer substrate 1 using the impedance analyzer 2 through the via V1 including the via V1a and the via V1b is shown by a solid line (measurement result 3), and includes the via V3a and the via V3b. The result of impedance measurement of the multilayer substrate 1 using the impedance analyzer 2 via the via V3 is indicated by a thick broken line (measurement result 4), and includes the via V4a and the via V4b that are farthest from the small capacitor. The result of the impedance measurement of the multilayer substrate 1 using the impedance analyzer 2 through the via V4 is shown by a fine broken line (measurement result 5).

  In any case, it is possible to confirm the separation of the resonance due to the presence or absence of the resonance frequency due to the large-capacitance capacitor and the presence or absence of the resonance frequency due to the small-capacitance capacitor, and that the impedance can be separated and extracted. Show.

  However, if the measurement probes 2a and 2b of the impedance analyzer 2 which is the measurement position are connected to a measurement terminal close to the small capacitor through a via closer to the small capacitor, the impedance reduction effect due to the small capacitor increases. The measurement terminal for observing the separation of resonance is optimally arranged near the small capacitor. This can be seen from the fact that the impedance change at the resonance frequency due to the small-capacitance capacitor C2 is the largest in the measurement result 3 of FIG. 6 which is the result of the impedance measurement of the multilayer substrate 1 via the via V1.

Next, when the magnitude relationship of the capacitance values of at least two or more capacitors is CV1 ≧ CV2 ≧... ≧ CVn (CVn is a capacitor capacitance value, n is a natural number), it is mounted on the electric component built-in board. (LV1 * CV1) ^1/2 > (LV2 * CV2) ^1/2 >...> (LVn * CVn) ^{1 / 2} (LVn is the capacitor, the common power supply pattern connected to the capacitor, and the inductance value including the common ground pattern connected to the capacitor, n is a natural number), the impedance measurement at a position An electrical component connection inspection method for an electrical component built-in board on which measurement terminal pads are arranged will be described with reference to FIG. In FIG. 7, a capacitor C3 having a capacitance CV3 of 1 nF obtained by connecting a resistor RV3 (10 mΩ) and an inductance LV3 (1.0 nH) in series with the capacitor C3 when measuring the capacitor C3 from the measurement terminal 4a and the measurement terminal 4b, and the measurement terminal A capacitor C4 having a capacitance CV4 of 10 nF obtained by connecting a resistor RV4 (15 mΩ) and an inductance LV4 (1.5 nH) when measuring the capacitor C4 from 4a and the measurement terminal 4b in series with the capacitor C4, and the measurement terminal 4a and the measurement terminal 4b Measure the capacitor C5 from the measurement terminal 4a and the measurement terminal 4b, and the capacitor C5 having a capacitance CV5 of 100 nF obtained by connecting the resistor RV5 (20 mΩ) and the inductance LV5 (2.0 nH) in series with the capacitor C5. When you do A circuit model in which RV6 (25 mΩ) and inductance LV5 (2.5 nH) are connected in series with a capacitor C6 and a capacitor C6 having a capacitance CV6 of 1000 nF is connected in parallel to the common power supply pattern VP and the common ground pattern GP in FIG. is there.

The time constant of the capacitor C3 is (capacitance CV3 × inductance LV3) ^1/2 = 5.0 × 10 ⁸ , and the time constant of the capacitor C4 is (capacitance CV4 × inductance LV4) ^1/2 = 1.4 × 10 ⁸ , The time constant of the capacitor C5 is (capacitance CV5 × inductance LV5) ^1/2 = 3.8 × 10 ⁹ , and the time constant of the capacitor C6 is (capacitance CV6 × inductance LV6) ^1/2 = 5.0 × 10 ⁹ , Capacitor C3, Capacitor C4, Capacitor C5, Capacitor C6 Capacitance Relationship (Capacitor C3 <Capacitor C4 <Capacitor C5 <Capacitor C6) and Time Constant of Capacitor (Capacitor C3 Time Constant <Capacitor C4 Time Constant) <The time constant of the capacitor C5 <the time constant of the capacitor C6) matches. Therefore, the impedance measurement using the resonance frequency corresponding to each capacitor as the measurement frequency can be performed in order using the impedance analyzer 2, and it is surely checked whether each capacitor is connected to the multilayer substrate 1. It becomes possible.

  FIG. 8 is a diagram of impedance waveforms showing the result of measuring or simulating the impedance of the circuit model shown in FIG.

  The resonance frequency corresponding to the capacitor C3 is the resonance frequency f3, the resonance frequency corresponding to the capacitor C4 is the resonance frequency f4, the resonance frequency corresponding to the capacitor C5 is the resonance frequency f5, and the resonance frequency corresponding to the capacitor C6 is The resonance frequency is f6.

  In this way, it is possible to reliably check whether or not a capacitor corresponding to the resonance frequency is connected to the substrate by measuring the impedance to confirm the presence or absence of each resonance frequency and measuring the impedance at each resonance frequency. Is possible.

Thus, in the multilayered electric component built-in substrate having at least two or more capacitors corresponding to the circuit model shown in FIG. 7 as the inner layer, it is closest to the measurement terminal pad (P4a) and the other measurement terminal pads (P4b). The capacitor (C3) having the smallest capacitance is arranged at the position, and the magnitude relationship of the time constants as viewed from the measurement terminal pad (P4a) and the other measurement terminal pad (P4b) is (LV3 * CV3) ^1/2 > (LV4 * CV4) ^1/2 > (LV5 * CV5) ^1/2 > (LV6 * CV6) ^1/2 > (LVn is connected to capacitor Cn, common power supply pattern connected to capacitor Cn, and capacitor Cn An inductance value including the common ground pattern, n = 3, 4, 5, 6) is satisfied. Here, if the number of capacitors is n, the relationship between the n capacitors can be shown by using C1 as the capacitor having the smallest capacity and n as a natural number.

  As described above, according to the present invention, the resonance frequency resulting from the combination of the common power supply pattern and the common ground pattern with each capacitor built in the electric component built-in substrate that is a multilayer substrate is separated. It is possible to perform an electrical inspection as to whether or not each capacitor built in the electrical component built-in board is connected to the circuit pattern by measuring impedance from the measurement terminal on the surface of the built-in component.

  Further, it is not necessary to draw out the wiring connected to the capacitor electrodes corresponding to the number of capacitors to the substrate surface. For this reason, it is not necessary to draw out a capacitor inspection wiring by the number of capacitors.

  In addition, since unnecessary wiring for capacitor inspection is not necessary, deterioration of electronic circuit characteristics in the board with built-in electrical components, increase in the board size of the board with built-in electrical components, increase in cost by increasing the number of terminals for inspection, and It is possible to solve the problem that the number of times of setting the measurement probe to the inspection terminal is required by the number of capacitors.

  In addition, since the combined impedance including the known inductance (L) due to the common power supply pattern and the common ground pattern of the electric component built-in substrate is measured in the known resonance frequency band, the presence or absence of the capacitor is surely inspected. It becomes possible.

  In addition, by measuring the impedance of each capacitor in the resonant frequency band, it is clear which capacitor is causing the connection failure, so that the electrical inspection of each capacitor built into the board with built-in electrical components can be performed reliably. It becomes possible to carry out.

  Further, even when a large-capacity capacitor and a small-capacitance capacitor are built in parallel on the electric component built-in substrate, each capacitor can be inspected. According to the present invention, it is possible to inspect even when many types of capacitors are built in as long as the magnitude relation of the capacitances of the capacitors built in the electric component built-in substrate matches the magnitude relation of the time constants. . As an example, electrical inspection can be performed even when 2.2 μF, 0.1 μF, and 10 nF capacitors are incorporated.

  In addition, in order to effectively express the LC resonance time constant due to the inductance of each power supply pattern and the common ground pattern built in the electric component built-in substrate, By arranging the external terminal so as to have a small inductance, the frequency difference between the resonance frequencies becomes large, and it becomes difficult for interference to occur between a plurality of resonance frequencies, so that the electrical inspection of each capacitor can be easily performed. It becomes possible.

  That is, since the focus is on measuring the combined impedance including the inductance component (L) and the capacitance component (C) of the capacitor built in and mounted on the electric component built-in substrate, the capacitor is built in. Inspection after the manufacture of the substrate can be easily executed.

  As described above, the present invention relates to a method for inspecting the conduction state of a capacitor after manufacturing the capacitor built-in substrate and the structure of the capacitor built-in substrate. In particular, it is possible to provide a capacitor built-in substrate that enables connection inspection of individual capacitors in a state where a plurality of capacitors having different capacities are connected to the same power source.

  In the above embodiment, the impedance analyzer 2 is used to measure the impedance using the resonance frequency of the capacitor built in the multilayer substrate 1 as the measurement frequency. However, the present application is not limited to this. Instead, any instrument that can measure impedance can be used.

  Further, in the multilayer substrate 1 in which the capacitor is not mounted, the combined impedance of the multilayer substrate 1 from the measurement terminal is measured by simulation (calculation) or an impedance measuring instrument such as the impedance analyzer 2, so that each capacitor after mounting the capacitor is measured. The resonant frequency can be predicted.

  Moreover, although the resonance frequency of the capacitor mounted on the multilayer substrate 1 varies depending on the position of the measurement terminal, the order of magnitude relationship of the capacitor capacity of the capacitor is determined by simulation (calculation) or actual measurement by an impedance measuring instrument such as the impedance analyzer 2. It is possible to determine the position of the measurement terminal so that the magnitude relationships of the resonance frequencies of the capacitors are aligned.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist of the present invention.

  Further, it is to be understood that the embodiments described and illustrated herein are exemplary only and should not be considered as limiting the scope of the present invention. Other changes and modifications may be made in accordance with the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 1 Multilayer substrate 2 Impedance analyzer 2a, 2b Measurement probe 4a, 4b The circuit pattern (measurement terminal) of the 4th layer
C1 Large capacity capacitor C2 Small capacity capacitor f1, f2a, f2b, f3, f4, f5, f6 Resonance frequency V1a, V1b, V2a, V2b, V3a, V3b, V4a, V4b, Via (conductor)
VP 3rd layer common power supply pattern GP 3rd layer common ground pattern

Claims (5)

An electrical component connection inspection method for an electrical component built-in board containing at least two capacitors,
In the electric component built-in substrate,
One end of the capacitor is connected to a common power supply pattern of the electric component built-in substrate, the other end of the capacitor is connected to a common ground pattern of the electric component built-in substrate, and the at least two or more capacitors are the common And connected in parallel between the power supply pattern and the common ground pattern ,
Resonance frequencies separated by a time constant defined by a combined impedance of the capacitor, the common power supply pattern connected to the capacitor, and a known inductance of each of the common ground patterns connected to the capacitor the measurement terminal pads for performing the impedance measurement and measurement frequency is disposed on a surface of the electric component-embedded board, the measurement terminal pads said capacitor one end, and, with the other measurement terminal pads other of said capacitor One end is connected via a conductor penetrating the inside of the electric component built-in substrate,
Furthermore, the capacitor disposed at the position closest to the measurement terminal pad and the other measurement terminal pad is the capacitor having the smallest capacitor capacitance value among the capacitors mounted on the electric component built-in substrate,
An electrical component connection testing method for an electrical component built-in board, wherein the electrical connection test of individual built-in components is performed by performing the impedance measurement using each of the separated resonance frequencies as the measurement frequency . In the electrical component connection inspection method according to claim 1,
The conductor penetrating the inside of the electric component built-in substrate is directly connected between the common power supply pattern to which one end of the capacitor is directly connected and the measurement terminal pad, and to the other end of the capacitor. An electrical component connection inspection method for an electrical component built-in board, wherein the electrical component connection inspection method is formed between the common ground pattern and the other measurement terminal pads . An electrical component connection inspection method for an electrical component built-in board containing at least two capacitors,
In the electric component built-in substrate,
One end of the capacitor is connected to a common power supply pattern of the electric component built-in substrate, the other end of the capacitor is connected to a common ground pattern of the electric component built-in substrate, and the at least two or more capacitors are the common Connected in parallel between the power supply pattern and the common ground pattern,
Resonance frequencies separated by a time constant defined by a combined impedance of the capacitor, the common power supply pattern connected to the capacitor, and a known inductance of each of the common ground patterns connected to the capacitor A measurement terminal pad for performing impedance measurement with the measurement frequency as the measurement frequency is disposed on the surface of the electric component built-in substrate, the measurement terminal pad and one end of the capacitor, and the other measurement terminal pad and the other capacitor One end is connected via a conductor penetrating the inside of the electric component built-in substrate,
Further, the conductor penetrating the inside of the electric component built-in substrate is connected between the common power supply pattern to which one end of the capacitor is directly connected and the measurement terminal pad, and the other end of the capacitor is directly connected. Formed between the connected common ground pattern and the other measurement terminal pads,
An electrical component connection inspection method for an electrical component built-in board, wherein the electrical connection inspection of individual embedded components is performed by performing the impedance measurement using each of the separated resonance frequencies as the measurement frequency . In the electrical component connection inspection method according to any one of claims 1 to 3 ,
Mounted on the electric component built-in substrate when the relationship between the capacitance values of the at least two capacitors is CV1 ≧ CV2 ≧... ≧ CVn (CVn is a capacitor capacitance value and n is a natural number). The time constant corresponding to the resonance frequency in the at least two capacitors is (LV1 * CV1) ^1/2 > (LV2 * CV2) ^1/2 >...> (LVn * CVn) ^The impedance measurement at a position where ^1/2 (LVn is an inductance value including the capacitor, the common power supply pattern connected to the capacitor, and the common ground pattern connected to the capacitor, and n is a natural number) electrical component soldering method for inspecting the electrical component-embedded substrate, characterized by arranging the measurement terminal pads for the A multilayer electric component built-in substrate having at least two capacitors in an inner layer,
One end of the capacitor is directly connected to a common power supply pattern on the inner layer of the electric component built-in substrate, and the other end of the capacitor is directly connected to a common ground pattern on the inner layer of the electric component built-in substrate, Two or more capacitors are mounted connected in parallel between the common power supply pattern and the common ground pattern,
One end of the capacitor is directly connected between the common power supply pattern and the measurement terminal pad on the outermost layer surface of the electric component built-in substrate, and the other end of the capacitor is directly connected Between the common ground pattern and another measurement terminal pad on the surface of the outermost layer of the electric component built-in substrate, a conductor penetrating the inside of the electric component built-in substrate is formed,
A capacitor having the smallest capacitance is arranged at a position closest to the measurement terminal pad and the other measurement terminal pads, and the magnitude relation of time constants as viewed from the measurement terminal pad and the other measurement terminal pads is (LV1 * CV1) ^{1 / 2} > (LV2 * CV2) ^1/2 >...> (LVn * CVn) ^1/2 (LVn is connected to the capacitor, the common power supply pattern connected to the capacitor, and the capacitor. inductance value including the common ground pattern, n represents the electrical component built board to satisfy the natural number).

Images