CN109041408B - Method and system for inhibiting plane resonance by placing capacitor position - Google Patents
Method and system for inhibiting plane resonance by placing capacitor position Download PDFInfo
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- CN109041408B CN109041408B CN201810972184.6A CN201810972184A CN109041408B CN 109041408 B CN109041408 B CN 109041408B CN 201810972184 A CN201810972184 A CN 201810972184A CN 109041408 B CN109041408 B CN 109041408B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000002401 inhibitory effect Effects 0.000 title abstract description 6
- 238000004458 analytical method Methods 0.000 claims abstract description 25
- 238000010586 diagram Methods 0.000 claims abstract description 7
- 238000004088 simulation Methods 0.000 claims description 5
- 238000005457 optimization Methods 0.000 claims description 4
- 230000000977 initiatory effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 13
- 230000005540 biological transmission Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000013178 mathematical model Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
Abstract
The invention provides a method and a system for inhibiting plane resonance by placing a capacitor position, which comprises the following steps: s1, obtaining different Dk and Df values and heights between the power supply layer and the ground layer based on different laminated structures of the chip; s2, performing impedance analysis and searching the position of the lowest natural frequency; s3, making a simulated resonance graph at the position of the lowest natural frequency, and analyzing the interference condition of the plane resonance on the signal; and S4, arranging a different number of decoupling capacitors below the high-speed device, and re-simulating a resonance diagram until the plane resonance is in a desired range. The purpose of improving the resonance of the frequency band by changing the cavity formed between the power supply layer and the stratum is achieved; the ground bounce effect caused by the resonance of the cavity can be reduced, so that the electromagnetic interference generated by the ground bounce effect is reduced; the influence of the de-resonance effect on the signals generated by different placing positions of the decoupling capacitor is expressed.
Description
Technical Field
The invention relates to the technical field of signal transmission, in particular to a method and a system for inhibiting plane resonance by placing a capacitor position.
Background
In a multilayer circuit board, the multilayer circuit board is generally divided into a power supply layer and a ground layer, a resonant cavity is formed between the power supply and the ground layer, and voltage between the power supply and the ground fluctuates when a high-speed digital signal passes through the resonant cavity. In case of resonance, a natural frequency is required, which is related to the shape of the power and ground planes, the medium parameters in between (dielectric constant, losses, thickness). Once these parameters are settled, the natural frequency is settled. The high speed signal has a rich spectral content, some of which are at the same natural frequency as the PCB power ground, and then fluctuates. If the lowest of the natural frequencies is up to 10GHz and the spectral content of the signal is not present beyond 5GHz, the signal is unable to cause voltage fluctuations between the power supply and ground. Impedance analysis yields impedance versus frequency, corresponding to natural frequencies, at which excitation causes resonance.
Such resonance can not only seriously affect the transmission of high-speed signals, but also generate an EMI phenomenon, which can destroy the transmission quality of the high-speed signals, cause serious interference to signal transmission, and transmit electromagnetism to places other than the PCB.
In the multilayer design of the PCB, a power supply layer and a ground layer are usually arranged in the middle layer, the power supply layer and the ground layer are connected up and down to form a cavity, and a plane resonance can be formed between the cavities and can affect a high-speed signal.
Disclosure of Invention
The invention aims to provide a method and a system for inhibiting plane resonance by placing a capacitor position, which aim to solve the problem that in the prior art, a cavity between a power supply layer and a stratum can cause plane resonance, reduce the ground bounce effect caused by cavity resonance and reduce electromagnetic interference.
In order to achieve the technical purpose, the invention provides a method for inhibiting plane resonance by placing a capacitor position, which comprises the following steps:
s1, obtaining different Dk and Df values and heights between the power supply layer and the ground layer based on different laminated structures of the chip;
s2, performing impedance analysis and searching the position of the lowest natural frequency;
s3, making a simulated resonance graph at the position of the lowest natural frequency, and analyzing the interference condition of the plane resonance on the signal;
and S4, arranging a different number of decoupling capacitors below the high-speed device, and re-simulating a resonance diagram until the plane resonance is in a desired range.
Preferably, the simulated resonance map is specifically operative to:
in the overlay information, a sine wave is added to the lowest natural frequency for AC analysis.
Preferably, the signal link signal between the high-speed devices is a PCIE3.0 signal.
Preferably, the decoupling capacitor is 22pF in size.
The invention also provides a system for suppressing planar resonance by locating a capacitance location, the system comprising:
the laminated information acquisition module is used for acquiring different Dk and Df values and the height between the power supply layer and the stratum based on different laminated structures of the chip;
the lowest frequency position determining module is used for performing impedance analysis and searching the position of the lowest natural frequency;
the resonance interference initial module is used for making a simulation resonance graph at the position of the lowest natural frequency and analyzing the interference condition of the plane resonance on the signal;
and the resonance optimization module is used for setting different decoupling capacitors below the high-speed device and re-simulating a resonance graph until the plane resonance is in a desired range.
Preferably, the resonance interference initiating module includes:
an AC analysis unit for adding a sine wave to the lowest natural frequency in the overlay information to perform AC analysis;
and the resonance interference analysis unit is used for analyzing the interference condition of the plane resonance on the signal.
Preferably, the signal link signal between the high-speed devices is a PCIE3.0 signal.
Preferably, the decoupling capacitor is 22pF in size.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, the invention realizes the purpose of improving the resonance of the frequency band by changing the cavity formed between the power layer and the stratum by analyzing the arrangement positions of different capacitors and transferring the plane resonance point to a place outside the working frequency; the ground bounce effect caused by the resonance of the cavity can be reduced, so that the electromagnetic interference generated by the ground bounce effect is reduced; the influence of the de-resonance effect on the signals generated by different placing positions of the decoupling capacitor is expressed.
In addition, when the signal integrity of a certain board card is not ideal, the server is a whole system, and other daughter cards can ensure the signal integrity, so that the running safety of the whole server is ensured. And the signal integrity and reliability of the RACK complete machine cabinet server are greatly enhanced.
Drawings
Fig. 1 is a flowchart of a method for suppressing planar resonance by locating a capacitor according to an embodiment of the present invention;
FIG. 2 is a plan resonance diagram and resonance points before optimization provided in an embodiment of the present invention;
FIG. 3 is a plane resonance diagram and resonance points optimized according to an embodiment of the present invention;
fig. 4 is a block diagram of a system for suppressing planar resonance by locating a capacitor according to an embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
A method and a system for suppressing plane resonance by locating a capacitor according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present invention discloses a method for suppressing plane resonance by placing capacitor locations, including the following steps:
s1, obtaining different Dk and Df values and heights between the power supply layer and the ground layer based on different laminated structures of the chip;
s2, performing impedance analysis and searching the position of the lowest natural frequency;
s3, making a simulated resonance graph at the position of the lowest natural frequency, and analyzing the interference condition of the plane resonance on the signal;
and S4, arranging a different number of decoupling capacitors below the high-speed device, and re-simulating a resonance diagram until the plane resonance is in a desired range.
Aiming at different projects, different laminated layers are adopted, so that different Dk and Df values and specific laminated thickness, namely the height between a power supply layer and a stratum can be obtained, the influence of short column resonance on the circuit board of the whole system can be accurately obtained by a mathematical model analysis method, the influence of ground holes on signals in the whole circuit design is greatly reduced, and the reliability of the whole operation of the system can be greatly promoted when the whole circuit board operates.
In the lamination information, one of the resonance frequencies is taken, and a sine wave is added to the resonance frequency to perform AC analysis, so that the resonance mode, namely the voltage distribution, on the power supply ground plane can be observed.
For PI design, impedance analysis is firstly carried out to find the position of the lowest natural frequency, and if the lowest natural frequency is too low, structural changes including power shape, medium thickness and the like are needed to improve the lowest natural frequency. And performing AC simulation analysis at several lower frequencies, checking whether the voltage fluctuation mode corresponding to each frequency is in the position where the fluctuation of the key device is maximum, adding a decoupling capacitor, and performing AC analysis again.
For example, in a certain PCB board, there are two transceiver modules of high-speed devices, the cavity is surrounded by a power layer and a ground plane, the signal frequency is 625MHz, and the signal link signal between the high-speed devices is a PCIE3.0 signal. The planar resonance is analyzed, as shown in fig. 2, the main resonance frequencies are 607MHz and 828MHz respectively, and the resonance hot spot is located near the center of the signal trace.
After placing 10 capacitors of 22pF under one device in the receiving and transmitting modules of two high-speed devices of the board card, and placing a capacitor of 22pF under the other device, it is found that the first resonance is transferred to 491MHz, in order to restrain the resonance in the board near 828MHz, a total of 12 decoupling capacitors of 22pF are placed in a hot spot area with the maximum resonance amplitude, a resonance graph is re-simulated, and as shown in FIG. 3, after the capacitors are placed again, the plane resonance can be reduced to a desired range, and the system requirements are met.
According to the embodiment of the invention, the plane resonance point is shifted beyond the working frequency by analyzing the arrangement positions of different capacitors, so that the purpose of improving the resonance of a frequency band by changing a cavity formed between a power supply layer and a stratum is realized; the ground bounce effect caused by the resonance of the cavity can be reduced, so that the electromagnetic interference generated by the ground bounce effect is reduced; the influence of the de-resonance effect on the signals generated by different placing positions of the decoupling capacitor is expressed.
In addition, when the signal integrity of a certain board card is not ideal, the server is a whole system, and other daughter cards can ensure the signal integrity, so that the running safety of the whole server is ensured. And the signal integrity and reliability of the RACK complete machine cabinet server are greatly enhanced.
As shown in fig. 4, the present invention also discloses a system for suppressing plane resonance by placing capacitance positions, which is characterized in that the system comprises:
the laminated information acquisition module is used for acquiring different Dk and Df values and the height between the power supply layer and the stratum based on different laminated structures of the chip;
the lowest frequency position determining module is used for performing impedance analysis and searching the position of the lowest natural frequency;
the resonance interference initial module is used for making a simulation resonance graph at the position of the lowest natural frequency and analyzing the interference condition of the plane resonance on the signal;
and the resonance optimization module is used for setting different decoupling capacitors below the high-speed device and re-simulating a resonance graph until the plane resonance is in a desired range.
In the lamination information, one of the resonance frequencies is taken, and a sine wave is added to the resonance frequency to perform AC analysis, so that the resonance mode, namely the voltage distribution, on the power supply ground plane can be observed.
For PI design, impedance analysis is firstly carried out to find the position of the lowest natural frequency, and if the lowest natural frequency is too low, structural changes including power shape, medium thickness and the like are needed to improve the lowest natural frequency. And performing AC simulation analysis at several lower frequencies, checking whether the voltage fluctuation mode corresponding to each frequency is in the position where the fluctuation of the key device is maximum, adding a decoupling capacitor, and performing AC analysis again.
And the signal link signals between the high-speed devices are PCIE3.0 signals.
The decoupling capacitance is 22pF in size.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A method for suppressing plane resonance by placing capacitance positions is characterized by comprising the following steps:
s1, obtaining different Dk and Df values and heights between the power supply layer and the ground layer based on different laminated structures of the chip;
s2, performing impedance analysis and searching the position of the lowest natural frequency; when the lowest natural frequency is too low, the shapes of a power supply and a ground plane and the thickness of a medium in the middle need to be changed, the lowest natural frequency is improved, and the position of the lowest natural frequency is determined;
s3, making a simulated resonance graph at the position of the lowest natural frequency, and analyzing the interference condition of the plane resonance on the signal;
and S4, arranging a different number of decoupling capacitors below the high-speed device, and re-simulating a resonance diagram until the plane resonance is in a desired range.
2. A method of suppressing planar resonance by locating capacitance positions as claimed in claim 1, wherein the simulated resonance plot is operative to:
in the overlay information, a sine wave is added to the lowest natural frequency for AC analysis.
3. The method of claim 1 or 2, wherein the signal of the signal link between the high speed devices is a PCIE3.0 signal.
4. A method of suppressing planar resonance by locating capacitors as claimed in claim 1 or 2, wherein the decoupling capacitors are of the order of 22 pF.
5. A system for suppressing planar resonance by locating capacitance, the system comprising:
the laminated information acquisition module is used for acquiring different Dk and Df values and the height between the power supply layer and the stratum based on different laminated structures of the chip;
the lowest frequency position determining module is used for performing impedance analysis, searching the position of the lowest natural frequency, and when the lowest natural frequency is too low, changing the shapes of a power supply and a ground plane and the thickness of a medium in the middle to improve the lowest natural frequency and determine the position of the lowest natural frequency;
the resonance interference initial module is used for making a simulation resonance graph at the position of the lowest natural frequency and analyzing the interference condition of the plane resonance on the signal;
and the resonance optimization module is used for setting different decoupling capacitors below the high-speed device and re-simulating a resonance graph until the plane resonance is in a desired range.
6. The system of claim 5, wherein the resonance interference initiating module comprises:
an AC analysis unit for adding a sine wave to the lowest natural frequency in the overlay information to perform AC analysis;
and the resonance interference analysis unit is used for analyzing the interference condition of the plane resonance on the signal.
7. The system according to claim 5 or 6, wherein the signal link between the high speed devices is a PCIE3.0 signal.
8. A system for suppressing planar resonances according to claim 5 or 6, characterized in that the decoupling capacitance has a magnitude of 22 pF.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810972184.6A CN109041408B (en) | 2018-08-21 | 2018-08-21 | Method and system for inhibiting plane resonance by placing capacitor position |
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| CN201810972184.6A CN109041408B (en) | 2018-08-21 | 2018-08-21 | Method and system for inhibiting plane resonance by placing capacitor position |
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| CN109041408B true CN109041408B (en) | 2021-01-15 |
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| CN105307390B (en) * | 2015-11-13 | 2018-12-11 | 廖建兴 | A kind of pcb board structure |
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Effective date of registration: 20201208 Address after: 215100 No. 1 Guanpu Road, Guoxiang Street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Applicant after: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 450018 Henan province Zheng Dong New District of Zhengzhou City Xinyi Road No. 278 16 floor room 1601 Applicant before: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY Co.,Ltd. |
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