JP5462228B2 - Semiconductor test apparatus and semiconductor test method - Google Patents

Description

  The present invention relates to a semiconductor test apparatus and a semiconductor test method, and more particularly to interface control between a handler and a tester of a test apparatus for a semiconductor integrated circuit.

  In the semiconductor test apparatus of the background art, the semiconductor integrated circuit is transported to the measuring jig by the transport section of the handler, the semiconductor integrated circuit and the contact section are connected, the test start signal is sent from the handler to the tester, and the measurement is performed by the tester. . In the inspection of semiconductor devices, efficient inspection processing is required to reduce inspection costs.

  Patent Document 1 relates to a semiconductor handling apparatus including a tester for determining whether product characteristics are good or not, and monitors and resets a signal indicating good or defective related to the previous measurement result before starting measurement of the product. It is described. Thus, it is described that erroneous determination due to timing deviation is prevented in the interface between the tester and the handler.

  Patent Document 2 relates to a semiconductor test apparatus that includes a plurality of sockets and can measure a plurality of semiconductor devices. FIG. 4 is a configuration diagram of the semiconductor test apparatus disclosed in Patent Document 2. In FIG. The semiconductor test apparatus includes a handler 107, two semiconductor inspection apparatuses 109a and 109b, and inspection boards 108a and 108b that are connected to the semiconductor inspection apparatuses 109a and 109b and include sockets 104a and 104b. Further, the handler 107 includes two contact arms 101a and 101b, contact jigs 102a and 102b that are attached to the tips of the contact arms 101a and 101b, and hold the semiconductor devices 103a and 103b to be tested. An arm control unit 106 that controls the lifting and lowering operations of the arms 101a and 101b, and a handler interface 105 that exchanges information between the arm control unit 106 and the semiconductor inspection devices 109a and 109b are provided. Patent Document 2 describes that the inspection is efficiently performed by the arm control unit 106 controlling the control timing for each of the contact arms 101a and 101b.

  Patent Document 3 relates to a semiconductor test apparatus for testing electrical characteristics of a semiconductor device. When a semiconductor device to be inspected is transferred to a socket, the transfer is detected by a sensor provided in each socket. It is described that the tester is requested to start a test on the socket and the test is sequentially performed using a signal from the sensor as a trigger.

JP-A-3-241757 JP 2008-14847 A JP 2001-264380 A

  However, the semiconductor inspection apparatus according to the background art described above has the following problems. In the semiconductor handling apparatus of Patent Document 1, when starting measurement, a signal related to the previous measurement result is monitored to test the semiconductor integrated circuit, so that it is estimated that the number of inspection steps increases. The reason is that there is a problem that it takes a processing time to reset the measurement result and the timing of the handling device individually and perform self-examination, and the index time increases.

  In the semiconductor test apparatus of Patent Document 2, after the handler 107 contacts the semiconductor device 103a to be inspected with the socket 104a, the arm control unit 106 transmits an inspection start signal to the semiconductor inspection apparatus 109a via the handler interface 105. The semiconductor inspection apparatus 109a starts inspection of the semiconductor device 103a after receiving the inspection start signal from the arm control unit 106. However, since a series of operation timings such as raising and lowering by the contact arms 101a and 101b and inspection by the semiconductor inspection apparatuses 109a and 109b with respect to the semiconductor device to be inspected are not taken into consideration, each element requires a waiting time, and the test time There is a problem that cannot be shortened sufficiently.

  Even in the semiconductor test apparatus described in Patent Document 3, since a series of operation timings such as transfer and transfer of a semiconductor device to be inspected and a test by a tester are not considered, each element requires a waiting time, and the test time There is a problem that cannot be shortened sufficiently. That is, in Patent Document 3, it is necessary to set a waiting time by the control program in the handler until the handler transport device transports the semiconductor device to be inspected and fixes it to the socket. Since the start signal from the control program to the tester is transmitted after receiving the signal from the sensor on the handler side, there is a problem that processing time is required.

  Accordingly, an object of the present invention is to provide a semiconductor test apparatus and a semiconductor test method capable of efficiently testing a semiconductor device.

In order to achieve the above object, a semiconductor test apparatus according to the present invention is a semiconductor test apparatus for testing a semiconductor device, and includes a measurement jig to which the semiconductor device is bonded for the test, and the semiconductor device as described above. A transport unit for transporting to a measurement jig, a tester for testing the semiconductor device, and a sensor for outputting a signal indicating a joint between the measurement jig and the semiconductor device,
A signal for instructing conveyance to the conveyance unit and a signal indicating the bonding between the measurement jig and the semiconductor device from the sensor are monitored, and when the signals are obtained, the test of the semiconductor device is performed on the tester. A start is instructed.

A semiconductor test method according to the present invention is a semiconductor test method for transporting a semiconductor device to be tested to a measurement jig, joining the semiconductor device to the measurement jig, and testing the semiconductor device.
A signal for instructing the conveyance of the semiconductor device to the measurement jig and a signal indicating the bonding between the measurement jig and the semiconductor device are monitored, and the test of the semiconductor device is performed when these signals are obtained. It is characterized by starting.

  The present invention can efficiently test a semiconductor device.

It is the schematic for demonstrating the semiconductor test apparatus and semiconductor test method by one embodiment of this invention. FIG. 2 is a detailed view of the semiconductor test apparatus of FIG. 1. 6 is a timing chart for explaining the operation of the semiconductor test apparatus according to the embodiment of the present invention. It is a block diagram of the semiconductor test apparatus shown by patent document 2. FIG.

  Preferred embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, a semiconductor test apparatus according to an embodiment of the present invention includes a nozzle 1 that sucks a semiconductor integrated circuit to be tested, a transport unit 2 that moves the nozzle 1, and a semiconductor integrated circuit to be tested. A measuring jig 6 having a contact portion 5 to be joined, a sensor 4 for outputting a signal indicating that the semiconductor integrated circuit and the contact portion 5 are normally joined, a tester 9 for testing the semiconductor integrated circuit to be tested, The handler 3 that controls the operation of the transport unit 2 and outputs a trigger signal to the tester 9 to start the test, and controls the interface between the handler 3 and the tester 9 and monitors the output signal from the sensor 4 A control unit 7 and an interface 8 connecting the handler 3 and the monitoring control unit 7 and between the monitoring control unit 7 and the tester are provided.

  Next, details of the handler 3, the monitoring control unit 7, and the tester 9 will be described in more detail with reference to FIG. The handler 3 includes a transport unit control unit 3a, a tester interface unit 3b, and a determination unit 3c. The transport unit control means 3 a outputs a transport unit control signal a to the transport unit 2 and the delay circuit 7 a of the monitoring control unit 7. The tester interface unit 3b outputs a start signal d for instructing the start of the test to the second determination circuit 7c of the monitoring controller 7. A signal f indicating a contact failure or a signal h indicating the end of the test is input from the gate circuit 7d of the monitoring control unit 7 to the determination unit 3c.

  The monitor control unit 7 includes a delay circuit 7a, a first determination circuit 7b, a second determination circuit 7c, and a gate circuit 7d. The delay circuit 7 a adjusts the timing until the semiconductor integrated circuit 10 is transported to the measurement jig 6 by the transport unit control signal a of the transport unit control means 3 a of the handler 3. The first determination circuit 7b receives the output signal b of the delay circuit 7a and the signal c indicating that the semiconductor integrated circuit 10 and the contact part 5 are normally joined by the sensor 4, and outputs a signal e indicating the determination result. To do. The second determination circuit 7 c receives the signal e from the first determination circuit 7 b and the output signal d from the tester interface means 3 b of the handler 3 and outputs a measurement start signal g to the tester 9. The gate circuit 7d is an OR gate in FIG. 2, and receives the signal f indicating the contact failure from the first determination circuit 7b and the signal h of the test end means 9b from the tester 9, and determines the determination means 3c of the handler 3. A signal i indicating the end of the test is output.

  The tester 9 has a test start means 9a and a test end means 9b. The test start means 9a receives the measurement start signal g from the second determination circuit 7c of the monitoring controller 7, and starts the test of the test target semiconductor integrated circuit 10. The test end means 9b outputs a signal h indicating the end of the test to the first determination circuit 7b, the second determination circuit 7c and the gate circuit 7d of the monitoring controller 7, and notifies the determination means 3c of the handler 3 of the end of the test. Then, the first determination circuit 7b and the second determination circuit 7c of the monitoring controller 7 are reset.

  Next, the operation of the semiconductor test apparatus of this embodiment will be described. As shown in FIG. 3, the transport unit control means 3a of the handler 3 outputs a transport unit control signal a (ON period T1). Receiving this, the transport unit 2 transports the test target semiconductor integrated circuit 10 adsorbed to the nozzle 1 to the contact unit 5 of the measurement jig 6. The delay circuit 7a of the supervisory control unit 7 that has received the transport unit control signal a outputs a signal b (ON period T2). The timing of outputting the ON period T2 and the signal b is adjusted with the moving time in which the transport unit 2 moves the semiconductor integrated circuit 10 to the contact unit 5 of the measuring jig 6. The delay time and the on period T2 of the delay circuit 7a are set so that the timing is adjusted.

  When the semiconductor integrated circuit 10 and the contact portion 5 are normally bonded, the sensor 4 outputs a signal c indicating that the semiconductor integrated circuit 10 and the contact portion 5 are normally bonded (ON period T3). When the semiconductor integrated circuit 10 and the contact portion 5 are not normally joined, the signal c is not output.

  When the signal c indicating that the semiconductor integrated circuit 10 and the contact part 5 are normally joined is output from the sensor 4 within the ON period T2 during which the delay circuit 7a outputs the signal b, the monitoring control part 7 The first determination means 7b outputs a signal e indicating the determination result (on period T5). When the signal d (ON period T4) instructing the start of the test is output from the tester interface unit 3b of the handler 3 while the first determination unit 7b outputs the signal e, the second determination unit 7c The measurement start signal g is output (ON period T6).

  The tester 9 performs a test on the semiconductor integrated circuit 10 to be tested. After the test for the semiconductor integrated circuit 10 to be tested is completed, the end means 9b of the tester 9 outputs a tester determination signal h (ON period T7). As a result, the signal e of the first determination unit 7b and the signal g of the second determination unit 7c of the monitoring control unit 7 are reset, and the gate circuit 7d of the monitoring control unit 7 signals to the determination unit 3c of the handler 3 that the test is finished. i is output (ON period T8). By such a series of sequences, the semiconductor integrated circuit 10 to be tested is moved, fitted to the contact portion 5, and the test by the tester 9 is performed.

  Next, an operation when a contact failure occurs in which the semiconductor integrated circuit 10 and the contact portion 5 are not normally joined will be described. As shown in FIG. 3, the transport unit control means 3a of the handler 3 outputs a transport unit control signal a (ON period T11). Receiving this, the transport unit 2 transports the test target semiconductor integrated circuit 10 adsorbed to the nozzle 1 to the contact unit 5 of the measurement jig 6. The delay circuit 7a of the supervisory control unit 7 that has received the transport unit control signal a outputs a signal b (ON period T12). The timing of outputting the ON period T12 and the signal b is as described above, and the delay time and the ON period T12 are set in the delay circuit 7a so that such timing adjustment can be performed. The length of the on period T12 is the same as the length of the on period T2.

  The sensor 4 does not output the signal c when the semiconductor integrated circuit 10 and the contact portion 5 are not normally joined. Since the signal c is not output from the sensor 4 within the on period T12 in which the delay circuit 7a outputs the signal b, the first determination unit 7b of the monitoring control unit 7 does not output the signal e indicating the determination result, and the first The 1 determination means 7b outputs a signal f indicating a contact failure (ON period T14). In other words, the signal c is not output from the sensor 4 even when the transfer unit 2 moves the semiconductor integrated circuit 10 and moves it to the contact unit 5 of the measuring jig 6, that is, the delay time of the delay circuit 7a. At this time, the first determination means 7b outputs a signal f indicating a contact failure (ON period T14).

  Since the first determination means 7b does not output the signal e, even if the output signal d (ON period T13) instructing the test start is output from the tester interface means 3b of the handler 3, the second determination means 7c Therefore, the tester 9 does not start the test for the semiconductor integrated circuit 10. A signal f indicating a contact failure is output to the gate circuit 7d, and the gate circuit 7d outputs a signal i indicating the end of the test to the determination means 3c of the handler 3 (ON period T15). By such a series of sequences, when the semiconductor integrated circuit 10 and the contact portion 5 are not normally joined, or when a contact failure occurs, the occurrence of the contact failure is immediately notified to the handler 3, and the test by the tester 9 is performed. Not done.

  The monitoring control unit 7 of the present embodiment controls the timing of the start signal d of the tester interface means 3b and the transfer start signal to the transfer unit 2 from the handler 3 to the tester 9, so that the semiconductor integrated circuit 10 can measure the measurement jig 6 As soon as the signal c of the sensor 4 for detecting the junction is output to the contact portion 5, the measurement can be started by the tester 9. Further, when the semiconductor integrated circuit 10 and the contact portion 5 of the measuring jig 6 cannot be joined, the test for contact failure by the tester 9 can be omitted, and the measurement time of the tester 9 can be reduced. If there is no signal c from the sensor 4 even if the delay time of the delay circuit 7a, which is equivalent to the transport time of the transport unit 2, elapses, the determination circuit 7b transmits a contact failure signal f to the handler 3, thereby It is possible to omit a contact failure test due to the above.

  Furthermore, the monitoring control unit 7 of the present embodiment does not require timing adjustment such as sending a measurement start signal to the tester after the control of the transport unit is completed from the handler as in the background art. For example, even if the transport unit control signal a of the transport unit control unit 3a of the handler 3 and the signal d instructing the test start of the tester interface unit 3b of the handler 3 are output simultaneously, the semiconductor integrated circuit 10 and the measurement jig 6 By inputting the signal c from the sensor 4 that monitors the bonding with the contact portion 5 to the first determination circuit 7b, the measurement start signal g can be transmitted to the tester 9 via the second determination circuit 7c. By simultaneously transmitting the transport unit control signal a of the transport unit control unit 3a of the handler 3 and the signal d instructing the test start of the tester interface unit 3b of the handler 3, the measurement start to the semiconductor integrated circuit 10 to be measured is started. Setup time can be reduced.

  The first determination circuit 7b and the second determination circuit 7c can be realized by logic gates such as AND gates, and do not require time adjustment controlled by software. Therefore, the measurement start setup time for the semiconductor integrated circuit 10 to be measured is increased. Can be reduced.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to embodiment mentioned above. For example, the delay circuit of the above-described embodiment can be realized by changing the pulse width of the counter, and the shift register is used for timing adjustment between the semiconductor integrated circuit and a sensor that monitors the fitting in the contact portion of the measurement jig. It can also be realized with a delay by a time constant circuit.

  Further, although FIG. 3 illustrates an example using a positive logic, that is, high active signal, the semiconductor test apparatus and the semiconductor test method of the present invention can be realized using a negative logic, that is, a low active signal. . In that case, an AND gate circuit may be used instead of the OR gate circuit 7d of FIG.

DESCRIPTION OF SYMBOLS 1 Nozzle 2 Conveyance part 3 Handler 3a Conveyance part control means 3b Tester interface means 3c Judgment means 4 Sensor 5 Contact part 6 Measuring jig 7 Monitoring control part 7a Delay circuit 7b 1st judgment circuit 7c 2nd judgment circuit 7d Gate circuit 8 Interface 9 Tester 9a Test start means 9b Test end means 10 Semiconductor integrated circuit

Claims (5)

A semiconductor test apparatus for testing a semiconductor device, wherein the measurement jig to which the semiconductor device is bonded for the test, a transport unit that conveys the semiconductor device to the measurement jig, and the semiconductor device are tested. A tester, and a sensor that outputs a signal indicating the bonding between the measurement jig and the semiconductor device,
A signal for instructing conveyance to the conveyance unit and a signal indicating the bonding between the measurement jig and the semiconductor device from the sensor are monitored, and when these signals are obtained, the test of the semiconductor device is performed on the tester. A semiconductor test apparatus characterized by instructing start. A handler for controlling the transport of the semiconductor device by the transport unit;
A signal for instructing conveyance to the conveyance unit, a signal indicating the bonding between the measurement jig and the semiconductor device from the sensor, and a test start signal from the handler are monitored, and when these signals are obtained, The semiconductor test apparatus according to claim 1, wherein a tester is instructed to start a test of the semiconductor device.   A first determination circuit that receives a signal for instructing conveyance to the conveyance unit, and a signal that indicates a connection between the measurement jig and the semiconductor device from the sensor, an output from the first determination circuit, and a handler 3. The semiconductor test apparatus according to claim 2, further comprising a monitoring control unit including a second determination circuit that receives the test start signal and instructs the tester to start the test of the semiconductor device.   The first determination circuit of the monitoring control unit outputs a signal indicating a contact failure to the handler when a signal indicating bonding between the measurement jig and the semiconductor device is not input from the sensor. The semiconductor test apparatus according to claim 3. In a semiconductor test method for transporting a semiconductor device to be tested to a measurement jig, connecting the semiconductor device to the measurement jig, and testing the semiconductor device,
A signal for instructing the conveyance of the semiconductor device to the measurement jig and a signal indicating the bonding between the measurement jig and the semiconductor device are monitored, and the test of the semiconductor device is performed when these signals are obtained. A semiconductor test method characterized by starting.

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