JP5460374B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device that picks up semiconductor chips from a semiconductor wafer, and more particularly to a method of manufacturing a semiconductor device in which semiconductor chips are arranged in a matrix from a semiconductor wafer on which a large number of semiconductor chips are formed by dicing. .

Currently, semiconductor chips formed on a semiconductor wafer have an extremely small shape. For example, a large number of tens of thousands of semiconductor chips are formed on a 4-inch semiconductor wafer. In order to take out a semiconductor chip from the semiconductor wafer and mount it on a circuit board, first, the semiconductor wafer is divided by dicing to form an aggregated body of semiconductor chips.

Then, as a method of manufacturing a semiconductor device by mounting an assembly of the semiconductor chips in close contact with each other on a circuit board, a method of picking up and mounting the semiconductor chips one by one, and a matrix form with a wide interval between the semiconductor chips in close contact with each other There is a so-called assembly mounting method in which the arrangement of the semiconductor chips in a matrix is collectively mounted on a circuit board.
In order to collectively mount semiconductor chips on a circuit board in a lump, various apparatuses and manufacturing methods have been proposed for rearranging and converting a set of semiconductor chips in close contact with each other in a matrix.

As a manufacturing method of such a prior art, a manufacturing method is disclosed in which an assembly in which the above-described semiconductor chips are in close contact with each other is widened in a matrix to perform assembly mounting. (For example, patent document 1).
Hereinafter, this conventional manufacturing method will be briefly described with reference to FIG.

  As shown in FIG. 33A, the large-diameter semiconductor wafer 112 is attached to the adhesive film 109 in a state where the scribe line 108 is formed by scribe processing. The large-diameter semiconductor wafer 112 containing the scribe line 108 is expanded in the direction of the arrow A that is the X-axis direction while maintaining parallelism, and after having a predetermined interval with respect to the X-axis, the Y-axis direction Expand in the direction of arrow B. Alternatively, the expansion to the X and Y axes is performed simultaneously. Therefore, the large-diameter semiconductor wafer 112 is separated by the scribe line 108, and the semiconductor chips 101 on the adhesive film 109 are maintained in parallel and are spread in a matrix in the same direction at equal intervals vertically and horizontally. At this time, since the film is expanded in the X and Y axis directions while maintaining parallelism, the surface of the adhesive film 109 is parallel to the adsorption surface of the adsorption collet 113 and the adhesion surface of the large-diameter circuit board 114. .

  Thus, by expanding in the X-axis and Y-axis directions, the semiconductor chips 101 on the adhesive film 109 are positioned in parallel with the suction collet 113 and the circuit board 114, respectively, as shown in FIG. The pitch of each semiconductor chip 101 is equal to the pitch of each collet 113a of the suction collet 113, and this pitch corresponds to each lattice-shaped chip formed on the large-diameter circuit board 114 by dicing lines.

As shown in FIG. 33C, the suction collet 113 vacuum-sucks the semiconductor chips 101 arranged at equal intervals in the vertical and horizontal directions and adheres them to the circuit board 114. Thereafter, the chips are separated for each chip along the dicing line 111 of the circuit board 114 by dicing or the like.
As a result, the method for assembling the semiconductor device with respect to the semiconductor chip 101 formed on the large-diameter semiconductor wafer 112 can be implemented all at once or in arbitrary blocks.

  Since the configuration and process are as described above, a large number of semiconductor chips can be bonded to the circuit board as an assembly mounting at a time, and thus it is necessary to arrange the semiconductor chips on a chip tray as in the conventional assembly. There is no need to assemble every chip, and the work time is shortened and the work becomes easy.

JP-A-6-77317 (page 4, FIG. 2)

  However, in the prior art shown in Patent Document 1, the semiconductor chip of the closely-attached assembly adhered to the adhesive tape is expanded in the direction of the arrow A and the direction of the arrow B, and the array is arranged at regular intervals in a matrix. As the purpose, tension is applied in the direction different by 90 ° between the arrow A and the arrow B, so that the adhesive tape forming the flat surface is distorted, and the semiconductor chips are not easily aligned and arranged at a constant interval. There is a problem that the semiconductor chips cannot be aligned and arranged at a desired pitch interval due to the elongation limit of the tape.

  The present invention has been made in view of the above problems, and a mass-produced semiconductor chip formed on a diced semiconductor wafer is closely arranged in a matrix at a predetermined interval with high accuracy. An object of the present invention is to provide a method of manufacturing a semiconductor device that enables assembly mounting on a certain circuit board.

  A method for manufacturing a semiconductor device according to the present invention for achieving a higher-level object is a method for manufacturing a semiconductor device in which a semiconductor wafer is cut and separated and arranged in a matrix, and a semiconductor wafer deposited on an expanded sheet is cut into a matrix. A step of inserting a spacer member between the rows of the cut semiconductor wafer in the X-axis direction to expand the space between the rows to the width of the spacer member, and a step of holding the space between the expanded rows of the X-axis direction A step of inserting a spacer member between each column of the semiconductor wafer in the Y-axis direction to expand the interval between the columns to the width of the spacer member, a step of holding between the expanded columns in the Y-axis direction, and a matrix shape And a step of peeling the expanded sheet from the semiconductor element disposed and held on the substrate.

  According to the above manufacturing method, the alignment width of the semiconductor chips can be easily regulated by inserting the spacer member having a predetermined width between the diced semiconductor wafers, and the semiconductor chips are arranged in a matrix. Can be easily done.

  The spacer member is provided with a cutting cutter portion, and it is preferable to cut the expanded sheet simultaneously with expanding the row and column intervals of the semiconductor wafer.

  According to the above configuration, the expansion and contraction between the semiconductor chips can be easily performed by cutting the expanded sheet simultaneously with the width regulation between the semiconductor chips.

  In the step of holding the rows between the X-axis direction and the step of holding the rows in the Y-axis direction, the semiconductor element expanded by the spacer member may be pressure-bonded to the slightly adhesive sheet.

  The step of peeling the expanded sheet may be performed by adsorbing and fixing semiconductor elements arranged in a matrix on an adsorption device.

  The step of expanding each row in the X-axis direction and the step of expanding each column in the Y-axis direction include an alignment guide member having a concave portion for allowing the spacer member to pass therethrough and a convex portion for holding the semiconductor chip in a comb shape. It is good to do using.

  According to the above configuration, the spacer member can be guided and operated, and at the same time, the semiconductor chip can be securely held.

  The convex portion for holding the semiconductor chip of the alignment guide member may have a vacuum suction means.

  As described above, according to the manufacturing method of the present invention, the alignment width of the semiconductor chips can be easily regulated by inserting the spacer member having a predetermined width between the diced semiconductor wafers. It can be easily arranged in a matrix with high accuracy. Therefore, in assembly mounting with a circuit board in the next process, it is possible to provide assembly mounting with good alignment accuracy and extremely low occurrence of defects.

It is a top view of the cutting state of the semiconductor wafer processed by the manufacturing method of the semiconductor device of this invention. It is a top view which shows the state which extended the semiconductor wafer attached to the expanded sheet shown in FIG. 1 to XY. FIG. 3 is a plan view showing a state in which the semiconductor wafers shown in FIG. 2 are aligned and arranged at a predetermined interval. It is a top view of the semiconductor element manufacturing apparatus used for the manufacturing method of Example 1 of this invention. It is AA sectional drawing in FIG. It is a top view of the semiconductor element manufacturing apparatus used for the manufacturing method of Example 1 of this invention. In Example 1 of this invention, it is a top view of the manufacturing process which expands a semiconductor chip from a semiconductor wafer. In Example 1 of this invention, it is a top view of the manufacturing process which expands a semiconductor chip from a semiconductor wafer. In Example 1 of this invention, it is a top view of the manufacturing process which expands a semiconductor chip from a semiconductor wafer. It is a top view of the vacuum suction apparatus used for Example 1 of the present invention. It is a top view which shows the state which attached the vacuum suction apparatus to the semiconductor element manufacturing apparatus in Example 1 of this invention. It is BB sectional drawing of FIG. FIG. 11 is a plan view showing a state in which the semiconductor wafers of the assembly are held in an array arranged in a matrix in the vacuum suction device in FIG. It is a partial cross section of the semiconductor element manufacturing apparatus in Example 2 of this invention. It is a partial cross section of the semiconductor element manufacturing apparatus in Example 2 of this invention. It is a fragmentary sectional view which shows the state which removed the expanded sheet and the slightly adhesive tape from FIG. It is a partial cross section of the semiconductor element manufacturing apparatus in Example 3 of this invention. It is a top view of the semiconductor element manufacturing apparatus used for the manufacturing method of Example 4 of this invention. It is a top view of the semiconductor element manufacturing apparatus used for the manufacturing method of Example 4 of this invention. It is a top view of the semiconductor element manufacturing apparatus used for the manufacturing method of Example 4 of this invention. It is a top view of the semiconductor element manufacturing apparatus used for the manufacturing method of Example 4 of this invention. It is a top view which shows the state by which G * LED was arranged in the arrangement jig apparatus in Example 5 of this invention. It is a top view which shows the state by which B * LED was arranged in the arrangement jig apparatus in Example 5 of this invention. It is a top view which shows the state by which R * LED was arranged in the arrangement jig apparatus in Example 5 of this invention. It is a top view which shows a part of large format circuit board 300 which mounted R * LED, G * LED, and B * LED in Example 5 of this invention. It is a top view which shows a part after transparent resin sealing of the large format circuit board 300 shown in FIG. It is a top view of the color light-emitting device manufactured by Example 5 of this invention. It is sectional drawing of the color light-emitting device manufactured by Example 5 of this invention. It is a top view which shows a part of large format circuit board 300 which mounted R * LED, G * LED, and B * LED in Example 6 of this invention. It is a top view which shows a part after transparent resin sealing of the large format circuit board 300 shown in FIG. It is a top view of the color light-emitting device manufactured by Example 6 of this invention. It is sectional drawing of the color light-emitting device manufactured by Example 5 of this invention. It is a perspective view which shows the manufacturing process of the semiconductor device in the conventional aggregate mounting system.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
1 to 3 are views for explaining a configuration of a semiconductor wafer processed by the method for manufacturing a semiconductor device of the present invention. FIG. 1 is a plan view showing a process of cutting a semiconductor wafer 1 deposited on an expanded sheet 9 which is an adhesive sheet into a matrix. As a dicing method in which the semiconductor wafer 1 is diced by the dicing line 3 to form a close contact assembly of the semiconductor elements 2 (hereinafter referred to as semiconductor chips 2), stealth dicing is preferably used. In other words, stealth dicing has no damage to the surface layer of the wafer compared to conventional dicing, there is no thermal effect on the active region, no debris contamination, and a reduction in reliability such as a reduction in bending strength due to the occurrence of microcracks at the chip edge is prevented. It is possible.

  FIG. 2 is a plan view in which the close contact assembly of the semiconductor chips 2 is formed in a matrix shape with a predetermined interval H1 by stretching the expand sheet 9 shown in FIG. 1 in the XY directions indicated by arrows. A circle indicated by a dotted line indicates an expanded range of the semiconductor wafer 1.

  FIG. 3 is a plan view in which the close-packed assembly of the semiconductor chips 2 stretched according to FIG. 2 is formed in a matrix shape with a predetermined interval H2 so as to be collectively mounted on a circuit board. A circle indicated by a dotted line indicates an expanded range of the semiconductor wafer 1. Actually, there are a number of rows and columns of other semiconductor chips 2 for one semiconductor wafer 1, but in order to facilitate understanding, in the embodiment, a semiconductor wafer of 9 rows and 9 columns is illustrated, It is indicated by X1 to X9 and Y1 to Y9.

  That is, according to the present invention, the expanded arrangement of the expanded sheet 9 shown in FIG. 2 is used to arrange the semiconductor wafers 1 that are stretched into the matrix shape with the interval H1 into the matrix shape arrangement with the actual mounting interval H2. Examples are described below.

  4 is a plan view of the semiconductor element manufacturing apparatus according to the first embodiment, and FIG. 5 is a partial cross-sectional view thereof. In FIG. 4, the alignment device 50 is configured to position and fix the mounting table 60 in the positioning recess 51, and further, a plurality of alignment squeegees SK1 to SK8 (this is slidable in the direction of the upper surface of the mounting table 60). The number is determined by the number of semiconductor chip rows and columns processed at one time, and is eight in this embodiment.) This alignment squeegee SK is a spacer that determines the widths of the semiconductor chip rows X and the semiconductor chip columns Y. It has a function as a member. Therefore, the width of the alignment squeegee SK is H2 which is the mounting interval of the semiconductor chip rows X and columns Y, and the interval between the alignment squeegees SK is the width H of the semiconductor chip 2.

  5 shows a partial cross-sectional view taken along the line AA in FIG. 4, the fine adhesive sheet 61 is attached to the entire upper surface of the mounting table 60, and the semiconductor chip 2 is attached to the upper surface of the fine adhesive sheet 61. The expanded sheet 9 is shown attached. The alignment squeegee SK is provided with a spacer part SKs and a cutting cutter part SKc. The spacer part SKs serves as a spacer to regulate the width between the semiconductor chips 2 and the cutting cutter part SKc completely covers the expanded sheet 9. And a portion of the slightly adhesive sheet 61 is cut.

  Next, the operation of aligning and arranging the semiconductor wafer 1 in the semiconductor element manufacturing apparatus will be described with reference to FIGS. First, in FIG. 4, the mounting table 60 is positioned and fixed in the positioning recess 51 of the alignment device 50. Further, the expanded sheet 9 expanded in the state shown in FIG. Regarding the positioning of the expanded sheet 9 with respect to the mounting table 60, since the expanded sheet 9 moves in the alignment and placement operation described later, the initial deposition position is determined in consideration of the movement allowance. In FIG. 4, first, in order to perform an alignment operation for restricting the width of the semiconductor wafer row X to H2, the mounting table 60 is positioned and fixed with respect to the alignment device 50. The sliding direction of the alignment squeegee SK is the same as that of the semiconductor wafer. It is fixed to be parallel to the direction of row X.

  4 and 5 show a state where the alignment squeegee SK1 has finished its operation and the alignment squeegee SK2 is in operation. That is, the alignment squeegee SK1 is in a state in which the space between the semiconductor chip rows X1 and X2 is expanded to H2, and the interval between the illustrated semiconductor wafers 2a is H2. Further, the alignment squeegee SK2 is in a state of being slid halfway, and the interval between the exemplified semiconductor wafers 2a is H2, but the interval between the exemplified semiconductor wafers 2b is in a state of H1. The interval between the semiconductor wafers 2b exemplified by the alignment squeegee SK2 sliding to the final position (the same position as SK1) is also restricted to H2.

  Next, the operation of aligning and arranging the semiconductor wafer rows X by the aligning squeegee SK will be described with reference to FIG. The reason why the slightly adhesive sheet 61 is attached to the entire top surface of the mounting table 60 in FIG. 5 is to prevent the cutting cutter part SKc of the alignment squeegee SK from coming into contact with and damaging the metal mounting table 60. This is because the expanded sheet 9 cut by the cutting cutter SKc of the alignment squeegee SK is slid and moved.

  As shown in the sectional view of FIG. 5, when the alignment squeegee SK1 slides between the semiconductor wafer rows X1 and X2, the cutting sheet SKc cuts the expanded sheet 9 and at the same time uses the sharp shape of the tip to make the width H1. The semiconductor wafer 2a2 is expanded to the width H2. That is, the cutting portion 9a of the expanded sheet 9 slides on the slightly adhesive sheet 61 when the semiconductor wafer 2a2 attached to the expanded sheet 9 is pushed in the arrow X direction by the alignment squeegee SK1.

  Next, when the alignment squeegee SK2 slides between the semiconductor wafer rows X2 and X3, the cutting sheet SKc cuts the expanded sheet 9, and at the same time, the tip H sharpness of the semiconductor wafer 2a3 having the width H1 is cut to H2. Restricts expansion to the width of. That is, the cutting portion 9a of the expanded sheet 9 slides on the slightly adhesive sheet 61 when the semiconductor wafer 2a3 attached to the expanded sheet 9 is pushed in the arrow X direction by the alignment squeegee SK2. Since the alignment squeegee SK3 has not yet been slid, the space between the semiconductor wafer rows X3 and X4 remains H1, and the semiconductor wafer 2c has not moved.

  As described above, the alignment squeegees SK3 and lower sequentially slide between the semiconductor wafer rows, whereby the width of each semiconductor wafer row is restricted to H2 by the spacer portion SKs of the alignment squeegee SK and the restriction of the spacer portion SKs. The expanded sheet 9 cut by the cutting cutter unit SKc and the semiconductor wafer 2 deposited thereon move by the pressure, but move in a direction not restricted by the previously operated alignment squeegee SK, that is, in the arrow X direction. As a result, the width is controlled by the squeegee SK for alignment and the expanded sheet 9 and the semiconductor wafer 2 attached thereto are moved, so that all the semiconductor wafer rows X are aligned and arranged.

6 is a plan view of the semiconductor element manufacturing apparatus described with reference to FIG. 4. The semiconductor wafer rows X1 and X2 described with reference to FIG. 3 are all restricted to the width H2 by the alignment squeegee SK1. Yes. Further, between the semiconductor wafer rows X2 and X3, half is regulated to the width H2 by the alignment squeegee SK2, and the other half remains the width H1 before regulation. Further, all the semiconductor wafer rows X3 to X9 remain the width H1 before regulation.
Further, FIG. 6 shows an aligned arrangement state of the semiconductor wafer rows, and all the widths of the semiconductor wafer columns Y1 to Y9 described in FIG.

  FIG. 7 is a plan view of the semiconductor element manufacturing apparatus showing a state in which the alignment arrangement of the semiconductor wafer rows is completed. All the alignment squeegees SK1 to SK9 perform the sliding operation so that the intervals between the semiconductor wafer rows X1 to X9 are all. This is a state restricted to the width of H2. The expanding sheet 9 is expanded in the direction of the arrow X by this aligning and arranging operation. In this state, since the semiconductor wafer column Y is not aligned and arranged, the interval between the semiconductor wafer columns Y1 to Y9 is H1, and the size of the expanded sheet 9 in the column direction is the length in the column direction shown in FIG. Sato has not changed.

  Next, the operation of aligning and arranging the semiconductor wafer rows Y will be described with reference to FIG. In the plan view of the semiconductor element manufacturing apparatus of FIG. 8, in order to perform the alignment and arrangement operation of the semiconductor wafer row Y, the mounting table 60 is positioned and fixed with respect to the alignment device 50. The sliding direction of the alignment squeegee SK is the semiconductor wafer row. It is fixed so as to be parallel to the Y direction.

  That is, in FIG. 7, in the state where all the alignment operation of the semiconductor wafer row X is completed, all the alignment squeegees SK are retracted and stored in the alignment device 50. In this state, the mounting table 60 is removed from the positioning recess 51 of the aligning device 50, the mounting table 60 is rotated by 90 degrees, and the sliding direction of the alignment squeegee SK is again in the positioning recess 51 of the aligning device 50. Fix it again in parallel with the Y direction.

  The position of the semiconductor wafer 2 attached to the expanded sheet 9 at the time of changing the mounting table 60 does not move because it is adhered to the slightly adhesive sheet 61 via the expanded sheet 9, but the semiconductor wafer 2 is not moved. In order to ensure the adhesion to the slightly adhesive sheet 61, it is desirable to securely adhere to the slightly adhesive sheet 61 by pressing from the upper side of the semiconductor wafer 2 using, for example, a flat plate jig or the like.

  FIG. 8 also shows a state in which the alignment squeegee SK1 has finished operating and the alignment squeegee SK2 is in operation as in FIG. That is, the alignment squeegee SK1 is in a state where the space between the semiconductor chip rows Y1 and Y2 is expanded to H2, and the interval between the semiconductor wafers 2a is H2. Further, the alignment squeegee SK2 is in a state of being slid halfway, and the interval between the exemplified semiconductor wafers 2a is H2, but the interval between the exemplified semiconductor wafers 2b is in a state of H1.

  Further, in FIG. 8, the semiconductor wafer rows X1 to X9 are all restricted to the width of H2 by the alignment and arrangement operation of the previous semiconductor wafer row X, and the width of the expand sheet 9 in the row direction is also increased. Therefore, in the alignment and placement operation of the semiconductor wafer row Y, the semiconductor shown in FIGS. 4 and 5 is different from the alignment and placement operation of the semiconductor wafer row X except that the sliding length of the alignment squeegee SK is larger. This is the same as the operation of aligning and arranging the wafer rows X, and a duplicate description is omitted.

  FIG. 9 is a plan view of the semiconductor device manufacturing apparatus showing a state in which the alignment arrangement of the semiconductor wafer rows is completed. All the alignment squeegees SK1 to SK9 perform the sliding operation so that the intervals between the semiconductor wafer rows Y1 to Y9 are all increased. This is a state restricted to the width of H2. The expanding sheet 9 is also expanded in the direction of the arrow Y by this aligning and arranging operation. In this state, the operation of aligning and arranging the semiconductor wafer rows X and the semiconductor wafer columns Y is performed, so that the intervals between the semiconductor wafer rows X1 to X9 and the semiconductor wafer columns Y1 to Y9 are all regulated to be H2. 3 is a matrix arrangement with the interval H2 shown in FIG. Therefore, the width H2 between the semiconductor wafers is accurately regulated by the width of the spacer portion SKs of the alignment squeegee SK.

  Next, the expanded sheet 9 and the slightly adhesive sheet 61 are peeled from the aggregated semiconductor chips 2 arranged in a matrix shape with an interval of H2 by the semiconductor element manufacturing apparatus according to FIGS. 10 to 13 and arranged on the suction plate. The method of making it explain.

  FIG. 10 is a plan view of the vacuum suction device 80. The vacuum suction device 80 is positioned in a rectangular shape with a size covering the mounting table 60 of the semiconductor element manufacturing apparatus in alignment with the positioning recess 51 of the alignment device 50. It has a convex part 81. FIG. 11 is a plan view in which the vacuum suction device 80 is set in the semiconductor element manufacturing apparatus. The vacuum suction device 80 is positioned by aligning the positioning convex portion 81 with the positioning concave portion 51 of the aligning device 50, so Is in contact with all the semiconductor chips 2.

  12 is a cross-sectional view taken along line BB showing a partial cross section of the semiconductor element manufacturing apparatus of FIG. In other words, the semiconductor chip 2 is adhered via the slightly adhesive sheet 61 and the expanded sheet 9 attached to the upper surface of the mounting table 60, but the semiconductor chip 2 is firmly attached to the vacuum suction device 80 in the state where the semiconductor chip 2 is firmly adhered. The expanded sheet 9 can be peeled off due to the difference in adhesion. In addition, when the expanding sheet 9 is irradiated with ultraviolet rays at the time of the peeling operation, the adhesive strength is reduced, so that the peeling can be further facilitated.

  FIG. 13 is a plan view showing a state in which the aggregate semiconductor chips 2 are aligned and arranged in a matrix shape with an H2 interval in the vacuum suction device 80, and in this state, the expanded sheet 9 has been peeled off, The vacuum suction device 80 can be mounted on the collective circuit board on which the circuit pattern of the same pitch is formed by positioning the outer shape of the vacuum suction device 80. In addition, the range shown with a dotted line is the range of the placing stand 60.

Next, a manufacturing method of the second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
The second embodiment is basically the same manufacturing method as the first embodiment, and the semiconductor chip 2 stretched into a matrix shape with the interval H1 by the expansion of the expanded sheet 9 is changed to the actual mounting interval H2. The alignment of the semiconductor wafers 1 formed in a matrix shape is the same as the alignment squeegee SK provided with the spacer portions SKs and the cutting cutter portions SKc.

  Therefore, in FIG. 14 which is a partial cross section of the semiconductor element manufacturing apparatus, the same elements as those in FIG. 5 which is a partial cross section of the semiconductor element manufacturing apparatus of the first embodiment are denoted by the same reference numerals, and redundant description is omitted. The difference between the second embodiment and the first embodiment is that the semiconductor wafers 2 positioned at the width H2 by the suction device 90 are aligned and arranged while being suction fixed.

  In FIG. 14, the suction device 90 is provided with an uneven alignment guide portion 92 continuous to the suction portion main body 91, and the concave portion 93 of the alignment guide portion 92 is the width of the spacer portion SKs of the alignment squeegee SK, that is, The regulation width H2 of the semiconductor wafer 2 is obtained. The width of the convex portion 94 is the width of the semiconductor wafer 2, that is, H, and a suction hole 95 connected to the suction mechanism of the suction portion main body 91 is provided at the center of the convex portion 94. In addition, the vertical line pattern of the suction hole 95 indicates the suction state, and white indicates the non-suction state.

  Next, with reference to FIGS. 14 and 15, the alignment operation in the second embodiment will be described. In FIG. 14, the suction device 90 is mounted on the expanded semiconductor wafer set on the mounting table 60 of the semiconductor element manufacturing apparatus shown in FIG. In this state, the concave portion 93 of the alignment guide portion 92 of the suction device 90 corresponds to the spacer portion SKs of each alignment squeegee SK, and the convex portion 94 is positioned at the position of the semiconductor chip 2 when aligned.

  In FIG. 14, the semiconductor chips 2a1, 2a2, and 2a3 have already been aligned by the alignment squeegee SK1 and the alignment squeegee SK2, and the semiconductor chips 2a1, 2a2, and 2a3 are adsorbed and fixed by the adsorption holes 95, respectively. Yes. Therefore, an operation in which the semiconductor chips 2a4 are aligned and arranged by the alignment squeegee SK3 will be described.

  When the alignment squeegee SK3 slides in the recess 93 of the alignment guide portion 92, the semiconductor chips 2a3 and 204 having the width H1 start to expand due to the tip shape of the alignment squeegee SK3. Since the semiconductor chip 2a3 adsorbed and fixed by the hole 95p cannot move, the semiconductor chip 2a4 not adsorbed and fixed by the adsorption hole 95n moves in the arrow X direction on the slightly adhesive sheet 61 together with the cut expanded sheet 9. When the semiconductor chips 2a3 and 2a4 are regulated to the width H2 by the spacer portion SKs of the row squeegee SK3, the semiconductor wafer 2a4 is positioned on the convex portion 94 of the alignment guide portion 92, and the suction hole 95n is in the suction state. Are aligned. By repeating the above operation, the alignment of all the semiconductor chips is completed as shown in FIG.

  FIG. 16 is a cross-sectional view showing a state where the expanded sheet 9 and the slightly adhesive sheet 61 are peeled off after the semiconductor wafers are aligned in FIG. In the second embodiment, all the semiconductor chips arranged and arranged are adsorbed and fixed to the convex portions 94 of the adsorbing device 90 by the adsorbing holes 95. Therefore, by moving the adsorbing device 90 upward, the first embodiment Similarly to the method described with reference to FIG. 12, the semiconductor chip 2 can be easily separated from the expanded sheet 9. The semiconductor chips 2 held in the suction device 90 in an aligned state can be collectively mounted on a collective circuit board on which circuit patterns with the same pitch are formed with the outer shape positioned.

Next, a manufacturing method of the third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
The third embodiment shown in FIG. 17 is based on basically the same manufacturing method as the second embodiment shown in FIG. 14, and the semiconductor chip is arranged and arranged using the suction device 90 in the same manner. Therefore, in FIG. 16 which is a partial cross section of the semiconductor element manufacturing apparatus in the third embodiment, the same elements as those in FIG. 14 which is a partial cross section of the semiconductor element manufacturing apparatus of the second embodiment are denoted by the same reference numerals, and redundant description is omitted. .

  The difference between the third embodiment and the second embodiment is that the alignment device 50 is provided with only one alignment squeegee SK1, and this single alignment squeegee SK1 is fixed inside the alignment device 50. By moving at a pitch (in this embodiment, three times the width of the semiconductor chip H, 3H) and sequentially regulating the alignment between the semiconductor chips, the alignment arrangement of all the semiconductor chips is completed.

  That is, in FIG. 17, the semiconductor wafers 2a1 and 2a2 are regulated by SK1 indicated by dotted lines, the next semiconductor wafers 2a2 and 2a3 are regulated by SK2 indicated by dotted lines, and the next semiconductor wafers 2a3 and 2a4 are regulated by SK1. The state which is going to be shown. Then, the method for peeling the expanded sheet 9 and the slightly adhesive sheet 61 after the arrangement of all the semiconductor chips is completed is the same as the method shown in FIG.

Next, a manufacturing method of the fourth embodiment of the manufacturing method of the semiconductor device according to the present invention will be described with reference to FIGS.
The fourth embodiment is based on the manufacturing method basically the same as the first and second embodiments, and the semiconductor chip 2 stretched into a matrix shape with the interval H1 by the expansion of the expanded sheet 9 is used as an actual mounting interval. The alignment of the semiconductor wafer 1 formed in the matrix shape of H2 is the same as the point performed by the alignment squeegee SK provided with the spacer part SKs and the cutting cutter part SKc, and the point moved and held by the suction device. It is.

  Accordingly, in the semiconductor element manufacturing apparatus, the same elements as those in the semiconductor element manufacturing apparatuses of the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The fourth embodiment is different from the first and second embodiments in the first and second embodiments, in which the entire rows and columns of the semiconductor wafer 1 are simultaneously arranged and supplied to the mounting line all at once. On the other hand, in the fourth embodiment, the alignment squeegee SK is expanded to H2 which is the mounting interval of the semiconductor wafer 1 for only one row (or even one column). The semiconductor chip group is sequentially supplied to the mounting line by holding the semiconductor chip by the suction device for one line and peeling it from the expanded sheet 9.

18 to 21 are plan views of the semiconductor element manufacturing apparatus used in the manufacturing method of the fourth embodiment, which are shown in the order of steps.
In FIG. 18, the mounting table 60, the expanded sheet 9 applied to the mounting table 60, and the expanded semiconductor wafer 1 applied to the expanded sheet 9 are the same as those in the first embodiment. However, the alignment device 500 is different from the alignment device 50 of the first embodiment in that it has a function of moving the mounting table 60 by one row of the semiconductor chip row in the direction indicated by the arrow S, and the alignment squeegee SK. The expansion / contraction range is limited to a range in which the width of one semiconductor chip 2 is expanded. The range of the positioning concave portion 510 of the aligning device 500 is the restriction expansion range, and the restriction expansion of the width H2 is performed on the semiconductor chip row for one column located in this range by the alignment squeegee SK.

  Further, the suction device 900 indicated by the dotted line is different from the suction device 90 of the first embodiment, whereas the suction device 90 has a function of sucking all semiconductor chips of the semiconductor wafer, whereas the suction device 900 has one line. It has only the adsorption holding function of the semiconductor chip row.

  The alignment holding operation for one row of the semiconductor chip 2 in the fourth embodiment will be described with reference to FIG. For convenience of explanation, all the semiconductor chips for one row existing in the first column, that is, the column of Y1, are all 2a, and all the semiconductor chips for one row existing in the second column, that is, the column of Y2, are all 2b. explain. FIG. 18 shows a state in which the semiconductor chips 2a of the first column in the semiconductor wafer 1, that is, one row of the Y1 column are aligned, and the first column Y1 is formed by one semiconductor row by five semiconductor chips 2a. Is configured. The state shown in the figure is a state in which four alignment squeegees SK 1 to SK4 are in operation, and the first operation of the alignment squeegee SK1 SK1 does not exist in the first row Y1, so the target squeegee SK1 is sent from In this state, the semiconductor chip 2b in the second row Y2 has a function of positioning the semiconductor chip 2b on the right side using the sharp shape of the tip.

  Next, the alignment squeegee SK2 is sent out, and the semiconductor element 2a on the right side is pressed to one side for positioning, and at the same time the semiconductor chip 2b in the second row Y2 is sharpened using the sharp shape of the tip. Align to the right. Next, when the alignment squeegee SK3 is sent out, the semiconductor chip 2a positioned by the alignment squeegee SK2 is used as a reference to press the semiconductor element 2a on the right side to the right to perform positioning. At the same time, it is the same that the semiconductor chips 2b in the second row Y2 are positioned to the right side by using the sharp shape of the tip. Further, the alignment squeegee SK4 shows an intermediate state of operation, and when it is sent to a prescribed position, the regulation expansion of the first row semiconductor chip 2a and the right alignment of the second row semiconductor chip 2b are performed. .

  FIG. 19 shows that the alignment squeegees SK1 to SK8 repeat this operation sequentially to extend the regulation of one row of the semiconductor chip 2a in the first column and position the semiconductor chip 2b in the second column to the right side. Shows the state. That is, the first row of semiconductor chips 2a are all regulated and expanded to a specified width H2 by the spacer portion SKs of the alignment squeegee SK, and at the same time, the second row of semiconductor chips 2b are moved to the right, which will be described later. In the next process, with the mounting table being fed into the aligning device 500 for one row, the second row of semiconductor chips 2b has moved to the operating range of the aligning squeegee SK.

  That is, in this state, the restriction expansion for one row of the semiconductor chip 2a constituting the first column Y1 is completed. In this state, each alignment squeegee SK is retracted and retracted into the alignment device 500, and at the same time, the suction device 900 is lowered and one row (five) of the semiconductor chips 2a constituting the first column Y1 in which the restriction is expanded. ) Is removed and the expanded sheet 9 is peeled from the semiconductor chip 2. This state can be performed, for example, by the same method as the adsorption separation shown in FIG. Further, the suction device 900 returns to the position shown in FIG. 18 after moving and mounting the sucked one row of semiconductor elements 2a to the mounting process on the circuit board. In each figure, X indicates the position of the semiconductor chip expanded by the expanded sheet 9, and the space between xx is the expanded width H2 of the semiconductor chip.

  Next, the operation in the intermediate process will be described with reference to FIG. FIG. 20 shows the operation in the fourth column Y4, and the column feed of the mounting table 60 is sequentially repeated in the direction indicated by the arrow S from the first column described in FIG. This shows the state where the regulatory expansion has been completed. That is, in the fourth column Y4, all the semiconductor chips 2a from X1 in the first row to X9 in the ninth row are regulated and expanded, and all the semiconductor chips 2b in the fifth column Y5 are aligned. In this case, the suction device 900 moves and mounts the nine semiconductor elements 2a to the expanded sheet peeling and mounting process.

  Next, the operation in the final process will be described with reference to FIG. That is, from the fourth column Y4 in FIG. 20, the column feed of the mounting table 60 by the alignment device 500 and the processing for each row by the suction device 900 proceed, and the regulation expansion operation of the ninth column Y9 is completed. Show. In this state, the number of semiconductor chips in the ninth column Y9 is the same as that for the five semiconductor chips 2a in the first row Y1.

  When the processing of the final process shown in FIG. 21 is completed, the mounting table 60 is sent out to the first position shown in FIG. 18 by the aligning device 500, and the semiconductor wafer attached to the new expanded sheet is set. Is repeated.

  The semiconductor element manufacturing apparatus in the fourth embodiment can use an alignment squeegee with a small stroke and an adsorption device for only one line, and can process semiconductor chips one line at a time. And increase the mounting speed.

  Next, with reference to FIG. 22 to FIG. 28, a description will be given of a manufacturing method of Embodiment 5 of the semiconductor device manufacturing method according to the present invention. 22 to 24 are plan views showing a state in which all alignment arrangements of the semiconductor wafer row X of the semiconductor wafer 1 have been completed by the alignment apparatus 50 or the alignment apparatus 500 of the present invention. That is, in FIG. 22, the intervals between all the semiconductor wafer rows X are restricted to the width H2 by the alignment squeegee SK, and the intervals between all the semiconductor wafer columns Y remain in the expanded state, H1.

  This state is, for example, a state in which all the arrangements of the semiconductor wafer rows X shown in FIG. 7 are aligned and extended, and the semiconductor wafer column Y is not expanded and the semiconductor chip is added to the vacuum suction device 80 shown in FIG. In this state, the expanded sheet 9 is peeled off by adsorbing 2 and positioned on the placement jig device 200. Accordingly, the semiconductor wafer row X is aligned with the regulated width H2 of the alignment squeegee SK from X1 to X4, and the interval between the semiconductor wafer columns Y is aligned with the expanded state width H1 (note that the aligned semiconductor chips 2 are arranged). (The numbers show only 4 rows and 6 columns, simplifying the drawing)

  In the aligned arrangement state shown in FIG. 22, in the fourth embodiment shown in FIG. 19, the alignment squeegee SK is expanded to H2, which is the mounting interval of the semiconductor wafer 1, for only one semiconductor wafer row. One column of the extended one row of semiconductor chips 1 is held by a suction device, peeled off from the expanded sheet 9, and placed and arranged on the placement jig device 200 at an interval H1 (possible with an arbitrary width). Also good.

  FIG. 22 shows a state in which green LEDs (abbreviated as G · LED) are arranged in an array. The letter G is given to the semiconductor chip 2 and the column numbers are Yg1 to Yg6. Similarly, FIG. 23 shows a state in which blue LEDs (abbreviated as “B / LED”) are arranged on the arrangement jig device 201, the letter B is given to the semiconductor chip 2, and the column numbers are Yb1 to Yb6. Similarly, FIG. 24 shows a state in which red LEDs (abbreviated as R · LED) are arranged on the arrangement jig device 202, the letter R is given to the semiconductor chip 2, and the column numbers are Yr1 to Yr6.

  FIG. 25 is a plan view showing a part of a large circuit board 300, showing a state in which an LED light emitting device mounted with R / LED, G / LED, and B / LED is mounted by a collective system. The manufacturing method will be described with reference to FIGS.

  In FIG. 25, wiring electrode arrays D1 to D6 (only a part of which are shown) are provided on the large circuit board 300, and the placement jig devices 200, 201, and 202 are shown in FIGS. The semiconductor chip rows arranged on the top are moved one by one on the large circuit board 300 by using the suction device 90 or 900 and placed at the position of the formed wiring electrode row (not shown). To go.

  In FIG. 25, Yb1 in the first row of B · LED is sucked and placed on the first wiring electrode row D1 from the placement jig device 201. Next, Yg1 of the first row of G · LED is sucked from the placement jig device 200 and placed on the second wiring electrode row D2. Further, the first Yr1 of the R • LED is sucked from the placement jig device 202 and placed on the third wiring electrode row D3.

  Further, the second row Yb2 of B · LED is sucked from the placement jig device 201 and placed on the fourth wiring electrode row D4. Next, the second row of G · LEDs Yg2 is sucked from the placement jig device 200 and placed on the fifth wiring electrode row D5. Further, the second Yr2 of the R • LED is sucked from the placement jig device 202 and placed on the sixth wiring electrode row D6.

  By repeating the above operation, when mounting of the R / LED, G / LED, and B / LED rows is completed on all the wiring electrode rows of the large circuit board 300, each semiconductor chip is reflowed to complete each semiconductor chip. In No. 2, face-down bonding is performed on wiring electrodes on a large circuit board. In FIG. 25, a dotted line surrounding one set of R • LED, G • LED, and B • LED indicates a cutting range in which a color light emitting device to be described later is formed by cutting later.

  FIG. 26 is a plan view showing a state in which the large circuit board 300 on which the semiconductor chip 2 shown in FIG. 25 is mounted is sealed with a transparent resin 301, and the satin pattern shows the sealing resin 301 and is cut from the semiconductor chip 2. The range is indicated by a dotted line.

  27 is a plan view of the color light emitting device 320 formed by being cut within the cutting range, and FIG. 28 is a cross-sectional view of the color light emitting device 320. In other words, R.LED, G.LED, B.LED rows are placed in the required order on the wiring electrode rows formed on the large circuit board 300, and each row includes each LED row after resin sealing. The color light emitting device 320 including each of the R • LED, G • LED, and B • LED semiconductor chips 2 can be mass-produced by cutting and separating in the direction.

  A manufacturing method according to the sixth embodiment of the present invention will be described with reference to FIGS. The sixth embodiment shown in FIG. 29 is basically the same as the manufacturing method of the fifth embodiment shown in FIG. 25, and the same elements are denoted by the same reference numerals and redundant description is omitted.

  The manufacturing method of Example 6 shown in FIG. 29 differs from the manufacturing method of Example 5 shown in FIG. 25 in that the LED row mounted on the wiring electrode row of the large circuit board 300 is the B / LED row. That is, there are two G and LED rows between the R and LED rows. That is, Yb1 in the first row of B • LEDs is sucked from the placement jig device 201 and placed on the first wiring electrode row D1 in the large circuit board 300. Next, the second and third wiring electrode rows D2 and D3 are sucked and placed from the placement jig apparatus 200 by the first Yg1 and the second Yg2 of the G • LED. Furthermore, Yr1 of the first row of R • LEDs is sucked from the placement jig device 202 and placed on the fourth wiring electrode row D4.

  Furthermore, the second row Yb2 of B / LED is sucked from the placement jig device 201 and placed on the fifth wiring electrode row D5. Next, the third and fourth rows of Yg3 and Yg4 of G / LED are sucked and placed on the sixth and seventh wiring electrode rows D6 and D7 from the placement jig apparatus 200. Further, the second row of R · LEDs Yr2 is sucked from the placement jig device 202 and placed on the eighth wiring electrode row D8.

  In FIG. 29, dotted lines surrounding one set of R • LED, G • LED, G • LED, and B • LED indicate a cutting range in which a color light emitting device to be described later is formed by cutting later. Further, after sealing with a transparent resin 310 shown in FIG. 30 and cutting and printing, as shown in the plan view of FIG. 31 and the cross-sectional view of FIG. 32, R.LED, G.LED, G.LED, B.LED The color light emitting device 330 including each semiconductor chip 2 can be mass-produced.

  As described above, according to the manufacturing method of the present invention, after a semiconductor wafer is cut into a matrix shape, a spacer member is inserted between each row of the cut semiconductor wafer in at least one axial direction, and a space between spacer rows is formed between each row. The semiconductor chip 2 is placed at the position of the wiring electrode for mounting the large-sized circuit board in units of columns by restricting the width to the width and forming wiring electrodes for mounting the large-sized circuit board in the expanded restricted width. can do. A desired color light emitting device can be mass-produced by arbitrarily selecting and arranging the light emitting color of the semiconductor chip 2 to be placed.

  Also, the interval between the columns of the semiconductor wafers may be restricted in advance to the width of the spacer member, or only the interval between the rows of the semiconductor wafers is restricted and the interval between the columns of the semiconductor wafers is adsorbed. You may make it regulate at the time of mounting by an apparatus.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and it is not necessary to perform all of them. Various modifications can be made within the scope of the contents described in the claims. It goes without saying that changes and omissions can be made.

1, 112 Semiconductor wafer 2, 2a, 2b, 2c, 2a, 2a, 2a3, 2a4,
DESCRIPTION OF SYMBOLS 101 Semiconductor chip 3 Dicing line 9 Expand sheet 9a Cutting part 50, 500 Alignment apparatus 51, 510 Positioning recessed part 60 Mounting base 61 Slight adhesive sheet 80 Vacuum suction sheet 81 Positioning recessed part 90, 900 Suction apparatus 91 Suction part main body 92 Alignment guide Part 93 concave part 94 convex part 95, 95p, 95n suction hole 109 adhesive film 111 suction collet 114 circuit board 200, 201, 202 placement jig device 300 large circuit board 310 transparent resin 320, 330 color light emitting device SK, SK1-SK9 alignment Squeegee SKs Spacer part SKc Cutting cutter part
X, X1 to X9 Semiconductor wafer row Y, Y1 to Y9 Semiconductor wafer column

Claims (7)

  In a method of manufacturing a semiconductor device in which a semiconductor wafer is cut and separated and arranged in a matrix, a step of cutting a semiconductor wafer deposited on an expanded sheet into a matrix, and at least one axial direction of the cut semiconductor wafer A step of inserting a spacer member between the rows to expand the space between the rows to the width of the spacer member, a step of holding the extended spaces in the one axial direction, and a semiconductor element disposed and held in the extended one axial direction A method for producing a semiconductor element, comprising the step of peeling the expanded sheet from the substrate.   In a method for manufacturing a semiconductor device in which a semiconductor wafer is cut and separated and arranged in a matrix, a step of cutting a semiconductor wafer deposited on an expanded sheet into a matrix, and a distance between each row in the X-axis direction of the cut semiconductor wafer Inserting a spacer member into the spacer to expand the space between the rows to the width of the spacer member, holding the expanded space between the rows in the X-axis direction, and inserting the spacer member between the columns in the Y-axis direction of the semiconductor wafer Expanding the distance between the columns to the width of the spacer member, maintaining the expanded space between the columns in the Y-axis direction, and separating the expanded sheet from the semiconductor elements arranged and held in a matrix. A method for manufacturing a semiconductor element, comprising:   3. The method of manufacturing a semiconductor device according to claim 2, wherein the spacer member is provided with a cutting cutter, and the expanded sheet is cut simultaneously with expanding the row and column intervals of the semiconductor wafer.   4. The step of holding between the rows in the X-axis direction and the step of holding between the columns in the Y-axis direction are steps of pressure-bonding the semiconductor element expanded by the spacer member to the slightly adhesive sheet. A method for manufacturing a semiconductor device.   5. The method of manufacturing a semiconductor element according to claim 2, wherein the step of peeling off the expanded sheet is performed by adsorbing and fixing semiconductor elements arranged in a matrix on an adsorption device. 6.   The step of expanding the rows in the X-axis direction and the step of expanding the columns in the Y-axis direction include an alignment guide including a concave portion that allows the spacer member to pass therethrough and a convex portion that holds the semiconductor chip in a comb shape. 6. The method of manufacturing a semiconductor element according to claim 2, wherein the method is performed using a member. The method of manufacturing a semiconductor element according to claim 6, wherein the convex portion for holding the semiconductor chip of the alignment guide member has a vacuum suction means.

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