JP5438534B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a structure of a semiconductor element having a configuration in which a p-type semiconductor layer and an n-type semiconductor layer are stacked on a support substrate, and a method for manufacturing the same.

  Group III nitride semiconductors are widely used as materials for light emitting elements such as blue and green LEDs (light emitting diodes) and LDs (laser diodes) because of their wide band gaps. In such a light emitting element, a p-type semiconductor layer (p-type layer) and an n-type semiconductor layer (n-type layer) are laminated by epitaxial growth. In the case of such a configuration, a structure in which electrical connection can be made directly to both the p-type layer and the n-type layer is necessary.

  In order to manufacture this structure with good quality and low cost, it is generally performed by epitaxially growing a p-type layer and an n-type layer on a growth substrate made of a material other than a group III nitride semiconductor. . In this case, in order to obtain a particularly good quality semiconductor layer, the growth substrate materials that can be used are limited. For example, gallium nitride (GaN), which is representative of a group III nitride semiconductor, is grown on a growth substrate made of SiC, sapphire, or the like by MOCVD (metal organic chemical vapor deposition) or HVPE (hydride vapor deposition). be able to. Here, in GaN, acceptor doping is more difficult than donor doping, and it is relatively difficult to obtain a high-quality p-type layer, particularly a high-conductivity p-type layer. For this reason, it is easy to increase the thickness of the n-type layer, but it is relatively difficult to increase the thickness of the p-type layer. Further, in order to obtain a good quality n-type layer and p-type layer on the same growth substrate, it is preferable to grow them sequentially in the order of the n-type layer and then the p-type layer on the growth substrate.

  On the other hand, in the actual operation of the light emitting element, a large current is passed through the n-type layer and the p-type layer, and the amount of heat generated thereby increases. The substrate that supports the n-type layer and the p-type layer also performs this heat dissipation.

  As described above, in the LED and LD, the material of the growth substrate greatly affects the characteristics. Here, the optimum growth substrate for obtaining a high-quality n-type layer and p-type layer is not necessarily the optimum substrate for device operation.

  Also, how to make electrical connection between the p-type layer and the n-type layer depends on the growth substrate. For example, in a configuration in which an n-type layer and a p-type layer are sequentially formed on a growth substrate, if the growth substrate is a conductive material (for example, SiC), electrical connection to the n-type layer through the growth substrate It is possible to take On the other hand, when the growth substrate is an insulator (for example, sapphire), it is difficult to make an electrical connection to the n-type layer through the growth substrate.

  FIG. 6 is a sectional view of an example of an LED having a configuration in which sapphire is used as a growth substrate and an n-type layer and a p-type layer are formed thereon. In this structure, an n-type GaN layer (n-type layer) 93 and a p-type GaN layer (p-type layer) 94 are sequentially formed on a growth substrate 91 via a buffer layer 92 by epitaxial growth. A thin p-side electrode 95 is formed on the p-type GaN layer 94. Here, in this LED, light is mainly extracted upward from the surface of the p-type GaN layer 94, and this light is emitted through the thin p-side electrode 95. Since it is difficult to increase the conductivity of the p-type GaN layer 94, the p-side electrode 95 is formed over almost the entire surface of the p-type GaN layer 94. The electrical connection to the p-side electrode 95 is performed by using, for example, a bonding wire through a thicker p-side pad electrode 96 formed on a part of the p-side electrode 95 (p-type GaN layer 94). Is called. However, since light is blocked by the thick p-side pad electrode 96, the p-side pad electrode 96 is partially formed on this surface so as to be able to connect a bonding wire.

  In the region on the right side in the drawing, this structure is partially dug by etching from the p-type GaN layer 94 side to the middle of the n-type GaN layer 93, and the surface of the n-type GaN layer 93 is exposed to the exposed surface. A side electrode 97 is formed. The electrical connection to the n-side electrode 97 is performed by, for example, connecting a bonding wire to the n-side electrode 97 in the same manner as on the p-side pad electrode 96.

  In this structure, when viewed from the substrate (growth substrate 91), electrical connection to the n-side electrode 97 (n-type GaN layer 93) and electrical connection to the p-side pad electrode 96 (p-type GaN layer 94) are performed. It can be taken from the same side (upper side in FIG. 6). The growth substrate 91 is used as a support substrate for the LED as it is, but the growth substrate 91 does not serve as a current path, and therefore conductivity is not required. For this reason, as the growth substrate 91, sapphire or the like from which a high quality n-type GaN layer 93 and p-type GaN layer 94 can be obtained is particularly preferably used.

  Here, in the case of the element having the structure shown in FIG. 6, the surface of the p-type GaN layer 94 having low conductivity is the light emitting surface. For this reason, the electric resistance between the p-side pad electrode 96 having a small area and the p-type GaN layer 94 is high, and the light emission efficiency is lowered by the presence of this electric resistance.

  As a form different from the structure of FIG. 6, Patent Document 1 describes a light-emitting element having a structure in which an n-type layer is disposed on the surface and a manufacturing method thereof. In this manufacturing method, after an n-type layer, a p-type layer, and a p-side electrode are sequentially formed on a sapphire substrate, a conductive substrate is newly bonded to the p-side electrode side as a support substrate. Thereafter, the sapphire substrate used as the growth substrate is removed by laser lift-off, and an n-side electrode is formed on the exposed n-type layer surface.

  According to this technique, by using sapphire as a growth substrate and sequentially forming an n-type layer and a p-type layer thereon, a high-quality n-type layer and a p-type layer can be obtained, and high luminous efficiency can be obtained. Can be obtained. On the other hand, in an actual LED, since it is possible to use a support substrate made of another material that is conductive and whose thermal conductivity and thermal expansion coefficient are optimized, high heat dissipation and reliability can also be obtained. Can do. In this case, electrical connection to the p-side electrode (p-type layer) is made from the back side through a conductive support substrate. On the other hand, the electrical connection to the n-side electrode (n-type layer) is taken from the surface side of the n-type layer on the opposite side. That is, unlike the structure of FIG. 6, in this case, the electrical connection to each layer is taken from different sides.

Japanese Patent Laid-Open No. 2006-324685

  However, when the electrical connection to the n-type layer and the electrical connection to the p-type layer are taken from different surfaces as in the technique described in Patent Document 1, a plurality of LED elements are connected side by side. This complicates the wiring structure and wiring connection method. For example, when forming the structure which arranged the some LED element in series, it is necessary to connect the wiring in the surface of a different side. To realize such a configuration, it is clear that the connection structure becomes complicated.

  On the other hand, in the case of the element having the structure of FIG. 6, the electrical connection to the n-type GaN layer 93 and the electrical connection to the p-type GaN layer 94 can be taken from the same side when viewed from the substrate side. This connection can be made simply. However, as described above, it is difficult to obtain high luminous efficiency in this case.

  That is, it is difficult to obtain a semiconductor element (light emitting element) having a simple light emitting structure and high light emission efficiency.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
In the semiconductor element manufacturing method of the present invention, a stacked body including at least an n-type semiconductor layer and a p-type semiconductor layer is formed on one main surface of a support substrate, and the n-type semiconductor layer and the p-type semiconductor layer are formed. A method for manufacturing a semiconductor device , wherein each has a structure that can be electrically connected to each other from the direction of the one main surface side, and light emission is extracted from the side of the stacked body on which the n-type semiconductor layer is formed. An epitaxial growth step of obtaining a stacked body in which the n-type semiconductor layer and the p-type semiconductor layer are sequentially formed on a growth substrate via a buffer layer that is a lift-off metal layer or metal nitride layer ; by etching a part of the body from the side of the p-type semiconductor layer to the growth substrate or the buffer layer is exposed, forming a isolation trench is divided into two kinds of regions having different areas of the laminate A separation groove forming step, a p-side electrode forming step for sequentially forming a p-side electrode and a first conductive bonding layer on the p-type semiconductor layer, and a second conductivity on the main surface of the support substrate. A support substrate bonding pre-process for forming a bonding layer; and a bonding process for bonding the laminate and the support substrate by bonding the first conductive bonding layer and the second conductive bonding layer; The growth substrate is lifted off to remove the buffer layer by infiltrating an etchant through the separation groove to dissolve the buffer layer and remove the buffer layer, thereby exposing the n-type semiconductor layer surface. A step of forming an n-side electrode on the exposed surface of the n-type semiconductor layer in the stacked body in the large-area region of the two types of regions, and The laminated body in the region of the smaller area To cover the surface of the second conductive bonding layer exposed to said supporting substrate, characterized by comprising a p-side pad electrode forming step of forming a p-side pad electrode.
In the method for manufacturing a semiconductor element of the present invention, the support substrate is any one of an insulating substrate, a metal substrate, a semiconductor substrate, and a metal ceramic bonding substrate .
In the method for manufacturing a semiconductor device of the present invention, the n-type semiconductor layer and the p-type semiconductor layer are made of a group III nitride semiconductor.
The method for manufacturing a semiconductor device according to the present invention is characterized in that an active layer is formed between the n-type semiconductor layer and the p-type semiconductor layer in the epitaxial growth step.
The semiconductor element of the present invention is manufactured by the method for manufacturing a semiconductor element .
The semiconductor element of the present invention is a light emitting element.

  Since the present invention is configured as described above, a simple wiring structure can be used and a semiconductor element having high luminous efficiency can be obtained.

It is process sectional drawing which shows the manufacturing method of the semiconductor element used as embodiment of this invention. It is a perspective view of the structure which connected the light emitting element manufactured by the manufacturing method of the semiconductor element used as embodiment of this invention in series. It is process sectional drawing which shows the modification of the manufacturing method of the semiconductor element used as embodiment of this invention. It is the result of having measured the relationship between the forward voltage Vf and the drive current If in an Example and a comparative example. It is the result of having measured the relationship between the emitted light intensity and the drive current If in an Example and a comparative example. It is sectional drawing which shows the structure of an example of the conventional light emitting element.

  Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. The n-type and p-type semiconductor layers used in this semiconductor element are obtained by epitaxial growth on a growth substrate. However, in a semiconductor device actually manufactured, this growth substrate is removed, and a support substrate different from the growth substrate is connected to the side opposite to the side where the growth substrate was present. The two electrodes connected to the n-type and p-type semiconductor layers are both taken out from the same side of the semiconductor element.

  FIG. 1 is a process sectional view showing this manufacturing method. Hereinafter, a description will be given based on this figure. Here, a case where a light emitting diode (LED) made of gallium nitride (GaN) is manufactured as the semiconductor element will be described. This LED uses light emission in a laminate of a GaN n-type layer and a p-type layer. In addition, in FIG. 1, the configuration of only one LED element is shown, but actually, a plurality of LEDs can be formed on a single support substrate, and these LEDs are connected in series or in parallel. Can be used.

  First, as shown in FIG. 1A, the buffer layer 12 is formed on the growth substrate 11. As the growth substrate 11, a sapphire single crystal ((0001) substrate) is particularly preferably used as in the case of Patent Document 1. Moreover, as the buffer layer 12 on this, metal chromium (Cr) with a film thickness of, for example, about 40 nm can be used as described in, for example, JP-A-2009-54888. The buffer layer 12 can be formed by sputtering, vacuum deposition, or the like.

  Next, as described in Japanese Patent Application Laid-Open No. 2009-54888, in this state, a nitriding treatment, for example, a step of raising the temperature to 1040 ° C. or higher in an ammonia atmosphere is performed. Thereby, as shown in FIG. 1B, the surface of the buffer layer (metal layer: Cr layer) 12 is nitrided to become a chromium nitride layer (metal nitride layer: CrN layer) 13. The thickness of the CrN layer 13 can be set by adjusting the processing time, temperature, and the like.

  Next, as described in JP 2009-54888 A, an n-type GaN layer (n-type semiconductor layer: n-type layer) 21 and a p-type GaN layer (p-type semiconductor layer: p) are formed on the CrN layer 13. The mold layer 22 is sequentially formed (epitaxial growth process). This film formation is performed, for example, by a hydride vapor phase epitaxy (HVPE method). The n-type layer 21 is doped with an impurity serving as a donor, and the p-type layer 22 is doped with an impurity serving as an acceptor. By this epitaxial growth step, a stacked body 20 including an n-type layer 21 and a p-type layer 22 is formed, and a GaN pn junction is formed therein (FIG. 1C). As described in JP 2009-54888 A and the like, the n-type layer 21 and the p-type layer 22 with few crystal defects can be grown on the CrN layer 13. Therefore, the GaN in the laminate 20 can be made high quality, and the emission intensity can be increased. In GaN, formation of the n-type layer 21 (donor doping) is easier than formation of the p-type layer 22 (acceptor doping). Therefore, the p-type layer 22 is thinner than the n-type layer 21, and the conductivity of the p-type layer 22 is lower than the conductivity of the n-type layer 21.

  Next, for this structure, as shown in FIG. 1D, a separation groove 30 having a depth reaching the surface of the growth substrate 11 from the upper side (p-type layer 22 side) in FIG. 1 is formed. (Separation groove forming step). Thereby, the stacked body 20 is divided on the substrate 11. In FIG. 1 (d), a cross section in one direction is shown, but the separation groove 30 is also formed in a different direction, and a stacked body 20 of a plurality of regions surrounded by the separation groove 30 is formed. The In FIG. 1D, the first laminated body 25 corresponding to the region having a larger area is divided on the left side, and the second laminated body 26 corresponding to the region having a smaller area is divided on the right side. Is done. The separation groove 30 can be formed, for example, by dry etching using a photoresist as a mask. In dry etching, it is possible to increase the selectivity of GaN constituting the stacked body 20, Cr, CrN constituting the buffer layer 12 and CrN layer 13, and sapphire. Is easy to do. It is sufficient that the separation groove 30 penetrates the n-type layer 21, and either the buffer layer 12 or the CrN layer 13 may be exposed on the bottom surface of the separation groove 30. In addition, as a method for forming the separation groove 30, a method other than dry etching can be used as long as this method can be realized. Since the growth substrate 11 itself is not divided immediately after the separation groove forming step, it is easy to handle this structure together with the growth substrate 11.

  Next, as shown in FIG. 1E, a p-side electrode 41 and a first conductive bonding layer 42 are sequentially formed on the entire surface of the p-type layer 22 existing in the uppermost surface in this state (p-side). Electrode forming step). The p-side electrode 41 is formed of a material capable of making ohmic contact with the p-type layer 22 and has, for example, a multilayer structure of nickel (Ni) and gold (Au), and the thickness thereof is about 5 nm and 20 nm, respectively. Can do. However, unlike the structure of FIG. 6, in this structure, the p-side electrode 41 does not become a light transmitting layer, so that it can be thickened. The first conductive bonding layer 42 is formed of, for example, a multilayer structure of gold (Au) or Au and tin (Sn). Both the p-side electrode 41 and the first conductive bonding layer 42 can be formed by sputtering or vacuum evaporation. In order to improve the ohmic property between the p-side electrode 41 and the p-type layer 22, it is preferable to perform a heat treatment at about 550 ° C. after forming the p-side electrode 41. It is also possible to change the order of the p-side electrode forming step and the separation groove forming step.

  The p-side electrode 41 may be made of Ni / Au or Co / Au, and these may be thinned to have translucency. Further, by using a transparent material such as ITO (Indium-Tin-Oxide), IZO (Indium-Zinc-Oxide), or IMO (Indium-Molybdenum-Oxide) for the p-side electrode 41, it is possible to provide translucency. It is. In such a case, a reflection layer is formed on the upper layer of the p-side electrode 41 (between the first conductive bonding layer 42), so that the light transmitted through the p-side electrode 41 is reflected and emitted from the opposite side. It is also possible to increase the luminous efficiency. In this case, the reflective layer can be formed of rhodium (Rh), ruthenium (Ru), silver (Ag), or the like.

  On the other hand, as shown in FIG. 1F, a second conductive bonding layer 51 is formed on one main surface of the support substrate 50 prepared separately from the above structure (pre-support substrate bonding step). As the support substrate 50, an arbitrary substrate having sufficient mechanical strength and high thermal conductivity can be used, and its electric conductivity is also arbitrary. For example, a single crystal silicon (Si) substrate which is a kind of semiconductor substrate can be used. The conductive bonding layer 51 is formed of a conductive material that can be bonded to the first conductive bonding layer 42 by thermocompression bonding. For example, Au, which is the same as the first conductive bonding layer 42, or Au and Sn is formed. It is formed with a multilayer structure. Note that a layer (for example, a Ti layer) for enhancing the adhesion may be inserted between the support substrate 50 and the second conductive bonding layer 51. As will be described later, the first stacked body 25 and the second stacked body 26 are joined on the support substrate 50 in a form with a separation groove 30 between them. The size of the support substrate 50 is appropriately set so that this step is realized.

  Next, as shown in FIG. 1 (g), the structure of FIG. 1 (f) and the structure of FIG. 1 (e) are combined with the second conductive bonding layer 51 and the first conductive bonding layer 42. And pressure bonding at high temperature (bonding process). The temperature at this time can be, for example, about 300 ° C. as a temperature at which they can be joined. In this case, the first stacked body 25 and the second stacked body 26 are not affected by this bonding. Through this step, the first stacked body 25 and the second stacked body 26 are bonded to the support substrate 50 via the p-side electrode 41, the first conductive bonding layer 42, and the second conductive bonding layer 51. Is done.

  Next, in the state after bonding, the buffer layer 12 and the CrN layer 13 are removed by chemical treatment (lift-off process). Specifically, the wet etching process using a mixed solution of perchloric acid and 2 ceric ammonium nitrate does not affect the stacked body 20 (GaN) and the like as shown in FIG. Only the layer 12 and the CrN layer 13 can be selectively removed. This wet etching proceeds from the location of the separation groove 30. This step is the same as the step known as chemical lift-off described in JP2009-54888A.

  Therefore, after the lift-off process, as shown in FIG. 1 (i), the n-type layer 21 comes to the surface side, and the first laminated body 25 and the second laminated body 26 are formed on the support substrate 50. Each is joined.

  In this state, as shown in FIG. 1 (j), an n-side electrode 61 is formed on a part of the first stacked body 25 on the n-type layer 21 (n-side electrode forming step). As the n-side electrode 61, for example, a multilayer structure of titanium (Ti) and aluminum (Al) can be used, and the respective thicknesses are, for example, 20 nm and 300 nm. In addition, since the light emission of the location where the n-side electrode 61 is formed in the first stacked body 25 is blocked, the area of the n-side electrode 61 is appropriately set from the viewpoint of the resistance between the n-type layer 21 and the light emission efficiency. Is done. In order to partially form the n-side electrode 61 on the surface of the n-type layer 21, for example, the photoresist is removed after forming the material of the n-side electrode 61 on the entire surface after forming the photoresist as a mask (see FIG. Lift-off method). Alternatively, after forming the material of the n-side electrode 61 on the entire surface, the electrode material may be etched after forming with the photoresist as a mask (etching method). Note that, similarly to the p-side electrode forming step, heat treatment may be performed after the n-side electrode 61 is formed. In addition, before forming the n-side electrode 61, a process for adjusting the state of the surface of the n-type layer 21 may be performed.

  Finally, as shown in FIG. 1 (k), a p-side pad electrode 62 is formed on a part of the second conductive bonding layer 51 so as to cover the entire second stacked body 26 (p-side pad electrode). Forming step). As the p-side pad electrode 62, a material having high adhesion to these structures can be used. For example, titanium (Ti) / platinum (Pt) / gold (Au), nickel (Ni) / Au, Ti / A laminated structure such as Au can be used. The thickness is such that wire bonding can be performed thereon. In order to partially form the p-side pad electrode 62, as with the n-side electrode 61, a lift-off method or an etching method can be used.

  Finally, an LED (semiconductor element) having the structure shown in FIG. The surface of the n-side electrode 61 and the surface of the p-side pad electrode 62 can be wire-bonded and can be electrically connected to an external wiring terminal. By energizing between the n-side electrode 61 and the p-side pad electrode 62, the first stacked body 25 can emit light.

  1 shows one LED element, a plurality of the above structures can be formed on a single support substrate 50. FIG. In this case, it is possible to separate each support chip by dicing the support substrate 50 thereafter. At this time, it is possible to adopt a configuration in which a plurality of LEDs on the same chip are arranged.

  At this time, in this LED, since both the n-side electrode 61 and the p-side pad electrode 62 are on the same side (the side opposite to the support substrate 50), Connection between is easy. For example, as described in Patent Document 1, in the configuration in which one electrode is taken out from the support substrate side, it is difficult to take a configuration in which a plurality of LEDs are connected in series unless the support substrate is divided and connected. On the other hand, in the above structure, it is easy to form a plurality of LEDs on a single support substrate 50 and connect them in series or in parallel.

  In addition, when the area of the electrode provided on the light emitting surface side is large, light emission is blocked by this electrode, so that the area is preferably small. However, when the conductivity of the layer to which the electrode is connected is low, the electrical resistance of this portion increases when the area is reduced, thereby reducing the light emission efficiency. On the other hand, since the electrode formed on the side opposite to the surface does not block light emission, the electrode can be formed on the entire surface. As described above, since the conductivity of the n-type layer 21 is generally higher than that of the p-type layer 22, from this point of view, the n-type layer 21 is on the surface side and the p-type layer 22 is on the opposite side. A configuration is preferred. In this configuration, by reducing the electrode area on the surface side (light emission extraction side) and increasing the electrode area on the side opposite to the surface, light emission is not blocked and electric resistance can be lowered. Is possible.

  On the other hand, in the epitaxial growth of GaN, when the n-type layer 21 and then the p-type layer 22 are formed on the growth substrate 11, it is possible to increase their crystallinity and obtain high luminous efficiency. According to the above manufacturing method, high-quality n-type layer 21 and p-type layer 22 can be obtained by performing epitaxial growth in this order, and at the same time, n-type layer 21 can be provided on the light emitting surface side, The area of the electrode 61 can be reduced. Therefore, an LED having high luminous efficiency can be obtained.

  In the structure of FIG. 1 (k), the heights of the n-side electrode 61 and the p-side pad electrode 62 to which wire bonding is applied from the support substrate 50 are substantially equal. Therefore, the bonding height adjustment in the wire bonder to be used is facilitated, and the bonding work is facilitated. In particular, as described above, even when a plurality of LEDs are formed on the same support substrate 50 and are connected in parallel or in series, this connection can be easily performed using wire bonding. FIG. 2 is a perspective view of an example of a configuration in which three LEDs having the above-described configuration are formed on a single support substrate 50 and these are connected in series using bonding wires 70. Such a configuration can be realized because the n-side electrode 61 and the p-side pad electrode 62 are formed on the same side with respect to the support substrate 50 (insulating or high-resistance substrate). Even when electrical connection is made by a method other than wire bonding, the n-side electrode 61 and the p-side pad electrode 62 have almost the same height, so that the connection is easy.

  FIG. 3 is a process cross-sectional view of a manufacturing method that is a modification of the above manufacturing method. Since this manufacturing method is the same as the manufacturing method described above up to the epitaxial growth step, description thereof is omitted. FIG. 3 shows only the process after the epitaxial growth process, and FIGS. 3A to 3H correspond to FIGS. 1D to 1K.

  In FIG. 3A, a groove forming step is performed in the same manner as in FIG. 1D to form a plurality of separation grooves 30 (separation groove forming step). However, in the example of FIG. 1, the first stacked body 25 and the second stacked body 26 are provided in one chip, but here, only the stacked body 27 is formed, and this is a region that emits light.

  Next, as shown in FIG. 3B, a p-side electrode 41 and a first conductive bonding layer 42 are sequentially formed on the surface of the p-type layer 22 existing on the uppermost surface in this state (p-side). Electrode forming step). This step is the same as in FIG. Further, as shown in FIG. 3C, a second conductive bonding layer 51 is formed on one main surface of the support substrate 50 prepared separately from the above structure (pre-support substrate bonding step). This process is also the same as in FIG. In the p-side electrode forming step, the reflective layer can be formed on the p-side electrode 41 as in the case described above.

  Next, as shown in FIG. 3 (d), the structure of FIG. 3 (b) and the structure of FIG. 3 (c) are combined with the second conductive bonding layer 51 and the first conductive bonding layer 42. And pressure bonding at high temperature (bonding process). This step is the same as that in FIG. 1G, except that only the laminate 27 is bonded.

  Next, as shown in FIG. 3E, the buffer layer 12 and the CrN layer 13 are removed by chemical treatment (lift-off process). This step is the same as in FIG. Therefore, after this step, as shown in FIG. 3 (f), the laminate 27 is bonded onto the support substrate 50 with the n-type layer 21 coming on the surface side.

  In this state, as shown in FIG. 3G, the n-side electrode 61 is formed on a part of the stacked body 27 on the n-type layer 21 (n-side electrode forming step). This step is the same as in FIG.

  Finally, as shown in FIG. 3 (h), the p-side pad electrode 62 is formed in a part of the portion where the second conductive bonding layer 51 is exposed except the portion where the stacked body 27 is bonded (see FIG. 3H). p-side pad electrode forming step). This process is the same as that in FIG. 1K except that the second stacked body 26 is not provided. The region where the p-side pad electrode 62 is formed becomes a part of the region where the separation groove 30 is formed.

  The structure shown in FIG. 3H is formed by the above manufacturing method. In this configuration, although the heights of the n-side electrode 61 and the p-side pad electrode 62 are not the same, as in the LED manufactured by the manufacturing method of FIG. The electrical connection between these elements is easy.

  1 and 3, in the lift-off process, chemical lift-off is used in order to separate the growth substrate 11 by removing the buffer layer 12 and the like. However, any other method can be used as long as the growth substrate 11 can be separated by removing the buffer layer 12 and the like and the surface of the n-type layer 21 can be exposed. Specifically, laser lift-off as described in Patent Document 1 can be used. However, it is particularly preferable to use a chemical lift-off that is easy to process, batch-processable, and highly productive. As the material of the buffer layer 12, any material other than Cr or CrN can be used as long as it can form a high-quality n-type layer 21 and the like on the same and at the same time be removed in the lift-off process. It is possible to select.

  Further, as the growth substrate 11, in addition to sapphire, a group III nitride semiconductor (n-type layer 21, p-type layer 22) such as high-quality GaN or AlGaN can be grown via the buffer layer 12 or the like. If so, it is possible to use other materials such as an AlN template or SiC.

  In addition, any material other than silicon can be used for the support substrate 50. However, since the support substrate 50 serves as a mechanical support substrate for the manufactured LED and at the same time serves as a heat dissipation substrate, it preferably has high mechanical strength and high thermal conductivity. In the above structure, electrical conduction between the p-side electrode 41 (p-type layer 22) and the p-side pad electrode 62 is performed by the first conductive bonding layer 42, the second conductive bonding layer 51, and the like. Therefore, the presence or absence of conductivity of the support substrate 50 is irrelevant to the operation of the LED. Therefore, the material of the support substrate 50 can be selected from a wide range of materials, and various insulating substrates, metal substrates, and semiconductor substrates can be used. A metal ceramic bonded substrate in which metal wiring is previously formed on an insulating ceramic substrate having high mechanical strength and thermal conductivity can also be used.

  The form of the support substrate 50 is also arbitrary. For example, in the case of using an insulating substrate, a metal substrate, or a semiconductor substrate, a large-diameter wafer is used as the support substrate 50, and the support substrate 50 is formed after forming the structure of FIGS. 1 (k) and 3 (h). It can be divided into individual chips. On the other hand, for example, when a metal ceramic bonding substrate is used, a submount substrate having a size corresponding to one chip in advance can be used.

In the above example, the laminate is composed of the n-type layer 21 and the p-type layer 22 both made of GaN. However, it is clear that the same effect can be obtained even in other cases. For example, instead of a simple pn junction LED, an LED or LD (laser diode) having a structure in which a multiple quantum well structure serving as an active layer is provided between an n-type layer and a p-type layer can be manufactured in the same manner. it is obvious. At this time, the n-type layer and the p-type layer are not GaN, but other group III nitride semiconductors such as Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1), and the values of a and b in each layer may be different. In this case, in the epitaxial growth step, the n-type layer 21 is formed on the growth substrate 11, the active layer is formed thereon, and then the p-type layer 22 is formed.

(Example)
Actually, an LED was manufactured by the process shown in FIG. 1, and the light emission characteristics of the single unit were compared with those of a conventional LED.

Here, the cross-sectional structure of an LED having a conventional structure as a comparative control is as shown in FIG. Example (structure of FIG. 1 (k)) and comparative example in which n-type layer 21 and p-type layer 22 having the same configuration are grown on the same growth substrate 11, buffer layer 12, and CrN layer 13 Regarding (the structure of FIG. 6), the relationship between the forward voltage V _f and the drive current _{If and} the relationship between the light emission intensity and the drive current _If were measured. Here, the light emission intensity is shown as the output P ₀ of the light receiving element that receives this light emission.

The relationship between the forward voltage V _f and the driving current I _f in the Examples and Comparative Examples 4, respectively in Figure 5 the relationship of the luminous intensity drive current I _f. If the same I _f is, V _f is low in Example (4), and the emission intensity is high (Figure 5). Therefore, it was confirmed that the luminous efficiency in the example was higher than that in the comparative example.

11, 91 Growth substrate 12, 92 Buffer layer (metal layer: Cr layer)
13 Chromium nitride layer (metal nitride layer: CrN layer)
20, 27 Laminate 21, 93 n-type GaN layer (n-type semiconductor layer: n-type layer)
22, 94 p-type GaN layer (p-type semiconductor layer: p-type layer)
25 First laminated body 26 Second laminated body 30 Separation groove 41, 95 p-side electrode 42 First conductive bonding layer 50 Support substrate 51 Second conductive bonding layer 61, 97 n-side electrode 62, 96 p Side pad electrode 70 Bonding wire

Claims (6)

A laminate including at least an n-type semiconductor layer and a p-type semiconductor layer is formed on one main surface of a support substrate, and the one main surface side with respect to each of the n-type semiconductor layer and the p-type semiconductor layer A method of manufacturing a semiconductor element having a structure that can be electrically connected to each other from the direction of the above, wherein light emission is extracted from the side of the stacked body on which the n-type semiconductor layer is formed ,
An epitaxial growth step of obtaining a stacked body in which the n-type semiconductor layer and the p-type semiconductor layer are sequentially formed on a growth substrate via a buffer layer that is a metal layer or a metal nitride layer that can be lifted off;
Separation that forms part of the stacked body from the p-type semiconductor layer side until the growth substrate or buffer layer is exposed, thereby forming separation grooves that divide the stacked body into two types of regions having different areas A groove forming step;
A p-side electrode forming step of sequentially forming a p-side electrode and a first conductive bonding layer on the p-type semiconductor layer;
A supporting substrate bonding pre-process for forming a second conductive bonding layer on the main surface of the supporting substrate;
A bonding step of bonding the stacked body and the support substrate by bonding the first conductive bonding layer and the second conductive bonding layer;
A lift-off process in which the growth substrate is lifted off to expose the surface of the n-type semiconductor layer by infiltrating an etching solution through the separation groove to dissolve the buffer layer and remove the buffer layer. When,
An n-side electrode forming step of forming an n-side electrode on the exposed surface of the n-type semiconductor layer in the stacked body in the larger area of the two types of regions ;
A p-side pad electrode is formed on the surface of the second conductive bonding layer exposed on the support substrate so as to cover the stacked body in the region having the smaller area of the two types of regions. A pad electrode forming step;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor element according to claim 1 , wherein the support substrate is one of an insulating substrate, a metal substrate, a semiconductor substrate, and a metal ceramic bonding substrate. The method according to claim 1 or 2 wherein the n-type semiconductor layer and the p-type semiconductor layer is characterized in that it is composed of a group III nitride semiconductor. In the epitaxial growth step, between the n-type semiconductor layer and the p-type semiconductor layer, the manufacture of semiconductor devices according to any one of claims 1, wherein the forming the active layer to claim 3 Method. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 4 . The semiconductor device according to claim 5 , wherein the semiconductor device is a light emitting device.

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