JP5429590B2 - Halftone mask - Google Patents

Description

  The present invention relates to a halftone mask, a manufacturing method thereof, and an active matrix display device.

  Liquid crystal display (Liquid Crystal Display) devices and OEL (Organic Electro-Luminescence) display devices are examples of active matrix display devices. In manufacturing such an active matrix display device, a method of reducing the number of photolithography processes using a reflow resist pattern is used.

  Japanese Patent Application Laid-Open No. 2002-334830 discloses a technique for forming a reflow resist pattern by reflowing resist patterns having different film thicknesses. This resist pattern is formed using a halftone mask as an exposure mask (see Patent Document 1).

  The reflow treatment method includes a heat reflow treatment method and a chemical solution reflow treatment method. The degree of spread of the resist by the chemical solution reflow process is larger than the heat reflow process. Therefore, the chemical solution reflow process can easily integrate adjacent resist patterns. Further, the chemical solution reflow process has stronger adhesion between the resist and the base than the heat reflow process.

  Such a reflow resist pattern is used for patterning an amorphous silicon (a-Si) film such as a thin film transistor (TFT) of an LCD device. Hereinafter, the “amorphous silicon film pattern” is referred to as an “a-Si pattern”. The a-Si pattern exists in the TFT region (the lower region of the source and drain electrodes, the upper region of the gate electrode, etc.) and the data line region (the lower region of the data line and the data line terminal, etc.).

  In the reflow resist pattern disclosed in Patent Document 1, the a-Si pattern width of the TFT region and the data line region is larger than the widths of the drain electrode, the source electrode, the data line, and the like (FIG. 5 to FIG. 5 of Patent Document 1). 7), the parasitic capacitance between the TFT region and the gate electrode increases. In addition, since the a-Si pattern width in the data line region is increased, the parasitic capacitance between the data line and the pixel electrode is also increased. Such an increase in parasitic capacitance causes a signal transmission delay and a decrease in TFT switching speed, resulting in display unevenness in the LCD device.

  A method of suppressing an increase in the a-Si pattern width in a data line region using a halftone mask 200 as shown in FIGS. 19A and 19B is known. FIG. 19A is a top view corresponding to the TFT region, and FIG. 19B is a cross-sectional view taken along line X1-X1 in FIG.

  The halftone mask 200 shown in FIGS. 19A and 19B includes first mask patterns 221 and 222 and second mask patterns 241 and 242. The first mask pattern 221 is a mask pattern corresponding to the drain region near the TFT channel, and the second mask pattern 241 is a mask pattern corresponding to the drain region away from the TFT channel. The first mask pattern 222 is a mask pattern corresponding to the source region near the TFT channel, and the second mask pattern 242 is a mask pattern corresponding to the source region far from the TFT channel.

  FIG. 19C shows a cross-sectional view of resist patterns 221 a, 222 a, 241 a, and 242 a formed using this halftone mask 200. Note that a positive resist is used as the resist. The resist patterns 221a, 222a, 241a, and 242a are formed on the substrate 250 on which the a-Si film 251 and the metal film 252 are stacked.

  As shown in FIG. 19C, the resist patterns 241a and 242a are formed corresponding to the second mask patterns 241 and 242, and the resist patterns 221a and 222a correspond to the first mask patterns 221 and 222. Formed. The resist patterns 241a and 242a formed by the second mask patterns 241 and 242 are thinner than the resist patterns 221a and 222a formed by the first mask patterns 221 and 222. The metal film 252 is etched using the resist patterns 221a, 222a, 241a, and 242a as etching masks.

  FIG. 19D is a cross-sectional view of a metal film pattern 252 a formed by etching the metal film 252. The reflow process is performed on the resist patterns 221a, 222a, 241a, and 242a after the metal film pattern 252a is formed.

  FIG. 19E is a cross-sectional view of the reflow resist patterns 221b, 222b, 241b, and 242b formed by the reflow process. Since the thick film resist patterns 221a and 222a are greatly expanded by the reflow process, the reflow resist patterns 221b and 222b are integrated. On the other hand, since the thin resist patterns 241a and 242a are only slightly expanded by the reflow process, the shape change is small.

  FIG. 19F is a cross-sectional view of the a-Si pattern 251a obtained by etching the a-Si film 251 using the reflow resist patterns 221b, 222b, 241b, and 242b as etching masks. As described above, since the shape change of the resist patterns 241 and 242 is small even when the reflow process is performed, an increase in the width dimension of the a-Si pattern 251a can be suppressed (see FIGS. 8 to 11 of Patent Document 1).

JP 2002-334830 A

  However, the a-Si pattern 251a formed corresponding to the second mask patterns 241 and 242 has a problem that the width dimension varies. Such a variation in the width dimension deteriorates the performance and reliability of the active matrix display device.

  This is because, as the film thickness is reduced, the variation in the width dimension of the resist pattern is likely to increase due to exposure light wraparound. Further, the edges of the thin resist patterns 241a and 242a are easily scraped in the process of etching the metal film 252, and the edge of the resist pattern is easily retracted in a drying process or the like.

  SUMMARY OF THE INVENTION The main object of the present invention is to provide a halftone mask, a manufacturing method thereof, and an active matrix display device capable of forming a pattern with an accurate dimension on a substrate.

  In order to achieve the above object, the present invention provides a halftone mask used for forming resist patterns having different film thicknesses, the first mask pattern used for forming the first resist pattern, and the first resist pattern. A second mask pattern used for forming a second resist pattern having a thinner thickness, and a resist pattern having a thicker film thickness than the second resist pattern, formed on at least a part of the edge region of the second mask pattern And a third mask pattern used in the above.

  According to the present invention, the third mask pattern is provided in addition to the first mask pattern for forming the thick resist film and the second mask pattern for forming the thin resist film. A pattern having an accurate dimension can be formed thereon.

  An embodiment of the present invention will be described. In the following embodiments, a positive halftone mask that exposes a positive resist will be described as an example. However, the present invention can also be applied to a negative halftone mask.

  Further, when defining the shape and dimensions of the mask pattern and resist pattern, they are described as “width”, “thickness”, “rectangular shape”, “linear shape”, and the like. “Width” is a dimension in the planar direction of the substrate, and “Thickness” is a dimension in the vertical direction of the substrate. “Rectangular shape” and “linear shape” mean shapes when the substrate is viewed from above.

  A first embodiment of the present invention will be described. FIG. 1A shows a top view of the halftone mask 500, and FIG. 1B shows an X2-X2 cross-sectional view of FIG.

  The halftone mask 500 includes a first mask pattern 502, a second mask pattern 503 having a higher transmittance than the first mask pattern 502, and a third mask pattern 504. The third mask pattern 504 is a linear mask pattern formed in at least a part of the edge region of the second mask pattern 503.

  Note that the edge region is a region corresponding to a region where dimensional variation is desired to be suppressed. Examples of such a region include a region along the edge of the second mask pattern 503 and a region that enters a predetermined distance pattern from the edge. When the third mask pattern 504 is formed along the edge of the second mask pattern 503, the edge of the second mask pattern 503 overlaps with the edge of the third mask pattern 504.

  Next, a process of forming a pattern on the substrate 510 using such a halftone mask 500 will be described with reference to FIGS. 2 (a) to 2 (e).

  Two kinds of etching layers are formed on the substrate 510, and a resist 513 is further applied. For convenience of explanation, the two types of etching layers are an a-Si film 511 and a metal film 512.

  First, exposure using the halftone mask 500 is performed (FIG. 2A). As a result, a first resist pattern 502a, a second resist pattern 503a, and a third resist pattern 504a corresponding to the first mask pattern 502, the second mask pattern 503, and the third mask pattern 504 are formed. (FIG. 2 (b)).

  In the partially enlarged view shown in FIG. 2A, the thickness of the second mask pattern 503 is indicated by “h1”, and the thickness of the third mask pattern 504 is indicated by “h2”. The width of the third mask pattern 504 is indicated by “La”. Similarly, in the partially enlarged view shown in FIG. 2B, the thickness of the second resist pattern 503a is indicated by “h3”, and the thickness of the third resist pattern 504a is indicated by “h4”. The width of the third resist pattern 504a is indicated by “Lb”.

  Using the resist patterns 502a, 503a, and 504a as etching masks, the metal film 512 is etched to form a metal pattern 512a (FIG. 2C).

  Next, reflow resist patterns 502b, 503b, and 504b are formed by performing a reflow process (FIG. 2D). Then, the a-Si film 511 is etched using the reflow resist patterns 502b, 503b, and 504b as an etching mask to form an a-Si pattern 511a (FIG. 2E).

  The third resist pattern 504a is formed in at least a part of the edge region of the second resist pattern 503a and has a small width. Since the edge region of the second resist pattern 503a is protected by the third resist pattern 504a, the edge of the second resist pattern 503a is not scraped by the etching process of the metal film 512. Therefore, variation in the width dimension of the second resist pattern 503a can be suppressed.

  In addition, since the edge region of the second resist pattern 503a is protected by the third resist pattern 504a, the retreat of the edge of the second resist pattern 503a is suppressed by the reflow process and the drying process.

  Incidentally, the film thickness h4 of the third resist pattern 504a is thicker than the film thickness h3 of the second resist pattern 503a. For this reason, there is a possibility that the third resist pattern 504a spreads greatly due to the reflow process and the dimensions thereof vary. However, since the width Lb of the third resist pattern 504a is narrow, the spread in the width direction is suppressed by the surface tension of the resist melted by the reflow process. Therefore, the dimensional variation of the a-Si pattern 511a formed using the third resist pattern 504a as an etching mask is reduced.

  Next, a second embodiment will be described. The present embodiment relates to a detailed manufacturing method of a halftone mask. FIG. 3A to FIG. 3F are explanatory diagrams of the halftone mask 300.

  3A shows a top view of the mask pattern corresponding to the TFT, and FIG. 3B shows a cross-sectional view taken along the line X6-X6 of FIG. FIG. 3C is a top view of the mask pattern corresponding to the data line terminal, and FIG. 3D is a cross-sectional view taken along line X7-X7 in FIG. FIG. 3E shows a mask pattern corresponding to a data line terminal including the third mask pattern 333, and FIG. 3F shows an X8-X8 cross-sectional view in FIG.

  The halftone mask 300 includes rectangular first mask patterns 321, 322 and 323, rectangular second mask patterns 341, 342, 343 and 344, and linear third mask patterns 331, 332 and 333. Is provided. Note that the first mask pattern 323 is formed in the second mask pattern 341.

  The film thicknesses of the second mask patterns 341, 342, 343, and 344 are thinner than those of the first mask patterns 321, 322, 331, and 332, and the third mask patterns 331, 332, and 333.

  Such a halftone mask 300 is manufactured through the steps shown in FIGS. 4 (a) to 4 (e) and FIGS. 5 (a) to 5 (d). For convenience of explanation, it is assumed that the halftone mask 300 has a mask pattern shown in FIG. In this case, the first mask pattern 30 and the third mask pattern 32 correspond to the overlapping region of the first light shielding film pattern 23 and the second light shielding film pattern 24, and the second mask pattern 31 is the second mask pattern 31. This corresponds to the region of only the light shielding film pattern 24.

  First, a first light shielding film 23a is formed on the glass substrate 21, and a first resist 25a is applied on the first light shielding film 23a (FIG. 4A). Then, exposure is performed using the exposure mask 26 to form a latent image 25c. Thereafter, development is performed to form a first resist pattern 25b (FIGS. 4B and 4C). The first resist pattern 25 b corresponds to the shape of the first mask pattern 30 and the third mask pattern 32.

  Using this first resist pattern 25b as an etching mask, the first light shielding film 23a is etched to form the first light shielding film pattern 23 (FIGS. 4D and 4E).

  Next, a second light shielding film 24a is formed, and a second resist 27a is applied thereon (FIG. 5A). Exposure is performed using the exposure mask 28 to form a latent image 27c (FIG. 5B).

  Development is performed to form a second resist pattern 27b (FIG. 5C). The second resist pattern 27 b corresponds to the shape of the second mask pattern 32. Using the second resist pattern 27b as an etching mask, the second light shielding film 24a is etched to form the second light shielding film pattern 24 (FIG. 5D).

  Accordingly, the first mask pattern 30 and the third mask pattern 32 correspond to the overlapping region of the first light shielding film pattern 23 and the second light shielding film pattern 24, and the second mask pattern 31 is the second mask pattern 31. This corresponds to the region of only the light shielding film pattern 24.

  In the above halftone mask manufacturing method, the second light shielding film pattern 24 is formed after the first light shielding film pattern 23 is formed. However, as described below, the second light shielding film pattern 24 can be formed before the first light shielding film pattern 23 is formed.

  A method of manufacturing this halftone mask will be described with reference to FIGS. 6 (a) to 6 (e) and FIGS. 7 (a) to 7 (d). First, the second light shielding film 24a is formed on the glass substrate 21, and the second resist 27a is applied thereon. Then, exposure is performed using the mask 28 to form a latent image 27c (FIGS. 6A and 6B).

  The exposed second resist 27a is developed to form a second resist pattern 27b (FIG. 6C). Using the second resist pattern 27b as an etching mask, the second light shielding film 24a is etched to form the second light shielding film pattern 24 (FIGS. 6D and 6E).

  Next, a first light shielding film 23a is formed, and a first resist 25a is applied thereon (FIG. 7A). Thereafter, exposure is performed using the mask 26 (FIG. 7B), and a first resist pattern 25b is formed (FIG. 7C).

  Using the first resist pattern 25b as an etching mask, the first light shielding film 23a is etched to form the first light shielding film pattern 23 (FIG. 7D).

  Thus, the first mask pattern 30 and the third mask pattern 32 correspond to the overlapping region of the first light shielding film pattern 23 and the second light shielding film pattern 24, and the second mask pattern 31 is the second mask pattern 31. This corresponds to the region of only the light shielding film pattern 24.

  In the halftone mask manufacturing method, an exposure process is performed after the film forming process. In such a case, it is preferable to mask the alignment mark so that the film formed in the film formation process does not cover the alignment mark. Or it is preferable to perform the process of removing the film | membrane which covered the alignment mark before an exposure process. By such processing, it is possible to prevent a decrease in mask alignment accuracy.

  In the halftone mask manufacturing method, the exposure step was performed twice. However, the exposure process can be performed once as described below. This manufacturing method will be described with reference to FIGS. 8 (a) to 8 (f).

  First, the second light-shielding film 24a and the first light-shielding film 23a are sequentially formed on the glass substrate 21, and a resist 29a is applied thereon (FIG. 8A). Then, exposure is performed to form a latent image 29c and development is performed to form a resist pattern 29b composed of a thick resist layer and a thin resist layer (FIGS. 8B and 8C). .

  Using the resist pattern 29b as an etching mask, the first light-shielding film 24a and the second light-shielding film 23a are etched to form the first light-shielding pattern 23b and the second light-shielding pattern 24 (FIG. 8D).

  Thereafter, a resist pattern 29d is formed by uniformly removing the resist pattern 29b by a predetermined amount by using ashing or the like. The predetermined amount is a thickness corresponding to a thin resist layer. Then, the first light shielding pattern 23 is formed by etching the first light shielding pattern 23b using the remaining resist pattern 29d (FIGS. 8E and 8F).

  Thus, the first mask pattern 30 and the third mask pattern 32 correspond to the overlapping region of the first light shielding film pattern 23 and the second light shielding film pattern 24, and the second mask pattern 31 is the second mask pattern 31. This corresponds to the region of only the light shielding film pattern 24.

  Since the first mask pattern and the third mask pattern in the halftone mask have the same film thickness, these transmittances have the same value. However, there are cases where it is desired to change the transmittance between the first mask pattern and the third mask pattern. In such a case, the film thickness of the third mask pattern is different from that of the first mask pattern.

  In the third mask pattern having a linear shape, the exposure light wrap-around ratio increases, so the resist pattern formed corresponding to the third mask pattern has a wide first mask pattern. It tends to be thinner. Therefore, when determining the film thickness of the third mask pattern, it is necessary to determine in consideration of the above.

  Chromium, tantalum, and molybdenum silicide can be used as the material of the second light shielding film. In addition, chromium oxide, chromium oxynitride, and fluorinated chromium oxide containing chromium as a main component can be used.

  In addition, as a material for the first light-shielding film, a multilayer film in which a film containing chromium as a main component or a film containing chromium as a main component can be used. Examples of the film containing chromium as a main component include chromium, chromium nitride, and chromium fluoride. As the multilayer film, a film in which a film containing chromium nitride as a main component and a film containing chromium oxide or chromium oxynitride as a main component can be exemplified.

  Furthermore, an intermediate film can be interposed between the first light shielding film and the second light shielding film. As such an intermediate film, silicon oxide, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, molybdenum oxide, tantalum oxide silicide, molybdenum oxide silicide, chromium fluoride, fluorinated chromium oxide, oxide Examples thereof include a film of tin, indium oxide, indium tin oxide, and zinc oxide, and a film in which a plurality of these films are combined.

  Further, the transmittance T1 of the first mask pattern, the transmittance T2 of the second mask pattern, and the transmittance T3 of the third mask pattern with respect to the exposure light are 0% ≦ T1 <5%, 10% ≦ T2 ≦ 70. %, 5% ≦ T3 ≦ 10%, and the types and film thicknesses of these materials are determined. Thereby, the resist pattern formed using the halftone mask has an appropriate film thickness.

  In addition, as shown in FIG. 9, it is preferable that the distance d between the edges of the third mask pattern and the second mask pattern satisfies 0 μm ≦ d ≦ 1.5 μm.

  The line width Lw1 of the third mask pattern preferably satisfies 0.5 μm ≦ Lw1 <3 μm, and the interval Lw2 between adjacent patterns preferably satisfies 1.0 μm ≦ Lw2 <10.0 μm.

  Furthermore, the area of the second mask pattern is preferably 10% or more with respect to the sum of the areas of the first mask pattern and the third mask pattern.

  By setting the material, film thickness, dimensions, etc. of the mask pattern so as to satisfy the above conditions, a resist pattern having an appropriate film thickness can be formed.

  In order to confirm the contribution of the third mask pattern to the width dimension accuracy of the resist pattern, resist patterns of Sample 1 and Sample 2 were prepared, and the width L1 was measured at 36 points.

  Sample 1 is a resist pattern formed using a mask pattern having a third mask pattern at the edge of the second mask pattern as shown in FIG. Sample 2 is a resist pattern formed using a mask pattern of only the second mask pattern as shown in FIG.

  FIG. 10 is a diagram showing measurement results. In FIG. 10, the band-shaped region in the rectangular region indicates the resist pattern of Sample 1 or Sample 2 and indicates that the measurement was performed on the width of the resist pattern.

  As can be seen from FIG. 10, the line width L1 of the sample 1 has an average value of 7.240 μm and a deviation value (3σ) of 0.762 μm, and the line width L1 of the sample 2 has an average value of 7.631 μm and a deviation value (3σ ) 1.565 μm.

  Therefore, the third mask pattern can suppress variation in the dimension of the resist pattern and improve the dimensional accuracy. In addition, since the third mask pattern can be formed at the same time as the first mask pattern, it is possible to improve the dimensional accuracy without adding a special process.

  Next, a third embodiment will be described. The present embodiment relates to a vertical electric field type LCD device manufactured using the halftone mask.

  Note that the halftone mask of the present invention can also be applied to a horizontal electric field type (IPS: In Plane Switching) liquid crystal display device. In addition to the LCD device, an organic EL (electroluminescence) display device or the like may be used as the active matrix display device.

  Although the reverse stagger type (bottom gate type) will be described as an example of the TFT, a stagger type (top gate type) may be used. An inverted staggered TFT has a structure in which a gate electrode is formed below a semiconductor layer, and a source electrode and a drain electrode are formed above the semiconductor layer.

  FIG. 11 shows a top view of the TFT substrate 1 in the liquid crystal display device, and FIG. 12 shows a schematic diagram of one pixel 3. The TFT substrate 1 includes a glass substrate 2 on which scanning lines 4, data lines 5, gate terminals 7, and data line terminals 9 are formed. The gate terminal 7 and the data line terminal 9 are formed in the end region of the TFT substrate 1.

  A plurality of scanning lines 4 and data lines 5 linked to each other divide the display area into a plurality of areas. One partition area corresponds to one pixel 3, and each pixel 3 is provided with a TFT 11 and a pixel electrode 3a.

  The scanning line 4 is electrically connected to the gate terminal 7 via the gate lead wiring 6, and the data line 5 is electrically connected to the data line terminal 9 via the signal lead wiring 8. The gate electrode 4 a of the TFT 11 is connected to the scanning line 4, and the drain electrode 5 a of the TFT 11 is connected to the data line 5.

  Then, the TFT 11 is turned on and off by changing the potential of the gate electrode 4a in accordance with the signal of the scanning line 4. When the TFT 11 is turned on, the signal of the data line 5 is applied to the pixel electrode 3a via the drain electrode 5a and the source electrode 5b.

  13A is a detailed plan view of the TFT 11, and FIG. 13B is an X3-X3 cross-sectional view of FIG. 14A is a plan view of the data line terminal 9 shown in FIG. 11, FIG. 14B is a sectional view taken along the line X4-X4 of FIG. 14A, and FIG. 14C is FIG. X5-X5 sectional drawing of is shown.

  As shown in FIG. 13B, a contact layer 10 a, a drain electrode 5 a, and a source electrode 5 b are formed on the semiconductor layer 10. In addition, a gate insulating film 12 and a gate electrode 4 a are formed under the semiconductor layer 10. The source electrode 5b is connected to the pixel electrode 3a through a contact hole 12b formed in the passivation film 12a. The gate electrode 4a and the scanning line 4 include the same metal film, and the drain electrode 5a and the data line 5 include the same metal film.

  As shown in FIGS. 14B and 14C, the data line terminal 9 and the signal lead-out wiring 8 are formed of a gate insulating film 12, a semiconductor layer 10, a contact layer 10a, a data line terminal electrode 5c, and a passivation film 12a. It is a laminate. However, it differs from the signal extraction wiring 8 in that a contact hole 12b is formed in the passivation film 12a of the data line terminal 9 and the data line terminal electrode 5c and the pixel electrode 3a are connected. The width dimension of the semiconductor layer 10 in the data line terminal 9 and the signal lead-out line 8 is the same as the width dimension of the data line terminal electrode 5c.

  A manufacturing method of such a TFT substrate 1 will be described with reference to FIGS. 15A to 15F, FIGS. 16A to 16E, and FIGS. 17A to 17E. To do.

  FIGS. 15A to 15F show the steps up to the formation of the resist pattern, FIGS. 16A to 16E show the steps up to the etching with the reflow resist pattern, and FIGS. FIG. 17E shows a process until formation of a transparent electrode.

  15A, the left side view is a top view of the TFT region corresponding to FIG. 3A, the center side view is a top view of the data line terminal corresponding to FIG. 3C, and the right side view is shown. It is a top view of a data line terminal provided with the 3rd mask pattern corresponding to Drawing 3 (e). 15 (b) to FIG. 15 (f), FIG. 16 (a) to FIG. 16 (e), and FIG. 17 (a) to FIG. 17 (e), the left side view is X9- in FIG. X9 sectional view, center side view shows X10-X10 sectional view, and right side view shows X11-X11 sectional view. Hereinafter, in order to distinguish the left view, the center view, and the right view, “L”, “M”, and “R” are added to the drawing numbers. For example, the left view of FIG. 15 (a) is described as FIG. 15 (a) -L, the center view of FIG. 15 (a) is described as FIGS. 15 (a) -M, and FIG. The right view is described as FIG. 15 (a) -R.

  With reference to FIG. 15, steps until a resist pattern is formed will be described. First, a metal film is formed on the glass substrate 2, and this metal film is processed using a known photolithography technique, etching technique, or the like to form the gate electrode 4a (FIG. 15B). At this time, the scanning line (not shown) is formed at the same time as the gate electrode 4a. However, the data line terminal 9 and the data line 5 do not have a wiring layer corresponding to the gate electrode 4a. Etching does not remain (FIG. 15 (b) -M, FIG. 15 (b) -R).

  A metal film using aluminum, molybdenum, chromium, an alloy containing these as a main component, or the like as a material is formed with a thickness of 100 nm to 500 nm by a sputtering method.

Next, the gate insulating film 12 made of a silicon nitride film or the like, the semiconductor layer 10 made of amorphous Si (a-Si), the contact layer 10a made of high impurity concentration n ⁺ amorphous Si (a-n ⁺ Si), chromium and aluminum The data line terminal electrode 5c made of an alloy is sequentially laminated (FIG. 15C). The gate insulating film 12, the semiconductor layer 10, and the contact layer 10a are formed using a plasma CVD method, and the film thicknesses are about 400 nm, about 300 nm, and about 50 nm, respectively. The data line terminal electrode 5c has a thickness of about 250 nm.

  Next, a positive photoresist is applied, and heat treatment is performed at 80 ° C. to 100 ° C. The solvent component in the photoresist is removed by the heat treatment, and a resist film 13 is formed (FIG. 15D).

  Next, exposure is performed using the halftone mask 16 having a predetermined pattern (FIG. 15E). The pattern of the halftone mask 16 includes first mask patterns 321, 322, 323, second mask patterns 341, 342, 343, and third mask patterns 331, 332, 333.

  The resist is exposed according to the transmittance of the first mask patterns 321, 322, 323, the second mask patterns 341, 342, 343, and the third mask patterns 331, 332, 333. After the exposure, development with a developing solution such as an alkaline solution is performed (FIG. 15 (f)).

  Thus, first resist patterns 321a, 322a, and 323a having film thicknesses of about 1.5 μm to 2.5 μm corresponding to the first mask patterns 321, 322, and 323 are formed. In addition, second resist patterns 341a, 342a, and 343a having film thicknesses of about 0.2 μm to 1.5 μm corresponding to the second mask patterns 341, 342, and 343 are formed. Further, third resist patterns 331a, 332a, and 333a having a film thickness of about 1.5 to 2.5 μm corresponding to the third mask patterns 331, 332, and 333 are formed. The thick films of the first resist patterns 321a, 322a, and 323a are thicker than the film thicknesses of the second resist patterns 341a, 342a, and 343a.

  In addition, third resist patterns 331a and 332a are formed on the edges and the like of the second resist patterns 341a and 342a that require a high-accuracy width dimension, thereby suppressing variations in the width dimension.

  Next, steps required until the resist pattern is reflowed will be described with reference to FIGS. First, the first resist patterns 321a, 322a, 323a, the second resist patterns 341a, 342a, 343a, and the third resist patterns 331a, 332a, 333a are used as etching masks to dry the data line terminal electrode 5c and the contact layer 10a. Etching is performed (FIG. 16B).

  By this etching, the drain electrode 5a, the source electrode 5b, the data line 5 and the contact layer 10a are formed. Further, the contact layer 10a in the source region and the drain region is separated, and a channel is formed in the semiconductor layer 10 (FIGS. 16A to 16L). In addition, the data line 5, the data line terminal 9, the data line terminal electrode 5c of the signal lead-out wiring 8, and the contact layer 10a are formed (FIGS. 16B to 16M and FIGS. 16B to 16R).

  After the data line terminal electrode 5c and the contact layer 10a are etched, the glass substrate 2 is exposed to an organic solvent vapor to perform a reflow process (FIG. 16C). Examples of the organic solvent include acetone and propylene glycol monoethyl ether. The exposure time can be exemplified by about 0.1 to 3 minutes.

  The organic solvent penetrates into the resist and melts and reflows. When the resist pattern is reflowed, the thick first resist patterns 321a, 322a, and 323a spread to form first reflow resist patterns 321b, 322b, and 323b.

  At this time, the first reflow resist pattern 321b and the first reflow resist pattern 322b are integrated in the region K (FIG. 16 (d) -L). This integrated region corresponds to the channel region of the TFT.

  The second resist patterns 341a and 342a are also reflowed to become second reflow resist patterns 341b and 342b. However, even if the second resist patterns 341a and 342a are reflowed, the spread is small due to the surface tension of the resist. Therefore, the shape change of the second resist patterns 341a and 342a is small.

  Thus, since the degree of reflow differs depending on the thickness of the resist pattern, the thickness of the resist pattern is set in consideration of the reduction of the resist film thickness due to reflow and the etching resistance required in the next etching step.

  Since the edge portion of the resist pattern is more easily etched by etching than the flat portion, the width dimension is likely to vary. As described above, the variation in the width dimension causes an increase in parasitic capacitance and deteriorates image display characteristics. Therefore, in the present invention, the thick third resist patterns 331a and 332a are formed in anticipation that the edge portion of the resist is etched away.

  The third resist patterns 331a and 332a have a narrow linear shape, and the spread of the resist pattern is very small due to the surface tension of the melted resist. Accordingly, variation in the dimensions of the second resist patterns 341a and 342a can be suppressed.

When the third mask pattern is provided in the second mask pattern region corresponding to the region facing the drain electrode 5a and the source electrode 5b, the third mask pattern may have an area of at least 9 μm ² or more. preferable. In the case where the third mask pattern is provided in the mask pattern in the region corresponding to the contact hole, the third mask pattern preferably has an area of at least 9 μm ² or more. By setting the area of the third mask pattern in this way, the force to reflow and spread and the surface tension are balanced, and variations in the dimensions of the second resist patterns 341a and 342a can be suppressed.

  Next, the semiconductor layer 10 is etched using such a reflow resist as an etching mask (FIG. 16D). Etching is performed by, for example, reactive ion etching.

  Since the first reflow resist pattern 321b and the first reflow resist pattern 322b corresponding to the source region and the drain region are integrated in the region K, a semiconductor region in which the source region, the channel region, and the drain region are integrated is formed. It is formed.

  Next, steps required until a transparent electrode is formed will be described with reference to FIG. After the reflow resist is removed, a passivation film 12a made of a silicon nitride film or a silicon oxide film is formed on the entire surface (FIG. 17A).

  Then, a resist 50 is applied on the passivation film 12a and exposed using a mask 54 having a mask pattern 55a corresponding to the contact hole 12b to form a latent image 50a (FIG. 17B).

  Thereafter, using the resist pattern obtained by developing the resist as an etching mask, the passivation film 12a is etched to form a contact hole 12b (FIG. 17C).

  Next, a transparent conductive film 56 such as ITO (Indium-Tin-Oxide) is formed on the entire surface, and a resist 57 is applied thereon. Then, exposure is performed using the mask 58 to form a latent image 57a, and then development is performed to form a resist pattern (FIG. 17D).

  Using this resist pattern as an etching mask, the transparent conductive film 56 is etched to form the pixel electrode 3a and the transparent electrode 3b of the data line terminal portion (FIG. 17E).

  FIG. 18 is a cross-sectional view of a liquid crystal display device using the TFT substrate thus formed. The liquid crystal display device 70 includes a TFT substrate 71 manufactured by the above method, a counter substrate 72 formed with a color filter, a black matrix, a counter electrode, an alignment film, and the like, and a liquid crystal filled between the counter substrate 72 and the TFT substrate 71. 73, a backlight 74 that irradiates light toward the TFT substrate 71, a polarizing plate 75, and the like.

  Then, the TFT is selected by a signal from the scanning line and is turned on and off. When the TFT is turned on, the data line signal is applied to the pixel 3.

  Since a constant voltage is applied to the counter electrode, an electric field is generated between the pixel electrode and the counter electrode, and the deflection direction of the liquid crystal changes according to the electric field, and the light emitted from the backlight is changed. Transmission is controlled. Thereby, an image is displayed.

  At this time, the line width of the scanning line and data line, the channel width of the TFT, and the like have dimensions of design values, so that an increase in parasitic capacitance is suppressed and high-quality image display becomes possible.

It is a figure which shows the structure of the halftone mask concerning 1st Embodiment, (a) is a top view, (b) is X2-X2 sectional drawing. It is a figure which shows the process of forming a reflow resist pattern using the halftone mask concerning 1st Embodiment, (a) is an exposure process, (b) and (c) is an etching process, (d) is a reflow process. (E) shows an etching process using a reflow resist. 5A and 5B are diagrams showing a configuration of a halftone mask according to a second embodiment, wherein FIG. 5A is a top view of a TFT region, FIG. 5B is a cross-sectional view taken along X6-X6, and FIG. (D) is X7-X7 sectional drawing, (e) is a top view of a data line terminal area provided with the 3rd mask pattern, (f) is X8-X8 sectional drawing. It is a figure which shows the process until formation of the 1st light shielding film pattern in the manufacturing method of the halftone mask concerning 2nd Embodiment, (a) And (b) shows an exposure process, (c)-(e ) Shows a patterning step. FIGS. 5A and 5B are diagrams illustrating steps following FIG. 4, in which FIGS. 4A and 4B illustrate an exposure process, and FIGS. It is a figure which shows the process until formation of the 2nd light shielding film pattern in the manufacturing method of the other halftone mask concerning 2nd Embodiment, (a) And (b) shows an exposure process, (c)- (E) shows a patterning process. FIGS. 7A and 6B are diagrams illustrating processes following FIG. 6, in which FIGS. 6A and 6B illustrate an exposure process, and FIGS. It is a figure which shows the process of the manufacturing method of the other halftone mask of 2nd Embodiment, (a) And (b) shows an exposure process, (c)-(f) shows a patterning process. It is a figure which shows the formation conditions of the 3rd mask pattern of 2nd Embodiment. It is a figure which shows the result of the dispersion | variation measurement of the line width of the resist pattern by the 3rd mask pattern of 2nd Embodiment. It is a partial top view of the TFT substrate concerning 3rd Embodiment. It is a top view of the pixel concerning 3rd Embodiment. 4A and 4B are diagrams showing a structure of a TFT according to a third embodiment, in which FIG. 5A is a top view and FIG. It is a figure which shows the structure of the data line terminal part concerning 3rd Embodiment, (a) is a top view, (b) is X4-X4 sectional drawing, (c) is X5-X5 sectional drawing. It is a figure which shows the process of forming the resist pattern used for manufacture of a TFT substrate using the halftone mask concerning 3rd Embodiment, (a) is a mask pattern, (b)-(e) is an exposure process. (F) shows a development process. FIGS. 15A and 15B are diagrams illustrating processes following FIG. 15, in which FIGS. 15A and 15B illustrate a process of etching using a resist pattern, FIG. 15C illustrates a reflow process, and FIGS. FIG. 17 is a diagram illustrating a process following FIG. 16, (a) to (c) illustrating a contact hole forming process, and (d) and (e) illustrating a transparent electrode forming process. It is sectional drawing of the liquid crystal display device concerning 3rd Embodiment. It is a figure explaining the related reflow technique, (a) is a top view of a halftone mask, (b) is an X1-X1 cross-sectional view, (c) is a resist pattern process, (d) is an etching process, (e) is A reflow process, (f) shows an etching process.

Explanation of symbols

500 halftone mask 502 first mask pattern 502a first resist pattern 502b reflow resist pattern 503 second mask pattern 503a second resist pattern 504 third mask pattern 504a third resist pattern

Claims (9)

A halftone mask used to form resist patterns with different film thicknesses,
A first mask pattern used to form a first resist pattern;
A second mask pattern used to form a second resist pattern that is thinner than the first resist pattern;
Is formed on at least a portion of the edge region of the second mask pattern, we have a third mask pattern used for forming a resist pattern of a thick film from the second resist pattern,
The transmittance of the third mask pattern used for the exposure of the positive resist is set to be smaller than the transmittance of the second mask pattern, and the transmittance of the third mask pattern used for the exposure of the negative resist is: Is set to a greater transmission than the second mask pattern; and
The half-tone mask, wherein the third mask pattern is formed at opposing edges of the second mask pattern at an opposing interval of 1.0 μm to 3 μm . The halftone mask according to claim 1 ,
The third mask pattern is a linear pattern having a predetermined width, and is a halftone mask. The halftone mask according to claim 2 ,
A line width of the third mask pattern is in a range of 0.5 μm to 3 μm. The halftone mask according to any one of claims 2 to 3 ,
The halftone mask is characterized in that the formation position of the third mask pattern is 0 μm to 1.5 μm from the edge of the second mask pattern toward the inside of the pattern. The halftone mask according to any one of claims 2 to 4 ,
An area of the second mask pattern is 10% or more of a total area of the first mask pattern and the third mask pattern. The halftone mask according to any one of claims 2 to 5 ,
The transmittance T1 of the first mask pattern is 0% ≦ T1 <5%, the transmittance T2 of the second mask pattern is 10% ≦ T2 ≦ 70%, and the third mask pattern The halftone mask is characterized in that the transmittance T3 of 5% ≦ T3 ≦ 10%. The halftone mask according to any one of claims 2 to 6 ,
The second mask pattern is a film containing tantalum, molybdenum silicide, or chromium as a main component,
The first mask pattern and the third mask pattern are multilayer films in which a film containing chromium as a main component and a film containing tantalum, molybdenum silicide, or chromium as a main component are stacked. Halftone mask. The halftone mask according to claim 7 ,
The multilayer film includes a film containing chromium nitride as a main component and a film containing chromium oxide or chromium oxynitride as a main component. The halftone mask according to claim 7 or 8 ,
The multilayer film is laminated on the second mask pattern via an intermediate film,
The intermediate film includes silicon oxide, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, molybdenum oxide, tantalum oxide silicide, molybdenum oxide silicide, chromium fluoride, fluorinated chromium oxide, tin oxide, A halftone mask comprising at least one of indium oxide, indium tin oxide, and zinc oxide.

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