JP5428404B2 - THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR - Google Patents

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor.

A characteristic required when a thin film transistor (TFT) having a semiconductor thin film of amorphous silicon or the like as a channel layer is used for a pixel circuit of a display device is low leakage current. If the leakage current of the TFT is high, the display image quality may deteriorate due to a decrease in contrast due to a decrease in the on / off ratio of the TFT.
In view of this, there is known a technique for reducing the leakage current by forming a notch in the end face of the channel protective film, which becomes a path around which the leakage current flows, to lengthen the leakage path (for example, Patent Document 1). reference.).

JP 2000-214485 A

However, in the case of the above-mentioned Patent Document 1, although the image quality is improved by reducing the leakage current, the fundamental solution has not been reached since the leakage current path is not cut off.
In addition, a portion where the semiconductor thin film is exposed in the channel layer under the channel protective film may be changed into a conductive compound (for example, silicide) in the transistor manufacturing process, and the leakage current flowing through the portion cannot be ignored. May have adverse effects.

  Therefore, an object of the present invention is to further reduce the leakage current.

In order to solve the above problems, one aspect of the present invention is a method of manufacturing a thin film transistor,
A semiconductor layer forming step of forming a semiconductor layer containing silicon on the upper surface side of the substrate;
A semiconductor film forming step of patterning the semiconductor layer to form an island-shaped semiconductor film;
A metal film forming step of forming a metal film in contact with a side surface of the semiconductor film on the substrate and covering the semiconductor film;
Patterning the metal film, forming an electrode layer on the semiconductor film, and forming an electrode layer projecting an end of the semiconductor film from the electrode layer;
An overcoat step of forming a first insulating film covering the electrode layer and the semiconductor film;
Forming an opening in a portion of the first insulating film corresponding to a part of a boundary portion between the side surface of the end of the semiconductor film protruding from the electrode layer and the first insulating film; An exposure process for exposing a part of the end; and
An edge removing step of removing a part of the exposed edge of the semiconductor film by etching through the opening;
It is characterized by having.
Preferably, in the exposing step, the semiconductor film is in contact with the metal film at the time of forming the metal film in the metal film forming process at an end portion of the semiconductor film, and along the side surface of the semiconductor film. Exposing a part of the region transformed into the formed conductive compound,
The edge removing step removes a part of the region of the semiconductor film that has been transformed into the conductive compound.
Preferably, the semiconductor layer forming step includes a step of forming a protective insulating film on the semiconductor layer,
After the semiconductor film forming step, the protective insulating film is patterned to form a protective film forming step of forming a protective film that covers a region to be a channel in the semiconductor layer,
In the semiconductor film forming step, an impurity semiconductor layer is formed on the semiconductor layer on which the protective film is formed, the impurity semiconductor layer is patterned, and a pair of impurity semiconductor films facing each other with the protective film interposed therebetween Including an impurity semiconductor film forming step of forming
The metal film forming step includes a step of forming the metal film so as to contact the side surfaces of the impurity semiconductor film, the protective film, and the semiconductor film and cover the semiconductor film,
The electrode layer forming step includes a step of patterning the metal film to form a source electrode and a drain electrode on the pair of impurity semiconductor films.
Preferably, prior to the semiconductor layer forming step, a gate electrode forming step of forming a gate electrode and a lower layer electrode on the upper surface of the substrate,
The semiconductor layer forming step includes: forming a second insulating film on the upper surface of the substrate so as to cover the gate electrode and the lower layer electrode formed in the gate electrode forming step; Forming the semiconductor layer, and
After the semiconductor film forming step, the terminal pad portion includes an electrode exposing step of etching the second insulating film to expose the lower layer electrode,
The metal film deposition step includes the step of depositing the metal film on the second insulating film and the exposed lower electrode,
The electrode layer forming step forms the upper layer electrode on the exposed lower layer electrode by patterning the metal film on the exposed lower layer electrode simultaneously with the formation of the electrode layer in the terminal pad portion. Including steps,
In the overcoat step, the first insulating film is formed so as to cover the upper electrode,
The exposing step includes a step of exposing at least a part of the upper layer electrode by etching the first insulating film on the upper layer electrode simultaneously with the formation of the opening in the terminal pad portion.
The thin film transistor is manufactured by this thin film transistor manufacturing method.

Another aspect of the present invention is a thin film transistor,
A semiconductor film containing silicon formed in an island shape on the upper surface side of the substrate;
An electrode layer made of a metal film and formed on the upper part of the semiconductor film in a shape in which an end of the semiconductor film protrudes;
A first insulating film covering the electrode layer and the semiconductor film;
A partition formed on the first insulating film;
With
The semiconductor film has a cutout portion from which a part of the semiconductor film is removed at the end portion, and the semiconductor film is formed of the metal film when forming the metal film forming the electrode layer in the cutout portion. In contact with the film, a region transformed into a conductive compound formed along the side surface of the semiconductor film is divided ,
The first insulating film has an opening formed at a position corresponding to the notch,
The opening is filled with a material for forming the partition wall .
Preferably, a protective film made of a protective insulating film is formed on a region to be a channel of the semiconductor film,
On the semiconductor film, a pair of impurity semiconductor films formed at positions facing each other with the protective film interposed therebetween,
With
The electrode layer is formed on the pair of impurity semiconductor films to form a source electrode and a drain electrode,
The first insulating film covers the source and drain electrodes, the impurity semiconductor film, the protective film, and the semiconductor film.

  According to the present invention, the leakage current in the thin film transistor can be further reduced.

It is a top view which shows the arrangement configuration of the pixel of an EL panel. It is a top view which shows schematic structure of EL panel. It is a circuit diagram showing a circuit corresponding to one pixel of an EL panel. It is the top view which showed 1 pixel of EL panel. It is arrow sectional drawing of the surface along the VV line of FIG. It is arrow sectional drawing of the surface along the VI-VI line of FIG. It is arrow sectional drawing of the surface along the VII-VII line of FIG. It is explanatory drawing which shows the gate formation process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the three-layer film-forming process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the protective film formation process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the impurity semiconductor layer film-forming process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the semiconductor film formation process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the electrode exposure process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the metal film film-forming process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the source / drain formation process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the overcoat process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the exposure process in the manufacture process of a thin-film transistor. It is explanatory drawing which shows the edge part removal process in the manufacture process of a thin-film transistor.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a plan view illustrating an arrangement configuration of a plurality of pixels P in an EL panel 1 that is a light emitting device, and FIG. 2 is a plan view illustrating a schematic configuration of the EL panel 1.

As shown in FIGS. 1 and 2, in the EL panel 1, a plurality of pixels P that respectively emit R (red), G (green), and B (blue) are arranged in a matrix with a predetermined pattern. .
In the EL panel 1, a plurality of scanning lines 2 are arranged so as to be substantially parallel to each other along the row direction, and the plurality of signal lines 3 are arranged along the column direction so as to be substantially orthogonal to the scanning lines 2 in plan view. They are arranged substantially parallel to each other. A voltage supply line 4 is provided along the scanning line 2 between the adjacent scanning lines 2. A range surrounded by the two signal lines 3 adjacent to the scanning lines 2 and the voltage supply lines 4 corresponds to the pixel P.
Further, the EL panel 1 is provided with a bank 13 that is a grid-like partition wall so as to cover the scanning line 2, the signal line 3, and the voltage supply line 4. A plurality of substantially rectangular openings 13a surrounded by the banks 13 are formed for each pixel P, and predetermined carrier transport layers (a hole injection layer 8b and a light emitting layer 8c described later) are formed in the openings 13a. ) Are provided and become a light emitting region of the pixel P. The carrier transport layer is a layer that transports holes or electrons when a voltage is applied.
A terminal pad T (see FIG. 18 and the like) is provided at one end of each of the plurality of scanning lines 2. The plurality of voltage supply lines 4 are connected to each other by one or more common wires outside the bank 13, and the common wires are connected to one or more terminal pads T.

  FIG. 3 is a circuit diagram showing a circuit corresponding to one pixel of the EL panel 1 operating in the active matrix driving method.

  As shown in FIG. 3, the EL panel 1 is provided with a scanning line 2, a signal line 3 intersecting with the scanning line 2, and a voltage supply line 4 along the scanning line 2. For each pixel P, a switch transistor 5 that is a thin film transistor, a drive transistor 6 that is a thin film transistor, a capacitor 7, and an EL element 8 are provided.

  In each pixel P, the gate of the switch transistor 5 is connected to the scanning line 2, one of the drain and source of the switch transistor 5 is connected to the signal line 3, and the other of the drain and source of the switch transistor 5 is It is connected to one electrode of the capacitor 7 and the gate of the driving transistor 6. One of the source and drain of the driving transistor 6 is connected to the voltage supply line 4, and the other of the source and drain of the driving transistor 6 is connected to the other electrode of the capacitor 7 and the anode of the EL element 8. Note that the cathodes of the EL elements 8 of all the pixels P are kept at a constant voltage Vcom (for example, grounded).

  Further, in the periphery of the EL panel 1, each scanning line 2 is connected to a scanning driver, each voltage supply line 4 is connected to a constant voltage source or a driver that outputs an appropriate voltage signal, and each signal line 3 is connected to a data driver. The EL panel 1 is driven by these drivers by an active matrix driving method. The voltage supply line 4 is supplied with predetermined power by a constant voltage source or a driver.

  Next, the circuit structure of the EL panel 1 and the pixel P will be described with reference to FIGS. Here, FIG. 4 is a plan view corresponding to one pixel P of the EL panel 1, FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 4, and FIG. FIG. 7 is a cross-sectional view taken along the line VI-VI, and FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. In FIG. 4, electrodes and wiring are mainly shown.

  As shown in FIG. 4, the switch transistor 5 and the drive transistor 6 are arranged along the signal line 3, the capacitor 7 is disposed in the vicinity of the switch transistor 5, and the EL element 8 is disposed in the vicinity of the drive transistor 6. ing. Further, a switch transistor 5, a drive transistor 6, a capacitor 7, and an EL element 8 are disposed between the scanning line 2 and the voltage supply line 4.

  As shown in FIGS. 4 to 6, a second insulating film 11 serving as a gate insulating film is formed on one surface of the substrate 10, and a first insulating film 12 is formed on the second insulating film 11. Has been. The signal line 3 is formed between the second insulating film 11 and the substrate 10, and the scanning line 2 and the voltage supply line 4 are formed between the second insulating film 11 and the first insulating film 12.

  Further, as shown in FIGS. 4 and 6, the switch transistor 5 is a thin film transistor having an inverted staggered structure. The switch transistor 5 includes a gate electrode 5a, a semiconductor film 5b, a channel protective film 5d, impurity semiconductor films 5f and 5g, a drain electrode 5h, a source electrode 5i, and the like.

The gate electrode 5 a is formed between the substrate 10 and the second insulating film 11. The gate electrode 5a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film. An insulating second insulating film 11 is formed on the gate electrode 5a, and the second insulating film 11 covers the gate electrode 5a.
The second insulating film 11 has, for example, optical transparency and is made of silicon nitride or silicon oxide. An intrinsic semiconductor film 5b is formed on the second insulating film 11 at a position corresponding to the gate electrode 5a, and the semiconductor film 5b is opposed to the gate electrode 5a with the second insulating film 11 interposed therebetween.
The semiconductor film 5b is made of, for example, amorphous silicon or polycrystalline silicon, and a channel is formed in the semiconductor film 5b. An insulating channel protective film 5d is formed on the central portion of the semiconductor film 5b. The channel protective film 5d is made of, for example, silicon nitride or silicon oxide.
An impurity semiconductor film 5f is formed on one end portion of the semiconductor film 5b so as to partially overlap the channel protective film 5d, and the impurity semiconductor film 5g is formed on the other end portion of the semiconductor film 5b. Is partially overlapped with the channel protective film 5d. The impurity semiconductor films 5f and 5g are formed on both ends of the semiconductor film 5b so as to be separated from each other. The impurity semiconductor films 5f and 5g are n-type semiconductors, but are not limited thereto, and may be p-type semiconductors.
A drain electrode 5h is formed on the impurity semiconductor film 5f. A source electrode 5i is formed on the impurity semiconductor film 5g. The drain electrode 5h and the source electrode 5i are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
An insulating first insulating film 12 serving as a protective film is formed on the channel protective film 5d, the drain electrode 5h, and the source electrode 5i, and the channel protective film 5d, the drain electrode 5h, and the source electrode 5i are first insulated. Covered by a membrane 12. The switch transistor 5 is covered with the first insulating film 12. The first insulating film 12 is made of, for example, silicon nitride or silicon oxide having a thickness of 100 nm to 200 nm.

  4 and 5, the driving transistor 6 is a thin film transistor having an inverted staggered structure. The drive transistor 6 includes a gate electrode 6a, a semiconductor film 6b, a channel protective film 6d, impurity semiconductor films 6f and 6g, a drain electrode 6h, a source electrode 6i, and the like.

The gate electrode 6a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film, and is formed between the substrate 10 and the second insulating film 11 similarly to the gate electrode 5a. . The gate electrode 6a is covered with a second insulating film 11 made of, for example, silicon nitride or silicon oxide.
On the second insulating film 11, a semiconductor film 6b in which a channel is formed is formed of amorphous silicon or polycrystalline silicon at a position corresponding to the gate electrode 6a. The semiconductor film 6b is opposed to the gate electrode 6a with the second insulating film 11 interposed therebetween.
An insulating channel protective film 6d is formed on the central portion of the semiconductor film 6b. The channel protective film 6d is made of, for example, silicon nitride or silicon oxide.
An impurity semiconductor film 6f is formed on one end portion of the semiconductor film 6b so as to partially overlap the channel protective film 6d, and the impurity semiconductor film 6g is formed on the other end portion of the semiconductor film 6b. Is partially overlapped with the channel protective film 6d. The impurity semiconductor films 6f and 6g are formed on both ends of the semiconductor film 6b so as to be separated from each other. The impurity semiconductor films 6f and 6g are n-type semiconductors, but are not limited thereto, and may be p-type semiconductors.
A drain electrode 6h is formed on the impurity semiconductor film 6f. A source electrode 6i is formed on the impurity semiconductor film 6g. The drain electrode 6h and the source electrode 6i are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
An insulating first insulating film 12 is formed on the channel protective film 6d, the drain electrode 6h, and the source electrode 6i, and the channel protective film 6d, the drain electrode 6h, and the source electrode 6i are covered with the second insulating film 12. Has been.

  The capacitor 7 is connected between the gate electrode 6 a and the source electrode 6 i of the driving transistor 6, and as shown in FIGS. 4 and 6, one electrode 7 a is interposed between the substrate 10 and the second insulating film 11. The other electrode 7b is formed between the second insulating film 11 and the first insulating film 12, and the electrode 7a and the electrode 7b are opposed to each other with the second insulating film 11 that is a dielectric interposed therebetween.

The signal line 3, the electrode 7a of the capacitor 7, the gate electrode 5a of the switch transistor 5, and the gate electrode 6a of the driving transistor 6 are formed by forming a conductive metal film on the entire surface of the substrate 10 by a photolithography method and an etching method. It is formed in a lump by processing the shape by means of, for example.
In addition, the scanning line 2, the voltage supply line 4, the electrode 7 b of the capacitor 7, the drain electrode 5 h and source electrode 5 i of the switch transistor 5, and the drain electrode 6 h and source electrode 6 i of the driving transistor 6 are flush with the second insulating film 11. The conductive metal film is formed by shape processing by a photolithography method, an etching method, or the like.

In the second insulating film 11, a contact hole 11a is formed in a region where the gate electrode 5a and the scanning line 2 overlap, and a contact hole 11b is formed in a region where the drain electrode 5h and the signal line 3 overlap. A contact hole 11c is formed in a region where 6a and the source electrode 5i overlap, and contact plugs 20a to 20c are buried in the contact holes 11a to 11c, respectively. The contact plug 20a electrically connects the gate electrode 5a of the switch transistor 5 and the scanning line 2, the contact plug 20b electrically connects the drain electrode 5h of the switch transistor 5 and the signal line 3, and the contact plug 20c electrically connects the switch transistor. 5 source electrode 5i and capacitor 7 electrode 7a are electrically connected, and source electrode 5i of switch transistor 5 and gate electrode 6a of drive transistor 6 are electrically connected. The scanning line 2 may be in direct contact with the gate electrode 5a, the drain electrode 5h may be in contact with the signal line 3, and the source electrode 5i may be in contact with the gate electrode 6a without using the contact plugs 20a to 20c.
Further, the gate electrode 6a of the driving transistor 6 is integrally connected to the electrode 7a of the capacitor 7, the drain electrode 6h of the driving transistor 6 is integrally connected to the voltage supply line 4, and the source electrode 6i of the driving transistor 6 is connected to the capacitor. 7 is integrally connected to the electrode 7b.

The pixel electrode 8 a is provided on the substrate 10 via the second insulating film 11 and is formed independently for each pixel P. The pixel electrode 8a is a transparent electrode, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium − It consists of tin oxide (CTO). The pixel electrode 8a partially overlaps the source electrode 6i of the driving transistor 6, and the pixel electrode 8a and the source electrode 6i are connected.
4 and 5, the first insulating film 12 includes the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, the peripheral portion of the pixel electrode 8 a, and the capacitor 7. It is formed so as to cover the electrode 7 b and the second insulating film 11. An opening 12a is formed in the first insulating film 12 so that the center of each pixel electrode 8a is exposed. Therefore, the second insulating film 12 is formed in a lattice shape in plan view.

  A panel in which the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, the capacitor 7, the pixel electrode 8a, and the first insulating film 12 are formed on the surface of the substrate 10 is a transistor array panel. It has become.

  As shown in FIGS. 4 and 5, the EL element 8 includes a pixel electrode 8a as a first electrode serving as an anode, a hole injection layer 8b that is a compound film formed on the pixel electrode 8a, and a hole. A light emitting layer 8c, which is a compound film formed on the injection layer 8b, and a counter electrode 8d as a second electrode formed on the light emitting layer 8c are provided. The counter electrode 8d is a single electrode common to all the pixels P, and is continuously formed in all the pixels P.

The hole injection layer 8b is a functional layer made of, for example, PEDOT (poly (ethylenedioxy) thiophene) that is a conductive polymer and PSS (polystyrene sulfonate) that is a dopant. This is a carrier injection layer that injects holes from the electrode 8a toward the light emitting layer 8c.
The light emitting layer 8c includes a material that emits any one of R (red), G (green), and B (blue) for each pixel P. For example, the light emitting layer 8c is made of a polyfluorene light emitting material or a polyphenylene vinylene light emitting material. This is a layer that emits light upon recombination of electrons supplied from the electrode 8d and holes injected from the hole injection layer 8b. For this reason, the pixel P that emits R (red), the pixel P that emits G (green), and the pixel P that emits B (blue) have different light emitting materials for the light emitting layer 8c. The R (red), G (green), and B (blue) pattern of the pixel P may be a delta arrangement or a stripe pattern in which the same color pixels are arranged in the vertical direction.

The counter electrode 8d is made of a material having a work function lower than that of the pixel electrode 8a. For example, the counter electrode 8d is made of a simple substance or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal.
The counter electrode 8d is an electrode common to all the pixels P, and covers a bank 13 described later together with a compound film such as the light emitting layer 8c.

As described above, the light emitting layer 8 c serving as a light emitting portion is partitioned for each pixel P by the first insulating film 12 and the bank 13.
And in the opening part 13a, the positive hole injection layer 8b and the light emitting layer 8c as a carrier transport layer are laminated | stacked on the pixel electrode 8a.

Specifically, when the hole injection layer 8b and the light emitting layer 8c are formed by a wet method, the bank 13 is adjacent to a liquid material in which a material for forming the hole injection layer 8b or the light emitting layer 8c is dissolved or dispersed in a solvent. It functions as a partition wall that prevents the pixel P from bleeding. The bank 13 is made of an insulating material such as polyimide, for example.
For example, as shown in FIG. 5, in the bank 13 provided on the first insulating film 12, an opening 13 a is formed inside the opening 12 a of the first insulating film 12.
Then, a liquid containing a material to be the hole injection layer 8b is applied on each pixel electrode 8a surrounded by each opening 13a, and the substrate 10 is heated to dry the liquid to form a film. The resulting compound film becomes the hole injection layer 8b which is the first carrier transport layer.
Further, a liquid material containing a material to be the light emitting layer 8c is applied on each hole injection layer 8b surrounded by each opening 13a, and the whole substrate 10 is heated to dry the liquid material to form a film. The compound film becomes the light emitting layer 8c which is the second carrier transport layer.
A counter electrode 8 d is provided so as to cover the light emitting layer 8 c and the bank 13.
As shown in FIG. 7, the first insulating film 12 is not covered with the source electrode 5 h and the drain electrode 5 i of the switch transistor 5, and protrudes in a direction intersecting the direction in which the source electrode 5 h and the drain electrode 5 i face each other. An opening 5j is formed in a part of the boundary portion between the end portion of the protective film 5d and the semiconductor film 5b and the first insulating film 12. A material for forming the bank 13 is buried in the opening 5j. Similarly, in the first insulating film 12, the protective film 6d that is not covered with the source electrode 6h and the drain electrode 6i of the switch transistor 6 and protrudes in a direction intersecting the direction in which the source electrode 6h and the drain electrode 6i face each other. An opening 6j is formed at a part of the boundary between the end of the semiconductor film 6b and the first insulating film 12, and the opening 5j is filled with a material for forming the bank 13.

In the EL panel 1, the pixel electrode 8a, the substrate 10 and the second insulating film 11 are transparent, and light emitted from the light emitting layer 8c is transmitted through the pixel electrode 8a, the second insulating film 11 and the substrate 10. Exit. Therefore, the back surface of the substrate 10 becomes a display surface.
The display surface may be the opposite side instead of the substrate 10 side. In this case, the counter electrode 8d is a transparent electrode, the pixel electrode 8a is a reflective electrode, and light emitted from the light emitting layer 8c is transmitted through the counter electrode 8d and emitted.

The EL panel 1 is driven as follows to emit light.
In a state where a predetermined level of voltage is applied to all the voltage supply lines 4, the scanning driver sequentially applies voltages to the scanning lines 2, thereby sequentially selecting the scanning lines 2.
When each scanning line 2 is selected, if a voltage of a level corresponding to the gradation is applied to all the signal lines 3 by the data driver, the switch transistor 5 corresponding to the selected scanning line 2 is turned on. Therefore, a voltage of a level corresponding to the gradation is applied to the gate electrode 6a of the drive transistor 6.
The potential difference between the gate electrode 6a and the source electrode 6i of the drive transistor 6 is determined according to the voltage applied to the gate electrode 6a of the drive transistor 6, and the magnitude of the drain-source current in the drive transistor 6 is determined. The EL element 8 emits light with brightness according to the drain-source current.
Thereafter, when the selection of the scanning line 2 is released, the switch transistor 5 is turned off, so that charges according to the voltage applied to the gate electrode 6a of the driving transistor 6 are stored in the capacitor 7, and the driving transistor 6 The potential difference between the gate electrode 6a and the source electrode 6i is maintained.
For this reason, the drive transistor 6 keeps flowing the drain-source current having the same current value as that at the time of selection, and maintains the luminance of the EL element 8.

Next, a method for manufacturing thin film transistors such as the switch transistor 5 and the drive transistor 6 used as drive elements in the EL panel 1 will be described with reference to the explanatory diagrams shown in FIGS.
8 to 18 are process diagrams showing an example of the manufacturing process of the thin film transistor according to the present invention. This process diagram shows a cross-sectional portion along the line AA in the plan view in the drawing, a cross-sectional portion along the line BB in the plan view in the drawing, and the scanning line 2 and the voltage supply line 4 formed simultaneously. It is explanatory drawing which shows the cross-sectional part of the terminal pad T, and the outline of a manufacturing method is demonstrated with reference to these figures.
The thin film transistors shown in the process diagrams (FIGS. 8 to 18) are described as conceptual thin film transistors common to the switch transistor 5 and the drive transistor 6, although the switch transistor 5 and the drive transistor 6 are partially different in shape. .

First, a gate metal layer is deposited on the substrate 10 by sputtering and patterned by a photolithography method, an etching method, or the like to form a gate electrode 5a (6a) as shown in FIG. In the terminal pad T portion, the lower layer electrode T1 is formed together with the gate electrode 5a (6a) (gate electrode forming step).
The signal line 3 and the electrode 7a of the capacitor 7 are formed together with the gate electrode 5a (6a) (see FIGS. 5 and 6).

  Next, as shown in FIG. 9, a second insulating film 11 such as silicon nitride, a semiconductor layer 9b such as amorphous silicon that becomes the semiconductor film 5b (6b), a channel protective film and silicon nitride that becomes 5d (6d) are formed by plasma CVD. A protective insulating film 9d is continuously deposited to form three layers (three-layer film forming step).

  Next, as shown in FIG. 10, the protective insulating film 9d is patterned by a photolithography method, an etching method, or the like to form a channel protective film 5d (6d) that covers a region to be a channel in the semiconductor film 5b (6b) ( Protective film forming step).

Next, as shown in FIG. 11, an impurity semiconductor layer 9f to be impurity semiconductor films 5f and 5g (6f and 6g) is formed on the semiconductor layer 9b on which the channel protective film 5d (6d) is formed.
In the case of a p-type TFT, the p + Si impurity semiconductor layer 9f is formed by mixing an acceptor-type impurity such as diborane in SiH ₄ gas to form a plasma film. In the case of an n-type TFT, the n + Si impurity semiconductor layer 9f is formed by mixing a SiH ₄ gas with a donor-type impurity such as arsine or phosphine to form a plasma film.

Next, as shown in FIG. 12, the impurity semiconductor layer 9f and the semiconductor layer 9b are successively patterned by photolithography to form the impurity semiconductor films 5f and 5g (6f and 6g) and the island-shaped semiconductor film 5b (6b). Form (semiconductor film forming step).
Note that the impurity semiconductor films 5f and 5g (6f and 6g) are formed on the semiconductor film 5b (6b) so as to face each other with the channel protective film 5d (6d) interposed therebetween.

  Next, as shown in FIG. 13, the second insulating film 11 in the terminal pad T portion is etched to form a contact hole 11t, and the lower layer electrode T1 is exposed (electrode exposure step).

Next, as shown in FIG. 14, the impurity semiconductor films 5f, 5g (6f, 6g), the channel protective film 5d (6d), the semiconductor film 5b (6b), and the second insulating film 11 on the substrate 10 are formed. The covering metal film 9h is formed by sputtering (metal film forming step). In the terminal pad T portion, the metal film 9h is also formed on the lower layer electrode T1 in the contact hole 11t.
In this metal film formation step, the end surface of the semiconductor film 5b (6b) between the second insulating film 11 and the channel protective film 5d (6d) is in contact with the metal film 9h formed by sputtering. May be altered to have conductivity, and the altered conductive portion 5j (6j) may be generated. For example, the altered conductive portion 5j (6j) is a portion in which silicon in the semiconductor film 5b (6b) is transformed into silicide, which is a conductive compound.
The alteration to the conductive compound will be described. Specifically, for example, it is known that when aluminum and silicon are brought into contact at 400 ° C. or higher, aluminum diffuses into silicon and eutectifies. In the metal film forming step, the steady temperature of the end face of the semiconductor film 5b (6b) in contact with the metal film 9h formed by sputtering is about 200 ° C. at the highest and exceeds 400 ° C. Although the temperature does not increase, the kinetic energy of the sputtered particles jumping out of the target is more than 100 times higher than the kinetic energy of the vacuum-deposited particles. Therefore, the sputtered particles at the moment of collision with the semiconductor film 5b (6b) are extremely hot. (For example, 400 ° C. or higher). Therefore, it is considered that the sputtered particles (aluminum) instantaneously react with silicon to form a conductive compound such as silicide, and the altered conductive portion 5j (6j) may be generated.

Next, as shown in FIG. 15, the metal film 9h is patterned by photolithography to form the source electrode 5i (6i) and the drain electrode 5h (6h) on the pair of impurity semiconductor films 5f and 5g (6f, 6g). (Electrode layer forming step). At this time, as shown in FIG. 15, the ends of the channel protective film 5d (6d) and the semiconductor film 5b (6b) in the direction intersecting the direction in which the source electrode 5i (6i) and the drain electrode 5h (6h) face each other. The part protrudes. The metal film 9h in the terminal pad T portion is patterned to form the upper layer electrode T2 on the lower layer electrode T1. The lower layer electrode T1 and the upper layer electrode T2 serve as a terminal pad T.
The scanning line 2, the voltage supply line 4, and the electrode 7b of the capacitor 7 are formed together with the source electrode 5i (6i) and the drain electrode 5h (6h). The pixel electrode 8a is formed after the source electrode 5i (6i) and the drain electrode 5h (6h) are formed.

Next, as shown in FIG. 16, a source electrode 5i (6i) and a drain electrode 5h (6h), an impurity semiconductor film, an impurity semiconductor film 5f, 5g (6f, 6g), a channel protective film 5d (6d), and a semiconductor A first insulating film 12 covering the film 5b (6b) and the second insulating film 11 is formed (overcoat process). The first insulating film 12 is formed by depositing silicon nitride or the like by plasma CVD, as with the second insulating film 11.
Further, a photoresist 15 is formed on the first insulating film 12. In this photoresist 15, the boundary between the first insulating film 12 and the channel protective film 5d (6d) protruding in a direction intersecting with one direction in which the source electrode 5i (6i) and the drain electrode 5h (6h) face each other An opening 15j is formed at a location corresponding to the portion. An opening 15t is formed in the terminal pad T portion of the photoresist 15.
Note that an opening is also formed in a portion of the photoresist 15 corresponding to the pixel electrode 8a.

  Next, as shown in FIG. 17, the source electrode 5i (6i) and the drain electrode 5h (6h) are not covered with the source electrode 5i (6i) and the drain electrode 5h (6h) in the first insulating film 12. The boundary portion between the channel protection film 5d (6d) protruding in the direction intersecting the opposite one direction and the first insulating film 12 is etched by dry etching to form an opening 12j, and the semiconductor film 5b (6b) ) To expose a part of the altered conductive portion 5j (6j) corresponding to the end portion (exposure step). At this time, in the terminal pad T portion, the first insulating film 12 on the upper electrode T2 is simultaneously etched to form an opening 12t, and a part of the upper electrode T2 is exposed. At this time, the portion of the first insulating film 12 corresponding to the pixel electrode 8a is also etched at the same time so that the pixel electrode 8a is exposed. Here, the step of etching the first insulating film 12 on the upper electrode T2 in the terminal pad T portion and the step of etching the portion corresponding to the pixel electrode 8a in the first insulating film 12 are also performed in the conventional manufacturing method. Since the opening 12j can be formed at the same time as these etching steps, the number of steps up to here is not increased.

Next, as shown in FIG. 18, the dry etching condition is changed to the condition for etching the semiconductor film, and the altered conductive portion 5j (6j) corresponding to the end of the exposed semiconductor film 5b (6b) is dried. Etching is removed by etching (edge removal step). In the above description, the exposure process for forming the opening 12j and the removal of the altered conductive portion 5j (6j) (end removal process) are separate processes. For example, the first insulating film 12 is set by dry etching condition setting. If the etching of the altered conductive portion 5j (6j) at the end of the semiconductor film 5b (6b) can be performed simultaneously, these may be performed in a single step.
It should be noted that at least a part of the altered conductive portion 5j (6j) may be removed and the source electrode 5i (6i) and the drain electrode 5h (6h) may be separated in one direction facing each other. The altered conductive portion 5j (6j) is divided, so that the source-drain leakage current path along the end face of the semiconductor film 5b (6b) is cut off.

  In this way, a part of the altered conductive portion 5j (6j) that has been altered so that the end portion of the semiconductor film 5b (6b) has conductivity is removed by etching, and the leakage current path is blocked, thereby further increasing the leakage current. Thin film transistors (switch transistor 5 and drive transistor 6) with reduced current are manufactured.

Then, a photosensitive resin such as polyimide is formed on the first insulating film 12 after removing the photoresist 15 to form the bank 13, and hole injection is performed on the pixel electrode 8 a in the opening 13 a of the bank 13. The EL element 8 is configured by forming the layer 8b and the light emitting layer 8c and further forming the counter electrode 8d, and the EL panel 1 is manufactured (see FIG. 5).
In addition, as shown in FIG. 7, in order to remove at least a part of the altered conductive portion 5j (6j), the opening 12j formed to block the leakage current path is filled with members constituting the bank 13. Therefore, the bank 13 is stably arranged on the first insulating film 12.

As described above, in the EL panel 1, the thin film transistors such as the switch transistor 5 and the drive transistor 6 used as drive elements have been altered so that the end portions of the semiconductor film 5b (6b) have conductivity. By removing a part of the altered conductive portion 5j (6j), the leakage current path between the source and the drain along the end face of the semiconductor film 5b (6b) is blocked, so that the leakage current can be further reduced. It has been.
The EL panel 1 in which the thin film transistor in which the leakage current is reduced is used as the drive element (switch transistor 5 and drive transistor 6) can improve the display image quality, so that a good image display is possible.

In addition, when there is a leakage current in the thin film transistor, if the leakage current can be eliminated, the EL panel and the liquid crystal panel have a considerable effect on improving the characteristics, but the EL panel reduces the leakage current. It is considered that the effect of improving the display image quality due to is great.
This is because, in the case of a liquid crystal panel, the liquid crystal element itself has capacitance, and gradation control is performed by holding charges corresponding to the gradation signal voltage in the storage capacitor Cs and the liquid crystal capacitor Clc via the drive transistor. Therefore, even if there is a leakage current in the thin film transistor that constitutes the driving transistor, there is no significant influence.
On the other hand, in the EL panel, since the gradation is controlled by controlling the current flowing between the source and the drain by applying the gradation signal voltage to the gate of the driving transistor, there is a leakage current in the thin film transistor forming the driving transistor. If so, the gradation control is significantly affected. Thus, the EL panel is more susceptible to the leakage current of the thin film transistor than the liquid crystal panel.
Therefore, it can be said that application of the present invention to a thin film transistor used as a driving element in an EL panel is useful in improving display image quality.

  The application of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.

1 EL panel 5 Switch transistor (thin film transistor)
6 Drive transistor (thin film transistor)
5a, 6a Gate electrode 5b, 6b Semiconductor film 5d, 6d Channel protective film (protective film)
5f, 6f Impurity semiconductor film 5g, 6g Impurity semiconductor film 5h, 6h Drain electrode 5i, 6i Source electrode 5j, 6j Altered conductive portion 8 EL element 9b Semiconductor layer 9d Protective insulating film 9f Impurity semiconductor layer 9h Metal film 10 Substrate 11 Second Insulating film 12 First insulating film 12j Contact hole 12t Contact hole 13 Bank 15 Photoresist 15j Opening 15t Opening T1 Lower layer electrode T2 Upper layer electrode T Terminal pad

Claims (6)

A semiconductor layer forming step of forming a semiconductor layer containing silicon on the upper surface side of the substrate;
A semiconductor film forming step of patterning the semiconductor layer to form an island-shaped semiconductor film;
A metal film forming step of forming a metal film in contact with a side surface of the semiconductor film on the substrate and covering the semiconductor film;
Patterning the metal film, forming an electrode layer on the semiconductor film, and forming an electrode layer projecting an end of the semiconductor film from the electrode layer;
An overcoat step of forming a first insulating film covering the electrode layer and the semiconductor film;
Forming an opening in a portion of the first insulating film corresponding to a part of a boundary portion between the side surface of the end of the semiconductor film protruding from the electrode layer and the first insulating film; An exposure process for exposing a part of the end; and
An edge removing step of removing a part of the exposed edge of the semiconductor film by etching through the opening;
A method for producing a thin film transistor, comprising: In the exposing step, the semiconductor film is formed along the side surface of the semiconductor film in contact with the metal film at the time of forming the metal film in the metal film forming step at the end of the semiconductor film. Expose part of the area transformed into a conductive compound,
2. The method of manufacturing a thin film transistor according to claim 1, wherein the edge removing step removes a part of a region of the semiconductor film that has changed into the conductive compound. 3. The semiconductor layer forming step includes a step of forming a protective insulating film on the semiconductor layer,
After the semiconductor film forming step, the protective insulating film is patterned to form a protective film forming step of forming a protective film that covers a region to be a channel in the semiconductor layer,
In the semiconductor film forming step, an impurity semiconductor layer is formed on the semiconductor layer on which the protective film is formed, the impurity semiconductor layer is patterned, and a pair of impurity semiconductor films facing each other with the protective film interposed therebetween Including an impurity semiconductor film forming step of forming
The metal film forming step includes a step of forming the metal film so as to contact the side surfaces of the impurity semiconductor film, the protective film, and the semiconductor film and cover the semiconductor film,
3. The method of manufacturing a thin film transistor according to claim 2, wherein the electrode layer forming step includes a step of patterning the metal film to form a source electrode and a drain electrode on the pair of impurity semiconductor films. Before the semiconductor layer forming step, a gate electrode forming step of forming a gate electrode and a lower layer electrode on the upper surface of the substrate,
The semiconductor layer forming step includes: forming a second insulating film on the upper surface of the substrate so as to cover the gate electrode and the lower layer electrode formed in the gate electrode forming step; Forming the semiconductor layer, and
After the semiconductor film forming step, the terminal pad portion includes an electrode exposing step of etching the second insulating film to expose the lower layer electrode,
The metal film deposition step includes the step of depositing the metal film on the second insulating film and the exposed lower electrode,
The electrode layer forming step forms the upper layer electrode on the exposed lower layer electrode by patterning the metal film on the exposed lower layer electrode simultaneously with the formation of the electrode layer in the terminal pad portion. Including steps,
In the overcoat step, the first insulating film is formed so as to cover the upper electrode,
The exposing step includes a step of exposing at least a part of the upper layer electrode by etching the first insulating film on the upper layer electrode simultaneously with the formation of the opening in the terminal pad portion. A method for producing a thin film transistor according to claim 3. A semiconductor film containing silicon formed in an island shape on the upper surface side of the substrate;
An electrode layer made of a metal film and formed on the upper part of the semiconductor film in a shape in which an end of the semiconductor film protrudes;
A first insulating film covering the electrode layer and the semiconductor film;
A partition formed on the first insulating film;
With
The semiconductor film has a cutout portion from which a part of the semiconductor film is removed at the end portion, and the semiconductor film is formed of the metal film when forming the metal film forming the electrode layer in the cutout portion. In contact with the film, a region transformed into a conductive compound formed along the side surface of the semiconductor film is divided ,
The first insulating film has an opening formed at a position corresponding to the notch,
A thin film transistor , wherein the opening is filled with a material for forming the partition . A protective film made of a protective insulating film formed on a region to be a channel of the semiconductor film;
On the semiconductor film, a pair of impurity semiconductor films formed at positions facing each other with the protective film interposed therebetween,
With
The electrode layer is formed on the pair of impurity semiconductor films to form a source electrode and a drain electrode,
6. The thin film transistor according to claim 5 , wherein the first insulating film covers the source and drain electrodes, the impurity semiconductor film, the protective film, and the semiconductor film.

Images