JP2010212328A5 - - Google Patents

Download PDF

Info

Publication number
JP2010212328A5
JP2010212328A5 JP2009054624A JP2009054624A JP2010212328A5 JP 2010212328 A5 JP2010212328 A5 JP 2010212328A5 JP 2009054624 A JP2009054624 A JP 2009054624A JP 2009054624 A JP2009054624 A JP 2009054624A JP 2010212328 A5 JP2010212328 A5 JP 2010212328A5
Authority
JP
Japan
Prior art keywords
film
semiconductor
forming
electrode
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009054624A
Other languages
Japanese (ja)
Other versions
JP2010212328A (en
JP5428404B2 (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2009054624A priority Critical patent/JP5428404B2/en
Priority claimed from JP2009054624A external-priority patent/JP5428404B2/en
Publication of JP2010212328A publication Critical patent/JP2010212328A/en
Publication of JP2010212328A5 publication Critical patent/JP2010212328A5/ja
Application granted granted Critical
Publication of JP5428404B2 publication Critical patent/JP5428404B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (7)

基板の上面側にシリコンを含む半導体層を形成する半導体層形成工程と、
前記半導体層をパターニングして島状の形状を有する半導体膜を形成する半導体膜形成工程と、
前記基板上における前記半導体膜の側面に接して該半導体膜を覆う金属膜を成膜する金属膜成膜工程と、
前記金属膜をパターニングして、前記半導体膜上に電極層を形成し、該電極層より前記半導体膜の端部を突出させる電極層形成工程と、
前記電極層及び前記半導体膜を覆う第一絶縁膜を成膜するオーバーコート工程と、
前記第一絶縁膜の、前記電極層から突出した前記半導体膜の端部の側面と前記第一絶縁膜との境界部分の一部に対応する箇所に開口部を形成して、前記半導体膜の端部の一部を露出させる露出工程と、
露出された前記半導体膜の端部の一部を、前記開口部を介してエッチングして取り除く端部除去工程と、
を備えることを特徴とする薄膜トランジスタの製造方法。
A semiconductor layer forming step of forming a semiconductor layer containing silicon on the upper surface side of the substrate;
A semiconductor film forming step of patterning the semiconductor layer to form an island-shaped semiconductor film;
A metal film forming step of forming a metal film in contact with a side surface of the semiconductor film on the substrate and covering the semiconductor film;
Patterning the metal film, forming an electrode layer on the semiconductor film, and forming an electrode layer projecting an end of the semiconductor film from the electrode layer;
An overcoat step of forming a first insulating film covering the electrode layer and the semiconductor film;
Forming an opening in a portion of the first insulating film corresponding to a part of a boundary portion between the side surface of the end of the semiconductor film protruding from the electrode layer and the first insulating film; An exposure process for exposing a part of the end; and
An edge removing step of removing a part of the exposed edge of the semiconductor film by etching through the opening;
A method for producing a thin film transistor, comprising:
前記露出工程は、前記半導体膜の端部における、前記金属膜成膜工程において前記半導体膜が前記金属膜の成膜時に該金属膜と接触して、前記半導体膜の側面に沿って形成された導電性化合物に変質した領域の一部を露出させ、
前記端部除去工程は、前記半導体膜の前記導電性化合物に変質した領域の一部を取り除くことを特徴とする請求項1に記載の薄膜トランジスタの製造方法。
In the exposing step, the semiconductor film is formed along the side surface of the semiconductor film in contact with the metal film at the time of forming the metal film in the metal film forming step at the end of the semiconductor film. Expose part of the area transformed into a conductive compound,
2. The method of manufacturing a thin film transistor according to claim 1, wherein the edge removing step removes a part of a region of the semiconductor film that has changed into the conductive compound. 3.
前記半導体層形成工程は、前記半導体層上に保護絶縁膜を形成する工程を含み、
前記半導体膜形成工程の後に、前記保護絶縁膜をパターニングして、前記半導体層におけるチャネルとなる領域を覆う保護膜を形成する保護膜形成工程を備え、
前記半導体膜形成工程は、前記保護膜が形成された前記半導体層上に、不純物半導体層を成膜し、前記不純物半導体層をパターニングして、前記保護膜を挟んで対向する一対の不純物半導体膜を形成する不純物半導体膜形成工程を含み、
前記金属膜成膜工程は、前記金属膜を前記不純物半導体膜と前記保護膜と前記半導体膜の側面に接して該半導体膜を覆うように成膜する工程を含み、
前記電極層形成工程は、前記金属膜をパターニングして、前記一対の不純物半導体膜上にソース電極及びドレイン電極を形成する工程を含むことを特徴とする請求項に記載の薄膜トランジスタの製造方法。
The semiconductor layer forming step includes a step of forming a protective insulating film on the semiconductor layer,
After the semiconductor film forming step, the protective insulating film is patterned to form a protective film forming step of forming a protective film that covers a region to be a channel in the semiconductor layer,
In the semiconductor film forming step, an impurity semiconductor layer is formed on the semiconductor layer on which the protective film is formed, the impurity semiconductor layer is patterned, and a pair of impurity semiconductor films facing each other with the protective film interposed therebetween Including an impurity semiconductor film forming step of forming
The metal film forming step includes a step of forming the metal film so as to contact the side surfaces of the impurity semiconductor film, the protective film, and the semiconductor film and cover the semiconductor film,
3. The method of manufacturing a thin film transistor according to claim 2 , wherein the electrode layer forming step includes a step of patterning the metal film to form a source electrode and a drain electrode on the pair of impurity semiconductor films.
前記半導体層形成工程の前に、前記基板の上面にゲート電極及び下層電極を形成するゲート電極形成工程を備え、
前記半導体層形成工程は、前記基板の上面に、前記ゲート電極形成工程により形成された前記ゲート電極及び前記下層電極を覆って第二絶縁膜を成膜する工程と、該第二絶縁膜上に前記半導体層を形成する工程と、を含み、
前記半導体膜形成工程の後に、端子パッド部において、前記第二絶縁膜をエッチングして、前記下層電極を露出させる電極露出工程を備え、
前記金属膜成膜工程は、前記金属膜を前記第二絶縁膜上及び前記露出された下層電極上に成膜する工程を含み、
前記電極層形成工程は、前記端子パッド部において、前記電極層の形成と同時に、前記露出された下層電極上の前記金属膜をパターニングして、前記露出された下層電極上に上層電極を形成する工程を含み、
前記オーバーコート工程は、前記第一絶縁膜を前記上層電極も覆うように成膜し、
前記露出工程は、前記端子パッド部において、前記開口部の形成と同時に、前記上層電極上の前記第一絶縁膜をエッチングして、該上層電極の少なくとも一部を露出させる工程を含むことを特徴とする請求項に記載の薄膜トランジスタの製造方法。
Before the semiconductor layer forming step, a gate electrode forming step of forming a gate electrode and a lower layer electrode on the upper surface of the substrate,
The semiconductor layer forming step includes: forming a second insulating film on the upper surface of the substrate so as to cover the gate electrode and the lower layer electrode formed in the gate electrode forming step; Forming the semiconductor layer, and
After the semiconductor film forming step, the terminal pad portion includes an electrode exposing step of etching the second insulating film to expose the lower layer electrode,
The metal film deposition step includes the step of depositing the metal film on the second insulating film and the exposed lower electrode,
The electrode layer forming step forms the upper layer electrode on the exposed lower layer electrode by patterning the metal film on the exposed lower layer electrode simultaneously with the formation of the electrode layer in the terminal pad portion. Including steps,
In the overcoat step, the first insulating film is formed so as to cover the upper electrode,
The exposing step includes a step of exposing at least a part of the upper layer electrode by etching the first insulating film on the upper layer electrode simultaneously with the formation of the opening in the terminal pad portion. A method for producing a thin film transistor according to claim 3 .
基板の上面側に島状に形成されたシリコンを含む半導体膜と、
金属膜からなり、前記半導体膜の上部に、該半導体膜の端部を突出させた形状に形成された電極層と、
を備え、
前記半導体膜は、前記端部において、該半導体膜の一部が取り除かれた切り欠き部を有し、該切り欠き部において、前記電極層をなす前記金属膜の形成時に前記半導体膜が前記金属膜と接触して、前記半導体膜の側面に沿って形成された導電性化合物に変質した領域が分断されていることを特徴とする薄膜トランジスタ。
A semiconductor film containing silicon formed in an island shape on the upper surface side of the substrate;
An electrode layer made of a metal film and formed on the upper part of the semiconductor film in a shape in which an end of the semiconductor film protrudes;
With
The semiconductor film has a cutout portion from which a part of the semiconductor film is removed at the end portion, and the semiconductor film is formed of the metal film when forming the metal film forming the electrode layer in the cutout portion. A thin film transistor, wherein a region transformed into a conductive compound formed along a side surface of the semiconductor film is divided in contact with the film.
前記電極層及び前記半導体膜を覆う第一絶縁膜と、
前記第一絶縁膜上に形成された隔壁と、
前記第一絶縁膜の前記切り欠き部に対応する位置に形成された開口部と、
を備え、
前記開口部に、前記隔壁を形成する材料が充填されていることを特徴とする請求項に記載の薄膜トランジスタ。
A first insulating film covering the electrode layer and the semiconductor film;
A partition formed on the first insulating film;
An opening formed at a position corresponding to the notch of the first insulating film;
With
6. The thin film transistor according to claim 5 , wherein the opening is filled with a material for forming the partition.
前記半導体膜のチャネルとなる領域の上に形成された、保護絶縁膜からなる保護膜と、
前記半導体膜上に、前記保護膜を挟んで対向する位置に形成された一対の不純物半導体膜と、
を備え、
前記電極層は、前記一対の不純物半導体膜上に形成されて、ソース電極及びドレイン電極をなし、
前記第一絶縁膜は、前記ソース電極及びドレイン電極と前記不純物半導体膜と前記保護膜と前記半導体膜を覆っていることを特徴とする請求項に記載の薄膜トランジスタ。
A protective film made of a protective insulating film formed on a region to be a channel of the semiconductor film;
On the semiconductor film, a pair of impurity semiconductor films formed at positions facing each other with the protective film interposed therebetween,
With
The electrode layer is formed on the pair of impurity semiconductor films to form a source electrode and a drain electrode,
The thin film transistor according to claim 6 , wherein the first insulating film covers the source and drain electrodes, the impurity semiconductor film, the protective film, and the semiconductor film.
JP2009054624A 2009-03-09 2009-03-09 THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR Expired - Fee Related JP5428404B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009054624A JP5428404B2 (en) 2009-03-09 2009-03-09 THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009054624A JP5428404B2 (en) 2009-03-09 2009-03-09 THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR

Publications (3)

Publication Number Publication Date
JP2010212328A JP2010212328A (en) 2010-09-24
JP2010212328A5 true JP2010212328A5 (en) 2011-11-17
JP5428404B2 JP5428404B2 (en) 2014-02-26

Family

ID=42972227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009054624A Expired - Fee Related JP5428404B2 (en) 2009-03-09 2009-03-09 THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR

Country Status (1)

Country Link
JP (1) JP5428404B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5595392B2 (en) * 2010-09-29 2014-09-24 パナソニック株式会社 EL display panel, EL display device, and method of manufacturing EL display panel
WO2012042567A1 (en) * 2010-09-29 2012-04-05 パナソニック株式会社 El display panel, el display device and method for producing el display panel

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3412277B2 (en) * 1994-08-23 2003-06-03 カシオ計算機株式会社 Thin film transistor and method of manufacturing the same
JP3865818B2 (en) * 1996-04-16 2007-01-10 三菱電機株式会社 Manufacturing method of active matrix substrate
JP3801687B2 (en) * 1996-06-06 2006-07-26 三菱電機株式会社 Thin film transistor and method for manufacturing the same
JP3323889B2 (en) * 1996-10-28 2002-09-09 三菱電機株式会社 Method for manufacturing thin film transistor
JPH10270701A (en) * 1997-03-27 1998-10-09 Advanced Display:Kk Thin film transistor and its production
JP2000214485A (en) * 1999-01-21 2000-08-04 Toshiba Corp Array substrate and liquid crystal display elements
JP5212683B2 (en) * 2007-03-20 2013-06-19 カシオ計算機株式会社 Transistor panel and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP6437574B2 (en) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE
JP2011044698A5 (en) Method for manufacturing semiconductor device
KR102094847B1 (en) Display substrate having a thin film transistor and method of manufacturing the same
JP2009033134A5 (en)
WO2013131380A1 (en) Array substrate, manufacturing method thereof and display device thereof
JP2007318112A5 (en)
WO2014127579A1 (en) Thin film transistor array substrate, manufacturing method and display device
JP2006352087A5 (en)
JP2008294408A5 (en)
TW200943421A (en) Method for manufacturing semiconductor device
JP2009124121A5 (en)
JP2009026800A5 (en)
JP2009027002A5 (en)
TW200727487A (en) Structure of thin film transistor array and method for making the same
TWI268615B (en) Methods for fabricating array substrate and thin film transistor array substrate
WO2015055030A1 (en) Array substrate, manufacturing method therefor and display device
JP2010040951A5 (en)
JP2015529017A5 (en)
JP2008182055A5 (en)
WO2013181915A1 (en) Tft array substrate, method of fabricating same, and display device
JP2010502013A5 (en)
JP2005109389A5 (en)
JP2010212328A5 (en)
TW201515234A (en) Active device and manufacturing method thereof
JP2009520364A5 (en)