JP5428208B2 - Semiconductor device - Google Patents

Description

  According to the present invention, a main semiconductor element that supplies a load current to a load, and a sense semiconductor element that is connected in parallel with the main semiconductor element and forms a current mirror circuit together with the main semiconductor element to detect the load current are the same. The present invention relates to a semiconductor device provided on a semiconductor substrate.

  Conventionally, in this type of semiconductor device, a current proportional to the ratio of the number of cells of both semiconductor elements flows through the main semiconductor element and the sense semiconductor element. For example, assuming that the number of cells constituting the main semiconductor element (hereinafter referred to as main cell) is 10,000 and the number of cells constituting the sense semiconductor element (hereinafter referred to as sense cell) is 10, the current mirror ratio is 1000: 1. Flows.

  In the above configuration, since a large amount of current flows through the main semiconductor element, its on-resistance has a very small resistance value compared to the on-resistance of the sense semiconductor element. For this reason, the resistance value ratio between the wiring resistance and the on-resistance differs between the main semiconductor element and the sense semiconductor element. For example, if the on-resistance and wiring resistance of the main semiconductor element are 110 mΩ and 40 mΩ, respectively, and the on-resistance and wiring resistance of the sense semiconductor element are 110 and 40 mΩ, respectively, the main semiconductor element is the sense semiconductor element. The resistance ratio of the wiring resistance is higher than

  Further, metal wiring, for example, Al wiring, is usually used for wiring in a semiconductor element such as a MOS transistor. For example, the temperature characteristics of the Al wiring and the MOS transistor are different from about 3000 ppm / T in the former and about 4500 ppm / T in the latter. For this reason, due to the difference in the resistance value ratio described above, the accuracy of the current mirror circuit ratio varies depending on the temperature, and there is a problem that the current detection accuracy deteriorates.

  Therefore, as a semiconductor device that solves the problem, a double-diffused field effect transistor (DMOS, Double-diffused MOSFET) described in Patent Document 1 has been proposed. In this DMOS, a main DMOS that supplies a load current to a load and a sense DMOS that detects the load current are formed in the same semiconductor substrate. The main and sense DMOSs share a drain terminal and a gate terminal, and constitute a current mirror circuit.

A source terminal and a Kelvin terminal are connected to the source of the main DMOS, and a mirror terminal for current detection is connected to the source of the sense DMOS. A resistor is connected between the source of the sense DMOS and the mirror terminal. This resistor is configured by connecting an electrode to an n− type diffusion layer formed on the outer peripheral surface portion of the sense DMOS.
Then, by setting the resistance component of the drain region and the temperature coefficient of resistance (change in resistance value with respect to temperature) to be the same, the dependence of the on-resistance ratio (current mirror ratio) on the gate voltage and channel temperature is reduced.

Japanese Patent No. 3237612 (23rd paragraph, FIG. 18).

  However, in the semiconductor device described in Patent Document 1, a resistor connected between the source and the mirror terminal of the sense DMOS has an electrode connected to an n− type diffusion layer formed on the outer peripheral surface portion of the sense DMOS. Since the structure is configured, an occupation region for disposing the resistor is required on the outer edge of the element, which causes a problem that the size of the semiconductor device is increased in the lateral direction.

  Accordingly, the present invention has been made to solve the above-described problem, and reduces the on-resistance ratio error between the main and sense DMOSs without increasing the size of the semiconductor device, thereby improving the current detection accuracy. With the goal.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a first conductive type first semiconductor layer (4) and a second conductive type formed on a surface layer portion of the first semiconductor layer. The second semiconductor layer (5), the third semiconductor layer (7) of the first conductivity type formed in the surface layer portion of the second semiconductor layer, and the surface layer portion of the second semiconductor layer. A fourth conductivity type fourth semiconductor layer (6) having an impurity concentration higher than that of the second semiconductor layer, and a gate electrode (8) formed from a surface layer portion of the third semiconductor layer via a gate insulating film, The first electrode (10) electrically connected to the third and fourth semiconductor layers through the interlayer insulating film and the first electrode is configured to pass a current between the first electrode by a voltage applied to the gate electrode. It consists of a plurality of cells having two electrodes (2), and supplies a load current (IS) to a load (70) A main semiconductor element (20) connected in parallel with the main semiconductor element for detecting the load current, and forming a current mirror circuit together with the main semiconductor element, the number of cells constituting the main semiconductor element In a semiconductor device (1) comprising a sense semiconductor element (30) constituted by a small number of cells, the resistance value of the third semiconductor layer constituting the cell is greater than that of each cell constituting the main semiconductor element. The technical means that each cell constituting the sense semiconductor element is larger is used.

The resistance value (so-called source resistance) of the third semiconductor layer (7) constituting the cell is larger in each cell constituting the sense semiconductor element (30) than in each cell constituting the main semiconductor element (20). That is, unlike the conventional case, it is not necessary to provide an occupied region for arranging the resistor at the outer edge of the sense semiconductor element.
Therefore, the error of the on-resistance ratio between the main and sense semiconductor elements can be reduced and the current detection accuracy can be increased without increasing the size of the semiconductor device (1).

  According to a second aspect of the present invention, in the semiconductor device (1) according to the first aspect, the third semiconductor layer (7) and the first electrode (10) constituting the cell are electrically connected. The technical means is used in which each cell constituting the sense semiconductor element (30) has a smaller area (11) than the cells constituting the main semiconductor element (20).

When the region (11) where the third semiconductor layer (7) and the first electrode (10) are electrically connected, that is, the so-called contact area is reduced, the resistance value of the third semiconductor layer can be increased.
Therefore, by making the contact area with the first electrode of the third semiconductor layer in each cell of the sense semiconductor element (30) smaller than each cell of the main semiconductor element (20), each cell constituting the sense semiconductor element is arranged. The resistance value of the third semiconductor layer can be made larger than each cell constituting the main semiconductor element.

  According to a third aspect of the present invention, in the semiconductor device (1) according to the first or second aspect, the planar shape of the surface layer portion of the gate electrode (8) constituting the adjacent cell is a stripe shape. Use technical means.

  Since the planar shape of the surface layer portion of the gate electrode (8) constituting the adjacent cell is a stripe shape, the fluctuation of the threshold voltage in the cell is small, so that the ON resistance ratio error between the main and sense semiconductor elements is reduced. The current detection accuracy can be further increased by further reducing the current detection accuracy.

  According to a fourth aspect of the present invention, in the semiconductor device (1) according to the second aspect, a plurality of the fourth semiconductor layers (6) are formed in each cell, and the cells adjacent to each other are formed in each cell. The area of the region (11) in which the third semiconductor layer (7) and the first electrode (10) between the fourth semiconductor layers are electrically connected is larger than that of the main semiconductor element (20). The technical means that the element (30) is smaller is used.

When the region (11) in which the third semiconductor layer (7) between the fourth semiconductor layers (6) adjacent to each other in the cell and the first electrode (10) are electrically connected, the so-called contact area is reduced, the third The resistance value of the semiconductor layer can be increased.
Therefore, in each cell of the sense semiconductor element (30), the contact area between the third semiconductor layer (7) and the first electrode (10) between the fourth semiconductor layers (6) is larger than that of each cell of the main semiconductor element (20). The resistance value of the third semiconductor layer of each cell constituting the sense semiconductor element can be made larger than that of each cell constituting the main semiconductor element.

  In the invention according to claim 5, in the semiconductor device (1) according to claim 1 or 2, the planar shape of the region surrounded by the surface layer portion of the gate electrode (8) constituting the adjacent cell is Use technical means of polygons.

  Since the space can be reduced by combining the sides of the cell, the degree of cell integration can be increased.

According to a sixth aspect of the present invention, in the semiconductor device (1) according to the fifth aspect, the third semiconductor layer (7) and the first electrode (10) in each cell constituting the sense semiconductor element (30). ) Are electrically connected to each other, and the region (11) is formed in a region corresponding to a side portion excluding a region corresponding to a corner portion of an outer edge of the polygonal planar cell region. The technical means is used.

  It is known that the threshold voltage is higher in the side portion of the cell where the crystal plane orientation is higher than in the lower side portion. Further, when forming the second semiconductor layer (5) by diffusing impurities, the concentration of the impurity diffused in the lateral direction becomes thinner at the corner than at the side of the cell due to the two-dimensional effect. For this reason, the impurity concentration in the channel region formed by the second semiconductor layer and the third semiconductor layer (7) in contact with the second semiconductor layer is lower at the corner than at the side of the cell, and the threshold voltage is reduced. It is also known that corners are lower than cell edges.

Accordingly, the region where the third semiconductor layer and the first electrode (10) in each cell constituting the sense semiconductor element (30) are electrically connected is defined as the outer edge of the polygonal planar cell region. The third semiconductor layer and the first electrode (10) are formed in a region corresponding to the side portion excluding a region corresponding to the corner portion, that is, a region having a high threshold voltage (region having a low current density). Since the distance between the electrically connected region and the region with low threshold voltage (region with high current density) can be increased, the resistance value of the third semiconductor layer can be increased. it can.
According to a seventh aspect of the present invention, in the semiconductor device (1) according to the fifth aspect, the third semiconductor layer (7) and the first electrode (10) in each cell constituting the sense semiconductor element (30). ) Are electrically connected to the region (11) excluding the region corresponding to the side of the crystal plane orientation where the threshold voltage is low, among the outer edges of the polygonal planar cell region The technical means of forming in the area | region corresponding to the side part of the crystal plane orientation to which the said threshold voltage becomes high is used.

According to an eighth aspect of the present invention, in the semiconductor device (1) according to any one of the first to seventh aspects, the third semiconductor layer (7) and the fourth semiconductor layer (6) in each cell. The technical means that the size of the surface area of the portion in contact with is different between the main semiconductor element (20) and the sense semiconductor element (30) is used.

By changing the surface area of the portion where the third semiconductor layer (7) and the fourth semiconductor layer (6) are in contact, the contact area between the third semiconductor layer and the first electrode (10) can be changed. Therefore, the resistance value of the third semiconductor layer can be changed.
Therefore, the surface area of the portion where the third semiconductor layer (7) and the fourth semiconductor layer (6) of each cell constituting the sense semiconductor element are in contact with each cell of the main semiconductor element (20) is different. Thus, the resistance value of the third semiconductor layer of each cell constituting the sense semiconductor element (30) can be adjusted.

According to a ninth aspect of the present invention, in the semiconductor device (1) according to any one of the first to eighth aspects, the third semiconductor layer (30) of each cell constituting the sense semiconductor element (30). 7) The technical means that the region (12) where the first electrode is not formed is arranged in the remaining part of the surface layer part by forming the first electrode on a part of the surface layer part of 7). Use.

If the region (12) where the first electrode (10) is not formed is arranged in the surface layer portion of the third semiconductor layer (7), the contact area between the third semiconductor layer and the first electrode can be reduced. The resistance value of the third semiconductor layer can be increased.
Accordingly, in each cell of the sense semiconductor element (30), each cell constituting the sense semiconductor element is arranged by disposing the region (12) where the first electrode (10) is not formed in the surface layer portion of the third semiconductor layer (7). The resistance value of the third semiconductor layer can be adjusted.

According to a tenth aspect of the present invention, in the semiconductor device (1) according to any one of the first to ninth aspects, the first conductivity type having a lower impurity concentration than the third semiconductor layer (7). The technical means that the fifth semiconductor layer (13) is formed in the third semiconductor layer of each cell constituting the sense semiconductor element (30) is used.

  By forming the first conductivity type fifth semiconductor layer (13) having a lower impurity concentration than the third semiconductor layer (7) in the third semiconductor layer of each cell constituting the sense semiconductor element (30), The adjustment range of the resistance value of the three semiconductor layers can be expanded.

In the invention according to claim 1 1, constituting the semiconductor device according to any one of claims 1 to 10 (1), said main semiconductor element (20) and sense the semiconductor elements (30) each A back electrode film (D) composed of a plurality of layers connected to the second electrode (2) of the cell is formed on the back surface of the semiconductor substrate, and the range corresponding to the sense semiconductor element in the back electrode film A technical means is used in which a region (D1) in which one or more layers of the back electrode film are not formed is disposed.

In the second electrode film (D), a region (D1) where one or more layers of the second electrode film are not formed is arranged in a range corresponding to the sense semiconductor element (30). 30), the resistance value between the first electrode (10) and the second electrode film of each cell can be increased.
Therefore, the resistance value of the sense semiconductor element can be adjusted.

In the invention according to claim 1 2, in the semiconductor device according to any one of claims 1 to 1 1 (1), the first electrode of each cell constituting the main semiconductor element (20) A main first electrode film (21) formed by connecting (10) and a first electrode film (31) formed by connecting the first electrode of each cell constituting the sense semiconductor element (30). Is used on the surface layer portion of the semiconductor substrate.

In the invention according to claim 1 3, in the semiconductor device according to claim 1 2 (1), a main terminal (S) connected to said main-side first electrode film (21), the said sensing side A sense-side terminal (M) connected to one electrode film (31); and a voltage detection terminal (K) connected to a location different from the main-side terminal in the main-side first electrode film. The sense-side terminal and the voltage detection terminal are configured to be connectable to a current detection circuit (50) for detecting a current flowing through the sense semiconductor element, and a wiring resistance value of the sense semiconductor element (30) ( Rc) and a wiring resistance value (Rc + Rd) obtained by adding together the wiring resistance value (Rd) between the sense side terminal and the current detection circuit gives the wiring resistance value (Rb) between the main side terminal and the voltage detection terminal. The main side Using technical means to become configured to be substantially equal to the wiring resistance value obtained by subtracting from the wiring resistance value (Ra + Rb) of the child.

  A wiring resistance value (Rc + Rd) obtained by adding the wiring resistance value (Rc) of the sense semiconductor element and the wiring resistance value (Rd) between the sense side terminal (M) and the current detection circuit (50) is the main side terminal (S ) And the wiring resistance value (Rb) between the voltage detection terminals (K) and the wiring resistance value (Ra) obtained by subtracting the wiring resistance value (Ra + Rb) of the main terminal from the main and Since an error in the on-resistance ratio (current mirror ratio) between the sense semiconductor elements can be reduced, current detection accuracy can be increased.

In the invention described in claim 1 4, claim 1 2 or claim 1 in third semiconductor device according to (1), the sense-side first electrode layer (31) electrically connected to to sense terminal ( M) uses a technical means that is arranged apart from the sense-side first electrode film.

Since the sense side terminal (M) electrically connected to the sense side first electrode film (31) is disposed apart from the sense side first electrode film, the sense side first electrode film and the sense side terminal You can put a resistance in between.
Therefore, the resistance value of the sense semiconductor element can be adjusted.

In the invention according to claim 1 5, wherein the semiconductor device according to claim 1 4 (1), the sense-side first electrode film (31) and said sense terminal (M) is a polysilicon resistor (15) The technical means of being connected by is used.

  Since the resistance value of the polysilicon resistor is determined by the amount of impurities implanted into the polysilicon layer, the resistance value of the sense semiconductor element (30) can be adjusted with high accuracy by controlling the ion implantation amount. .

  In addition, the code | symbol in each said parenthesis shows the correspondence with the specific means as described in embodiment mentioned later.

<First Embodiment>
A first embodiment according to the present invention will be described with reference to the drawings. In the following embodiments, a vertical MOS transistor element (VDMOS, Vertical Diffused Metal Oxide Semiconductor) will be described as a semiconductor device according to the present invention. FIG. 1 is a circuit diagram showing an application example of VDMOS.

(Main configuration of VDMOS)
As shown in FIG. 1, the VDMOS 1 includes a main VDMOS 20 for supplying a load current IS to a load 70 and a sense VDMOS 30 for detecting the load current IS. The main VDMOS 20 and the sense VDMOS 30 are formed on the same semiconductor substrate (for example, an SOI substrate), and the main VDMOS 20 and the sense VDMOS 30 are each composed of a plurality of cells that function as VDMOSs. In the example shown in FIG. 1, the main VDMOS 20 and the sense VDMOS 30 are each an N-channel type VDMOS.

  The main VDMOS 20 and the sense VDMOS 30 have a drain terminal D and a gate terminal G connected in common, and constitute a current mirror circuit. In this embodiment, the on-resistance ratio (current mirror ratio) of both VDMOSs is set to about 1,000. Therefore, the cell ratio of the cells constituting both VDMOSs is also about 1,000, the number of cells is about 20,000 for the main VDMOS 20, and 20 for the sense VDMOS 30.

  A load 70 is connected to the source terminal S of the main VDMOS 20, and a power supply (not shown) is connected to the drain terminal D. Further, the Kelvin terminal K for detecting the source voltage of the main VDMOS 20 is connected to the source terminal S. A mirror terminal M is connected to the source electrode of the sense VDMOS 30. The mirror terminal M is connected to the inverting input terminal 51a of the operational amplifier 51 of the detection circuit 50 by the bonding wire 16 (FIG. 2).

  The Kelvin terminal K is connected to the non-inverting input terminal 51 b of the operational amplifier 51 by the bonding wire 17. The output of the operational amplifier 51 is connected to a control circuit 60 for controlling the gate voltage, and the control circuit 60 is connected to a gate drive circuit 80 for applying a gate voltage to the gate terminal G.

  In the above circuit, the main VDMOS 20 and the sense VDMOS 30 divide the current flowing from the drain terminal D according to the on-resistance ratio (current mirror ratio), and the current flowing from the current IM flowing to the mirror terminal M side to the source terminal S side. Detect IS. The current IS flowing to the source terminal S is detected from the voltage across the resistor R1 (voltage drop across the resistor R1), and the control circuit 60 determines the gate voltage based on the detected current value to control the load current IS.

  FIG. 2 is an explanatory plan view of the VDMOS 1. On the surface layer portion of the VDMOS 1, a main-side source electrode film 21 is formed as a wiring layer connecting the source electrodes of the main cells constituting the main VDMOS 20. A pad-like source terminal S is connected to the main-side source electrode film 21. Further, a sense-side source electrode film 31 as a wiring layer formed by connecting the source electrodes of the sense cells constituting the sense VDMOS 30 is formed at the corner of the surface of the VDMOS 1. A pad-like mirror terminal (sense-side source terminal) M is connected to the sense-side source electrode film 31.

  On the back surface of the VDMOS 1, a drain electrode film 2 (FIG. 3B) formed by commonly connecting the drain electrodes of the cells constituting the main VDMOS 20 and the sense VDMOS 30 is formed. A drain terminal D (FIG. 1) is connected to the drain electrode film 2. In this embodiment, the main-side source electrode film 21, the sense-side source electrode film 31, and the drain electrode film 2 are each formed in a solid shape from Al (aluminum).

  Around the main-side source electrode film 21 and the sense-side source electrode film 31, a gate electrode film (gate runner) is formed by commonly connecting the gate electrodes 8 (FIG. 3) of the cells constituting the main VDMOS 20 and the sense VDMOS 30. 5 is formed. A pad-shaped gate terminal G is connected to the gate electrode film 5. At the boundary between the main-side source electrode film 21, the sense-side source electrode film 31 and the gate electrode film 5, an insulating region 1a where no electrode film is formed is formed.

A pad-shaped Kelvin terminal K for detecting the voltage of the main VDMOS 20 is connected to the main-side source electrode film 21.
In this embodiment, the source terminal S is disposed in the vicinity of one end in the longitudinal direction of the main-side source electrode film 21 formed in a rectangular shape, and the Kelvin terminal K is disposed at the other end in the longitudinal direction of the main-side source electrode film 21. It is arranged near one corner.

  A path (hereinafter referred to as a drain current path) 14 of the drain current flowing from the drain terminal D to the source terminal S on the main-side source electrode film 21 is a path between the start point P1 and the end point P2 set in the main-side source electrode film 21. Suppose that The wiring resistance value of the main-side source electrode film 21 in the drain current path 14 between the starting point P1 and the Kelvin terminal K is Ra, and the wiring resistance value of the main-side source electrode film 21 in the drain current path 14 between the Kelvin terminal K and the source terminal S. Is Rb.

In addition, the wiring resistance value of the sense side source electrode film 31 is Rc, the resistance value added by adjusting the sense VDMOS 30 is the adjustment resistance value Rs, the wiring resistance value between the mirror terminal M and the inverting input terminal 51 a of the operational amplifier 51 is Let Rd.
The Kelvin terminal K is arranged according to the adjustment degree of the wiring resistance values Ra and Rb. When the wiring resistance value Rb is increased, the Kelvin terminal K is arranged at a position as far as possible from the source terminal S as shown in FIG.

  In order to equalize the on-resistance ratio of the main VDMOS 20 and the sense VDMOS 30, it is necessary to set Ra = (Rc + Rd). Therefore, in this embodiment, the error of the on-resistance ratio between the main VDMOS 20 and the sense VDMOS 30 is minimized by adding the adjustment resistance value Rs to the sense VDMOS 30. Hereinafter, a configuration for adding the adjustment resistance value Rs to the sense VDMOS 30 will be described.

(Cell structure)
3A and 3B are explanatory views showing the structure of the main cell constituting the main VDMOS 20, wherein FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along line AA in FIG. 4A and 4B are explanatory views showing the structure of the sense cell constituting the sense VDMOS 30, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line AA in FIG. 5A and 5B are explanatory views showing the structure of the sense cell, where FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along the line AA in FIG.

  As shown in FIGS. 3A and 4A, the planar shapes of the surface layer portions of the gate electrodes 8 constituting the main cell Ma and the sense cell Se are both striped. An N + type source layer 7 having a stripe shape is disposed between adjacent gate electrodes 8, and a plurality of P + type body layers 6 extend from the N + type source layer 7 in the N + type source layer 7. A plurality are arranged along the direction. A center cell between adjacent gate electrodes 8 forms one cell (unit cell), and the cell is repeatedly formed in the width direction.

  As shown in FIGS. 3B and 4B, the main cell Ma and the sense cell Se include the drain electrode 2, an N + type layer 3 formed on the surface layer portion thereof, and an N formed on the surface layer portion thereof. − Type layer 4, channel P layer 5 formed on the surface layer portion, N + type source layer 7 formed on the surface layer portion, and P + type body selectively formed on the surface layer portion of channel P layer 5 Layer 6, trench 8 a formed from the surface layer portion of N + -type source layer 7 to the inside of N − -type layer 4 between P + -type body layer 6, and a gate oxide film (not shown) in trench 8 a And a gate electrode 8 formed via As shown in FIG. 3B, the main VDMOS 20 includes a main-side source electrode film 21 formed so as to cover the surface layer portion of each main cell Ma via the interlayer insulating film 9, and the sense VDMOS 30 As shown in FIG. 4B, a sense-side source electrode film 31 is provided so as to cover the surface layer portion of each sense cell Se with the interlayer insulating film 9 interposed therebetween.

  In FIG. 3A, a region surrounded by reference numeral 11 represents a contact region (electrically connected region) between the main-side source electrode film 21 and the N + type source layer 7 and the P + type body layer 6. . The contact region 11 is defined by a contact hole (not shown) formed through the interlayer insulating film 9. The planar shape of the contact region 11 of the main cell Ma has a stripe shape, and the contact widths in the N + type source layer 7 and the P + type body layer 6 are set to the same C1. The cell pitch is set to E1.

  As shown in FIGS. 4A and 5A, the contact region 11 between the sense-side source electrode film 31 and the N + type source layer 7 and the P + type body layer 6 in the sense cell Se is a contact of the main cell Ma. The shape is different from the region 11. The contact width of the sense cell Se in the P + type body layer 6 is the same C1 as that of the main cell Ma, but the contact width C2 in the N + type source layer 7 is narrower than the contact width C1 of the main cell Ma (C2 <C1). ).

  That is, the contact area between the N + type source layer 7 of the sense cell Se and the sense side source electrode film 31 is smaller than the contact area between the N + type source layer 7 and the main side source electrode film 21 of the main cell Ma. The sense cell Se has the same structure as the main cell Ma except that the contact region 11 is different.

  Thus, since the contact area of the N + type source layer 7 in the sense cell Se is smaller than that of the main cell Ma, the resistance value of the N + type source layer 7 as the adjustment resistance value Rs in the sense VDMOS 30 can be increased. Further, the adjustment resistance value Rs can be adjusted by changing the contact width C2.

FIG. 6 is an explanatory diagram showing the on-resistance ratio per unit area of the main VDMOS 20 and the sense VDMOS 30. FIG. 7 is an explanatory diagram showing the on-resistance ratio of a VDMOS that does not include an adjustment resistor in the sense VDMOS.
In the VDMOS shown in FIG. 7, since there is no adjustment resistor in the sense VDMOS, the wiring resistance value Ra of the main VDMOS is not equal to the wiring resistance value (Rc + Rd) of the sense VDMOS.

  However, as shown in FIG. 6, according to the VDMOS 1 of the above embodiment, since the adjustment resistance value Rs can be added in the sense VDMOS 30, the wiring resistance value Ra of the main VDMOS 20 = (wiring resistance value (Rc + Rd) of the sense VDMOS 30) + Adjustment resistance value Rs).

In other words, unlike the prior art, it is not necessary to provide an occupied area for arranging the resistor at the outer edge of the sense VDMOS 30.
Therefore, the error of the on-resistance ratio between the main and sense VDMOS can be reduced and the current detection accuracy can be increased without increasing the size of the VDMOS 1.
Further, since the contact area of the P + type body layer 6 is larger than the contact area of the N + type source layer 7, the parasitic transistor becomes difficult to operate, so that it is difficult to be destroyed.

(Adjustment resistance value Rs adjustment method 1)
Next, the adjustment method 1 of the adjustment resistance value Rs will be described with reference to the drawings. FIG. 8A is a plan view of the sense cell Se.

  As shown in FIG. 8A, in the sense cell Se, a contact region 11 is independently formed in each P + type body layer 6, and the contact regions 11 are connected between adjacent P + type body layers 6. It has not been configured. The contact region 11 with the N + type source layer 7 is formed so as to protrude in a small area from the end of the P + type body layer 6 facing each other.

  Increasing the distance L1 between the protruding portions 11a can increase the resistance value of the N + -type source layer 7, and decreasing the distance L1 can decrease the resistance value of the N + -type source layer 7. That is, in the sense cell Se, the adjustment resistance value Rs of the sense VDMOS 30 can be finely adjusted by changing the interval L1 between the protruding portions 11a formed in the opposing P + type body layer 6.

(Adjustment resistance value Rs adjustment method 2)
Next, the adjustment method 2 of the adjustment resistance value Rs will be described with reference to the drawings. FIG. 8B is a plan view of the sense cell Se.

  Of the N + type source layer 7 of the sense cell Se, the sense side source electrode film 31 is formed on the sense side source electrode film 31 formed corresponding to the surface layer portion of the N + type source layer 7 between the adjacent P + type body layers 6. A region 12 where no is formed is arranged.

That is, since the contact area between the N + type source layer 7 and the sense-side source electrode film 31 can be reduced by the amount of the region 12, the resistance value of the N + type source layer 7 can be increased. . When the area of the region 12 is increased, the resistance value of the N + type source layer 7 is increased, and when the area of the region 12 is decreased, the resistance value of the N + type source layer 7 is decreased.
Therefore, the adjustment resistance value Rs of the sense VDMOS 30 can be finely adjusted by changing the area of the region 12.

(Adjustment resistance value Rs adjustment method 3)
Next, the adjustment method 3 of the adjustment resistance value Rs will be described with reference to the drawings. FIG. 9 is an explanatory plan view of the sense cell Se.

  The adjustment resistance value Rs is adjusted by making the size of the N + type source layer 7 or the P + type body layer 6 different between the main cell Ma and the sense cell Se. For example, as shown in FIG. 9A, the length L2 corresponding to the direction (longitudinal direction) in which the gate electrode 8 extends in the P + type body layer 6 of the sense cell Se is changed.

  That is, the arrangement interval L3 of the N + type source layer 7 formed between the P + type body layers 6 is changed. When the length L3 of the N + type source layer 7 is shortened, the contact region of the N + type source layer 7 is reduced. Therefore, the resistance value of the N + type source layer 7 is increased, and when the length L3 is increased, the N + type source layer 7 is increased. Therefore, the resistance value of the N + type source layer 7 is reduced.

  Therefore, the adjustment resistance value Rs of the sense VDMOS 30 can be finely adjusted by changing the length of the P + type body layer 6 or the N + type source layer 7 corresponding to the extending direction of the gate electrode 8 in the sense cell Se.

  Further, as shown in FIG. 9B, the adjustment resistance value Rs of the sense VDMOS 30 can be finely adjusted by changing the length of the contact region 11 in the P + type body layer 6 and the N + type source layer 7.

(Adjustment resistance value Rs adjustment method 4)
Next, the adjustment method 4 of the adjustment resistance value Rs will be described with reference to the drawings. 10A and 10B are explanatory diagrams of the sense cell Se, where FIG. 10A is an explanatory plan view, and FIG. 10B is a cross-sectional view taken along line AA in FIG.

An N− layer 13 having an impurity concentration lower than that of the N + type source layer 7 is formed in the N + type source layer 7 of the sense cell Se except for the portion along the gate electrode 8 and the contact region 11. Thereby, the resistance value of the N + type source layer 7 can be increased. The resistance value of the N + -type source layer 7 increases in accordance with the increase in the impurity concentration injected into the N − layer 13.
That is, by forming the N− layer 13 in the N + type source layer 7 of the sense cell Se, the adjustment range of the adjustment resistance value Rs in the sense VDMOS 30 can be expanded.

(Example of change)
FIG. 11 is an explanatory diagram showing a modification of the first embodiment. As shown in FIG. 11A, the N− layer 13 can be enlarged and formed also in a portion along the gate electrode 8. According to this structure, the adjustment range of the adjustment resistance value Rs in the sense VDMOS 30 can be further expanded.

  Further, as shown in FIG. 11B, in the structure shown in FIG. 11A, the contact region 11 can be made the same as the main cell Ma. According to this structure, the adjustment resistance value Rs in the sense VDMOS 30 can be attached without changing the contact region 11 between the main cell Ma and the sense cell Se.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to the drawings. The VDMOS according to this embodiment is characterized in that the shape of the cell is a quadrangle. FIG. 12 is an explanatory plan view of the cell, (a) is an explanatory plan view of the main cell Ma, and (b) is an explanatory plan view of the sense cell Se.

  As shown in FIG. 12A, in the main cell Ma, the planar shape of the region surrounded by the surface layer portion of the gate electrode 8 is a quadrangle. An N + type source layer 7 having a square shape in plan view is formed inside the gate electrode 8 formed in a frame shape having a square shape in plan view, and a P + type body layer 6 having a square shape in plan view is formed inside the gate electrode 8. ing. A frame-shaped contact region 11 is formed in the N + type source layer 7 so as to surround the P + type body layer 6.

  As shown in FIG. 12B, the sense cell Se includes a gate electrode 8, an N + type source layer 7 and a P + type body layer 6 having the same structure as the main cell Ma. The contact region with the N + type source layer 7 is smaller than the main cell. In this embodiment, the contact region 11b with the N + type source layer 7 is formed to project from the end of the P + type body layer 6 at a position corresponding to the center of the four sides 30a of the sense cell Se.

As described above, since the resistance value of the N + type source layer 7 in the sense cell Se can be increased by reducing the contact region with the N + type source layer 7 in the sense cell Se, the adjustment resistance value Rs is attached to the sense VDMOS 30. be able to.
In other words, unlike the prior art, it is not necessary to provide an occupied area for arranging the resistor at the outer edge of the sense VDMOS 30.

Therefore, the error of the on-resistance ratio between the main and sense VDMOS can be reduced and the current detection accuracy can be increased without increasing the size of the VDMOS 1.
Further, since the contact area of the P + type body layer 6 is larger than the contact area of the N + type source layer 7, the parasitic transistor is difficult to operate and can be hardly destroyed. The main cell Ma and the sense cell Se may have a hexagonal shape, an octagonal shape, or the like in plan view. Further, the contact region 11b may be formed only at a portion corresponding to the predetermined side portion 30a.

<Third Embodiment>
Next, a third embodiment of the invention will be described with reference to the drawings. The VDMOS according to this embodiment is characterized in that the contact region of the N + type source layer 7 is provided only in a portion having a high threshold voltage in the sense cell. FIG. 13A is an explanatory plan view of the sense cell Se.

  When the channel P layer 5 (FIG. 4B) is formed by diffusing impurities, the concentration of the impurity diffused in the lateral direction becomes thinner at the corners than at the sides of the cell due to the two-dimensional effect. For this reason, the impurity concentration in the channel region formed by the channel P layer 5 and the N + type source layer 7 in contact with the channel P layer 5 is lighter at the corners than at the sides of the cells, and the threshold voltage is It is known that the corner is lower than the side.

  Therefore, the resistance value of the N + type source layer 7 is increased by forming a contact region only in a region corresponding to the side portion of the sense cell Se having a high threshold voltage in the N + type source layer 7 in the sense cell Se.

  In the example shown in FIG. 13A, the contact region 11 is formed in a square shape. In the P + type body layer 6, the N + type source layer 7 enters the inside of the P + type body layer 6 from a portion corresponding to the central portion of each side 30 a of the sense cell Se. The N + type source layer 7a in the part where it enters is a contact region.

As described above, since the contact region with the N + type source layer 7 in the sense cell Se is formed only in the region having a high threshold voltage, the resistance value of the N + type source layer 7 in each sense cell Se is increased. Can do.
Similarly, since the contact region 11b of the sense cell Se shown in FIG. 12B is also formed only in the region corresponding to the side portion having a high threshold voltage, the N + type is coupled with the reduction of the contact region. The resistance value of the source layer 7 can be increased.
The main cell Ma and the sense cell Se may have a hexagonal shape, an octagonal shape, or the like in plan view. Further, the N + type source layer 7a may be formed only at a portion corresponding to the predetermined side portion 30a.

(Modification 1)
FIG. 13B is an explanatory plan view of a sense cell according to the first modification of the third embodiment. An N− layer 13 having an impurity concentration lower than that of the N + type source layer 7 is formed in a portion of the N + type source layer 7 of the sense cell Se excluding the N + type source layer 7a corresponding to the contact region 11. Thus, by changing the contact position with the sense-side source electrode film 31, the distance from the channel to the source contact is increased, so that the resistance value of the N + type source layer 7 can be increased. In addition, the resistance value of the N + type source layer 7 increases in response to the increase in the impurity concentration of the N− layer 13.

  That is, by forming the N− layer 13 in the channel region of the N + type source layer 7 of the sense cell, the adjustment range of the adjustment resistance value Rs in the sense VDMOS 30 can be expanded. The main cell Ma and the sense cell Se may have a hexagonal shape, an octagonal shape, or the like in plan view. Further, the N + type source layer 7a may be formed only at a portion corresponding to the predetermined side portion 30a.

(Modification 2)
FIG. 14 is an explanatory plan view of a sense cell Se according to Modification 2 of the third embodiment. The sense cell Se is formed in a rectangular shape in plan view with respect to the main cell Ma having a square shape in plan view, and an N + type source from a portion of the P + type body layer 6 corresponding to the central portion of the opposing short side portion of the sense cell Se. Layer 7 penetrates into P + type body layer 6.

The boundary of the contact region 11 is formed at the boundary between the P + type body layer 6 and the N + type source layer 7, and the P + type body layer 6 is formed in a concave shape at the short side. Due to the concave boundary 11d, the current path in the channel region wraps around and becomes longer.
With this configuration, the resistance value of the sense cell Se can be increased in combination with the reduction of the contact region of the N + type source layer 7.

  Note that the same effect as described above can be obtained even when the N + type source layer 7b is formed on the long side portion of the P + type body layer 6. Further, the N + type source layer 7b may be formed on each side portion of the P + type body layer 6, and the number of the N + type source layers 7b is not limited.

<Fourth embodiment>
Next, a fourth embodiment of the invention will be described with reference to the drawings. The VDMOS according to this embodiment is characterized in that the planar shape of the cell is a hexagon. FIG. 15 is an explanatory plan view of the cell, (a) is an explanatory plan view of the main cell Ma, and (b) is an explanatory plan view of the sense cell Se.

  In the main cell Ma and the sense cell Se, the planar shape of the region surrounded by the surface layer portion of the gate electrode 8 is formed in a hexagon. A hexagonal N + type source layer 7 is formed inside the gate electrode 8, and a hexagonal P + type body layer 6 is formed inside the gate electrode 8. The N + type source layer 7 and the P + type body layer 6 are similar.

  As shown in FIG. 15A, the contact region 11 of the main cell Ma is formed in a size including the entire region of the P + type body layer 6 and a predetermined region on the periphery thereof. The shape is similar to that of the P + type body layer 6. On the other hand, the contact region 11 with the N + type source layer 7 in the sense cell Se is smaller than the main cell. In the example shown in FIG. 15B, the N + type source layer 7c included in the contact region 11 is P +. It is formed at four locations around the mold body layer 6.

Thereby, since the resistance value of the N + type source layer 7 in each sense cell Se can be increased, the adjustment resistance value Rs can be attached to the sense VDMOS 30.
In other words, unlike the prior art, it is not necessary to provide an occupied area for arranging the resistor at the outer edge of the sense VDMOS 30.

Therefore, the error of the on-resistance ratio between the main and sense VDMOS can be reduced and the current detection accuracy can be increased without increasing the size of the VDMOS 1.
Further, since the contact area of the P + type body layer 6 is larger than the contact area of the N + type source layer 7, the parasitic transistor is difficult to operate and can be hardly destroyed.

(Modification 1)
The VDMOS according to the first modification of the fourth embodiment is characterized in that, in the sense cell Se, the contact region of the N + type source layer 7 is provided only in a portion having a high threshold voltage. FIG. 16A is a plan view of the sense cell Se.

It is known that the threshold voltage of the side portion of the cell is higher in the side portion having a higher crystal plane orientation than in the lower side portion.
Therefore, the resistance value of the N + type source layer 7 is increased by forming a contact region only in a region corresponding to the side portion having a high threshold voltage in the N + type source layer 7 in the sense cell Se.

In the example shown in FIG. 16A, the sense cells Se are formed in a regular hexagonal shape in plan view, and the hexagonal interior angles are all 120 °. The crystal plane orientation of the two opposing side portions 30a is the (100) plane, and the crystal plane orientation of the other four side portions 30b is the (023) plane. That is, the threshold voltage is higher in the portion corresponding to the side portion 30b than in the portion corresponding to the side portion 30a.
Therefore, the N + type source layer 7d included in the contact region 11 is formed only in a portion corresponding to one pair of two opposing side portions 30b among the four side portions 30b.

  As described above, since the contact region with the N + type source layer 7 in the sense cell Se is formed only in the region having a high threshold voltage, the resistance value of the N + type source layer 7 in each sense cell Se is increased. Can do.

  As another shape of the sense cell Se, two opposing corners are hexagons having an inner angle of 90 ° and the other four corners having an inner angle of 135 °. There is also a shape in which the side is along the crystal plane orientation (100) and the remaining side is the side along the crystal plane orientation (110). In this case, if the N + type source layer 7d is formed only in the portion corresponding to the side forming the inner angle of 135 °, the same effect as described above can be obtained.

(Modification 2)
FIG. 16B is an explanatory plan view of the sense cell Se according to the modification 2 of the fourth embodiment. An N− layer 13 having an impurity concentration lower than that of the N + type source layer 7 is formed in a portion of the N + type source layer 7 of the sense cell Se excluding the N + type source layer 7d corresponding to the contact region 11. Thereby, the resistance value of the N + type source layer 7 can be increased.

In addition, the resistance value of the N + type source layer 7 increases in response to the increase in the impurity concentration of the N− layer 13.
That is, the adjustment range of the adjustment resistance value Rs can be expanded by forming the N− layer 13 in the channel region of the N + type source layer 7 of the sense cell Se.

(Modification 3)
FIG. 17A is an explanatory plan view of a sense cell Se according to Modification 3 of the fourth embodiment. The sense cell Se is formed in a hexagonal shape different from the main cell Ma, and the area of the contact region of the N + type source layer 7 is smaller than that of the main cell. Further, the sense cell Se is formed in a vertically long shape so that the distance L6 between the N + type source layer 7e that contacts the sense side source electrode film 31 and the channel region is uniform in any region of the sense cell Se. Yes. Thereby, the resistance value in each region of the N + type source layer 7 can be made uniform.

(Modification 4)
FIG. 17B is an explanatory plan view of the sense cell Se according to Modification 4 of the fourth embodiment. The sense cell Se is formed in a hexagonal shape in plan view, the crystal plane orientation of the pair of long side portions 30b facing each other is the (100) plane, and the crystal plane orientations of the remaining four short side portions 30a are (111). ) That is, by extending the side portion 30b having a low threshold voltage to be a long side, the region having a low threshold voltage can be separated from the N + type source layer 7e in contact with the sense-side source electrode film 31. , The resistance value of the N + type source layer 7 can be increased.

<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described with reference to the drawings. The VDMOS according to this embodiment is characterized in that the drain electrode film 2 is not formed in a region corresponding to the sense VDMOS 30 in the drain electrode film 2. FIG. 18A is a plan view of the drain electrode film 2, and FIG. 18B is a cross-sectional view of the sense cell Se.

  As shown in FIG. 18A, in the drain electrode film 2 formed on the back surface of the VDMOS 1, a non-formation region 2a where the drain electrode film 2 is not formed is arranged in a region corresponding to the sense VDMOS 30. Yes. As a result, as shown in FIG. 18B, the current flowing from the drain electrode film 2 into the sense cell Se passes through the N + type layer 3 in the lateral direction and becomes a detour path, so that the resistance ΔRs is added accordingly. Is done.

  That is, the adjustment resistance value Rs of the sense VDMOS 30 can be adjusted by disposing the non-formation region 2 a where the drain electrode film 2 is not formed in a region corresponding to the sense VDMOS 30 in the drain electrode film 2. Further, when the non-forming region 2a is increased, the resistance ΔRs is increased. Therefore, the resistance ΔRs can be finely adjusted depending on the size of the non-forming region 2a.

  Also, the drain electrode film 2 is not formed at all in the region corresponding to the sense VDMOS 30 in the drain electrode film 2, but one or more layers among the plurality of layers constituting the drain electrode film 2 are not selectively formed. You can also For example, when the drain electrode film 2 is formed by stacking Au (or Ag), Ni, Ti, and Al in this order from the bottom layer, a layer made of Au (or Ag) for preventing electrode oxidation is formed. Do not. Further, a layer made of Ni (or Ag) and Ni having good solder wettability is not formed. Furthermore, a resistor for adjusting the adjustment resistor Rs may be formed in the non-formation region 2a.

<Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described with reference to the drawings. The VDMOS according to this embodiment is characterized in that the mirror terminal M is disposed apart from the sense-side source electrode film 31. FIG. 19 is an explanatory plan view showing the positional relationship between the mirror terminal M and the sense-side source electrode film 31.

  As shown in FIG. 19A, the mirror terminal M is disposed away from the sense-side source electrode film 31, and the mirror terminal M and the sense-side source electrode film 31 are connected by a wiring 31a. Thereby, since the resistance ΔRs of the wiring 31a is added, the adjustment resistance value Rs of the sense VDMOS 30 can be increased. In addition, since the magnitude of the resistance ΔRs can be changed by changing at least one of the length and the width of the wiring 31a, the adjustment resistance value Rs can be finely adjusted. In this embodiment, the wiring 31a is made of Al.

  In the example shown in FIG. 19B, the mirror terminal M and the sense-side source electrode film 31 are connected by the polysilicon resistor 15. Thereby, since the resistance ΔRs of the polysilicon resistor 15 is added, the adjustment resistance value Rs of the sense VDMOS 30 can be increased. In addition, since the resistance value of the polysilicon resistor is determined by the amount of impurities ion-implanted into the polysilicon layer, the magnitude of the resistance ΔRs can be changed by controlling the ion implantation amount. Can be finely adjusted with high accuracy.

<Other embodiments>
(1) In each of the embodiments described above, the area ratio of the N + -type source layer 7 and the P + -type body layer 6 in the channel region of the sense cell Se is the same as that of the main cell Ma, and the area of the N + -type source layer 7 of the sense cell Se Can be made wider than the main cell Ma, the resistance value of the N + type source layer 7 of the sense cell Se can be increased.
(2) In the above-described embodiments, the VDMOS has been described as an example of the semiconductor device according to the present invention. However, the present invention can also be applied to a lateral MOS transistor element (LDMOS, Lateral Double Diffused MOS). The gate electrode may be a planar type. Furthermore, the present invention can also be applied to a P-channel type MOS.

(3) In each of the above-described embodiments, the MOS device has been described as an example of the semiconductor device according to the present invention. However, the present invention can also be applied to an insulated gate bipolar transistor (IGBT). In this case, a portion corresponding to the source electrode of the VDMOS 1 becomes an emitter electrode, and a portion corresponding to the drain electrode becomes a collector electrode.

  In addition, “substantially equal” described in the claims and the like means including not only completely equal but also substantially equal.

It is a circuit diagram which shows the example of application of VDMOS. It is a plane explanatory view of VDMOS1. It is explanatory drawing which shows the structure of the main cell which comprises the main VDMOS20, (a) is a top view, (b) is AA arrow sectional drawing of (a). It is explanatory drawing which shows the structure of the sense cell which comprises sense VDMOS30, (a) is a top view, (b) is AA arrow sectional drawing of (a). It is explanatory drawing which shows the structure of a sense cell, (a) is a top view, (b) is AA arrow sectional drawing of (a). 5 is an explanatory diagram showing an on-resistance ratio per unit area of the main VDMOS 20 and the sense VDMOS 30. FIG. It is explanatory drawing which shows ON resistance ratio of VDMOS which is not provided with adjustment resistance in sense VDMOS. It is a plane explanatory view of sense cell Se. It is a plane explanatory view of sense cell Se. It is explanatory drawing of sense cell Se, (a) is plane explanatory drawing, (b) is AA arrow sectional drawing of (a). It is explanatory drawing which shows the example of a change of 1st Embodiment. It is a plane explanatory view of a cell concerning a 2nd embodiment, (a) is a plane explanatory view of main cell Ma, and (b) is a plane explanatory view of sense cell Se. (A) is plane | planar explanatory drawing of the sense cell Se which concerns on 3rd Embodiment, (b) is plane | planar explanatory drawing of the sense cell which concerns on the modification 1 of 3rd Embodiment. It is a plane explanatory view of sense cell Se concerning modification 2 of a 3rd embodiment. It is a plane explanatory view of a cell concerning a 4th embodiment, (a) is a plane explanatory view of main cell Ma, and (b) is a plane explanatory view of sense cell Se. (A) is plane | planar explanatory drawing of the sense cell Se which concerns on the modification 1 of 4th Embodiment, (b) is plane | planar explanatory drawing of the sense cell Se which concerns on the modification 2 of 4th Embodiment. (A) is plane explanatory drawing of the sense cell Se which concerns on the modification 3 of 4th Embodiment, (b) is plane explanatory drawing of the sense cell Se which concerns on the modification 4 of 4th Embodiment. (A) is plane explanatory drawing of the drain electrode film 2 which concerns on 5th Embodiment, (b) is sectional drawing of sense cell Se. It is a plane explanatory view showing the arrangement relation of mirror terminal M and sense side source electrode film 31 in a 6th embodiment.

Explanation of symbols

1 ... VDMOS (semiconductor device) 5 ... Gate electrode film 11 ... Contact region
20 .. Main VDMOS (main semiconductor element),
21..Main side source electrode film (main side first electrode film),
30..Sense VDMOS (sense semiconductor element),
31..Sense-side source electrode film (sense-side first electrode film),
50 .. Current detection circuit,
K ·· Kelvin terminal (voltage detection terminal),
M ·· mirror terminal (sense side terminal), Ma ·· main cell, Ra to Rd ·· wiring resistance,
Rs ... adjustment resistor, S ... source terminal (main side terminal), Se ... sense cell.

Claims (15)

A first conductivity type first semiconductor layer; a second conductivity type second semiconductor layer formed on a surface layer portion of the first semiconductor layer; and a first conductivity type formed on a surface layer portion of the second semiconductor layer. A third semiconductor layer, a second conductive type fourth semiconductor layer selectively formed in a surface layer portion of the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer, and a gate insulating film A gate electrode formed from a surface layer portion of the third semiconductor layer, a first electrode electrically connected to the third and fourth semiconductor layers through an interlayer insulating film, and a voltage applied to the gate electrode A main semiconductor element configured to include a plurality of cells having a second electrode for passing a current between the first electrode and a load current to a load;
A sense semiconductor element that is connected in parallel with the main semiconductor element to detect the load current, forms a current mirror circuit together with the main semiconductor element, and includes fewer cells than the cells constituting the main semiconductor element When,
In a semiconductor device comprising:
A semiconductor device, wherein a resistance value of the third semiconductor layer constituting a cell is larger in the sense semiconductor element than in the main semiconductor element.   The area of a region where the third semiconductor layer and the first electrode constituting the cell are electrically connected is smaller in the sense semiconductor element than in the main semiconductor element. A semiconductor device according to 1.   3. The semiconductor device according to claim 1, wherein a planar shape of a surface layer portion of the gate electrode constituting an adjacent cell is a stripe shape. 4. Each cell is formed with a plurality of the fourth semiconductor layers,
In each cell, the area of the region where the third semiconductor layer and the first electrode between the adjacent fourth semiconductor layers are electrically connected is smaller in the sense semiconductor element than in the main semiconductor element. The semiconductor device according to claim 2.   3. The semiconductor device according to claim 1, wherein a planar shape of a region surrounded by a surface layer portion of the gate electrode constituting an adjacent cell is a polygon. The region where the third semiconductor layer and the first electrode in each cell constituting the sense semiconductor element are electrically connected is at the corner of the outer edge of the planar cell region which is the polygon. 6. The semiconductor device according to claim 5, wherein the semiconductor device is formed in a region corresponding to a side portion excluding the corresponding region. A region where the third semiconductor layer and the first electrode in each cell constituting the sense semiconductor element are electrically connected is a threshold value among outer edges of the planar cell region which is the polygon. 6. The method according to claim 5 , wherein the voltage is formed in a region corresponding to the side portion of the crystal plane orientation where the threshold voltage is increased, excluding a region corresponding to the side portion of the crystal plane orientation where the voltage is lowered. Semiconductor device. Of claims 1 to 7 the size of the surface area of the third semiconductor layer and the portion where the fourth semiconductor layer in contact in each cell, characterized in that the different between the main semiconductor element and the sensing semiconductor device The semiconductor device according to any one of the above. Region in which the first electrode is not formed on the remaining portion of the surface layer portion by forming the first electrode on a portion of the surface layer portion of the third semiconductor layer of each cell constituting the sense semiconductor element The semiconductor device according to claim 1, wherein the semiconductor device is arranged . The fifth semiconductor layer of the first conductivity type having an impurity concentration lower than that of the third semiconductor layer is formed in the third semiconductor layer of each cell constituting the sense semiconductor element. The semiconductor device according to claim 9. A back electrode film composed of a plurality of layers connected to the second electrode of each cell constituting the main semiconductor element and the sense semiconductor element is formed on the back surface of the semiconductor substrate;
11. The region according to claim 1, wherein one or more layers of the back electrode film are not formed in a range corresponding to the sense semiconductor element in the back electrode film. The semiconductor device as described in any one. A main-side first electrode film formed by connecting the first electrodes of the cells constituting the main semiconductor element;
Claims 1, characterized in that the sense side first electrode film formed by connecting the first electrode of each cell constituting the sense semiconductor element is being made form a surface portion of said semiconductor substrate 11. The semiconductor device according to any one of 11 above. A main-side terminal connected to the main-side first electrode film;
A sense side terminal connected to the sense side first electrode film;
A voltage detection terminal connected to a location different from the main side terminal in the main side first electrode film,
The sense side terminal and the voltage detection terminal are configured to be connectable to a current detection circuit for detecting a current flowing through the sense semiconductor element,
The wiring resistance value obtained by adding the wiring resistance value of the sense semiconductor element and the wiring resistance value between the sense side terminal and the current detection circuit is the wiring resistance value between the main side terminal and the voltage detection terminal. the semiconductor device according to claim 1 2, characterized in that is configured to be substantially equal to the wiring resistance value obtained by subtracting from the wiring resistance value of the terminal. The sense-side first electrode layer electrically connected to the sense terminal is according to claim 1 2 or claim 13, characterized in that are arranged spaced apart from the sense-side first electrode film Semiconductor device. 15. The semiconductor device according to claim 14, wherein the sense-side first electrode film and the sense-side terminal are connected by a polysilicon resistor.

Images