JP5418308B2 - Mounting structure - Google Patents

Mounting structure Download PDF

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JP5418308B2
JP5418308B2 JP2010050170A JP2010050170A JP5418308B2 JP 5418308 B2 JP5418308 B2 JP 5418308B2 JP 2010050170 A JP2010050170 A JP 2010050170A JP 2010050170 A JP2010050170 A JP 2010050170A JP 5418308 B2 JP5418308 B2 JP 5418308B2
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power supply
terminal
hole
terminals
wiring
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JP2011187605A (en
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真 伏見
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

本発明は、少なくとも１つのグランド配線層と少なくとも１つの信号配線層とを含む複数の配線層を備えた配線基板の一方の基板面に少なくとも１つの半導体素子チップが実装された実装構造に関するものである。   The present invention relates to a mounting structure in which at least one semiconductor element chip is mounted on one substrate surface of a wiring board having a plurality of wiring layers including at least one ground wiring layer and at least one signal wiring layer. is there.

図５は、多層プリント配線基板にＬＳＩチップ等の半導体素子チップを実装した実装構造の従来例を示す断面図である。図示する実装構造１０１は、配線基板１１０の一方の基板面（図示上面）にＬＳＩチップ等の半導体素子チップが収容された半導体パッケージ１２０が実装されたものである。この図では、半導体パッケージ１２０はＢＧＡ（Ball grid array）パッケージであり、図中、符号１２１は外部接続端子（この例ではＢＧＡ端子）、符号１２２はアンダーフィル樹脂を示している。
配線基板１１０内には、複数の配線層が絶縁層（符号略）を介して積層されている。配線基板１１０内には、複数の配線層として、少なくとも１つのグランド配線層１１１と少なくとも１つの信号配線層１１２と少なくとも１つの電源配線層１１３とが形成されている。 FIG. 5 is a cross-sectional view showing a conventional example of a mounting structure in which a semiconductor element chip such as an LSI chip is mounted on a multilayer printed wiring board. In the illustrated mounting structure 101, a semiconductor package 120 in which a semiconductor element chip such as an LSI chip is accommodated is mounted on one substrate surface (upper surface in the drawing) of a wiring substrate 110. In this figure, the semiconductor package 120 is a BGA (Ball grid array) package. In the figure, reference numeral 121 denotes an external connection terminal (BGA terminal in this example), and reference numeral 122 denotes an underfill resin.
In the wiring substrate 110, a plurality of wiring layers are stacked via insulating layers (reference numerals omitted). In the wiring substrate 110, at least one ground wiring layer 111, at least one signal wiring layer 112, and at least one power wiring layer 113 are formed as a plurality of wiring layers.

半導体プロセス技術の発達により、ＬＳＩチップの微細化・多機能化に伴って、半導体パッケージでは信号端子数の増数化や寸法の大型化が発生している。そのため、配線基板では、多数の配線を引き回すために配線間隔の狭小化や配線層数の多層化が必要となっている。
ＬＳＩの駆動電圧は低電圧化してきているが、システムＬＳＩ化により１チップあたりの消費電力は増加しており、各種配線にかかる抵抗による電力損失が大きくなってきている。大電力を要するＬＳＩチップを実装する場合、配線基板にはグランド配線層及び電源配線層の厚膜化・太線化・短線化などにより、配線抵抗を下げる設計が必要となってきている。
配線設計にはノイズ特性や反射などの電気伝送特性や電力損失などを考慮する必要もある。
以上の理由から、配線基板の設計は益々複雑なものとなってきている。 With the development of semiconductor process technology, the number of signal terminals and the size of semiconductor packages are increasing with the miniaturization and multifunctionality of LSI chips. Therefore, in the wiring board, it is necessary to narrow the wiring interval and to increase the number of wiring layers in order to route a large number of wirings.
Although the driving voltage of LSI has been lowered, the power consumption per chip has increased due to the system LSI, and the power loss due to the resistance applied to various wirings has increased. When an LSI chip that requires high power is mounted, it is necessary to design the wiring board to reduce wiring resistance by increasing the thickness, thickening, and shortening of the ground wiring layer and the power supply wiring layer.
In wiring design, it is necessary to consider electric transmission characteristics such as noise characteristics and reflection, and power loss.
For these reasons, the design of wiring boards has become increasingly complex.

また、消費電力の多いシステムＬＳＩを実装した場合、電力損失が熱へと変換され、ＬＳＩチップ及び配線基板からの発熱量も多くなる。発熱によりＬＳＩ温度が高くなりすぎると、動作に支障が出る恐れがある。   When a system LSI with high power consumption is mounted, power loss is converted into heat, and the amount of heat generated from the LSI chip and the wiring board also increases. If the LSI temperature becomes too high due to heat generation, the operation may be hindered.

特許文献１の図１には、配線基板（１０）内に、導体金属棒（５２）と導体金属筒（５３）と絶縁材（５４）とからなる給電構造体（５１）を設けることが提案されている。この給電構造体（５１）はＩＣチップ（２１）から離れた位置に設けられている。段落００３５には、給電構造体（５１）の径はスルーホールよりも小さいことが記載されている。   In FIG. 1 of Patent Document 1, it is proposed to provide a power feeding structure (51) composed of a conductive metal rod (52), a conductive metal cylinder (53), and an insulating material (54) in a wiring board (10). Has been. The power feeding structure (51) is provided at a position away from the IC chip (21). Paragraph 0035 describes that the diameter of the feeding structure (51) is smaller than the through hole.

特許文献２の第１図には、配線基板が信号配線基板（２００）と電源供給基板（３００）の２つの基板に分けられた構造が記載されている。この構造では、ＩＣチップ（１）と信号配線基板（２００）と電源供給基板（３００）との接続はスルーホール（５）でなされている。同文献の第３図には、電源供給基板（３００）に外部から給電する構造（８）が記載されている。   FIG. 1 of Patent Document 2 describes a structure in which a wiring board is divided into two boards, a signal wiring board (200) and a power supply board (300). In this structure, the IC chip (1), the signal wiring board (200), and the power supply board (300) are connected by a through hole (5). FIG. 3 of the document describes a structure (8) for supplying power to the power supply board (300) from the outside.

特許文献３の図１及び図２には、配線基板（７）に給電用の大きな孔部（１０）を開ける一方、ＩＣチップ（１）に電源電極（５）を取り付け、孔部（１０）内にＩＣチップ（１）の電源電極（５）を挿入した構造が記載されている。
特許文献４の図１には、ＬＳＩチップに電源給電パターン（１２）を有する配線基板（１１）を接続した構造が記載されている。 In FIG. 1 and FIG. 2 of Patent Document 3, a large hole (10) for power feeding is opened in the wiring board (7), while a power supply electrode (5) is attached to the IC chip (1), and the hole (10). A structure in which the power supply electrode (5) of the IC chip (1) is inserted therein is described.
FIG. 1 of Patent Document 4 describes a structure in which a wiring board (11) having a power supply pattern (12) is connected to an LSI chip.

特開2008-177554号公報JP 2008-177554 A 特開昭60-247992号公報Japanese Unexamined Patent Publication No. 60-247992 特開平05-218218号公報Japanese Patent Laid-Open No. 05-218218 特開平07-297225号公報Japanese Unexamined Patent Publication No. 07-297225

特許文献１及び２では、配線基板内に、半導体素子チップの給電用にスルーホール又はそれより小さい径の孔部を設けている。かかる構成では、半導体素子チップへの給電量には限界がある。そのため、半導体素子チップに大きな電力を供給しようとすると、多数の給電用の孔部を開孔するなどの対応が必要である。多数の給電用の孔部を開孔しても、供給できる電力量には限界がある。   In Patent Documents 1 and 2, a through-hole or a hole having a smaller diameter is provided in a wiring board for power supply of a semiconductor element chip. With this configuration, there is a limit to the amount of power supplied to the semiconductor element chip. Therefore, in order to supply a large electric power to the semiconductor element chip, it is necessary to take measures such as opening a large number of power supply holes. There is a limit to the amount of power that can be supplied even if a large number of power feeding holes are opened.

特許文献３では、配線基板に給電用の大きな孔部を開ける一方、半導体素子チップに電源電極を取り付け、孔部内に半導体素子チップに電源電極を挿入しているので、電源電極を介して半導体素子チップに特許文献１及び２よりも大きな電力を供給できる。しかしながら、特許文献３では、半導体素子チップ側に電源電極を取り付けており、半導体素子チップ側の改造が必要である。そのため、実装する半導体素子チップが変われば、半導体素子チップの改造がその都度行う必要があり、種々のタイプの半導体素子チップに対応ができず、高コスト化に繋がる。
特許文献４では、半導体素子チップに２つの配線基板を接続しているので、部品点数が多く、小面積化に対応できない。 In Patent Document 3, a large hole for power feeding is formed in a wiring board, while a power supply electrode is attached to the semiconductor element chip, and the power supply electrode is inserted into the semiconductor element chip in the hole. The chip can be supplied with electric power larger than those in Patent Documents 1 and 2. However, in patent document 3, the power supply electrode is attached to the semiconductor element chip side, and the semiconductor element chip side needs to be modified. For this reason, if the semiconductor element chip to be mounted is changed, it is necessary to modify the semiconductor element chip each time, and it is not possible to cope with various types of semiconductor element chips, leading to higher costs.
In Patent Document 4, since two wiring boards are connected to a semiconductor element chip, the number of components is large and it is not possible to cope with a reduction in area.

本発明は上記事情に鑑みてなされたものであり、半導体素子チップの改造を要することなく、半導体素子チップに大きな電力を供給することが可能な実装構造を提供することを目的とするものである。
本発明はまた、半導体素子チップの改造を要することなく、高い放熱効果が得られる実装構造を提供することを目的とするものである。 The present invention has been made in view of the above circumstances, and an object thereof is to provide a mounting structure capable of supplying large power to a semiconductor element chip without requiring modification of the semiconductor element chip. .
It is another object of the present invention to provide a mounting structure that can obtain a high heat dissipation effect without requiring modification of a semiconductor element chip.

本発明の第１の実装構造は、少なくとも１つのグランド配線層と少なくとも１つの信号配線層とを含む複数の配線層を備えた配線基板の一方の基板面に少なくとも１つの半導体素子チップが実装された実装構造であって、
前記配線基板は、当該配線基板を厚み方向に貫通して開孔されたスルーホールより大きい少なくとも１つの孔部を有し、当該孔部内に外部から前記半導体素子チップの外部接続端子に給電するための給電端子が挿入され、当該給電端子が絶縁材により前記孔部内に固定されたものである。 In the first mounting structure of the present invention, at least one semiconductor element chip is mounted on one substrate surface of a wiring board having a plurality of wiring layers including at least one ground wiring layer and at least one signal wiring layer. Mounting structure,
The wiring board has at least one hole portion larger than a through-hole opened through the wiring board in the thickness direction, and feeds power from the outside to the external connection terminal of the semiconductor element chip in the hole portion. The power supply terminal is inserted, and the power supply terminal is fixed in the hole by an insulating material.

本発明の第２の実装構造は、少なくとも１つのグランド配線層と少なくとも１つの信号配線層とを含む複数の配線層を備えた配線基板の一方の基板面に少なくとも１つの半導体素子チップが実装された実装構造であって、
前記半導体素子チップは放熱端子を有するものであり、
前記配線基板は、当該配線基板を厚み方向に貫通して開孔されたスルーホールより大きい少なくとも１つの孔部を有し、当該孔部内に前記半導体素子チップの放熱端子から外部への放熱を行う外部放熱端子が挿入され、当該外部放熱端子が絶縁材により前記孔部内に固定されたものである。 In the second mounting structure of the present invention, at least one semiconductor element chip is mounted on one substrate surface of a wiring board having a plurality of wiring layers including at least one ground wiring layer and at least one signal wiring layer. Mounting structure,
The semiconductor element chip has a heat dissipation terminal,
The wiring board has at least one hole larger than a through hole opened through the wiring board in the thickness direction, and radiates heat from the heat radiation terminal of the semiconductor element chip to the outside in the hole. An external heat radiating terminal is inserted, and the external heat radiating terminal is fixed in the hole by an insulating material.

本発明の第１の実装構造によれば、半導体素子チップの改造を要することなく、半導体素子チップに大きな電力を供給することが可能な実装構造を提供することができる。
本発明の第２の実装構造によれば、半導体素子チップの改造を要することなく、高い放熱効果が得られる実装構造を提供することができる。 According to the first mounting structure of the present invention, it is possible to provide a mounting structure capable of supplying large power to the semiconductor element chip without requiring modification of the semiconductor element chip.
According to the second mounting structure of the present invention, it is possible to provide a mounting structure that provides a high heat dissipation effect without requiring modification of the semiconductor element chip.

本発明に係る第１実施形態の実装構造の断面図である。It is sectional drawing of the mounting structure of 1st Embodiment which concerns on this invention. 本発明に係る第２実施形態の実装構造の断面図である。It is sectional drawing of the mounting structure of 2nd Embodiment which concerns on this invention. 本発明に係る第３実施形態の実装構造の断面図である。It is sectional drawing of the mounting structure of 3rd Embodiment which concerns on this invention. 本発明に係る第４実施形態の実装構造の断面図である。It is sectional drawing of the mounting structure of 4th Embodiment which concerns on this invention. 従来の実装構造の断面図である。It is sectional drawing of the conventional mounting structure.

「第１実施形態」
図面を参照して、本発明に係る第１実施形態の実装構造について説明する。図１は、本実施形態の実装構造の断面図である。視認しやすくするため、各構成要素の縮尺は実際のものとは適宜異ならせてある。 “First Embodiment”
A mounting structure according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the mounting structure of this embodiment. In order to facilitate visual recognition, the scale of each component is appropriately different from the actual one.

本実施形態の実装構造１は、配線基板１０にＬＳＩチップ等の半導体素子チップが収容された半導体パッケージ２０が実装されたものである。本実施形態において、半導体パッケージ２０はＢＧＡ（Ball grid array）パッケージである。   The mounting structure 1 of the present embodiment is obtained by mounting a semiconductor package 20 in which a semiconductor element chip such as an LSI chip is accommodated on a wiring board 10. In the present embodiment, the semiconductor package 20 is a BGA (Ball grid array) package.

配線基板１０内には、複数の配線層が絶縁層（符号略）を介して積層されている。配線基板１０内には、複数の配線層として、少なくとも１つのグランド配線層１１と少なくとも１つの信号配線層１２とが形成されている。本実施形態では、配線基板１０は内部に配線層として電源配線層を有していない。
配線基板１０の一方の基板面（図示上面）に、半導体パッケージ２０が実装されている。半導体パッケージ２０はその底面に複数の外部接続端子２１を有し、これら外部接続端子２１が配線基板１０に半田等の導電材を介して接合されている。配線基板１０と半導体パッケージ２０との間隙には、接合強化や異物流入防止等のために、アンダーフィル樹脂２２が充填されている。アンダーフィル樹脂２２は必須なものではない。 In the wiring substrate 10, a plurality of wiring layers are laminated via insulating layers (reference numerals omitted). In the wiring substrate 10, at least one ground wiring layer 11 and at least one signal wiring layer 12 are formed as a plurality of wiring layers. In the present embodiment, the wiring board 10 does not have a power wiring layer as a wiring layer inside.
A semiconductor package 20 is mounted on one substrate surface (illustrated upper surface) of the wiring substrate 10. The semiconductor package 20 has a plurality of external connection terminals 21 on its bottom surface, and these external connection terminals 21 are joined to the wiring substrate 10 via a conductive material such as solder. The gap between the wiring substrate 10 and the semiconductor package 20 is filled with an underfill resin 22 for the purpose of strengthening bonding, preventing foreign matter inflow, and the like. The underfill resin 22 is not essential.

配線基板１０は、半導体パッケージ２０の直下に配線基板１０を厚み方向に貫通して開孔されたスルーホールより大きい少なくとも１つの孔部３０を有している。この孔部３０内に外部から半導体パッケージ２０の外部接続端子２１に給電するための給電端子３１が挿入され、給電端子３１が絶縁材３２により孔部３０内に固定されている。図示する例では、孔部３０は１個であるが、複数設けても構わない。
絶縁材３２としては樹脂材が好ましい。絶縁材３２としては任意の樹脂を使用できるが、アンダーフィル樹脂２２と同じ樹脂を用いれば、使用する材料が少なくて済み、簡便である。 The wiring board 10 has at least one hole 30 that is larger than a through hole that is formed through the wiring board 10 in the thickness direction immediately below the semiconductor package 20. A power supply terminal 31 for supplying power from the outside to the external connection terminal 21 of the semiconductor package 20 is inserted into the hole 30, and the power supply terminal 31 is fixed in the hole 30 by an insulating material 32. In the example shown in the figure, the number of the holes 30 is one, but a plurality of holes 30 may be provided.
The insulating material 32 is preferably a resin material. Any resin can be used as the insulating material 32. However, if the same resin as the underfill resin 22 is used, the amount of material used is small and simple.

本実施形態において、給電端子３１は断面視コ字状とされ、その一部（図示下端部）が配線基板１０の外側に引き出されている。この引出し部分に、外部から給電端子３１に給電するための導電材（導電性配線、導電性金属板、及び導電性シート等）からなる給電部材３３が取り付けられている。給電端子３１及び給電部材３３の形状やサイズは適宜設計できる。
本実施形態において、金属製のネジ（固定部材）３４により給電端子３１と給電部材３３とが互いに機械的に固定されている。給電端子３１と給電部材３３との固定態様については適宜設計できる。
給電端子３１、給電部材３３、及びネジ３４の材質としては特に制限されず、大電流を流した場合の損失の少ない低抵抗材料が好ましい。これらの材質としては、低抵抗で加工が容易で安価なＣｕあるいはＣｕ合金等の低抵抗材料が好ましい。
本明細書において、「低抵抗材料からなる部材」とは、材料自身の電気抵抗率が小さく、電気伝導率が大きいものを言う。さらに複数の部材を接続する部分で発生する接触抵抗が低く、総じて電気が流れやすいものを言う。 In the present embodiment, the power supply terminal 31 is U-shaped in cross section, and a part (the lower end portion in the drawing) is drawn to the outside of the wiring board 10. A power supply member 33 made of a conductive material (conductive wiring, a conductive metal plate, a conductive sheet, etc.) for supplying power to the power supply terminal 31 from the outside is attached to the drawer portion. The shapes and sizes of the power supply terminal 31 and the power supply member 33 can be designed as appropriate.
In the present embodiment, the power supply terminal 31 and the power supply member 33 are mechanically fixed to each other by a metal screw (fixing member) 34. About the fixation aspect of the electric power feeding terminal 31 and the electric power feeding member 33, it can design suitably.
The material of the power supply terminal 31, the power supply member 33, and the screw 34 is not particularly limited, and a low-resistance material with little loss when a large current is passed is preferable. As these materials, low resistance materials such as Cu or Cu alloy which are low resistance, easy to process and inexpensive are preferable.
In the present specification, the “member made of a low resistance material” refers to a material having a low electrical resistivity and a high electrical conductivity. Furthermore, the contact resistance which generate | occur | produces in the part which connects a some member is low, and the thing which tends to flow electricity generally says.

本実施形態において、半導体パッケージ２０の複数の外部接続端子２１は、グランド配線層１１に接続される複数のグランド端子と、信号配線層１２に接続される複数の信号端子と、給電端子３１に接続される複数の電源端子とに分けられている。図中、複数のグランド端子／信号端子の群に符号２１Ａを付し、複数の電源端子の群に符号２１Ｂを付してある。本実施形態において、複数の電源端子２１Ｂは半導体パッケージ２０の底面中央部にかためて配置されており、その周りに複数のグランド端子／信号端子２１Ａが配置されている。   In the present embodiment, the plurality of external connection terminals 21 of the semiconductor package 20 are connected to the plurality of ground terminals connected to the ground wiring layer 11, the plurality of signal terminals connected to the signal wiring layer 12, and the power supply terminal 31. Are divided into a plurality of power terminals. In the figure, a group of a plurality of ground terminals / signal terminals is denoted by reference numeral 21A, and a group of a plurality of power supply terminals is denoted by reference numeral 21B. In the present embodiment, the plurality of power supply terminals 21B are arranged so as to cover the center of the bottom surface of the semiconductor package 20, and a plurality of ground terminals / signal terminals 21A are arranged around the power supply terminals 21B.

配線基板１０に開孔された孔部３０は半導体パッケージ２０の複数の電源端子２１Ｂの群の直下に開孔されており、複数の電源端子２１Ｂの群と給電端子３１とが半田等の導電材を介して接続されている。
本実施形態において、複数の外部接続端子２１（複数のグランド端子／信号端子２１Ａと複数の電源端子２１Ｂ）は、互いに半田等による接合が可能な離間距離を保ち、かつ異なる種類の端子同士が接合時に接触しないよう、位置が設計されている。ただし、複数の電源端子２１Ｂについては、端子同士が互いに結合されても構わない。 The hole 30 opened in the wiring substrate 10 is opened immediately below the group of the plurality of power supply terminals 21B of the semiconductor package 20, and the group of the plurality of power supply terminals 21B and the power supply terminal 31 are electrically conductive materials such as solder. Connected through.
In the present embodiment, the plurality of external connection terminals 21 (the plurality of ground terminals / signal terminals 21A and the plurality of power supply terminals 21B) maintain a separation distance that can be joined together by solder or the like, and different types of terminals are joined together. The position is designed to avoid contact at times. However, the plurality of power supply terminals 21B may be coupled to each other.

本実施形態において、孔部３０はスルーホールより大きい径で開孔されており、複数の電源端子２１Ｂの群の径（電源端子エリア径）とほぼ同じ径で開孔されている。
例えば、ＢＧＡ構造のＬＳＩパッケージでは、外部接続端子のピンピッチは通常０．８〜１．０ｍｍ、最も小さいもので０．５ｍｍピッチである。０．５ｍｍピッチで４ピンの電源端子２１Ｂが四角状に配置されたものでは、電源端子２１Ｂの群の面積は０．５ｍｍ×０．５ｍｍ＝０．２５ｍｍ２となる。この場合、孔部３０の径は０．５ｍｍ程度、面積は０．２５ｍｍ２程度となる。これは最も小さく見積もったときの値である。実際には、これよりピン数は多くなるので、孔部３０の径は０．５ｍｍ以上となる。 In the present embodiment, the hole 30 is opened with a diameter larger than that of the through hole, and is opened with a diameter substantially equal to the diameter of the group of the plurality of power supply terminals 21B (power supply terminal area diameter).
For example, in an LSI package having a BGA structure, the pin pitch of the external connection terminals is usually 0.8 to 1.0 mm, and the smallest is 0.5 mm. When the 4-pin power supply terminals 21B are arranged in a square shape at a pitch of 0.5 mm, the area of the group of the power supply terminals 21B is 0.5 mm × 0.5 mm = 0.25 mm 2 . In this case, the diameter of the hole 30 is about 0.5 mm, and the area is about 0.25 mm 2 . This is the smallest estimated value. Actually, since the number of pins is larger than this, the diameter of the hole 30 is 0.5 mm or more.

上記のような大きな径の孔部３０内に給電端子３１を挿入し、複数の電源端子２１Ｂの群と給電端子３１とを半田等により接続するだけでは、これらの接合強度が不充分となる恐れがある。そのため、本実施形態では、樹脂材等の絶縁材３２で給電端子３１を孔部３０に固定し、給電端子３１及び給電部材３３の取付け強度を確保している。   If the power supply terminal 31 is inserted into the hole 30 having a large diameter as described above, and the group of the plurality of power supply terminals 21B and the power supply terminal 31 are simply connected by soldering or the like, their bonding strength may be insufficient. There is. Therefore, in this embodiment, the power supply terminal 31 is fixed to the hole 30 with an insulating material 32 such as a resin material, and the mounting strength of the power supply terminal 31 and the power supply member 33 is ensured.

孔部３０の径は、複数の電源端子２１Ｂの群の径（電源端子エリア径）より大きくしても構わない。ただし、複数の電源端子２１Ｂへの電力供給と、配線基板１０内の配線密度とを考慮すれば、孔部３０の径は複数の電源端子２１Ｂの群の径（電源端子エリア径）とほぼ同じとすることが好ましい。   The diameter of the hole 30 may be larger than the diameter of the group of the plurality of power supply terminals 21B (power supply terminal area diameter). However, considering the power supply to the plurality of power supply terminals 21B and the wiring density in the wiring board 10, the diameter of the hole 30 is substantially the same as the diameter of the group of the plurality of power supply terminals 21B (power supply terminal area diameter). It is preferable that

本実施形態の実装構造１においては、
配線基板１０に厚み方向に貫通して開孔されたスルーホールより大きい孔部３０が設けられ、孔部３０内に外部から半導体パッケージ２０の複数の電源端子２１Ｂに給電するための給電端子３１が挿入されているので、電力損失の大きい半導体パッケージ２０の複数の電源端子２１Ｂに対して、給電端子３１から配線層を介さずに直接大きな電力を供給することができる。 In the mounting structure 1 of this embodiment,
The wiring board 10 is provided with a hole 30 that is larger than the through-hole that is penetrated in the thickness direction, and a power supply terminal 31 for supplying power to the plurality of power supply terminals 21B of the semiconductor package 20 from outside is provided in the hole 30. Since it is inserted, large power can be directly supplied from the power supply terminal 31 to the plurality of power supply terminals 21B of the semiconductor package 20 with large power loss without going through the wiring layer.

本実施形態では、給電端子３１を絶縁材３２により孔部３０に固定しているので、孔部３０の径を大きくしても、給電端子３１を安定的に保持できる。したがって、孔部３０の径をスルーホールより大きく確保することができ、半導体パッケージ２０に大きな電力を供給できる。上記したように、少なく見積もっても０．５ｍｍ径以上（０．５ｍｍ×０．５ｍｍ角以上）の孔部３０を開孔することができ、半導体パッケージ２０に大きな電力を供給できる。   In the present embodiment, since the power supply terminal 31 is fixed to the hole 30 by the insulating material 32, the power supply terminal 31 can be stably held even if the diameter of the hole 30 is increased. Therefore, the diameter of the hole 30 can be secured larger than that of the through hole, and a large amount of power can be supplied to the semiconductor package 20. As described above, the hole 30 having a diameter of 0.5 mm or more (0.5 mm × 0.5 mm square or more) can be opened even if it is estimated to be small, and large power can be supplied to the semiconductor package 20.

本実施形態では、半導体パッケージ２０の底面中央部に、大電流が流れ電力損失が大きい複数の電源端子２１Ｂをかためて配置し、その周りにグランド端子／信号端子２１Ａを配置している。かかる構成は配線の引回しに都合がよく、配線基板１０内の配線構造を簡素化し、配線層の少層化を図ることができる。   In the present embodiment, a plurality of power supply terminals 21B through which a large current flows and a large power loss is disposed at the center of the bottom surface of the semiconductor package 20, and ground terminals / signal terminals 21A are disposed around the power supply terminals 21B. Such a configuration is convenient for routing the wiring, simplifies the wiring structure in the wiring substrate 10, and reduces the number of wiring layers.

本実施形態では、配線基板１０内にグランド配線層１１／信号配線層１２を狭ピッチで配線することができるので、半導体素子チップの微細化・多機能化に対応できる。一方、給電端子３１から半導体パッケージ２０に対して外部から直接電力を供給できるので、配線基板１０内に電源配線層を設ける必要がなく、配線基板１０内の配線層数を少なくできるので、電力損失を低減でき、基板設計（配線層数、配線長、配線ピッチ等）も容易となる。   In the present embodiment, since the ground wiring layer 11 / signal wiring layer 12 can be wired in the wiring substrate 10 at a narrow pitch, it is possible to cope with the miniaturization and multifunctionalization of the semiconductor element chip. On the other hand, since power can be directly supplied from the power supply terminal 31 to the semiconductor package 20 from the outside, it is not necessary to provide a power supply wiring layer in the wiring board 10 and the number of wiring layers in the wiring board 10 can be reduced. Board design (number of wiring layers, wiring length, wiring pitch, etc.) becomes easy.

本実施形態では、配線基板１０内の電源配線層は必須ではないが、配線基板１０内に電源配線層を設け、給電端子３１と電源配線層とを併用しても構わない。この場合でも、電源配線層数は従来よりも少なくでき、電力損失の低減及び基板設計の容易化の効果は得られる。   In the present embodiment, the power supply wiring layer in the wiring board 10 is not essential, but a power supply wiring layer may be provided in the wiring board 10 and the power supply terminal 31 and the power supply wiring layer may be used in combination. Even in this case, the number of power supply wiring layers can be reduced as compared with the prior art, and the effects of reducing power loss and facilitating board design can be obtained.

本実施形態では、配線基板１０内に電源配線層を設ける必要がなく、配線基板１０内の配線層数を少なくできることで、配線基板１０内の電力損失を少なくできるので、電力損失による発熱が抑えられ、配線基板１０や半導体パッケージ２０を発熱から守ることができる。   In the present embodiment, it is not necessary to provide a power supply wiring layer in the wiring board 10 and the number of wiring layers in the wiring board 10 can be reduced, so that power loss in the wiring board 10 can be reduced. Therefore, the wiring board 10 and the semiconductor package 20 can be protected from heat generation.

本実施形態では、給電端子３１に接続する給電部材３３の設計自由度が高く、給電部材３３の形状や材質を自由に設計できる。そのため、給電部材３３から給電端子３１に低損失で大きな電力を供給できる。
本実施形態では、給電端子３１及び給電部材３３として低抵抗材料を使用できるので、配線基板１０内に電源配線層を設ける必要がないこと、及び配線基板１０内の配線層数を低減できることと合わせて、全体的な電力損失を大幅に少なくできる。 In this embodiment, the design flexibility of the power supply member 33 connected to the power supply terminal 31 is high, and the shape and material of the power supply member 33 can be freely designed. Therefore, large power can be supplied from the power supply member 33 to the power supply terminal 31 with low loss.
In the present embodiment, since a low-resistance material can be used as the power supply terminal 31 and the power supply member 33, it is not necessary to provide a power supply wiring layer in the wiring board 10 and the number of wiring layers in the wiring board 10 can be reduced. Thus, the overall power loss can be greatly reduced.

以上説明したように、本実施形態によれば、半導体素子チップ２０の改造を要することなく、半導体素子チップ２０に大きな電力を供給することが可能な実装構造１を提供することができる。   As described above, according to the present embodiment, it is possible to provide the mounting structure 1 that can supply large power to the semiconductor element chip 20 without requiring modification of the semiconductor element chip 20.

「第２実施形態」
図面を参照して、本発明に係る第２実施形態の半導体素子チップの実装構造について説明する。図２は、本実施形態の実装構造の断面図である。視認しやすくするため、各構成要素の縮尺は実際のものとは適宜異ならせてある。第１実施形態と同じ構成要素については同じ参照符号を付して説明を省略する。 “Second Embodiment”
A semiconductor element chip mounting structure according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a cross-sectional view of the mounting structure of the present embodiment. In order to facilitate visual recognition, the scale of each component is appropriately different from the actual one. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

本実施形態の実装構造２は、配線基板１０にＬＳＩチップ等の半導体素子チップ４１が収容された半導体パッケージ４０が実装されたものである。本実施形態において、半導体パッケージ４０はＳＯＰ（Small Outline Package）あるいはＱＦＰ（Quad Flat Package）等のエクスポーズドパッケージである。   The mounting structure 2 of the present embodiment is obtained by mounting a semiconductor package 40 in which a semiconductor element chip 41 such as an LSI chip is accommodated on a wiring board 10. In the present embodiment, the semiconductor package 40 is an exposed package such as SOP (Small Outline Package) or QFP (Quad Flat Package).

本実施形態においても、配線基板１０は、半導体パッケージ４０の直下に配線基板１０を厚み方向に貫通して開孔されたスルーホールより大きい少なくとも１つの孔部３０を有している。この孔部３０内に外部から半導体パッケージ４０の外部接続端子４１に給電するための給電端子３１が挿入され、給電端子３１が絶縁材３２により孔部３０内に固定されている。図示する例では、孔部３０は１個であるが、複数設けても構わない。
本実施形態においても、給電端子３１に、外部から給電端子３１に給電するための給電部材３３が取り付けられている。本実施形態においても、金属製のネジ（固定部材）３４により給電端子３１と給電部材３３とが互いに機械的に固定されている。 Also in the present embodiment, the wiring board 10 has at least one hole portion 30 that is larger than a through hole that is opened through the wiring board 10 in the thickness direction immediately below the semiconductor package 40. A power supply terminal 31 for supplying power from the outside to the external connection terminal 41 of the semiconductor package 40 is inserted into the hole 30, and the power supply terminal 31 is fixed in the hole 30 by an insulating material 32. In the example shown in the figure, the number of the holes 30 is one, but a plurality of holes 30 may be provided.
Also in the present embodiment, a power supply member 33 for supplying power to the power supply terminal 31 from the outside is attached to the power supply terminal 31. Also in this embodiment, the power supply terminal 31 and the power supply member 33 are mechanically fixed to each other by a metal screw (fixing member) 34.

エクスポーズドパッケージには、パッケージ底面にグランド接続強化や放熱等のために専用端子が設けられていることがある。本実施形態では、この専用端子が電源端子として使用されている。
半導体パッケージ４０には複数の外部接続端子４２が設けられており、半導体パッケージ４０の側方から延びた複数の外部接続端子４２Ａがグランド配線層１１に接続される複数のグランド端子と信号配線層１２に接続される複数の信号端子とされ、半導体パッケージ４０の底面に取り付けられた上記専用端子からなる外部接続端子４２Ｂが給電端子３１に接続される複数の電源端子とされている。本実施形態において、複数の電源端子４２Ｂは、半導体パッケージ４０の底面中央部にかためて配置されている。
本実施形態においても、配線基板１０に開孔された孔部３０は半導体パッケージ４０の複数の電源端子４２Ｂの群の直下に開孔されており、複数の電源端子４２Ｂの群と給電端子３１とが半田等により接続されている。 In the exposed package, a dedicated terminal may be provided on the bottom surface of the package for enhancing ground connection, heat dissipation, or the like. In the present embodiment, this dedicated terminal is used as a power supply terminal.
The semiconductor package 40 is provided with a plurality of external connection terminals 42, and the plurality of external connection terminals 42 </ b> A extending from the side of the semiconductor package 40 are connected to the ground wiring layer 11 and the signal wiring layer 12. The external connection terminals 42 </ b> B including the dedicated terminals attached to the bottom surface of the semiconductor package 40 are a plurality of power supply terminals connected to the power supply terminal 31. In the present embodiment, the plurality of power supply terminals 42 </ b> B are disposed so as to overlap the central portion of the bottom surface of the semiconductor package 40.
Also in the present embodiment, the hole 30 opened in the wiring substrate 10 is opened immediately below the group of the plurality of power supply terminals 42B of the semiconductor package 40, and the group of the plurality of power supply terminals 42B, the power supply terminals 31, and the like. Are connected by solder or the like.

本実施形態においても、孔部３０はスルーホールより大きいものであり、複数の電源端子４２Ｂの郡の径とほぼ同じ径で開孔されている。ＳＯＰやＱＦＰのエクスポーズドパッケージの場合は、パッケージ底面に専用端子を有している。そのため、パッケージサイズ（樹脂部分の大きさ）よりは小さくなるがピンピッチに依存しないため、開孔の大きさはピンピッチからパッケージサイズ（樹脂部分と同等程度）までが可能となる。ＳＯＰやＱＦＰのピンピッチは０．５ｍｍ程度が最小であるので、第１実施形態と同様、孔部３０の径は０．５ｍｍ以上となる。
本実施形態においても、樹脂材等の絶縁材３２で給電端子３１を孔部３０に固定し、給電端子３１及び給電部材３３の取付け強度を確保している。
本実施形態においても、第１実施形態と同様の効果が得られる。 Also in the present embodiment, the hole 30 is larger than the through hole, and is opened with a diameter substantially the same as the diameter of the plurality of power supply terminals 42B. In the case of an exposed package of SOP or QFP, a dedicated terminal is provided on the bottom of the package. Therefore, although it is smaller than the package size (size of the resin portion), it does not depend on the pin pitch, so that the size of the opening can be from the pin pitch to the package size (equivalent to the resin portion). Since the pin pitch of SOP or QFP is about 0.5 mm, the diameter of the hole 30 is 0.5 mm or more, as in the first embodiment.
Also in this embodiment, the power supply terminal 31 is fixed to the hole 30 with an insulating material 32 such as a resin material, and the mounting strength of the power supply terminal 31 and the power supply member 33 is ensured.
Also in this embodiment, the same effect as the first embodiment can be obtained.

「第３実施形態」
図面を参照して、本発明に係る第３実施形態の半導体素子チップの実装構造について説明する。図３は、本実施形態の実装構造の断面図である。視認しやすくするため、各構成要素の縮尺は実際のものとは適宜異ならせてある。第２実施形態と同じ構成要素については同じ参照符号を付して説明を省略する。 “Third Embodiment”
A semiconductor element chip mounting structure according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view of the mounting structure of this embodiment. In order to facilitate visual recognition, the scale of each component is appropriately different from the actual one. The same components as those in the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

本実施形態の実装構造３は、配線基板１０にＬＳＩチップ等の半導体素子チップ５１が収容された半導体パッケージ５０が実装されたものである。本実施形態においては、半導体パッケージ５０はＳＯＰあるいはＱＦＰ等である。本実施形態の半導体パッケージ５０の底面には、第２実施形態にある専用端子がない。   The mounting structure 3 of the present embodiment is obtained by mounting a semiconductor package 50 in which a semiconductor element chip 51 such as an LSI chip is accommodated on a wiring board 10. In the present embodiment, the semiconductor package 50 is SOP or QFP. There is no dedicated terminal in the second embodiment on the bottom surface of the semiconductor package 50 of the present embodiment.

半導体パッケージ５０には複数の外部接続端子５２が設けられており、半導体パッケージ５０の側方から延びた一部の複数の外部接続端子５２Ａがグランド配線層１１に接続される複数のグランド端子と信号配線層１２に接続される複数の信号端子とされ、半導体パッケージ５０の側方から延びた他の複数の外部接続端子５２Ｂが給電端子３１に接続される複数の電源端子とされている。   The semiconductor package 50 is provided with a plurality of external connection terminals 52, and some of the plurality of external connection terminals 52 </ b> A extending from the side of the semiconductor package 50 are connected to the ground wiring layer 11 and a signal. A plurality of signal terminals connected to the wiring layer 12 and a plurality of other external connection terminals 52 </ b> B extending from the side of the semiconductor package 50 are a plurality of power supply terminals connected to the power supply terminal 31.

本実施形態において、配線基板１０は、複数の外部接続端子５２Ｂの直下に配線基板１０を厚み方向に貫通して開孔されたスルーホールより大きい少なくとも１つの孔部３０を有している。この孔部３０内に外部から半導体素子チップ５０の複数の外部接続端子５２Ｂに給電するための給電端子３１が挿入され、給電端子３１が絶縁材３２により孔部３０内に固定されている。図示する例では、孔部３０は１個であるが、複数設けても構わない。
本実施形態においても、孔部３０はスルーホールより大きいものであり、複数の外部接続端子５２Ｂの郡の径とほぼ同じ径で開孔されている。ＳＯＰやＱＦＰの場合、ピンピッチは０．５ｍｍ程度が最小であるので、第１実施形態と同様、孔部３０の径は０．５ｍｍ以上となる。 In the present embodiment, the wiring board 10 has at least one hole portion 30 that is larger than a through hole that is opened through the wiring board 10 in the thickness direction immediately below the plurality of external connection terminals 52B. A power supply terminal 31 for supplying power to the plurality of external connection terminals 52 </ b> B of the semiconductor element chip 50 from the outside is inserted into the hole 30, and the power supply terminal 31 is fixed in the hole 30 by an insulating material 32. In the example shown in the figure, the number of the holes 30 is one, but a plurality of holes 30 may be provided.
Also in the present embodiment, the hole 30 is larger than the through hole, and is opened with a diameter substantially the same as the diameter of the plurality of external connection terminals 52B. In the case of SOP and QFP, since the pin pitch is about 0.5 mm, the diameter of the hole 30 is 0.5 mm or more as in the first embodiment.

本実施形態においても、給電端子３１に、外部から給電端子３１に給電するための給電部材３３が取り付けられている。本実施形態において、金属製のネジ（固定部材）３４により給電端子３１と給電部材３３とが互いに機械的に固定されている。
給電端子３１と外部接続端子５２Ｂとは半田等の導電材５３を介して接合されている。
本実施形態においても、第１実施形態と同様の効果が得られる。 Also in the present embodiment, a power supply member 33 for supplying power to the power supply terminal 31 from the outside is attached to the power supply terminal 31. In the present embodiment, the power supply terminal 31 and the power supply member 33 are mechanically fixed to each other by a metal screw (fixing member) 34.
The power supply terminal 31 and the external connection terminal 52B are joined via a conductive material 53 such as solder.
Also in this embodiment, the same effect as the first embodiment can be obtained.

「第４実施形態」
図面を参照して、本発明に係る第４実施形態の半導体素子チップの実装構造について説明する。図４は、本実施形態の実装構造の断面図である。視認しやすくするため、各構成要素の縮尺は実際のものとは適宜異ならせてある。 “Fourth Embodiment”
With reference to the drawings, a mounting structure of a semiconductor element chip according to a fourth embodiment of the present invention will be described. FIG. 4 is a cross-sectional view of the mounting structure of this embodiment. In order to facilitate visual recognition, the scale of each component is appropriately different from the actual one.

本実施形態の実装構造４は、配線基板６０にＬＳＩチップ等の半導体素子チップが収容された半導体パッケージ７０が実装されたものである。半導体パッケージ７０はＢＧＡ（Ball grid array）パッケージである。   The mounting structure 4 of the present embodiment is obtained by mounting a semiconductor package 70 in which a semiconductor element chip such as an LSI chip is accommodated on a wiring board 60. The semiconductor package 70 is a BGA (Ball grid array) package.

配線基板６０内には、複数の配線層が絶縁層（符号略）を介して積層されている。配線基板６０には、複数の配線層として、少なくとも１つのグランド配線層６１と少なくとも１つの信号配線層６２とが形成されている。
配線基板６０の一方の基板面（図示上面）に、半導体パッケージ７０が実装されている。半導体パッケージ７０はその底面に複数の外部接続端子７１を有し、これら外部接続端子７１が配線基板６０に半田等の導電材を介して接合されている。配線基板６０と半導体パッケージ７０との間隙には、接合強化や異物流入防止等のために、アンダーフィル樹脂２２が充填されている。アンダーフィル樹脂２２は必須なものではない。 In the wiring board 60, a plurality of wiring layers are laminated via insulating layers (reference numerals omitted). On the wiring board 60, at least one ground wiring layer 61 and at least one signal wiring layer 62 are formed as a plurality of wiring layers.
A semiconductor package 70 is mounted on one substrate surface (illustrated upper surface) of the wiring substrate 60. The semiconductor package 70 has a plurality of external connection terminals 71 on its bottom surface, and these external connection terminals 71 are joined to the wiring board 60 via a conductive material such as solder. The gap between the wiring board 60 and the semiconductor package 70 is filled with an underfill resin 22 for strengthening the bonding, preventing foreign matter from flowing in, and the like. The underfill resin 22 is not essential.

本実施形態において、半導体パッケージ７０の複数の外部接続端子７１は、グランド配線層６１に接続される複数のグランド端子と、信号配線層６２に接続される複数の信号端子と、複数の電源端子とに分けられている。本実施形態において、電源端子は放熱端子を兼ねている。
図中、複数のグランド端子／信号端子の群に符号７１Ａを付し、複数の放熱端子（電源端子）の群に符号７１Ｂを付してある。本実施形態において、複数の放熱端子（電源端子）７１Ｂは半導体パッケージ７０の底面中央部にかためて配置されており、その周りに複数のグランド端子／信号端子７１Ａが配置されている。 In the present embodiment, the plurality of external connection terminals 71 of the semiconductor package 70 include a plurality of ground terminals connected to the ground wiring layer 61, a plurality of signal terminals connected to the signal wiring layer 62, and a plurality of power supply terminals. It is divided into. In the present embodiment, the power supply terminal also serves as a heat dissipation terminal.
In the figure, reference numeral 71A is assigned to a group of a plurality of ground terminals / signal terminals, and reference numeral 71B is assigned to a group of a plurality of heat radiation terminals (power supply terminals). In the present embodiment, a plurality of heat radiation terminals (power supply terminals) 71B are arranged at the center of the bottom surface of the semiconductor package 70, and a plurality of ground terminals / signal terminals 71A are arranged therearound.

本実施形態において、配線基板６０は、半導体パッケージ７０の直下に配線基板６０を厚み方向に貫通して開孔されたスルーホールより大きい少なくとも１つの孔部８０を有している。この孔部８０内に半導体パッケージ７０の放熱端子（電源端子）７１Ｂから外部に放熱するための外部放熱端子８１が挿入され、外部放熱端子８１が絶縁材８２により孔部８０内に固定されている。孔部８０は１個であるが、複数設けても構わない。本実施形態において、外部放熱端子８１は放熱端子（電源端子）７１Ｂに給電する給電端子を兼ねている。
絶縁材８２としては樹脂材が好ましい。絶縁材８２としては任意の樹脂を使用できるが、アンダーフィル樹脂２２と同じ樹脂を用いれば、使用する材料が少なくて済み、簡便である。 In the present embodiment, the wiring board 60 has at least one hole 80 that is larger than a through hole that is formed through the wiring board 60 in the thickness direction immediately below the semiconductor package 70. An external heat radiating terminal 81 for radiating heat from the heat radiating terminal (power supply terminal) 71B of the semiconductor package 70 is inserted into the hole 80, and the external heat radiating terminal 81 is fixed in the hole 80 by an insulating material 82. . Although there is one hole 80, a plurality of holes 80 may be provided. In the present embodiment, the external heat dissipation terminal 81 also serves as a power supply terminal that supplies power to the heat dissipation terminal (power supply terminal) 71B.
The insulating material 82 is preferably a resin material. Although any resin can be used as the insulating material 82, if the same resin as the underfill resin 22 is used, the amount of material used is small, which is convenient.

本実施形態において、外部放熱端子（給電端子）８１に、導電材（導電性配線、導電性金属板、及び導電性シート等）からなる第１の放熱部材８３が取り付けられている。本実施形態において、金属製のネジ（固定部材）８４により外部放熱端子８１と第１の放熱部材８３とが互いに機械的に固定されている。本実施形態において、第１の放熱部材８３は外部放熱端子（給電端子）８１に給電する給電部材を兼ねている。
外部放熱端子（給電端子）８１、第１の放熱部材（給電部材）８３、及びネジ８４の材質としては特に制限されず、大電流を流した場合の損失の少なく、熱伝導率が高く放熱効果の高い低抵抗材料が好ましい。これらの材質としては、低抵抗で熱伝導率が高く加工が容易で安価なＣｕあるいはＣｕ合金等の低抵抗材料が好ましい。 In the present embodiment, a first heat radiating member 83 made of a conductive material (conductive wiring, conductive metal plate, conductive sheet, etc.) is attached to an external heat radiating terminal (power feeding terminal) 81. In the present embodiment, the external heat radiating terminal 81 and the first heat radiating member 83 are mechanically fixed to each other by a metal screw (fixing member) 84. In the present embodiment, the first heat dissipation member 83 also serves as a power supply member that supplies power to the external heat dissipation terminal (power supply terminal) 81.
The material of the external heat radiating terminal (power feeding terminal) 81, the first heat radiating member (power feeding member) 83, and the screw 84 is not particularly limited, and there is little loss when a large current is passed, the heat conductivity is high, and the heat radiation effect. High resistance material with high resistance is preferable. These materials are preferably low-resistance materials such as Cu or Cu alloys that have low resistance, high thermal conductivity, are easy to process, and are inexpensive.

配線基板６０に開孔された孔部８０は半導体パッケージ７０の複数の放熱端子（電源端子）７１Ｂの群の直下に開孔されており、複数の放熱端子（電源端子）７１Ｂの群と外部放熱端子（給電端子）８１とが半田等により接続されている。孔部８０はスルーホールより大きいものであり、複数の放熱端子（電源端子）７１Ｂの群の径（放熱端子エリア径（電源端子エリア径））とほぼ同じ径で開孔されている。
例えば、ＢＧＡ構造のＬＳＩパッケージでは、端子のピンピッチは通常０．８〜１．０ｍｍ、最も小さいもので０．５ｍｍピッチである。０．５ｍｍピッチで４ピンの放熱端子（電源端子）７１Ｂが四角状に配置されたものでは、放熱端子（電源端子）７１Ｂの群の面積は０．５ｍｍ×０．５ｍｍ＝０．２５ｍｍ２となる。この場合、孔部８０の径は０．５ｍｍ程度、面積は０．２５ｍｍ２程度となる。これは最も小さく見積もったときの値である。実際には、これよりピン数は多くなるので、孔部８０の径は０．５ｍｍ以上となる。 The hole 80 opened in the wiring board 60 is opened immediately below a group of a plurality of heat radiating terminals (power supply terminals) 71B of the semiconductor package 70, and external heat dissipation with the group of the plurality of heat radiating terminals (power supply terminals) 71B. A terminal (power supply terminal) 81 is connected by solder or the like. The hole 80 is larger than the through hole, and is opened with a diameter substantially equal to the diameter of the group of the plurality of heat radiation terminals (power supply terminals) 71B (heat radiation terminal area diameter (power supply terminal area diameter)).
For example, in an LSI package having a BGA structure, the pin pitch of terminals is usually 0.8 to 1.0 mm, and the smallest is 0.5 mm pitch. In the case where 4-pin heat dissipation terminals (power supply terminals) 71B are arranged in a square shape at a pitch of 0.5 mm, the area of the group of heat dissipation terminals (power supply terminals) 71B is 0.5 mm × 0.5 mm = 0.25 mm 2 . Become. In this case, the diameter of the hole 80 is about 0.5 mm, and the area is about 0.25 mm 2 . This is the smallest estimated value. Actually, since the number of pins is larger than this, the diameter of the hole 80 is 0.5 mm or more.

上記のような大きな径の孔部８０内に外部放熱端子（給電端子）８１を挿入し、複数の放熱端子（電源端子）７１Ｂの群と外部放熱端子（給電端子）８１とを半田等により接続するだけでは、これらの接合強度が不充分となる恐れがある。そのため、本実施形態では、樹脂材等の絶縁材８２で外部放熱端子（給電端子）８１を孔部８０に固定し、外部放熱端子（給電端子）８１及び第１の放熱部材（給電部材）８３の取付け強度を確保している。   An external heat radiation terminal (power supply terminal) 81 is inserted into the hole 80 having a large diameter as described above, and a group of a plurality of heat radiation terminals (power supply terminals) 71B and the external heat radiation terminals (power supply terminals) 81 are connected by soldering or the like. If this is done, the bonding strength may be insufficient. Therefore, in this embodiment, the external heat radiation terminal (power supply terminal) 81 is fixed to the hole 80 with an insulating material 82 such as a resin material, and the external heat radiation terminal (power supply terminal) 81 and the first heat radiation member (power supply member) 83. The mounting strength of is secured.

孔部８０の径は、複数の放熱端子（電源端子）７１Ｂの群の径（放熱端子エリア径（電源端子エリア径））より大きくしても構わない。ただし、複数の放熱端子（電源端子）７１Ｂへの給電と、複数の放熱端子（電源端子）７１Ｂからの放熱と、配線基板６０内の配線密度とを考慮すれば、孔部８０の径は複数の放熱端子（電源端子）７１Ｂの群の径（放熱端子エリア径（電源端子エリア径））とほぼ同じとすることが好ましい。   The diameter of the hole 80 may be larger than the diameter of the group of the plurality of heat radiation terminals (power supply terminals) 71B (heat radiation terminal area diameter (power supply terminal area diameter)). However, considering the power feeding to the plurality of heat radiation terminals (power supply terminals) 71B, the heat radiation from the plurality of heat radiation terminals (power supply terminals) 71B, and the wiring density in the wiring board 60, the diameter of the hole 80 is plural. It is preferable that the diameter of the group of heat radiation terminals (power supply terminals) 71B (heat radiation terminal area diameter (power supply terminal area diameter)) is substantially the same.

本実施形態では、第１の放熱部材８３の底面に放熱板等の第２の放熱部材９０が取り付けられている。第２の放熱部材９０はネジ８４によって第１の放熱部材８３に固定されている。第２の放熱部材９０の固定態様については適宜設計できる。   In the present embodiment, a second heat radiating member 90 such as a heat radiating plate is attached to the bottom surface of the first heat radiating member 83. The second heat radiating member 90 is fixed to the first heat radiating member 83 with screws 84. About the fixation aspect of the 2nd heat radiating member 90, it can design suitably.

放熱端子を有する半導体パッケージを実装する場合、従来であれば放熱端子に配線基板を接続するので、放熱端子から配線基板に熱が伝わる。本実施形態では、配線基板６０を介さずに外部放熱端子８１から外部に直接放熱できるので、配線基板６０に熱が伝わらず配線基板６０の温度上昇が抑えられ、かつ、高い放熱効果が得られる。   When mounting a semiconductor package having a heat radiating terminal, conventionally, since the wiring board is connected to the heat radiating terminal, heat is transferred from the heat radiating terminal to the wiring board. In this embodiment, heat can be directly radiated from the external heat radiation terminal 81 to the outside without going through the wiring board 60, so that heat is not transmitted to the wiring board 60, the temperature rise of the wiring board 60 is suppressed, and a high heat radiation effect is obtained. .

本実施形態では、外部放熱端子８１に第１の放熱部材８３と第２の放熱部材９０とを接続しているので、外部放熱端子８１からの放熱が促進され、好ましい。本実施形態では、第１の放熱部材８３によって配線基板６０から離れた箇所に熱を逃がすことができ、放熱板等からなる第２の放熱部材９０によって、空気中に効果的に熱を逃がすことができ、これら複数の放熱部材によって高い放熱効果が得られる。外部放熱端子８１に取り付ける放熱部材の種類及び数については適宜設計できる。   In the present embodiment, since the first heat radiating member 83 and the second heat radiating member 90 are connected to the external heat radiating terminal 81, heat radiation from the external heat radiating terminal 81 is promoted, which is preferable. In the present embodiment, heat can be released to a place away from the wiring board 60 by the first heat radiating member 83, and heat can be effectively released to the air by the second heat radiating member 90 made of a heat radiating plate or the like. A high heat dissipation effect can be obtained by the plurality of heat dissipation members. About the kind and number of the thermal radiation members attached to the external thermal radiation terminal 81, it can design suitably.

本実施形態では、放熱端子７１Ｂが電源端子であり、外部放熱端子８１が給電端子であり、第１の放熱部材８３が給電部材である場合について説明した。かかる構成は第１実施形態と同様であるので、第１実施形態と同様の効果も得られる。
本実施形態では、配線基板６０内の電源配線層は必須ではないが、配線基板６０内に電源配線層を設け、給電端子である外部放熱端子８１と電源配線層とを併用しても構わない。この場合でも、電源配線層数は従来よりも少なくでき、電力損失の低減及び基板設計の容易化の効果は得られる。
本発明は、放熱端子７１Ｂがグランド端子であり、外部放熱端子８１が放熱機能を有するグランド接続端子であり、第１の放熱部材８３が放熱機能を有するグランド接続部材である場合にも適用できる。この場合は、配線基板内に電源配線層は必要である。 In the present embodiment, the case where the heat dissipation terminal 71B is a power supply terminal, the external heat dissipation terminal 81 is a power supply terminal, and the first heat dissipation member 83 is a power supply member has been described. Since this configuration is the same as that of the first embodiment, the same effect as that of the first embodiment can be obtained.
In the present embodiment, the power supply wiring layer in the wiring board 60 is not essential, but a power supply wiring layer may be provided in the wiring board 60 and the external heat radiation terminal 81 that is a power supply terminal and the power supply wiring layer may be used in combination. . Even in this case, the number of power supply wiring layers can be reduced as compared with the prior art, and the effects of reducing power loss and facilitating board design can be obtained.
The present invention can also be applied to the case where the heat dissipation terminal 71B is a ground terminal, the external heat dissipation terminal 81 is a ground connection terminal having a heat dissipation function, and the first heat dissipation member 83 is a ground connection member having a heat dissipation function. In this case, a power wiring layer is necessary in the wiring board.

（設計変更）
本発明は上記態様に限らず、本発明の趣旨を逸脱しない範囲内において適宜設計変更が可能である。 (Design changes)
The present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope not departing from the gist of the present invention.

１〜４ 実装構造
１０ 配線基板
１１ グランド配線層
１２ 信号配線層
２０ 半導体パッケージ
２１ 外部接続端子
２１Ａ グランド端子／信号端子
２１Ｂ 電源端子
３０ 孔部
３１ 給電端子
３２ 絶縁材
３３ 給電部材
４０ 半導体パッケージ
４１ 半導体素子チップ
４２ 外部接続端子
４２Ａ グランド端子／信号端子
４２Ｂ 電源端子
５０ 半導体パッケージ
５１ 半導体素子チップ
５２ 外部接続端子
５２Ａ グランド端子／信号端子
５２Ｂ 電源端子
６０ 配線基板
６１ グランド配線層
６２ 信号配線層
７０ 半導体パッケージ
７１Ａ 外部接続端子（グランド端子／信号端子／電源端子）
７１Ｂ 放熱端子
８０ 孔部
８１ 外部放熱端子
８２ 絶縁材
８３ 第１の放熱部材
９０ 第２の放熱部材 1-4 Mounting Structure 10 Wiring Board 11 Ground Wiring Layer 12 Signal Wiring Layer 20 Semiconductor Package 21 External Connection Terminal 21A Ground Terminal / Signal Terminal 21B Power Terminal 30 Hole 31 Feeding Terminal 32 Insulating Material 33 Feeding Member 40 Semiconductor Package 41 Semiconductor Element Chip 42 External connection terminal 42A Ground terminal / signal terminal 42B Power supply terminal 50 Semiconductor package 51 Semiconductor element chip 52 External connection terminal 52A Ground terminal / signal terminal 52B Power supply terminal 60 Wiring board 61 Ground wiring layer 62 Signal wiring layer 70 Semiconductor package 71A External Connection terminal (ground terminal / signal terminal / power supply terminal)
71B Heat dissipation terminal 80 Hole 81 External heat dissipation terminal 82 Insulating material 83 First heat dissipation member 90 Second heat dissipation member

Claims (5)

少なくとも１つのグランド配線層と少なくとも１つの信号配線層とを含む複数の配線層を備えた配線基板の一方の基板面に少なくとも１つの半導体素子チップが実装された実装構造であって、
前記配線基板は、当該配線基板を厚み方向に貫通し、前記半導体素子チップの外部接続端子の径以上の径で開孔された少なくとも１つの孔部を有し、当該孔部内に外部から前記半導体素子チップの外部接続端子に給電するための給電端子が挿入され、当該給電端子が絶縁材により前記孔部内に固定され、内部に電源配線層を有していない
ことを特徴とする実装構造。 A mounting structure in which at least one semiconductor element chip is mounted on one substrate surface of a wiring board having a plurality of wiring layers including at least one ground wiring layer and at least one signal wiring layer,
The wiring board through the wiring board in the thickness direction, the semiconductor device has one hole even without least is aperture in diameter larger than the diameter of the external connection terminals of the chip, from the outside into the said hole A power supply terminal for supplying power to the external connection terminal of the semiconductor element chip is inserted, the power supply terminal is fixed in the hole by an insulating material, and does not have a power wiring layer inside
Implementation structure, characterized in that. 前記孔部は前記半導体素子チップの前記外部接続端子の直下に開孔された請求項１に記載の実装構造。 2. The mounting structure according to claim 1 , wherein the hole is formed immediately below the external connection terminal of the semiconductor element chip. 前記絶縁材が樹脂材である請求項１又は２に記載の実装構造。 The mounting structure according to claim 1, wherein the insulating material is a resin material. 前記給電端子に、外部から当該給電端子に給電するための給電部材が取り付けられた請求項１〜３のいずれかに記載の実装構造。 Wherein the feeding terminal, mounting structure according to any one of claims 1 to 3, the power supply member is mounted for feeding externally to said feeding terminal. 前記給電端子及び前記給電部材が低抵抗材料からなる請求項４に記載の実装構造。 The mounting structure according to claim 4 , wherein the power supply terminal and the power supply member are made of a low-resistance material.
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